arch/ia64/include/asm/native/inst.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /******************************************************************************
   3  * arch/ia64/include/asm/native/inst.h
   4  *
   5  * Copyright (c) 2008 Isaku Yamahata <yamahata at valinux co jp>
   6  *                    VA Linux Systems Japan K.K.
   7  */
   8
   9 #define DO_SAVE_MIN             IA64_NATIVE_DO_SAVE_MIN
  10
  11 #define MOV_FROM_IFA(reg)       \
  12         mov reg = cr.ifa
  13
  14 #define MOV_FROM_ITIR(reg)      \
  15         mov reg = cr.itir
  16
  17 #define MOV_FROM_ISR(reg)       \
  18         mov reg = cr.isr
  19
  20 #define MOV_FROM_IHA(reg)       \
  21         mov reg = cr.iha
  22
  23 #define MOV_FROM_IPSR(pred, reg)        \
  24 (pred)  mov reg = cr.ipsr
  25
  26 #define MOV_FROM_IIM(reg)       \
  27         mov reg = cr.iim
  28
  29 #define MOV_FROM_IIP(reg)       \
  30         mov reg = cr.iip
  31
  32 #define MOV_FROM_IVR(reg, clob) \
  33         mov reg = cr.ivr
  34
  35 #define MOV_FROM_PSR(pred, reg, clob)   \
  36 (pred)  mov reg = psr
  37
  38 #define MOV_FROM_ITC(pred, pred_clob, reg, clob)        \
  39 (pred)  mov reg = ar.itc
  40
  41 #define MOV_TO_IFA(reg, clob)   \
  42         mov cr.ifa = reg
  43
  44 #define MOV_TO_ITIR(pred, reg, clob)    \
  45 (pred)  mov cr.itir = reg
  46
  47 #define MOV_TO_IHA(pred, reg, clob)     \
  48 (pred)  mov cr.iha = reg
  49
  50 #define MOV_TO_IPSR(pred, reg, clob)            \
  51 (pred)  mov cr.ipsr = reg
  52
  53 #define MOV_TO_IFS(pred, reg, clob)     \
  54 (pred)  mov cr.ifs = reg
  55
  56 #define MOV_TO_IIP(reg, clob)   \
  57         mov cr.iip = reg
  58
  59 #define MOV_TO_KR(kr, reg, clob0, clob1)        \
  60         mov IA64_KR(kr) = reg
  61
  62 #define ITC_I(pred, reg, clob)  \
  63 (pred)  itc.i reg
  64
  65 #define ITC_D(pred, reg, clob)  \
  66 (pred)  itc.d reg
  67
  68 #define ITC_I_AND_D(pred_i, pred_d, reg, clob)  \
  69 (pred_i) itc.i reg;                             \
  70 (pred_d) itc.d reg
  71
  72 #define THASH(pred, reg0, reg1, clob)           \
  73 (pred)  thash reg0 = reg1
  74
  75 #define SSM_PSR_IC_AND_DEFAULT_BITS_AND_SRLZ_I(clob0, clob1)            \
  76         ssm psr.ic | PSR_DEFAULT_BITS                                   \
  77         ;;                                                              \
  78         srlz.i /* guarantee that interruption collectin is on */        \
  79         ;;
  80
  81 #define SSM_PSR_IC_AND_SRLZ_D(clob0, clob1)     \
  82         ssm psr.ic                              \
  83         ;;                                      \
  84         srlz.d
  85
  86 #define RSM_PSR_IC(clob)        \
  87         rsm psr.ic
  88
  89 #define SSM_PSR_I(pred, pred_clob, clob)        \
  90 (pred)  ssm psr.i
  91
  92 #define RSM_PSR_I(pred, clob0, clob1)   \
  93 (pred)  rsm psr.i
  94
  95 #define RSM_PSR_I_IC(clob0, clob1, clob2)       \
  96         rsm psr.i | psr.ic
  97
  98 #define RSM_PSR_DT              \
  99         rsm psr.dt
 100
 101 #define RSM_PSR_BE_I(clob0, clob1)      \
 102         rsm psr.be | psr.i
 103
 104 #define SSM_PSR_DT_AND_SRLZ_I   \
 105         ssm psr.dt              \
 106         ;;                      \
 107         srlz.i
 108
 109 #define BSW_0(clob0, clob1, clob2)      \
 110         bsw.0
 111
 112 #define BSW_1(clob0, clob1)     \
 113         bsw.1
 114
 115 #define COVER   \
 116         cover
 117
 118 #define RFI     \
 119         rfi