arch/arm/mach-s3c24xx/common.c

   1 /* linux/arch/arm/plat-s3c24xx/cpu.c
   2  *
   3  * Copyright (c) 2004-2005 Simtec Electronics
   4  *      http://www.simtec.co.uk/products/SWLINUX/
   5  *      Ben Dooks <ben@simtec.co.uk>
   6  *
   7  * Common code for S3C24XX machines
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  22 */
  23
  24 #include <linux/dma-mapping.h>
  25 #include <linux/init.h>
  26 #include <linux/module.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/ioport.h>
  29 #include <linux/serial_core.h>
  30 #include <linux/serial_s3c.h>
  31 #include <clocksource/samsung_pwm.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/delay.h>
  34 #include <linux/io.h>
  35 #include <linux/platform_data/dma-s3c24xx.h>
  36 #include <linux/dmaengine.h>
  37
  38 #include <mach/hardware.h>
  39 #include <mach/regs-clock.h>
  40 #include <asm/irq.h>
  41 #include <asm/cacheflush.h>
  42 #include <asm/system_info.h>
  43 #include <asm/system_misc.h>
  44
  45 #include <asm/mach/arch.h>
  46 #include <asm/mach/map.h>
  47
  48 #include <mach/regs-gpio.h>
  49 #include <mach/dma.h>
  50
  51 #include <plat/cpu.h>
  52 #include <plat/devs.h>
  53 #include <plat/cpu-freq.h>
  54 #include <plat/pwm-core.h>
  55
  56 #include "common.h"
  57
  58 /* table of supported CPUs */
  59
  60 static const char name_s3c2410[]  = "S3C2410";
  61 static const char name_s3c2412[]  = "S3C2412";
  62 static const char name_s3c2416[]  = "S3C2416/S3C2450";
  63 static const char name_s3c2440[]  = "S3C2440";
  64 static const char name_s3c2442[]  = "S3C2442";
  65 static const char name_s3c2442b[]  = "S3C2442B";
  66 static const char name_s3c2443[]  = "S3C2443";
  67 static const char name_s3c2410a[] = "S3C2410A";
  68 static const char name_s3c2440a[] = "S3C2440A";
  69
  70 static struct cpu_table cpu_ids[] __initdata = {
  71         {
  72                 .idcode         = 0x32410000,
  73                 .idmask         = 0xffffffff,
  74                 .map_io         = s3c2410_map_io,
  75                 .init_uarts     = s3c2410_init_uarts,
  76                 .init           = s3c2410_init,
  77                 .name           = name_s3c2410
  78         },
  79         {
  80                 .idcode         = 0x32410002,
  81                 .idmask         = 0xffffffff,
  82                 .map_io         = s3c2410_map_io,
  83                 .init_uarts     = s3c2410_init_uarts,
  84                 .init           = s3c2410a_init,
  85                 .name           = name_s3c2410a
  86         },
  87         {
  88                 .idcode         = 0x32440000,
  89                 .idmask         = 0xffffffff,
  90                 .map_io         = s3c2440_map_io,
  91                 .init_uarts     = s3c244x_init_uarts,
  92                 .init           = s3c2440_init,
  93                 .name           = name_s3c2440
  94         },
  95         {
  96                 .idcode         = 0x32440001,
  97                 .idmask         = 0xffffffff,
  98                 .map_io         = s3c2440_map_io,
  99                 .init_uarts     = s3c244x_init_uarts,
 100                 .init           = s3c2440_init,
 101                 .name           = name_s3c2440a
 102         },
 103         {
 104                 .idcode         = 0x32440aaa,
 105                 .idmask         = 0xffffffff,
 106                 .map_io         = s3c2442_map_io,
 107                 .init_uarts     = s3c244x_init_uarts,
 108                 .init           = s3c2442_init,
 109                 .name           = name_s3c2442
 110         },
 111         {
 112                 .idcode         = 0x32440aab,
 113                 .idmask         = 0xffffffff,
 114                 .map_io         = s3c2442_map_io,
 115                 .init_uarts     = s3c244x_init_uarts,
 116                 .init           = s3c2442_init,
 117                 .name           = name_s3c2442b
 118         },
 119         {
 120                 .idcode         = 0x32412001,
 121                 .idmask         = 0xffffffff,
 122                 .map_io         = s3c2412_map_io,
 123                 .init_uarts     = s3c2412_init_uarts,
 124                 .init           = s3c2412_init,
 125                 .name           = name_s3c2412,
 126         },
 127         {                       /* a newer version of the s3c2412 */
 128                 .idcode         = 0x32412003,
 129                 .idmask         = 0xffffffff,
 130                 .map_io         = s3c2412_map_io,
 131                 .init_uarts     = s3c2412_init_uarts,
 132                 .init           = s3c2412_init,
 133                 .name           = name_s3c2412,
 134         },
 135         {                       /* a strange version of the s3c2416 */
 136                 .idcode         = 0x32450003,
 137                 .idmask         = 0xffffffff,
 138                 .map_io         = s3c2416_map_io,
 139                 .init_uarts     = s3c2416_init_uarts,
 140                 .init           = s3c2416_init,
 141                 .name           = name_s3c2416,
 142         },
 143         {
 144                 .idcode         = 0x32443001,
 145                 .idmask         = 0xffffffff,
 146                 .map_io         = s3c2443_map_io,
 147                 .init_uarts     = s3c2443_init_uarts,
 148                 .init           = s3c2443_init,
 149                 .name           = name_s3c2443,
 150         },
 151 };
 152
 153 /* minimal IO mapping */
 154
 155 static struct map_desc s3c_iodesc[] __initdata = {
 156         IODESC_ENT(GPIO),
 157         IODESC_ENT(IRQ),
 158         IODESC_ENT(MEMCTRL),
 159         IODESC_ENT(UART)
 160 };
 161
 162 /* read cpu identificaiton code */
 163
 164 static unsigned long s3c24xx_read_idcode_v5(void)
 165 {
 166 #if defined(CONFIG_CPU_S3C2416)
 167         /* s3c2416 is v5, with S3C24XX_GSTATUS1 instead of S3C2412_GSTATUS1 */
 168
 169         u32 gs = __raw_readl(S3C24XX_GSTATUS1);
 170
 171         /* test for s3c2416 or similar device */
 172         if ((gs >> 16) == 0x3245)
 173                 return gs;
 174 #endif
 175
 176 #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
 177         return __raw_readl(S3C2412_GSTATUS1);
 178 #else
 179         return 1UL;     /* don't look like an 2400 */
 180 #endif
 181 }
 182
 183 static unsigned long s3c24xx_read_idcode_v4(void)
 184 {
 185         return __raw_readl(S3C2410_GSTATUS1);
 186 }
 187
 188 static void s3c24xx_default_idle(void)
 189 {
 190         unsigned long tmp = 0;
 191         int i;
 192
 193         /* idle the system by using the idle mode which will wait for an
 194          * interrupt to happen before restarting the system.
 195          */
 196
 197         /* Warning: going into idle state upsets jtag scanning */
 198
 199         __raw_writel(__raw_readl(S3C2410_CLKCON) | S3C2410_CLKCON_IDLE,
 200                      S3C2410_CLKCON);
 201
 202         /* the samsung port seems to do a loop and then unset idle.. */
 203         for (i = 0; i < 50; i++)
 204                 tmp += __raw_readl(S3C2410_CLKCON); /* ensure loop not optimised out */
 205
 206         /* this bit is not cleared on re-start... */
 207
 208         __raw_writel(__raw_readl(S3C2410_CLKCON) & ~S3C2410_CLKCON_IDLE,
 209                      S3C2410_CLKCON);
 210 }
 211
 212 static struct samsung_pwm_variant s3c24xx_pwm_variant = {
 213         .bits           = 16,
 214         .div_base       = 1,
 215         .has_tint_cstat = false,
 216         .tclk_mask      = (1 << 4),
 217 };
 218
 219 void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
 220 {
 221         arm_pm_idle = s3c24xx_default_idle;
 222
 223         /* initialise the io descriptors we need for initialisation */
 224         iotable_init(mach_desc, size);
 225         iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
 226
 227         if (cpu_architecture() >= CPU_ARCH_ARMv5) {
 228                 samsung_cpu_id = s3c24xx_read_idcode_v5();
 229         } else {
 230                 samsung_cpu_id = s3c24xx_read_idcode_v4();
 231         }
 232
 233         s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 234
 235         samsung_pwm_set_platdata(&s3c24xx_pwm_variant);
 236 }
 237
 238 void __init samsung_set_timer_source(unsigned int event, unsigned int source)
 239 {
 240         s3c24xx_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
 241         s3c24xx_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));
 242 }
 243
 244 void __init samsung_timer_init(void)
 245 {
 246         unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
 247                 IRQ_TIMER0, IRQ_TIMER1, IRQ_TIMER2, IRQ_TIMER3, IRQ_TIMER4,
 248         };
 249
 250         samsung_pwm_clocksource_init(S3C_VA_TIMER,
 251                                         timer_irqs, &s3c24xx_pwm_variant);
 252 }
 253
 254 /* Serial port registrations */
 255
 256 #define S3C2410_PA_UART0      (S3C24XX_PA_UART)
 257 #define S3C2410_PA_UART1      (S3C24XX_PA_UART + 0x4000 )
 258 #define S3C2410_PA_UART2      (S3C24XX_PA_UART + 0x8000 )
 259 #define S3C2443_PA_UART3      (S3C24XX_PA_UART + 0xC000 )
 260
 261 static struct resource s3c2410_uart0_resource[] = {
 262         [0] = DEFINE_RES_MEM(S3C2410_PA_UART0, SZ_16K),
 263         [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX0, \
 264                         IRQ_S3CUART_ERR0 - IRQ_S3CUART_RX0 + 1, \
 265                         NULL, IORESOURCE_IRQ)
 266 };
 267
 268 static struct resource s3c2410_uart1_resource[] = {
 269         [0] = DEFINE_RES_MEM(S3C2410_PA_UART1, SZ_16K),
 270         [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX1, \
 271                         IRQ_S3CUART_ERR1 - IRQ_S3CUART_RX1 + 1, \
 272                         NULL, IORESOURCE_IRQ)
 273 };
 274
 275 static struct resource s3c2410_uart2_resource[] = {
 276         [0] = DEFINE_RES_MEM(S3C2410_PA_UART2, SZ_16K),
 277         [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX2, \
 278                         IRQ_S3CUART_ERR2 - IRQ_S3CUART_RX2 + 1, \
 279                         NULL, IORESOURCE_IRQ)
 280 };
 281
 282 static struct resource s3c2410_uart3_resource[] = {
 283         [0] = DEFINE_RES_MEM(S3C2443_PA_UART3, SZ_16K),
 284         [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX3, \
 285                         IRQ_S3CUART_ERR3 - IRQ_S3CUART_RX3 + 1, \
 286                         NULL, IORESOURCE_IRQ)
 287 };
 288
 289 struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = {
 290         [0] = {
 291                 .resources      = s3c2410_uart0_resource,
 292                 .nr_resources   = ARRAY_SIZE(s3c2410_uart0_resource),
 293         },
 294         [1] = {
 295                 .resources      = s3c2410_uart1_resource,
 296                 .nr_resources   = ARRAY_SIZE(s3c2410_uart1_resource),
 297         },
 298         [2] = {
 299                 .resources      = s3c2410_uart2_resource,
 300                 .nr_resources   = ARRAY_SIZE(s3c2410_uart2_resource),
 301         },
 302         [3] = {
 303                 .resources      = s3c2410_uart3_resource,
 304                 .nr_resources   = ARRAY_SIZE(s3c2410_uart3_resource),
 305         },
 306 };
 307
 308 #define s3c24xx_device_dma_mask (*((u64[]) { DMA_BIT_MASK(32) }))
 309
 310 #if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
 311         defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
 312 static struct resource s3c2410_dma_resource[] = {
 313         [0] = DEFINE_RES_MEM(S3C24XX_PA_DMA, S3C24XX_SZ_DMA),
 314         [1] = DEFINE_RES_IRQ(IRQ_DMA0),
 315         [2] = DEFINE_RES_IRQ(IRQ_DMA1),
 316         [3] = DEFINE_RES_IRQ(IRQ_DMA2),
 317         [4] = DEFINE_RES_IRQ(IRQ_DMA3),
 318 };
 319 #endif
 320
 321 #if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2442)
 322 static struct s3c24xx_dma_channel s3c2410_dma_channels[DMACH_MAX] = {
 323         [DMACH_XD0] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 0), },
 324         [DMACH_XD1] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 1), },
 325         [DMACH_SDI] = { S3C24XX_DMA_APB, false, S3C24XX_DMA_CHANREQ(2, 0) |
 326                                                 S3C24XX_DMA_CHANREQ(2, 2) |
 327                                                 S3C24XX_DMA_CHANREQ(1, 3),
 328         },
 329         [DMACH_SPI0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 1), },
 330         [DMACH_SPI1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 3), },
 331         [DMACH_UART0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 0), },
 332         [DMACH_UART1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 1), },
 333         [DMACH_UART2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 3), },
 334         [DMACH_TIMER] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 0) |
 335                                                  S3C24XX_DMA_CHANREQ(3, 2) |
 336                                                  S3C24XX_DMA_CHANREQ(3, 3),
 337         },
 338         [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 1) |
 339                                                   S3C24XX_DMA_CHANREQ(1, 2),
 340         },
 341         [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 2), },
 342         [DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 0), },
 343         [DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 1), },
 344         [DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 2), },
 345         [DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 3), },
 346 };
 347
 348 static struct s3c24xx_dma_platdata s3c2410_dma_platdata = {
 349         .num_phy_channels = 4,
 350         .channels = s3c2410_dma_channels,
 351         .num_channels = DMACH_MAX,
 352 };
 353
 354 struct platform_device s3c2410_device_dma = {
 355         .name           = "s3c2410-dma",
 356         .id             = 0,
 357         .num_resources  = ARRAY_SIZE(s3c2410_dma_resource),
 358         .resource       = s3c2410_dma_resource,
 359         .dev    = {
 360                 .dma_mask = &s3c24xx_device_dma_mask,
 361                 .coherent_dma_mask = DMA_BIT_MASK(32),
 362                 .platform_data = &s3c2410_dma_platdata,
 363         },
 364 };
 365 #endif
 366
 367 #ifdef CONFIG_CPU_S3C2412
 368 static struct s3c24xx_dma_channel s3c2412_dma_channels[DMACH_MAX] = {
 369         [DMACH_XD0] = { S3C24XX_DMA_AHB, true, 17 },
 370         [DMACH_XD1] = { S3C24XX_DMA_AHB, true, 18 },
 371         [DMACH_SDI] = { S3C24XX_DMA_APB, false, 10 },
 372         [DMACH_SPI0_RX] = { S3C24XX_DMA_APB, true, 1 },
 373         [DMACH_SPI0_TX] = { S3C24XX_DMA_APB, true, 0 },
 374         [DMACH_SPI1_RX] = { S3C24XX_DMA_APB, true, 3 },
 375         [DMACH_SPI1_TX] = { S3C24XX_DMA_APB, true, 2 },
 376         [DMACH_UART0] = { S3C24XX_DMA_APB, true, 19 },
 377         [DMACH_UART1] = { S3C24XX_DMA_APB, true, 21 },
 378         [DMACH_UART2] = { S3C24XX_DMA_APB, true, 23 },
 379         [DMACH_UART0_SRC2] = { S3C24XX_DMA_APB, true, 20 },
 380         [DMACH_UART1_SRC2] = { S3C24XX_DMA_APB, true, 22 },
 381         [DMACH_UART2_SRC2] = { S3C24XX_DMA_APB, true, 24 },
 382         [DMACH_TIMER] = { S3C24XX_DMA_APB, true, 9 },
 383         [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, 5 },
 384         [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, 4 },
 385         [DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, 13 },
 386         [DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, 14 },
 387         [DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, 15 },
 388         [DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, 16 },
 389 };
 390
 391 static struct s3c24xx_dma_platdata s3c2412_dma_platdata = {
 392         .num_phy_channels = 4,
 393         .channels = s3c2412_dma_channels,
 394         .num_channels = DMACH_MAX,
 395 };
 396
 397 struct platform_device s3c2412_device_dma = {
 398         .name           = "s3c2412-dma",
 399         .id             = 0,
 400         .num_resources  = ARRAY_SIZE(s3c2410_dma_resource),
 401         .resource       = s3c2410_dma_resource,
 402         .dev    = {
 403                 .dma_mask = &s3c24xx_device_dma_mask,
 404                 .coherent_dma_mask = DMA_BIT_MASK(32),
 405                 .platform_data = &s3c2412_dma_platdata,
 406         },
 407 };
 408 #endif
 409
 410 #if defined(CONFIG_CPU_S3C2440)
 411 static struct s3c24xx_dma_channel s3c2440_dma_channels[DMACH_MAX] = {
 412         [DMACH_XD0] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 0), },
 413         [DMACH_XD1] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 1), },
 414         [DMACH_SDI] = { S3C24XX_DMA_APB, false, S3C24XX_DMA_CHANREQ(2, 0) |
 415                                                 S3C24XX_DMA_CHANREQ(6, 1) |
 416                                                 S3C24XX_DMA_CHANREQ(2, 2) |
 417                                                 S3C24XX_DMA_CHANREQ(1, 3),
 418         },
 419         [DMACH_SPI0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 1), },
 420         [DMACH_SPI1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 3), },
 421         [DMACH_UART0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 0), },
 422         [DMACH_UART1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 1), },
 423         [DMACH_UART2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 3), },
 424         [DMACH_TIMER] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 0) |
 425                                                  S3C24XX_DMA_CHANREQ(3, 2) |
 426                                                  S3C24XX_DMA_CHANREQ(3, 3),
 427         },
 428         [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 1) |
 429                                                   S3C24XX_DMA_CHANREQ(1, 2),
 430         },
 431         [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(5, 0) |
 432                                                    S3C24XX_DMA_CHANREQ(0, 2),
 433         },
 434         [DMACH_PCM_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(6, 0) |
 435                                                   S3C24XX_DMA_CHANREQ(5, 2),
 436         },
 437         [DMACH_PCM_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(5, 1) |
 438                                                   S3C24XX_DMA_CHANREQ(6, 3),
 439         },
 440         [DMACH_MIC_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(6, 2) |
 441                                                   S3C24XX_DMA_CHANREQ(5, 3),
 442         },
 443         [DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 0), },
 444         [DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 1), },
 445         [DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 2), },
 446         [DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 3), },
 447 };
 448
 449 static const struct dma_slave_map s3c2440_dma_slave_map[] = {
 450         /* TODO: DMACH_XD0 */
 451         /* TODO: DMACH_XD1 */
 452         { "s3c2440-sdi", "rx-tx", (void *)DMACH_SDI },
 453         { "s3c2410-spi.0", "rx", (void *)DMACH_SPI0 },
 454         { "s3c2410-spi.0", "tx", (void *)DMACH_SPI0 },
 455         { "s3c2410-spi.1", "rx", (void *)DMACH_SPI1 },
 456         { "s3c2410-spi.1", "tx", (void *)DMACH_SPI1 },
 457         { "s3c2440-uart.0", "rx", (void *)DMACH_UART0 },
 458         { "s3c2440-uart.0", "tx", (void *)DMACH_UART0 },
 459         { "s3c2440-uart.1", "rx", (void *)DMACH_UART1 },
 460         { "s3c2440-uart.1", "tx", (void *)DMACH_UART1 },
 461         { "s3c2440-uart.2", "rx", (void *)DMACH_UART2 },
 462         { "s3c2440-uart.2", "tx", (void *)DMACH_UART2 },
 463         { "s3c2440-uart.3", "rx", (void *)DMACH_UART3 },
 464         { "s3c2440-uart.3", "tx", (void *)DMACH_UART3 },
 465         /* TODO: DMACH_TIMER */
 466         { "s3c24xx-iis", "rx", (void *)DMACH_I2S_IN },
 467         { "s3c24xx-iis", "tx", (void *)DMACH_I2S_OUT },
 468         { "samsung-ac97", "rx", (void *)DMACH_PCM_IN },
 469         { "samsung-ac97", "tx", (void *)DMACH_PCM_OUT },
 470         { "samsung-ac97", "rx", (void *)DMACH_MIC_IN },
 471         { "s3c-hsudc", "rx0", (void *)DMACH_USB_EP1 },
 472         { "s3c-hsudc", "rx1", (void *)DMACH_USB_EP2 },
 473         { "s3c-hsudc", "rx2", (void *)DMACH_USB_EP3 },
 474         { "s3c-hsudc", "rx3", (void *)DMACH_USB_EP4 },
 475         { "s3c-hsudc", "tx0", (void *)DMACH_USB_EP1 },
 476         { "s3c-hsudc", "tx1", (void *)DMACH_USB_EP2 },
 477         { "s3c-hsudc", "tx2", (void *)DMACH_USB_EP3 },
 478         { "s3c-hsudc", "tx3", (void *)DMACH_USB_EP4 }
 479 };
 480
 481 static struct s3c24xx_dma_platdata s3c2440_dma_platdata = {
 482         .num_phy_channels = 4,
 483         .channels = s3c2440_dma_channels,
 484         .num_channels = DMACH_MAX,
 485         .slave_map = s3c2440_dma_slave_map,
 486         .slavecnt = ARRAY_SIZE(s3c2440_dma_slave_map),
 487 };
 488
 489 struct platform_device s3c2440_device_dma = {
 490         .name           = "s3c2410-dma",
 491         .id             = 0,
 492         .num_resources  = ARRAY_SIZE(s3c2410_dma_resource),
 493         .resource       = s3c2410_dma_resource,
 494         .dev    = {
 495                 .dma_mask = &s3c24xx_device_dma_mask,
 496                 .coherent_dma_mask = DMA_BIT_MASK(32),
 497                 .platform_data = &s3c2440_dma_platdata,
 498         },
 499 };
 500 #endif
 501
 502 #if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416)
 503 static struct resource s3c2443_dma_resource[] = {
 504         [0] = DEFINE_RES_MEM(S3C24XX_PA_DMA, S3C24XX_SZ_DMA),
 505         [1] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA0),
 506         [2] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA1),
 507         [3] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA2),
 508         [4] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA3),
 509         [5] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA4),
 510         [6] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA5),
 511 };
 512
 513 static struct s3c24xx_dma_channel s3c2443_dma_channels[DMACH_MAX] = {
 514         [DMACH_XD0] = { S3C24XX_DMA_AHB, true, 17 },
 515         [DMACH_XD1] = { S3C24XX_DMA_AHB, true, 18 },
 516         [DMACH_SDI] = { S3C24XX_DMA_APB, false, 10 },
 517         [DMACH_SPI0_RX] = { S3C24XX_DMA_APB, true, 1 },
 518         [DMACH_SPI0_TX] = { S3C24XX_DMA_APB, true, 0 },
 519         [DMACH_SPI1_RX] = { S3C24XX_DMA_APB, true, 3 },
 520         [DMACH_SPI1_TX] = { S3C24XX_DMA_APB, true, 2 },
 521         [DMACH_UART0] = { S3C24XX_DMA_APB, true, 19 },
 522         [DMACH_UART1] = { S3C24XX_DMA_APB, true, 21 },
 523         [DMACH_UART2] = { S3C24XX_DMA_APB, true, 23 },
 524         [DMACH_UART3] = { S3C24XX_DMA_APB, true, 25 },
 525         [DMACH_UART0_SRC2] = { S3C24XX_DMA_APB, true, 20 },
 526         [DMACH_UART1_SRC2] = { S3C24XX_DMA_APB, true, 22 },
 527         [DMACH_UART2_SRC2] = { S3C24XX_DMA_APB, true, 24 },
 528         [DMACH_UART3_SRC2] = { S3C24XX_DMA_APB, true, 26 },
 529         [DMACH_TIMER] = { S3C24XX_DMA_APB, true, 9 },
 530         [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, 5 },
 531         [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, 4 },
 532         [DMACH_PCM_IN] = { S3C24XX_DMA_APB, true, 28 },
 533         [DMACH_PCM_OUT] = { S3C24XX_DMA_APB, true, 27 },
 534         [DMACH_MIC_IN] = { S3C24XX_DMA_APB, true, 29 },
 535 };
 536
 537 static struct s3c24xx_dma_platdata s3c2443_dma_platdata = {
 538         .num_phy_channels = 6,
 539         .channels = s3c2443_dma_channels,
 540         .num_channels = DMACH_MAX,
 541 };
 542
 543 struct platform_device s3c2443_device_dma = {
 544         .name           = "s3c2443-dma",
 545         .id             = 0,
 546         .num_resources  = ARRAY_SIZE(s3c2443_dma_resource),
 547         .resource       = s3c2443_dma_resource,
 548         .dev    = {
 549                 .dma_mask = &s3c24xx_device_dma_mask,
 550                 .coherent_dma_mask = DMA_BIT_MASK(32),
 551                 .platform_data = &s3c2443_dma_platdata,
 552         },
 553 };
 554 #endif
 555
 556 #if defined(CONFIG_COMMON_CLK) && defined(CONFIG_CPU_S3C2410)
 557 void __init s3c2410_init_clocks(int xtal)
 558 {
 559         s3c2410_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR);
 560 }
 561 #endif
 562
 563 #ifdef CONFIG_CPU_S3C2412
 564 void __init s3c2412_init_clocks(int xtal)
 565 {
 566         s3c2412_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR);
 567 }
 568 #endif
 569
 570 #ifdef CONFIG_CPU_S3C2416
 571 void __init s3c2416_init_clocks(int xtal)
 572 {
 573         s3c2443_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR);
 574 }
 575 #endif
 576
 577 #if defined(CONFIG_COMMON_CLK) && defined(CONFIG_CPU_S3C2440)
 578 void __init s3c2440_init_clocks(int xtal)
 579 {
 580         s3c2410_common_clk_init(NULL, xtal, 1, S3C24XX_VA_CLKPWR);
 581 }
 582 #endif
 583
 584 #if defined(CONFIG_COMMON_CLK) && defined(CONFIG_CPU_S3C2442)
 585 void __init s3c2442_init_clocks(int xtal)
 586 {
 587         s3c2410_common_clk_init(NULL, xtal, 2, S3C24XX_VA_CLKPWR);
 588 }
 589 #endif
 590
 591 #ifdef CONFIG_CPU_S3C2443
 592 void __init s3c2443_init_clocks(int xtal)
 593 {
 594         s3c2443_common_clk_init(NULL, xtal, 1, S3C24XX_VA_CLKPWR);
 595 }
 596 #endif
 597
 598 #if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2440) || \
 599         defined(CONFIG_CPU_S3C2442)
 600 static struct resource s3c2410_dclk_resource[] = {
 601         [0] = DEFINE_RES_MEM(0x56000084, 0x4),
 602 };
 603
 604 struct platform_device s3c2410_device_dclk = {
 605         .name           = "s3c2410-dclk",
 606         .id             = 0,
 607         .num_resources  = ARRAY_SIZE(s3c2410_dclk_resource),
 608         .resource       = s3c2410_dclk_resource,
 609 };
 610 #endif