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Linux 4.9.199
[linux/fpc-iii.git] / arch / s390 / net / bpf_jit_comp.c
blob9b15a1dc662878b64d56d54cb4eb0de737711594
1 /*
2 * BPF Jit compiler for s390.
3 *
4 * Minimum build requirements:
5 *
6 * - HAVE_MARCH_Z196_FEATURES: laal, laalg
7 * - HAVE_MARCH_Z10_FEATURES: msfi, cgrj, clgrj
8 * - HAVE_MARCH_Z9_109_FEATURES: alfi, llilf, clfi, oilf, nilf
9 * - PACK_STACK
10 * - 64BIT
11 *
12 * Copyright IBM Corp. 2012,2015
13 *
14 * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
15 * Michael Holzheu <holzheu@linux.vnet.ibm.com>
16 */
17
18 #define KMSG_COMPONENT "bpf_jit"
19 #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
20
21 #include <linux/netdevice.h>
22 #include <linux/filter.h>
23 #include <linux/init.h>
24 #include <linux/bpf.h>
25 #include <asm/cacheflush.h>
26 #include <asm/dis.h>
27 #include <asm/facility.h>
28 #include <asm/nospec-branch.h>
29 #include "bpf_jit.h"
30
31 struct bpf_jit {
32 u32 seen; /* Flags to remember seen eBPF instructions */
33 u32 seen_reg[16]; /* Array to remember which registers are used */
34 u32 *addrs; /* Array with relative instruction addresses */
35 u8 *prg_buf; /* Start of program */
36 int size; /* Size of program and literal pool */
37 int size_prg; /* Size of program */
38 int prg; /* Current position in program */
39 int lit_start; /* Start of literal pool */
40 int lit; /* Current position in literal pool */
41 int base_ip; /* Base address for literal pool */
42 int ret0_ip; /* Address of return 0 */
43 int exit_ip; /* Address of exit */
44 int r1_thunk_ip; /* Address of expoline thunk for 'br %r1' */
45 int r14_thunk_ip; /* Address of expoline thunk for 'br %r14' */
46 int tail_call_start; /* Tail call start offset */
47 int labels[1]; /* Labels for local jumps */
48 };
49
50 #define BPF_SIZE_MAX 0xffff /* Max size for program (16 bit branches) */
51
52 #define SEEN_SKB 1 /* skb access */
53 #define SEEN_MEM 2 /* use mem[] for temporary storage */
54 #define SEEN_RET0 4 /* ret0_ip points to a valid return 0 */
55 #define SEEN_LITERAL 8 /* code uses literals */
56 #define SEEN_FUNC 16 /* calls C functions */
57 #define SEEN_TAIL_CALL 32 /* code uses tail calls */
58 #define SEEN_SKB_CHANGE 64 /* code changes skb data */
59 #define SEEN_REG_AX 128 /* code uses constant blinding */
60 #define SEEN_STACK (SEEN_FUNC | SEEN_MEM | SEEN_SKB)
61
62 /*
63 * s390 registers
64 */
65 #define REG_W0 (MAX_BPF_JIT_REG + 0) /* Work register 1 (even) */
66 #define REG_W1 (MAX_BPF_JIT_REG + 1) /* Work register 2 (odd) */
67 #define REG_SKB_DATA (MAX_BPF_JIT_REG + 2) /* SKB data register */
68 #define REG_L (MAX_BPF_JIT_REG + 3) /* Literal pool register */
69 #define REG_15 (MAX_BPF_JIT_REG + 4) /* Register 15 */
70 #define REG_0 REG_W0 /* Register 0 */
71 #define REG_1 REG_W1 /* Register 1 */
72 #define REG_2 BPF_REG_1 /* Register 2 */
73 #define REG_14 BPF_REG_0 /* Register 14 */
74
75 /*
76 * Mapping of BPF registers to s390 registers
77 */
78 static const int reg2hex[] = {
79 /* Return code */
80 [BPF_REG_0] = 14,
81 /* Function parameters */
82 [BPF_REG_1] = 2,
83 [BPF_REG_2] = 3,
84 [BPF_REG_3] = 4,
85 [BPF_REG_4] = 5,
86 [BPF_REG_5] = 6,
87 /* Call saved registers */
88 [BPF_REG_6] = 7,
89 [BPF_REG_7] = 8,
90 [BPF_REG_8] = 9,
91 [BPF_REG_9] = 10,
92 /* BPF stack pointer */
93 [BPF_REG_FP] = 13,
94 /* Register for blinding (shared with REG_SKB_DATA) */
95 [BPF_REG_AX] = 12,
96 /* SKB data pointer */
97 [REG_SKB_DATA] = 12,
98 /* Work registers for s390x backend */
99 [REG_W0] = 0,
100 [REG_W1] = 1,
101 [REG_L] = 11,
102 [REG_15] = 15,
103 };
104
105 static inline u32 reg(u32 dst_reg, u32 src_reg)
106 {
107 return reg2hex[dst_reg] << 4 | reg2hex[src_reg];
108 }
109
110 static inline u32 reg_high(u32 reg)
111 {
112 return reg2hex[reg] << 4;
113 }
114
115 static inline void reg_set_seen(struct bpf_jit *jit, u32 b1)
116 {
117 u32 r1 = reg2hex[b1];
118
119 if (!jit->seen_reg[r1] && r1 >= 6 && r1 <= 15)
120 jit->seen_reg[r1] = 1;
121 }
122
123 #define REG_SET_SEEN(b1) \
124 ({ \
125 reg_set_seen(jit, b1); \
126 })
127
128 #define REG_SEEN(b1) jit->seen_reg[reg2hex[(b1)]]
129
130 /*
131 * EMIT macros for code generation
132 */
133
134 #define _EMIT2(op) \
135 ({ \
136 if (jit->prg_buf) \
137 *(u16 *) (jit->prg_buf + jit->prg) = op; \
138 jit->prg += 2; \
139 })
140
141 #define EMIT2(op, b1, b2) \
142 ({ \
143 _EMIT2(op | reg(b1, b2)); \
144 REG_SET_SEEN(b1); \
145 REG_SET_SEEN(b2); \
146 })
147
148 #define _EMIT4(op) \
149 ({ \
150 if (jit->prg_buf) \
151 *(u32 *) (jit->prg_buf + jit->prg) = op; \
152 jit->prg += 4; \
153 })
154
155 #define EMIT4(op, b1, b2) \
156 ({ \
157 _EMIT4(op | reg(b1, b2)); \
158 REG_SET_SEEN(b1); \
159 REG_SET_SEEN(b2); \
160 })
161
162 #define EMIT4_RRF(op, b1, b2, b3) \
163 ({ \
164 _EMIT4(op | reg_high(b3) << 8 | reg(b1, b2)); \
165 REG_SET_SEEN(b1); \
166 REG_SET_SEEN(b2); \
167 REG_SET_SEEN(b3); \
168 })
169
170 #define _EMIT4_DISP(op, disp) \
171 ({ \
172 unsigned int __disp = (disp) & 0xfff; \
173 _EMIT4(op | __disp); \
174 })
175
176 #define EMIT4_DISP(op, b1, b2, disp) \
177 ({ \
178 _EMIT4_DISP(op | reg_high(b1) << 16 | \
179 reg_high(b2) << 8, disp); \
180 REG_SET_SEEN(b1); \
181 REG_SET_SEEN(b2); \
182 })
183
184 #define EMIT4_IMM(op, b1, imm) \
185 ({ \
186 unsigned int __imm = (imm) & 0xffff; \
187 _EMIT4(op | reg_high(b1) << 16 | __imm); \
188 REG_SET_SEEN(b1); \
189 })
190
191 #define EMIT4_PCREL(op, pcrel) \
192 ({ \
193 long __pcrel = ((pcrel) >> 1) & 0xffff; \
194 _EMIT4(op | __pcrel); \
195 })
196
197 #define _EMIT6(op1, op2) \
198 ({ \
199 if (jit->prg_buf) { \
200 *(u32 *) (jit->prg_buf + jit->prg) = op1; \
201 *(u16 *) (jit->prg_buf + jit->prg + 4) = op2; \
202 } \
203 jit->prg += 6; \
204 })
205
206 #define _EMIT6_DISP(op1, op2, disp) \
207 ({ \
208 unsigned int __disp = (disp) & 0xfff; \
209 _EMIT6(op1 | __disp, op2); \
210 })
211
212 #define _EMIT6_DISP_LH(op1, op2, disp) \
213 ({ \
214 u32 _disp = (u32) disp; \
215 unsigned int __disp_h = _disp & 0xff000; \
216 unsigned int __disp_l = _disp & 0x00fff; \
217 _EMIT6(op1 | __disp_l, op2 | __disp_h >> 4); \
218 })
219
220 #define EMIT6_DISP_LH(op1, op2, b1, b2, b3, disp) \
221 ({ \
222 _EMIT6_DISP_LH(op1 | reg(b1, b2) << 16 | \
223 reg_high(b3) << 8, op2, disp); \
224 REG_SET_SEEN(b1); \
225 REG_SET_SEEN(b2); \
226 REG_SET_SEEN(b3); \
227 })
228
229 #define EMIT6_PCREL_LABEL(op1, op2, b1, b2, label, mask) \
230 ({ \
231 int rel = (jit->labels[label] - jit->prg) >> 1; \
232 _EMIT6(op1 | reg(b1, b2) << 16 | (rel & 0xffff), \
233 op2 | mask << 12); \
234 REG_SET_SEEN(b1); \
235 REG_SET_SEEN(b2); \
236 })
237
238 #define EMIT6_PCREL_IMM_LABEL(op1, op2, b1, imm, label, mask) \
239 ({ \
240 int rel = (jit->labels[label] - jit->prg) >> 1; \
241 _EMIT6(op1 | (reg_high(b1) | mask) << 16 | \
242 (rel & 0xffff), op2 | (imm & 0xff) << 8); \
243 REG_SET_SEEN(b1); \
244 BUILD_BUG_ON(((unsigned long) imm) > 0xff); \
245 })
246
247 #define EMIT6_PCREL(op1, op2, b1, b2, i, off, mask) \
248 ({ \
249 /* Branch instruction needs 6 bytes */ \
250 int rel = (addrs[i + off + 1] - (addrs[i + 1] - 6)) / 2;\
251 _EMIT6(op1 | reg(b1, b2) << 16 | (rel & 0xffff), op2 | mask); \
252 REG_SET_SEEN(b1); \
253 REG_SET_SEEN(b2); \
254 })
255
256 #define EMIT6_PCREL_RILB(op, b, target) \
257 ({ \
258 int rel = (target - jit->prg) / 2; \
259 _EMIT6(op | reg_high(b) << 16 | rel >> 16, rel & 0xffff); \
260 REG_SET_SEEN(b); \
261 })
262
263 #define EMIT6_PCREL_RIL(op, target) \
264 ({ \
265 int rel = (target - jit->prg) / 2; \
266 _EMIT6(op | rel >> 16, rel & 0xffff); \
267 })
268
269 #define _EMIT6_IMM(op, imm) \
270 ({ \
271 unsigned int __imm = (imm); \
272 _EMIT6(op | (__imm >> 16), __imm & 0xffff); \
273 })
274
275 #define EMIT6_IMM(op, b1, imm) \
276 ({ \
277 _EMIT6_IMM(op | reg_high(b1) << 16, imm); \
278 REG_SET_SEEN(b1); \
279 })
280
281 #define EMIT_CONST_U32(val) \
282 ({ \
283 unsigned int ret; \
284 ret = jit->lit - jit->base_ip; \
285 jit->seen |= SEEN_LITERAL; \
286 if (jit->prg_buf) \
287 *(u32 *) (jit->prg_buf + jit->lit) = (u32) val; \
288 jit->lit += 4; \
289 ret; \
290 })
291
292 #define EMIT_CONST_U64(val) \
293 ({ \
294 unsigned int ret; \
295 ret = jit->lit - jit->base_ip; \
296 jit->seen |= SEEN_LITERAL; \
297 if (jit->prg_buf) \
298 *(u64 *) (jit->prg_buf + jit->lit) = (u64) val; \
299 jit->lit += 8; \
300 ret; \
301 })
302
303 #define EMIT_ZERO(b1) \
304 ({ \
305 /* llgfr %dst,%dst (zero extend to 64 bit) */ \
306 EMIT4(0xb9160000, b1, b1); \
307 REG_SET_SEEN(b1); \
308 })
309
310 /*
311 * Fill whole space with illegal instructions
312 */
313 static void jit_fill_hole(void *area, unsigned int size)
314 {
315 memset(area, 0, size);
316 }
317
318 /*
319 * Save registers from "rs" (register start) to "re" (register end) on stack
320 */
321 static void save_regs(struct bpf_jit *jit, u32 rs, u32 re)
322 {
323 u32 off = STK_OFF_R6 + (rs - 6) * 8;
324
325 if (rs == re)
326 /* stg %rs,off(%r15) */
327 _EMIT6(0xe300f000 | rs << 20 | off, 0x0024);
328 else
329 /* stmg %rs,%re,off(%r15) */
330 _EMIT6_DISP(0xeb00f000 | rs << 20 | re << 16, 0x0024, off);
331 }
332
333 /*
334 * Restore registers from "rs" (register start) to "re" (register end) on stack
335 */
336 static void restore_regs(struct bpf_jit *jit, u32 rs, u32 re)
337 {
338 u32 off = STK_OFF_R6 + (rs - 6) * 8;
339
340 if (jit->seen & SEEN_STACK)
341 off += STK_OFF;
342
343 if (rs == re)
344 /* lg %rs,off(%r15) */
345 _EMIT6(0xe300f000 | rs << 20 | off, 0x0004);
346 else
347 /* lmg %rs,%re,off(%r15) */
348 _EMIT6_DISP(0xeb00f000 | rs << 20 | re << 16, 0x0004, off);
349 }
350
351 /*
352 * Return first seen register (from start)
353 */
354 static int get_start(struct bpf_jit *jit, int start)
355 {
356 int i;
357
358 for (i = start; i <= 15; i++) {
359 if (jit->seen_reg[i])
360 return i;
361 }
362 return 0;
363 }
364
365 /*
366 * Return last seen register (from start) (gap >= 2)
367 */
368 static int get_end(struct bpf_jit *jit, int start)
369 {
370 int i;
371
372 for (i = start; i < 15; i++) {
373 if (!jit->seen_reg[i] && !jit->seen_reg[i + 1])
374 return i - 1;
375 }
376 return jit->seen_reg[15] ? 15 : 14;
377 }
378
379 #define REGS_SAVE 1
380 #define REGS_RESTORE 0
381 /*
382 * Save and restore clobbered registers (6-15) on stack.
383 * We save/restore registers in chunks with gap >= 2 registers.
384 */
385 static void save_restore_regs(struct bpf_jit *jit, int op)
386 {
387
388 int re = 6, rs;
389
390 do {
391 rs = get_start(jit, re);
392 if (!rs)
393 break;
394 re = get_end(jit, rs + 1);
395 if (op == REGS_SAVE)
396 save_regs(jit, rs, re);
397 else
398 restore_regs(jit, rs, re);
399 re++;
400 } while (re <= 15);
401 }
402
403 /*
404 * For SKB access %b1 contains the SKB pointer. For "bpf_jit.S"
405 * we store the SKB header length on the stack and the SKB data
406 * pointer in REG_SKB_DATA if BPF_REG_AX is not used.
407 */
408 static void emit_load_skb_data_hlen(struct bpf_jit *jit)
409 {
410 /* Header length: llgf %w1,<len>(%b1) */
411 EMIT6_DISP_LH(0xe3000000, 0x0016, REG_W1, REG_0, BPF_REG_1,
412 offsetof(struct sk_buff, len));
413 /* s %w1,<data_len>(%b1) */
414 EMIT4_DISP(0x5b000000, REG_W1, BPF_REG_1,
415 offsetof(struct sk_buff, data_len));
416 /* stg %w1,ST_OFF_HLEN(%r0,%r15) */
417 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W1, REG_0, REG_15, STK_OFF_HLEN);
418 if (!(jit->seen & SEEN_REG_AX))
419 /* lg %skb_data,data_off(%b1) */
420 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_SKB_DATA, REG_0,
421 BPF_REG_1, offsetof(struct sk_buff, data));
422 }
423
424 /*
425 * Emit function prologue
426 *
427 * Save registers and create stack frame if necessary.
428 * See stack frame layout desription in "bpf_jit.h"!
429 */
430 static void bpf_jit_prologue(struct bpf_jit *jit)
431 {
432 if (jit->seen & SEEN_TAIL_CALL) {
433 /* xc STK_OFF_TCCNT(4,%r15),STK_OFF_TCCNT(%r15) */
434 _EMIT6(0xd703f000 | STK_OFF_TCCNT, 0xf000 | STK_OFF_TCCNT);
435 } else {
436 /* j tail_call_start: NOP if no tail calls are used */
437 EMIT4_PCREL(0xa7f40000, 6);
438 _EMIT2(0);
439 }
440 /* Tail calls have to skip above initialization */
441 jit->tail_call_start = jit->prg;
442 /* Save registers */
443 save_restore_regs(jit, REGS_SAVE);
444 /* Setup literal pool */
445 if (jit->seen & SEEN_LITERAL) {
446 /* basr %r13,0 */
447 EMIT2(0x0d00, REG_L, REG_0);
448 jit->base_ip = jit->prg;
449 }
450 /* Setup stack and backchain */
451 if (jit->seen & SEEN_STACK) {
452 if (jit->seen & SEEN_FUNC)
453 /* lgr %w1,%r15 (backchain) */
454 EMIT4(0xb9040000, REG_W1, REG_15);
455 /* la %bfp,STK_160_UNUSED(%r15) (BPF frame pointer) */
456 EMIT4_DISP(0x41000000, BPF_REG_FP, REG_15, STK_160_UNUSED);
457 /* aghi %r15,-STK_OFF */
458 EMIT4_IMM(0xa70b0000, REG_15, -STK_OFF);
459 if (jit->seen & SEEN_FUNC)
460 /* stg %w1,152(%r15) (backchain) */
461 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W1, REG_0,
462 REG_15, 152);
463 }
464 if (jit->seen & SEEN_SKB)
465 emit_load_skb_data_hlen(jit);
466 if (jit->seen & SEEN_SKB_CHANGE)
467 /* stg %b1,ST_OFF_SKBP(%r0,%r15) */
468 EMIT6_DISP_LH(0xe3000000, 0x0024, BPF_REG_1, REG_0, REG_15,
469 STK_OFF_SKBP);
470 }
471
472 /*
473 * Function epilogue
474 */
475 static void bpf_jit_epilogue(struct bpf_jit *jit)
476 {
477 /* Return 0 */
478 if (jit->seen & SEEN_RET0) {
479 jit->ret0_ip = jit->prg;
480 /* lghi %b0,0 */
481 EMIT4_IMM(0xa7090000, BPF_REG_0, 0);
482 }
483 jit->exit_ip = jit->prg;
484 /* Load exit code: lgr %r2,%b0 */
485 EMIT4(0xb9040000, REG_2, BPF_REG_0);
486 /* Restore registers */
487 save_restore_regs(jit, REGS_RESTORE);
488 if (IS_ENABLED(CC_USING_EXPOLINE) && !nospec_disable) {
489 jit->r14_thunk_ip = jit->prg;
490 /* Generate __s390_indirect_jump_r14 thunk */
491 if (test_facility(35)) {
492 /* exrl %r0,.+10 */
493 EMIT6_PCREL_RIL(0xc6000000, jit->prg + 10);
494 } else {
495 /* larl %r1,.+14 */
496 EMIT6_PCREL_RILB(0xc0000000, REG_1, jit->prg + 14);
497 /* ex 0,0(%r1) */
498 EMIT4_DISP(0x44000000, REG_0, REG_1, 0);
499 }
500 /* j . */
501 EMIT4_PCREL(0xa7f40000, 0);
502 }
503 /* br %r14 */
504 _EMIT2(0x07fe);
505
506 if (IS_ENABLED(CC_USING_EXPOLINE) && !nospec_disable &&
507 (jit->seen & SEEN_FUNC)) {
508 jit->r1_thunk_ip = jit->prg;
509 /* Generate __s390_indirect_jump_r1 thunk */
510 if (test_facility(35)) {
511 /* exrl %r0,.+10 */
512 EMIT6_PCREL_RIL(0xc6000000, jit->prg + 10);
513 /* j . */
514 EMIT4_PCREL(0xa7f40000, 0);
515 /* br %r1 */
516 _EMIT2(0x07f1);
517 } else {
518 /* ex 0,S390_lowcore.br_r1_tampoline */
519 EMIT4_DISP(0x44000000, REG_0, REG_0,
520 offsetof(struct lowcore, br_r1_trampoline));
521 /* j . */
522 EMIT4_PCREL(0xa7f40000, 0);
523 }
524 }
525 }
526
527 /*
528 * Compile one eBPF instruction into s390x code
529 *
530 * NOTE: Use noinline because for gcov (-fprofile-arcs) gcc allocates a lot of
531 * stack space for the large switch statement.
532 */
533 static noinline int bpf_jit_insn(struct bpf_jit *jit, struct bpf_prog *fp, int i)
534 {
535 struct bpf_insn *insn = &fp->insnsi[i];
536 int jmp_off, last, insn_count = 1;
537 unsigned int func_addr, mask;
538 u32 dst_reg = insn->dst_reg;
539 u32 src_reg = insn->src_reg;
540 u32 *addrs = jit->addrs;
541 s32 imm = insn->imm;
542 s16 off = insn->off;
543
544 if (dst_reg == BPF_REG_AX || src_reg == BPF_REG_AX)
545 jit->seen |= SEEN_REG_AX;
546 switch (insn->code) {
547 /*
548 * BPF_MOV
549 */
550 case BPF_ALU | BPF_MOV | BPF_X: /* dst = (u32) src */
551 /* llgfr %dst,%src */
552 EMIT4(0xb9160000, dst_reg, src_reg);
553 break;
554 case BPF_ALU64 | BPF_MOV | BPF_X: /* dst = src */
555 /* lgr %dst,%src */
556 EMIT4(0xb9040000, dst_reg, src_reg);
557 break;
558 case BPF_ALU | BPF_MOV | BPF_K: /* dst = (u32) imm */
559 /* llilf %dst,imm */
560 EMIT6_IMM(0xc00f0000, dst_reg, imm);
561 break;
562 case BPF_ALU64 | BPF_MOV | BPF_K: /* dst = imm */
563 /* lgfi %dst,imm */
564 EMIT6_IMM(0xc0010000, dst_reg, imm);
565 break;
566 /*
567 * BPF_LD 64
568 */
569 case BPF_LD | BPF_IMM | BPF_DW: /* dst = (u64) imm */
570 {
571 /* 16 byte instruction that uses two 'struct bpf_insn' */
572 u64 imm64;
573
574 imm64 = (u64)(u32) insn[0].imm | ((u64)(u32) insn[1].imm) << 32;
575 /* lg %dst,<d(imm)>(%l) */
576 EMIT6_DISP_LH(0xe3000000, 0x0004, dst_reg, REG_0, REG_L,
577 EMIT_CONST_U64(imm64));
578 insn_count = 2;
579 break;
580 }
581 /*
582 * BPF_ADD
583 */
584 case BPF_ALU | BPF_ADD | BPF_X: /* dst = (u32) dst + (u32) src */
585 /* ar %dst,%src */
586 EMIT2(0x1a00, dst_reg, src_reg);
587 EMIT_ZERO(dst_reg);
588 break;
589 case BPF_ALU64 | BPF_ADD | BPF_X: /* dst = dst + src */
590 /* agr %dst,%src */
591 EMIT4(0xb9080000, dst_reg, src_reg);
592 break;
593 case BPF_ALU | BPF_ADD | BPF_K: /* dst = (u32) dst + (u32) imm */
594 if (!imm)
595 break;
596 /* alfi %dst,imm */
597 EMIT6_IMM(0xc20b0000, dst_reg, imm);
598 EMIT_ZERO(dst_reg);
599 break;
600 case BPF_ALU64 | BPF_ADD | BPF_K: /* dst = dst + imm */
601 if (!imm)
602 break;
603 /* agfi %dst,imm */
604 EMIT6_IMM(0xc2080000, dst_reg, imm);
605 break;
606 /*
607 * BPF_SUB
608 */
609 case BPF_ALU | BPF_SUB | BPF_X: /* dst = (u32) dst - (u32) src */
610 /* sr %dst,%src */
611 EMIT2(0x1b00, dst_reg, src_reg);
612 EMIT_ZERO(dst_reg);
613 break;
614 case BPF_ALU64 | BPF_SUB | BPF_X: /* dst = dst - src */
615 /* sgr %dst,%src */
616 EMIT4(0xb9090000, dst_reg, src_reg);
617 break;
618 case BPF_ALU | BPF_SUB | BPF_K: /* dst = (u32) dst - (u32) imm */
619 if (!imm)
620 break;
621 /* alfi %dst,-imm */
622 EMIT6_IMM(0xc20b0000, dst_reg, -imm);
623 EMIT_ZERO(dst_reg);
624 break;
625 case BPF_ALU64 | BPF_SUB | BPF_K: /* dst = dst - imm */
626 if (!imm)
627 break;
628 /* agfi %dst,-imm */
629 EMIT6_IMM(0xc2080000, dst_reg, -imm);
630 break;
631 /*
632 * BPF_MUL
633 */
634 case BPF_ALU | BPF_MUL | BPF_X: /* dst = (u32) dst * (u32) src */
635 /* msr %dst,%src */
636 EMIT4(0xb2520000, dst_reg, src_reg);
637 EMIT_ZERO(dst_reg);
638 break;
639 case BPF_ALU64 | BPF_MUL | BPF_X: /* dst = dst * src */
640 /* msgr %dst,%src */
641 EMIT4(0xb90c0000, dst_reg, src_reg);
642 break;
643 case BPF_ALU | BPF_MUL | BPF_K: /* dst = (u32) dst * (u32) imm */
644 if (imm == 1)
645 break;
646 /* msfi %r5,imm */
647 EMIT6_IMM(0xc2010000, dst_reg, imm);
648 EMIT_ZERO(dst_reg);
649 break;
650 case BPF_ALU64 | BPF_MUL | BPF_K: /* dst = dst * imm */
651 if (imm == 1)
652 break;
653 /* msgfi %dst,imm */
654 EMIT6_IMM(0xc2000000, dst_reg, imm);
655 break;
656 /*
657 * BPF_DIV / BPF_MOD
658 */
659 case BPF_ALU | BPF_DIV | BPF_X: /* dst = (u32) dst / (u32) src */
660 case BPF_ALU | BPF_MOD | BPF_X: /* dst = (u32) dst % (u32) src */
661 {
662 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
663
664 jit->seen |= SEEN_RET0;
665 /* ltr %src,%src (if src == 0 goto fail) */
666 EMIT2(0x1200, src_reg, src_reg);
667 /* jz <ret0> */
668 EMIT4_PCREL(0xa7840000, jit->ret0_ip - jit->prg);
669 /* lhi %w0,0 */
670 EMIT4_IMM(0xa7080000, REG_W0, 0);
671 /* lr %w1,%dst */
672 EMIT2(0x1800, REG_W1, dst_reg);
673 /* dlr %w0,%src */
674 EMIT4(0xb9970000, REG_W0, src_reg);
675 /* llgfr %dst,%rc */
676 EMIT4(0xb9160000, dst_reg, rc_reg);
677 break;
678 }
679 case BPF_ALU64 | BPF_DIV | BPF_X: /* dst = dst / src */
680 case BPF_ALU64 | BPF_MOD | BPF_X: /* dst = dst % src */
681 {
682 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
683
684 jit->seen |= SEEN_RET0;
685 /* ltgr %src,%src (if src == 0 goto fail) */
686 EMIT4(0xb9020000, src_reg, src_reg);
687 /* jz <ret0> */
688 EMIT4_PCREL(0xa7840000, jit->ret0_ip - jit->prg);
689 /* lghi %w0,0 */
690 EMIT4_IMM(0xa7090000, REG_W0, 0);
691 /* lgr %w1,%dst */
692 EMIT4(0xb9040000, REG_W1, dst_reg);
693 /* dlgr %w0,%dst */
694 EMIT4(0xb9870000, REG_W0, src_reg);
695 /* lgr %dst,%rc */
696 EMIT4(0xb9040000, dst_reg, rc_reg);
697 break;
698 }
699 case BPF_ALU | BPF_DIV | BPF_K: /* dst = (u32) dst / (u32) imm */
700 case BPF_ALU | BPF_MOD | BPF_K: /* dst = (u32) dst % (u32) imm */
701 {
702 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
703
704 if (imm == 1) {
705 if (BPF_OP(insn->code) == BPF_MOD)
706 /* lhgi %dst,0 */
707 EMIT4_IMM(0xa7090000, dst_reg, 0);
708 break;
709 }
710 /* lhi %w0,0 */
711 EMIT4_IMM(0xa7080000, REG_W0, 0);
712 /* lr %w1,%dst */
713 EMIT2(0x1800, REG_W1, dst_reg);
714 /* dl %w0,<d(imm)>(%l) */
715 EMIT6_DISP_LH(0xe3000000, 0x0097, REG_W0, REG_0, REG_L,
716 EMIT_CONST_U32(imm));
717 /* llgfr %dst,%rc */
718 EMIT4(0xb9160000, dst_reg, rc_reg);
719 break;
720 }
721 case BPF_ALU64 | BPF_DIV | BPF_K: /* dst = dst / imm */
722 case BPF_ALU64 | BPF_MOD | BPF_K: /* dst = dst % imm */
723 {
724 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
725
726 if (imm == 1) {
727 if (BPF_OP(insn->code) == BPF_MOD)
728 /* lhgi %dst,0 */
729 EMIT4_IMM(0xa7090000, dst_reg, 0);
730 break;
731 }
732 /* lghi %w0,0 */
733 EMIT4_IMM(0xa7090000, REG_W0, 0);
734 /* lgr %w1,%dst */
735 EMIT4(0xb9040000, REG_W1, dst_reg);
736 /* dlg %w0,<d(imm)>(%l) */
737 EMIT6_DISP_LH(0xe3000000, 0x0087, REG_W0, REG_0, REG_L,
738 EMIT_CONST_U64(imm));
739 /* lgr %dst,%rc */
740 EMIT4(0xb9040000, dst_reg, rc_reg);
741 break;
742 }
743 /*
744 * BPF_AND
745 */
746 case BPF_ALU | BPF_AND | BPF_X: /* dst = (u32) dst & (u32) src */
747 /* nr %dst,%src */
748 EMIT2(0x1400, dst_reg, src_reg);
749 EMIT_ZERO(dst_reg);
750 break;
751 case BPF_ALU64 | BPF_AND | BPF_X: /* dst = dst & src */
752 /* ngr %dst,%src */
753 EMIT4(0xb9800000, dst_reg, src_reg);
754 break;
755 case BPF_ALU | BPF_AND | BPF_K: /* dst = (u32) dst & (u32) imm */
756 /* nilf %dst,imm */
757 EMIT6_IMM(0xc00b0000, dst_reg, imm);
758 EMIT_ZERO(dst_reg);
759 break;
760 case BPF_ALU64 | BPF_AND | BPF_K: /* dst = dst & imm */
761 /* ng %dst,<d(imm)>(%l) */
762 EMIT6_DISP_LH(0xe3000000, 0x0080, dst_reg, REG_0, REG_L,
763 EMIT_CONST_U64(imm));
764 break;
765 /*
766 * BPF_OR
767 */
768 case BPF_ALU | BPF_OR | BPF_X: /* dst = (u32) dst | (u32) src */
769 /* or %dst,%src */
770 EMIT2(0x1600, dst_reg, src_reg);
771 EMIT_ZERO(dst_reg);
772 break;
773 case BPF_ALU64 | BPF_OR | BPF_X: /* dst = dst | src */
774 /* ogr %dst,%src */
775 EMIT4(0xb9810000, dst_reg, src_reg);
776 break;
777 case BPF_ALU | BPF_OR | BPF_K: /* dst = (u32) dst | (u32) imm */
778 /* oilf %dst,imm */
779 EMIT6_IMM(0xc00d0000, dst_reg, imm);
780 EMIT_ZERO(dst_reg);
781 break;
782 case BPF_ALU64 | BPF_OR | BPF_K: /* dst = dst | imm */
783 /* og %dst,<d(imm)>(%l) */
784 EMIT6_DISP_LH(0xe3000000, 0x0081, dst_reg, REG_0, REG_L,
785 EMIT_CONST_U64(imm));
786 break;
787 /*
788 * BPF_XOR
789 */
790 case BPF_ALU | BPF_XOR | BPF_X: /* dst = (u32) dst ^ (u32) src */
791 /* xr %dst,%src */
792 EMIT2(0x1700, dst_reg, src_reg);
793 EMIT_ZERO(dst_reg);
794 break;
795 case BPF_ALU64 | BPF_XOR | BPF_X: /* dst = dst ^ src */
796 /* xgr %dst,%src */
797 EMIT4(0xb9820000, dst_reg, src_reg);
798 break;
799 case BPF_ALU | BPF_XOR | BPF_K: /* dst = (u32) dst ^ (u32) imm */
800 if (!imm)
801 break;
802 /* xilf %dst,imm */
803 EMIT6_IMM(0xc0070000, dst_reg, imm);
804 EMIT_ZERO(dst_reg);
805 break;
806 case BPF_ALU64 | BPF_XOR | BPF_K: /* dst = dst ^ imm */
807 /* xg %dst,<d(imm)>(%l) */
808 EMIT6_DISP_LH(0xe3000000, 0x0082, dst_reg, REG_0, REG_L,
809 EMIT_CONST_U64(imm));
810 break;
811 /*
812 * BPF_LSH
813 */
814 case BPF_ALU | BPF_LSH | BPF_X: /* dst = (u32) dst << (u32) src */
815 /* sll %dst,0(%src) */
816 EMIT4_DISP(0x89000000, dst_reg, src_reg, 0);
817 EMIT_ZERO(dst_reg);
818 break;
819 case BPF_ALU64 | BPF_LSH | BPF_X: /* dst = dst << src */
820 /* sllg %dst,%dst,0(%src) */
821 EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg, dst_reg, src_reg, 0);
822 break;
823 case BPF_ALU | BPF_LSH | BPF_K: /* dst = (u32) dst << (u32) imm */
824 if (imm == 0)
825 break;
826 /* sll %dst,imm(%r0) */
827 EMIT4_DISP(0x89000000, dst_reg, REG_0, imm);
828 EMIT_ZERO(dst_reg);
829 break;
830 case BPF_ALU64 | BPF_LSH | BPF_K: /* dst = dst << imm */
831 if (imm == 0)
832 break;
833 /* sllg %dst,%dst,imm(%r0) */
834 EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg, dst_reg, REG_0, imm);
835 break;
836 /*
837 * BPF_RSH
838 */
839 case BPF_ALU | BPF_RSH | BPF_X: /* dst = (u32) dst >> (u32) src */
840 /* srl %dst,0(%src) */
841 EMIT4_DISP(0x88000000, dst_reg, src_reg, 0);
842 EMIT_ZERO(dst_reg);
843 break;
844 case BPF_ALU64 | BPF_RSH | BPF_X: /* dst = dst >> src */
845 /* srlg %dst,%dst,0(%src) */
846 EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg, dst_reg, src_reg, 0);
847 break;
848 case BPF_ALU | BPF_RSH | BPF_K: /* dst = (u32) dst >> (u32) imm */
849 if (imm == 0)
850 break;
851 /* srl %dst,imm(%r0) */
852 EMIT4_DISP(0x88000000, dst_reg, REG_0, imm);
853 EMIT_ZERO(dst_reg);
854 break;
855 case BPF_ALU64 | BPF_RSH | BPF_K: /* dst = dst >> imm */
856 if (imm == 0)
857 break;
858 /* srlg %dst,%dst,imm(%r0) */
859 EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg, dst_reg, REG_0, imm);
860 break;
861 /*
862 * BPF_ARSH
863 */
864 case BPF_ALU64 | BPF_ARSH | BPF_X: /* ((s64) dst) >>= src */
865 /* srag %dst,%dst,0(%src) */
866 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg, dst_reg, src_reg, 0);
867 break;
868 case BPF_ALU64 | BPF_ARSH | BPF_K: /* ((s64) dst) >>= imm */
869 if (imm == 0)
870 break;
871 /* srag %dst,%dst,imm(%r0) */
872 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg, dst_reg, REG_0, imm);
873 break;
874 /*
875 * BPF_NEG
876 */
877 case BPF_ALU | BPF_NEG: /* dst = (u32) -dst */
878 /* lcr %dst,%dst */
879 EMIT2(0x1300, dst_reg, dst_reg);
880 EMIT_ZERO(dst_reg);
881 break;
882 case BPF_ALU64 | BPF_NEG: /* dst = -dst */
883 /* lcgr %dst,%dst */
884 EMIT4(0xb9030000, dst_reg, dst_reg);
885 break;
886 /*
887 * BPF_FROM_BE/LE
888 */
889 case BPF_ALU | BPF_END | BPF_FROM_BE:
890 /* s390 is big endian, therefore only clear high order bytes */
891 switch (imm) {
892 case 16: /* dst = (u16) cpu_to_be16(dst) */
893 /* llghr %dst,%dst */
894 EMIT4(0xb9850000, dst_reg, dst_reg);
895 break;
896 case 32: /* dst = (u32) cpu_to_be32(dst) */
897 /* llgfr %dst,%dst */
898 EMIT4(0xb9160000, dst_reg, dst_reg);
899 break;
900 case 64: /* dst = (u64) cpu_to_be64(dst) */
901 break;
902 }
903 break;
904 case BPF_ALU | BPF_END | BPF_FROM_LE:
905 switch (imm) {
906 case 16: /* dst = (u16) cpu_to_le16(dst) */
907 /* lrvr %dst,%dst */
908 EMIT4(0xb91f0000, dst_reg, dst_reg);
909 /* srl %dst,16(%r0) */
910 EMIT4_DISP(0x88000000, dst_reg, REG_0, 16);
911 /* llghr %dst,%dst */
912 EMIT4(0xb9850000, dst_reg, dst_reg);
913 break;
914 case 32: /* dst = (u32) cpu_to_le32(dst) */
915 /* lrvr %dst,%dst */
916 EMIT4(0xb91f0000, dst_reg, dst_reg);
917 /* llgfr %dst,%dst */
918 EMIT4(0xb9160000, dst_reg, dst_reg);
919 break;
920 case 64: /* dst = (u64) cpu_to_le64(dst) */
921 /* lrvgr %dst,%dst */
922 EMIT4(0xb90f0000, dst_reg, dst_reg);
923 break;
924 }
925 break;
926 /*
927 * BPF_ST(X)
928 */
929 case BPF_STX | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = src_reg */
930 /* stcy %src,off(%dst) */
931 EMIT6_DISP_LH(0xe3000000, 0x0072, src_reg, dst_reg, REG_0, off);
932 jit->seen |= SEEN_MEM;
933 break;
934 case BPF_STX | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = src */
935 /* sthy %src,off(%dst) */
936 EMIT6_DISP_LH(0xe3000000, 0x0070, src_reg, dst_reg, REG_0, off);
937 jit->seen |= SEEN_MEM;
938 break;
939 case BPF_STX | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = src */
940 /* sty %src,off(%dst) */
941 EMIT6_DISP_LH(0xe3000000, 0x0050, src_reg, dst_reg, REG_0, off);
942 jit->seen |= SEEN_MEM;
943 break;
944 case BPF_STX | BPF_MEM | BPF_DW: /* (u64 *)(dst + off) = src */
945 /* stg %src,off(%dst) */
946 EMIT6_DISP_LH(0xe3000000, 0x0024, src_reg, dst_reg, REG_0, off);
947 jit->seen |= SEEN_MEM;
948 break;
949 case BPF_ST | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = imm */
950 /* lhi %w0,imm */
951 EMIT4_IMM(0xa7080000, REG_W0, (u8) imm);
952 /* stcy %w0,off(dst) */
953 EMIT6_DISP_LH(0xe3000000, 0x0072, REG_W0, dst_reg, REG_0, off);
954 jit->seen |= SEEN_MEM;
955 break;
956 case BPF_ST | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = imm */
957 /* lhi %w0,imm */
958 EMIT4_IMM(0xa7080000, REG_W0, (u16) imm);
959 /* sthy %w0,off(dst) */
960 EMIT6_DISP_LH(0xe3000000, 0x0070, REG_W0, dst_reg, REG_0, off);
961 jit->seen |= SEEN_MEM;
962 break;
963 case BPF_ST | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = imm */
964 /* llilf %w0,imm */
965 EMIT6_IMM(0xc00f0000, REG_W0, (u32) imm);
966 /* sty %w0,off(%dst) */
967 EMIT6_DISP_LH(0xe3000000, 0x0050, REG_W0, dst_reg, REG_0, off);
968 jit->seen |= SEEN_MEM;
969 break;
970 case BPF_ST | BPF_MEM | BPF_DW: /* *(u64 *)(dst + off) = imm */
971 /* lgfi %w0,imm */
972 EMIT6_IMM(0xc0010000, REG_W0, imm);
973 /* stg %w0,off(%dst) */
974 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W0, dst_reg, REG_0, off);
975 jit->seen |= SEEN_MEM;
976 break;
977 /*
978 * BPF_STX XADD (atomic_add)
979 */
980 case BPF_STX | BPF_XADD | BPF_W: /* *(u32 *)(dst + off) += src */
981 /* laal %w0,%src,off(%dst) */
982 EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W0, src_reg,
983 dst_reg, off);
984 jit->seen |= SEEN_MEM;
985 break;
986 case BPF_STX | BPF_XADD | BPF_DW: /* *(u64 *)(dst + off) += src */
987 /* laalg %w0,%src,off(%dst) */
988 EMIT6_DISP_LH(0xeb000000, 0x00ea, REG_W0, src_reg,
989 dst_reg, off);
990 jit->seen |= SEEN_MEM;
991 break;
992 /*
993 * BPF_LDX
994 */
995 case BPF_LDX | BPF_MEM | BPF_B: /* dst = *(u8 *)(ul) (src + off) */
996 /* llgc %dst,0(off,%src) */
997 EMIT6_DISP_LH(0xe3000000, 0x0090, dst_reg, src_reg, REG_0, off);
998 jit->seen |= SEEN_MEM;
999 break;
1000 case BPF_LDX | BPF_MEM | BPF_H: /* dst = *(u16 *)(ul) (src + off) */
1001 /* llgh %dst,0(off,%src) */
1002 EMIT6_DISP_LH(0xe3000000, 0x0091, dst_reg, src_reg, REG_0, off);
1003 jit->seen |= SEEN_MEM;
1004 break;
1005 case BPF_LDX | BPF_MEM | BPF_W: /* dst = *(u32 *)(ul) (src + off) */
1006 /* llgf %dst,off(%src) */
1007 jit->seen |= SEEN_MEM;
1008 EMIT6_DISP_LH(0xe3000000, 0x0016, dst_reg, src_reg, REG_0, off);
1009 break;
1010 case BPF_LDX | BPF_MEM | BPF_DW: /* dst = *(u64 *)(ul) (src + off) */
1011 /* lg %dst,0(off,%src) */
1012 jit->seen |= SEEN_MEM;
1013 EMIT6_DISP_LH(0xe3000000, 0x0004, dst_reg, src_reg, REG_0, off);
1014 break;
1015 /*
1016 * BPF_JMP / CALL
1017 */
1018 case BPF_JMP | BPF_CALL:
1019 {
1020 /*
1021 * b0 = (__bpf_call_base + imm)(b1, b2, b3, b4, b5)
1022 */
1023 const u64 func = (u64)__bpf_call_base + imm;
1024
1025 REG_SET_SEEN(BPF_REG_5);
1026 jit->seen |= SEEN_FUNC;
1027 /* lg %w1,<d(imm)>(%l) */
1028 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_W1, REG_0, REG_L,
1029 EMIT_CONST_U64(func));
1030 if (IS_ENABLED(CC_USING_EXPOLINE) && !nospec_disable) {
1031 /* brasl %r14,__s390_indirect_jump_r1 */
1032 EMIT6_PCREL_RILB(0xc0050000, REG_14, jit->r1_thunk_ip);
1033 } else {
1034 /* basr %r14,%w1 */
1035 EMIT2(0x0d00, REG_14, REG_W1);
1036 }
1037 /* lgr %b0,%r2: load return value into %b0 */
1038 EMIT4(0xb9040000, BPF_REG_0, REG_2);
1039 if (bpf_helper_changes_skb_data((void *)func)) {
1040 jit->seen |= SEEN_SKB_CHANGE;
1041 /* lg %b1,ST_OFF_SKBP(%r15) */
1042 EMIT6_DISP_LH(0xe3000000, 0x0004, BPF_REG_1, REG_0,
1043 REG_15, STK_OFF_SKBP);
1044 emit_load_skb_data_hlen(jit);
1045 }
1046 break;
1047 }
1048 case BPF_JMP | BPF_CALL | BPF_X:
1049 /*
1050 * Implicit input:
1051 * B1: pointer to ctx
1052 * B2: pointer to bpf_array
1053 * B3: index in bpf_array
1054 */
1055 jit->seen |= SEEN_TAIL_CALL;
1056
1057 /*
1058 * if (index >= array->map.max_entries)
1059 * goto out;
1060 */
1061
1062 /* llgf %w1,map.max_entries(%b2) */
1063 EMIT6_DISP_LH(0xe3000000, 0x0016, REG_W1, REG_0, BPF_REG_2,
1064 offsetof(struct bpf_array, map.max_entries));
1065 /* clrj %b3,%w1,0xa,label0: if (u32)%b3 >= (u32)%w1 goto out */
1066 EMIT6_PCREL_LABEL(0xec000000, 0x0077, BPF_REG_3,
1067 REG_W1, 0, 0xa);
1068
1069 /*
1070 * if (tail_call_cnt++ > MAX_TAIL_CALL_CNT)
1071 * goto out;
1072 */
1073
1074 if (jit->seen & SEEN_STACK)
1075 off = STK_OFF_TCCNT + STK_OFF;
1076 else
1077 off = STK_OFF_TCCNT;
1078 /* lhi %w0,1 */
1079 EMIT4_IMM(0xa7080000, REG_W0, 1);
1080 /* laal %w1,%w0,off(%r15) */
1081 EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W1, REG_W0, REG_15, off);
1082 /* clij %w1,MAX_TAIL_CALL_CNT,0x2,label0 */
1083 EMIT6_PCREL_IMM_LABEL(0xec000000, 0x007f, REG_W1,
1084 MAX_TAIL_CALL_CNT, 0, 0x2);
1085
1086 /*
1087 * prog = array->ptrs[index];
1088 * if (prog == NULL)
1089 * goto out;
1090 */
1091
1092 /* llgfr %r1,%b3: %r1 = (u32) index */
1093 EMIT4(0xb9160000, REG_1, BPF_REG_3);
1094 /* sllg %r1,%r1,3: %r1 *= 8 */
1095 EMIT6_DISP_LH(0xeb000000, 0x000d, REG_1, REG_1, REG_0, 3);
1096 /* lg %r1,prog(%b2,%r1) */
1097 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_1, BPF_REG_2,
1098 REG_1, offsetof(struct bpf_array, ptrs));
1099 /* clgij %r1,0,0x8,label0 */
1100 EMIT6_PCREL_IMM_LABEL(0xec000000, 0x007d, REG_1, 0, 0, 0x8);
1101
1102 /*
1103 * Restore registers before calling function
1104 */
1105 save_restore_regs(jit, REGS_RESTORE);
1106
1107 /*
1108 * goto *(prog->bpf_func + tail_call_start);
1109 */
1110
1111 /* lg %r1,bpf_func(%r1) */
1112 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_1, REG_1, REG_0,
1113 offsetof(struct bpf_prog, bpf_func));
1114 /* bc 0xf,tail_call_start(%r1) */
1115 _EMIT4(0x47f01000 + jit->tail_call_start);
1116 /* out: */
1117 jit->labels[0] = jit->prg;
1118 break;
1119 case BPF_JMP | BPF_EXIT: /* return b0 */
1120 last = (i == fp->len - 1) ? 1 : 0;
1121 if (last && !(jit->seen & SEEN_RET0))
1122 break;
1123 /* j <exit> */
1124 EMIT4_PCREL(0xa7f40000, jit->exit_ip - jit->prg);
1125 break;
1126 /*
1127 * Branch relative (number of skipped instructions) to offset on
1128 * condition.
1129 *
1130 * Condition code to mask mapping:
1131 *
1132 * CC | Description | Mask
1133 * ------------------------------
1134 * 0 | Operands equal | 8
1135 * 1 | First operand low | 4
1136 * 2 | First operand high | 2
1137 * 3 | Unused | 1
1138 *
1139 * For s390x relative branches: ip = ip + off_bytes
1140 * For BPF relative branches: insn = insn + off_insns + 1
1141 *
1142 * For example for s390x with offset 0 we jump to the branch
1143 * instruction itself (loop) and for BPF with offset 0 we
1144 * branch to the instruction behind the branch.
1145 */
1146 case BPF_JMP | BPF_JA: /* if (true) */
1147 mask = 0xf000; /* j */
1148 goto branch_oc;
1149 case BPF_JMP | BPF_JSGT | BPF_K: /* ((s64) dst > (s64) imm) */
1150 mask = 0x2000; /* jh */
1151 goto branch_ks;
1152 case BPF_JMP | BPF_JSGE | BPF_K: /* ((s64) dst >= (s64) imm) */
1153 mask = 0xa000; /* jhe */
1154 goto branch_ks;
1155 case BPF_JMP | BPF_JGT | BPF_K: /* (dst_reg > imm) */
1156 mask = 0x2000; /* jh */
1157 goto branch_ku;
1158 case BPF_JMP | BPF_JGE | BPF_K: /* (dst_reg >= imm) */
1159 mask = 0xa000; /* jhe */
1160 goto branch_ku;
1161 case BPF_JMP | BPF_JNE | BPF_K: /* (dst_reg != imm) */
1162 mask = 0x7000; /* jne */
1163 goto branch_ku;
1164 case BPF_JMP | BPF_JEQ | BPF_K: /* (dst_reg == imm) */
1165 mask = 0x8000; /* je */
1166 goto branch_ku;
1167 case BPF_JMP | BPF_JSET | BPF_K: /* (dst_reg & imm) */
1168 mask = 0x7000; /* jnz */
1169 /* lgfi %w1,imm (load sign extend imm) */
1170 EMIT6_IMM(0xc0010000, REG_W1, imm);
1171 /* ngr %w1,%dst */
1172 EMIT4(0xb9800000, REG_W1, dst_reg);
1173 goto branch_oc;
1174
1175 case BPF_JMP | BPF_JSGT | BPF_X: /* ((s64) dst > (s64) src) */
1176 mask = 0x2000; /* jh */
1177 goto branch_xs;
1178 case BPF_JMP | BPF_JSGE | BPF_X: /* ((s64) dst >= (s64) src) */
1179 mask = 0xa000; /* jhe */
1180 goto branch_xs;
1181 case BPF_JMP | BPF_JGT | BPF_X: /* (dst > src) */
1182 mask = 0x2000; /* jh */
1183 goto branch_xu;
1184 case BPF_JMP | BPF_JGE | BPF_X: /* (dst >= src) */
1185 mask = 0xa000; /* jhe */
1186 goto branch_xu;
1187 case BPF_JMP | BPF_JNE | BPF_X: /* (dst != src) */
1188 mask = 0x7000; /* jne */
1189 goto branch_xu;
1190 case BPF_JMP | BPF_JEQ | BPF_X: /* (dst == src) */
1191 mask = 0x8000; /* je */
1192 goto branch_xu;
1193 case BPF_JMP | BPF_JSET | BPF_X: /* (dst & src) */
1194 mask = 0x7000; /* jnz */
1195 /* ngrk %w1,%dst,%src */
1196 EMIT4_RRF(0xb9e40000, REG_W1, dst_reg, src_reg);
1197 goto branch_oc;
1198 branch_ks:
1199 /* lgfi %w1,imm (load sign extend imm) */
1200 EMIT6_IMM(0xc0010000, REG_W1, imm);
1201 /* cgrj %dst,%w1,mask,off */
1202 EMIT6_PCREL(0xec000000, 0x0064, dst_reg, REG_W1, i, off, mask);
1203 break;
1204 branch_ku:
1205 /* lgfi %w1,imm (load sign extend imm) */
1206 EMIT6_IMM(0xc0010000, REG_W1, imm);
1207 /* clgrj %dst,%w1,mask,off */
1208 EMIT6_PCREL(0xec000000, 0x0065, dst_reg, REG_W1, i, off, mask);
1209 break;
1210 branch_xs:
1211 /* cgrj %dst,%src,mask,off */
1212 EMIT6_PCREL(0xec000000, 0x0064, dst_reg, src_reg, i, off, mask);
1213 break;
1214 branch_xu:
1215 /* clgrj %dst,%src,mask,off */
1216 EMIT6_PCREL(0xec000000, 0x0065, dst_reg, src_reg, i, off, mask);
1217 break;
1218 branch_oc:
1219 /* brc mask,jmp_off (branch instruction needs 4 bytes) */
1220 jmp_off = addrs[i + off + 1] - (addrs[i + 1] - 4);
1221 EMIT4_PCREL(0xa7040000 | mask << 8, jmp_off);
1222 break;
1223 /*
1224 * BPF_LD
1225 */
1226 case BPF_LD | BPF_ABS | BPF_B: /* b0 = *(u8 *) (skb->data+imm) */
1227 case BPF_LD | BPF_IND | BPF_B: /* b0 = *(u8 *) (skb->data+imm+src) */
1228 if ((BPF_MODE(insn->code) == BPF_ABS) && (imm >= 0))
1229 func_addr = __pa(sk_load_byte_pos);
1230 else
1231 func_addr = __pa(sk_load_byte);
1232 goto call_fn;
1233 case BPF_LD | BPF_ABS | BPF_H: /* b0 = *(u16 *) (skb->data+imm) */
1234 case BPF_LD | BPF_IND | BPF_H: /* b0 = *(u16 *) (skb->data+imm+src) */
1235 if ((BPF_MODE(insn->code) == BPF_ABS) && (imm >= 0))
1236 func_addr = __pa(sk_load_half_pos);
1237 else
1238 func_addr = __pa(sk_load_half);
1239 goto call_fn;
1240 case BPF_LD | BPF_ABS | BPF_W: /* b0 = *(u32 *) (skb->data+imm) */
1241 case BPF_LD | BPF_IND | BPF_W: /* b0 = *(u32 *) (skb->data+imm+src) */
1242 if ((BPF_MODE(insn->code) == BPF_ABS) && (imm >= 0))
1243 func_addr = __pa(sk_load_word_pos);
1244 else
1245 func_addr = __pa(sk_load_word);
1246 goto call_fn;
1247 call_fn:
1248 jit->seen |= SEEN_SKB | SEEN_RET0 | SEEN_FUNC;
1249 REG_SET_SEEN(REG_14); /* Return address of possible func call */
1250
1251 /*
1252 * Implicit input:
1253 * BPF_REG_6 (R7) : skb pointer
1254 * REG_SKB_DATA (R12): skb data pointer (if no BPF_REG_AX)
1255 *
1256 * Calculated input:
1257 * BPF_REG_2 (R3) : offset of byte(s) to fetch in skb
1258 * BPF_REG_5 (R6) : return address
1259 *
1260 * Output:
1261 * BPF_REG_0 (R14): data read from skb
1262 *
1263 * Scratch registers (BPF_REG_1-5)
1264 */
1265
1266 /* Call function: llilf %w1,func_addr */
1267 EMIT6_IMM(0xc00f0000, REG_W1, func_addr);
1268
1269 /* Offset: lgfi %b2,imm */
1270 EMIT6_IMM(0xc0010000, BPF_REG_2, imm);
1271 if (BPF_MODE(insn->code) == BPF_IND)
1272 /* agfr %b2,%src (%src is s32 here) */
1273 EMIT4(0xb9180000, BPF_REG_2, src_reg);
1274
1275 /* Reload REG_SKB_DATA if BPF_REG_AX is used */
1276 if (jit->seen & SEEN_REG_AX)
1277 /* lg %skb_data,data_off(%b6) */
1278 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_SKB_DATA, REG_0,
1279 BPF_REG_6, offsetof(struct sk_buff, data));
1280 /* basr %b5,%w1 (%b5 is call saved) */
1281 EMIT2(0x0d00, BPF_REG_5, REG_W1);
1282
1283 /*
1284 * Note: For fast access we jump directly after the
1285 * jnz instruction from bpf_jit.S
1286 */
1287 /* jnz <ret0> */
1288 EMIT4_PCREL(0xa7740000, jit->ret0_ip - jit->prg);
1289 break;
1290 default: /* too complex, give up */
1291 pr_err("Unknown opcode %02x\n", insn->code);
1292 return -1;
1293 }
1294 return insn_count;
1295 }
1296
1297 /*
1298 * Compile eBPF program into s390x code
1299 */
1300 static int bpf_jit_prog(struct bpf_jit *jit, struct bpf_prog *fp)
1301 {
1302 int i, insn_count;
1303
1304 jit->lit = jit->lit_start;
1305 jit->prg = 0;
1306
1307 bpf_jit_prologue(jit);
1308 for (i = 0; i < fp->len; i += insn_count) {
1309 insn_count = bpf_jit_insn(jit, fp, i);
1310 if (insn_count < 0)
1311 return -1;
1312 /* Next instruction address */
1313 jit->addrs[i + insn_count] = jit->prg;
1314 }
1315 bpf_jit_epilogue(jit);
1316
1317 jit->lit_start = jit->prg;
1318 jit->size = jit->lit;
1319 jit->size_prg = jit->prg;
1320 return 0;
1321 }
1322
1323 /*
1324 * Classic BPF function stub. BPF programs will be converted into
1325 * eBPF and then bpf_int_jit_compile() will be called.
1326 */
1327 void bpf_jit_compile(struct bpf_prog *fp)
1328 {
1329 }
1330
1331 /*
1332 * Compile eBPF program "fp"
1333 */
1334 struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *fp)
1335 {
1336 struct bpf_prog *tmp, *orig_fp = fp;
1337 struct bpf_binary_header *header;
1338 bool tmp_blinded = false;
1339 struct bpf_jit jit;
1340 int pass;
1341
1342 if (!bpf_jit_enable)
1343 return orig_fp;
1344
1345 tmp = bpf_jit_blind_constants(fp);
1346 /*
1347 * If blinding was requested and we failed during blinding,
1348 * we must fall back to the interpreter.
1349 */
1350 if (IS_ERR(tmp))
1351 return orig_fp;
1352 if (tmp != fp) {
1353 tmp_blinded = true;
1354 fp = tmp;
1355 }
1356
1357 memset(&jit, 0, sizeof(jit));
1358 jit.addrs = kcalloc(fp->len + 1, sizeof(*jit.addrs), GFP_KERNEL);
1359 if (jit.addrs == NULL) {
1360 fp = orig_fp;
1361 goto out;
1362 }
1363 /*
1364 * Three initial passes:
1365 * - 1/2: Determine clobbered registers
1366 * - 3: Calculate program size and addrs arrray
1367 */
1368 for (pass = 1; pass <= 3; pass++) {
1369 if (bpf_jit_prog(&jit, fp)) {
1370 fp = orig_fp;
1371 goto free_addrs;
1372 }
1373 }
1374 /*
1375 * Final pass: Allocate and generate program
1376 */
1377 if (jit.size >= BPF_SIZE_MAX) {
1378 fp = orig_fp;
1379 goto free_addrs;
1380 }
1381 header = bpf_jit_binary_alloc(jit.size, &jit.prg_buf, 2, jit_fill_hole);
1382 if (!header) {
1383 fp = orig_fp;
1384 goto free_addrs;
1385 }
1386 if (bpf_jit_prog(&jit, fp)) {
1387 bpf_jit_binary_free(header);
1388 fp = orig_fp;
1389 goto free_addrs;
1390 }
1391 if (bpf_jit_enable > 1) {
1392 bpf_jit_dump(fp->len, jit.size, pass, jit.prg_buf);
1393 if (jit.prg_buf)
1394 print_fn_code(jit.prg_buf, jit.size_prg);
1395 }
1396 if (jit.prg_buf) {
1397 set_memory_ro((unsigned long)header, header->pages);
1398 fp->bpf_func = (void *) jit.prg_buf;
1399 fp->jited = 1;
1400 }
1401 free_addrs:
1402 kfree(jit.addrs);
1403 out:
1404 if (tmp_blinded)
1405 bpf_jit_prog_release_other(fp, fp == orig_fp ?
1406 tmp : orig_fp);
1407 return fp;
1408 }
1409
1410 /*
1411 * Free eBPF program
1412 */
1413 void bpf_jit_free(struct bpf_prog *fp)
1414 {
1415 unsigned long addr = (unsigned long)fp->bpf_func & PAGE_MASK;
1416 struct bpf_binary_header *header = (void *)addr;
1417
1418 if (!fp->jited)
1419 goto free_filter;
1420
1421 set_memory_rw(addr, header->pages);
1422 bpf_jit_binary_free(header);
1423
1424 free_filter:
1425 bpf_prog_unlock_free(fp);
1426 }
Linux with added FPC-III support