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Linux 4.9.199
[linux/fpc-iii.git] / arch / x86 / kvm / svm.c
blobf7a7b98b3271a6fc5df234854d86174c8222a5a0
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
8 *
9 * Authors:
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
18 #define pr_fmt(fmt) "SVM: " fmt
19
20 #include <linux/kvm_host.h>
21
22 #include "irq.h"
23 #include "mmu.h"
24 #include "kvm_cache_regs.h"
25 #include "x86.h"
26 #include "cpuid.h"
27 #include "pmu.h"
28
29 #include <linux/module.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/kernel.h>
32 #include <linux/vmalloc.h>
33 #include <linux/highmem.h>
34 #include <linux/sched.h>
35 #include <linux/trace_events.h>
36 #include <linux/slab.h>
37 #include <linux/amd-iommu.h>
38 #include <linux/hashtable.h>
39 #include <linux/frame.h>
40
41 #include <asm/apic.h>
42 #include <asm/perf_event.h>
43 #include <asm/tlbflush.h>
44 #include <asm/desc.h>
45 #include <asm/debugreg.h>
46 #include <asm/kvm_para.h>
47 #include <asm/irq_remapping.h>
48 #include <asm/microcode.h>
49 #include <asm/spec-ctrl.h>
50
51 #include <asm/virtext.h>
52 #include "trace.h"
53
54 #define __ex(x) __kvm_handle_fault_on_reboot(x)
55
56 MODULE_AUTHOR("Qumranet");
57 MODULE_LICENSE("GPL");
58
59 static const struct x86_cpu_id svm_cpu_id[] = {
60 X86_FEATURE_MATCH(X86_FEATURE_SVM),
61 {}
62 };
63 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
64
65 #define IOPM_ALLOC_ORDER 2
66 #define MSRPM_ALLOC_ORDER 1
67
68 #define SEG_TYPE_LDT 2
69 #define SEG_TYPE_BUSY_TSS16 3
70
71 #define SVM_FEATURE_NPT (1 << 0)
72 #define SVM_FEATURE_LBRV (1 << 1)
73 #define SVM_FEATURE_SVML (1 << 2)
74 #define SVM_FEATURE_NRIP (1 << 3)
75 #define SVM_FEATURE_TSC_RATE (1 << 4)
76 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
77 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
78 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
79 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
80
81 #define SVM_AVIC_DOORBELL 0xc001011b
82
83 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
84 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
85 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
86
87 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
88
89 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
90 #define TSC_RATIO_MIN 0x0000000000000001ULL
91 #define TSC_RATIO_MAX 0x000000ffffffffffULL
92
93 #define AVIC_HPA_MASK ~((0xFFFULL << 52) | 0xFFF)
94
95 /*
96 * 0xff is broadcast, so the max index allowed for physical APIC ID
97 * table is 0xfe. APIC IDs above 0xff are reserved.
98 */
99 #define AVIC_MAX_PHYSICAL_ID_COUNT 255
100
101 #define AVIC_UNACCEL_ACCESS_WRITE_MASK 1
102 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK 0xFF0
103 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK 0xFFFFFFFF
104
105 /* AVIC GATAG is encoded using VM and VCPU IDs */
106 #define AVIC_VCPU_ID_BITS 8
107 #define AVIC_VCPU_ID_MASK ((1 << AVIC_VCPU_ID_BITS) - 1)
108
109 #define AVIC_VM_ID_BITS 24
110 #define AVIC_VM_ID_NR (1 << AVIC_VM_ID_BITS)
111 #define AVIC_VM_ID_MASK ((1 << AVIC_VM_ID_BITS) - 1)
112
113 #define AVIC_GATAG(x, y) (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \
114 (y & AVIC_VCPU_ID_MASK))
115 #define AVIC_GATAG_TO_VMID(x) ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK)
116 #define AVIC_GATAG_TO_VCPUID(x) (x & AVIC_VCPU_ID_MASK)
117
118 static bool erratum_383_found __read_mostly;
119
120 static const u32 host_save_user_msrs[] = {
121 #ifdef CONFIG_X86_64
122 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
123 MSR_FS_BASE,
124 #endif
125 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
126 MSR_TSC_AUX,
127 };
128
129 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
130
131 struct kvm_vcpu;
132
133 struct nested_state {
134 struct vmcb *hsave;
135 u64 hsave_msr;
136 u64 vm_cr_msr;
137 u64 vmcb;
138
139 /* These are the merged vectors */
140 u32 *msrpm;
141
142 /* gpa pointers to the real vectors */
143 u64 vmcb_msrpm;
144 u64 vmcb_iopm;
145
146 /* A VMEXIT is required but not yet emulated */
147 bool exit_required;
148
149 /* cache for intercepts of the guest */
150 u32 intercept_cr;
151 u32 intercept_dr;
152 u32 intercept_exceptions;
153 u64 intercept;
154
155 /* Nested Paging related state */
156 u64 nested_cr3;
157 };
158
159 #define MSRPM_OFFSETS 16
160 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
161
162 /*
163 * Set osvw_len to higher value when updated Revision Guides
164 * are published and we know what the new status bits are
165 */
166 static uint64_t osvw_len = 4, osvw_status;
167
168 struct vcpu_svm {
169 struct kvm_vcpu vcpu;
170 struct vmcb *vmcb;
171 unsigned long vmcb_pa;
172 struct svm_cpu_data *svm_data;
173 uint64_t asid_generation;
174 uint64_t sysenter_esp;
175 uint64_t sysenter_eip;
176 uint64_t tsc_aux;
177
178 u64 msr_decfg;
179
180 u64 next_rip;
181
182 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
183 struct {
184 u16 fs;
185 u16 gs;
186 u16 ldt;
187 u64 gs_base;
188 } host;
189
190 u64 spec_ctrl;
191 /*
192 * Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be
193 * translated into the appropriate L2_CFG bits on the host to
194 * perform speculative control.
195 */
196 u64 virt_spec_ctrl;
197
198 u32 *msrpm;
199
200 ulong nmi_iret_rip;
201
202 struct nested_state nested;
203
204 bool nmi_singlestep;
205
206 unsigned int3_injected;
207 unsigned long int3_rip;
208 u32 apf_reason;
209
210 /* cached guest cpuid flags for faster access */
211 bool nrips_enabled : 1;
212
213 u32 ldr_reg;
214 struct page *avic_backing_page;
215 u64 *avic_physical_id_cache;
216 bool avic_is_running;
217
218 /*
219 * Per-vcpu list of struct amd_svm_iommu_ir:
220 * This is used mainly to store interrupt remapping information used
221 * when update the vcpu affinity. This avoids the need to scan for
222 * IRTE and try to match ga_tag in the IOMMU driver.
223 */
224 struct list_head ir_list;
225 spinlock_t ir_list_lock;
226 };
227
228 /*
229 * This is a wrapper of struct amd_iommu_ir_data.
230 */
231 struct amd_svm_iommu_ir {
232 struct list_head node; /* Used by SVM for per-vcpu ir_list */
233 void *data; /* Storing pointer to struct amd_ir_data */
234 };
235
236 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFF)
237 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31)
238
239 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK (0xFFULL)
240 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12)
241 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62)
242 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63)
243
244 static DEFINE_PER_CPU(u64, current_tsc_ratio);
245 #define TSC_RATIO_DEFAULT 0x0100000000ULL
246
247 #define MSR_INVALID 0xffffffffU
248
249 static const struct svm_direct_access_msrs {
250 u32 index; /* Index of the MSR */
251 bool always; /* True if intercept is always on */
252 } direct_access_msrs[] = {
253 { .index = MSR_STAR, .always = true },
254 { .index = MSR_IA32_SYSENTER_CS, .always = true },
255 #ifdef CONFIG_X86_64
256 { .index = MSR_GS_BASE, .always = true },
257 { .index = MSR_FS_BASE, .always = true },
258 { .index = MSR_KERNEL_GS_BASE, .always = true },
259 { .index = MSR_LSTAR, .always = true },
260 { .index = MSR_CSTAR, .always = true },
261 { .index = MSR_SYSCALL_MASK, .always = true },
262 #endif
263 { .index = MSR_IA32_SPEC_CTRL, .always = false },
264 { .index = MSR_IA32_PRED_CMD, .always = false },
265 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
266 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
267 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
268 { .index = MSR_IA32_LASTINTTOIP, .always = false },
269 { .index = MSR_INVALID, .always = false },
270 };
271
272 /* enable NPT for AMD64 and X86 with PAE */
273 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
274 static bool npt_enabled = true;
275 #else
276 static bool npt_enabled;
277 #endif
278
279 /* allow nested paging (virtualized MMU) for all guests */
280 static int npt = true;
281 module_param(npt, int, S_IRUGO);
282
283 /* allow nested virtualization in KVM/SVM */
284 static int nested = true;
285 module_param(nested, int, S_IRUGO);
286
287 /* enable / disable AVIC */
288 static int avic;
289 #ifdef CONFIG_X86_LOCAL_APIC
290 module_param(avic, int, S_IRUGO);
291 #endif
292
293 /* AVIC VM ID bit masks and lock */
294 static DECLARE_BITMAP(avic_vm_id_bitmap, AVIC_VM_ID_NR);
295 static DEFINE_SPINLOCK(avic_vm_id_lock);
296
297 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
298 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
299 static void svm_complete_interrupts(struct vcpu_svm *svm);
300
301 static int nested_svm_exit_handled(struct vcpu_svm *svm);
302 static int nested_svm_intercept(struct vcpu_svm *svm);
303 static int nested_svm_vmexit(struct vcpu_svm *svm);
304 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
305 bool has_error_code, u32 error_code);
306
307 enum {
308 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
309 pause filter count */
310 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
311 VMCB_ASID, /* ASID */
312 VMCB_INTR, /* int_ctl, int_vector */
313 VMCB_NPT, /* npt_en, nCR3, gPAT */
314 VMCB_CR, /* CR0, CR3, CR4, EFER */
315 VMCB_DR, /* DR6, DR7 */
316 VMCB_DT, /* GDT, IDT */
317 VMCB_SEG, /* CS, DS, SS, ES, CPL */
318 VMCB_CR2, /* CR2 only */
319 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
320 VMCB_AVIC, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
321 * AVIC PHYSICAL_TABLE pointer,
322 * AVIC LOGICAL_TABLE pointer
323 */
324 VMCB_DIRTY_MAX,
325 };
326
327 /* TPR and CR2 are always written before VMRUN */
328 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
329
330 #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL
331
332 static inline void mark_all_dirty(struct vmcb *vmcb)
333 {
334 vmcb->control.clean = 0;
335 }
336
337 static inline void mark_all_clean(struct vmcb *vmcb)
338 {
339 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
340 & ~VMCB_ALWAYS_DIRTY_MASK;
341 }
342
343 static inline void mark_dirty(struct vmcb *vmcb, int bit)
344 {
345 vmcb->control.clean &= ~(1 << bit);
346 }
347
348 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
349 {
350 return container_of(vcpu, struct vcpu_svm, vcpu);
351 }
352
353 static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data)
354 {
355 svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK;
356 mark_dirty(svm->vmcb, VMCB_AVIC);
357 }
358
359 static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu)
360 {
361 struct vcpu_svm *svm = to_svm(vcpu);
362 u64 *entry = svm->avic_physical_id_cache;
363
364 if (!entry)
365 return false;
366
367 return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
368 }
369
370 static void recalc_intercepts(struct vcpu_svm *svm)
371 {
372 struct vmcb_control_area *c, *h;
373 struct nested_state *g;
374
375 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
376
377 if (!is_guest_mode(&svm->vcpu))
378 return;
379
380 c = &svm->vmcb->control;
381 h = &svm->nested.hsave->control;
382 g = &svm->nested;
383
384 c->intercept_cr = h->intercept_cr | g->intercept_cr;
385 c->intercept_dr = h->intercept_dr | g->intercept_dr;
386 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
387 c->intercept = h->intercept | g->intercept;
388 }
389
390 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
391 {
392 if (is_guest_mode(&svm->vcpu))
393 return svm->nested.hsave;
394 else
395 return svm->vmcb;
396 }
397
398 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
399 {
400 struct vmcb *vmcb = get_host_vmcb(svm);
401
402 vmcb->control.intercept_cr |= (1U << bit);
403
404 recalc_intercepts(svm);
405 }
406
407 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
408 {
409 struct vmcb *vmcb = get_host_vmcb(svm);
410
411 vmcb->control.intercept_cr &= ~(1U << bit);
412
413 recalc_intercepts(svm);
414 }
415
416 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
417 {
418 struct vmcb *vmcb = get_host_vmcb(svm);
419
420 return vmcb->control.intercept_cr & (1U << bit);
421 }
422
423 static inline void set_dr_intercepts(struct vcpu_svm *svm)
424 {
425 struct vmcb *vmcb = get_host_vmcb(svm);
426
427 vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
428 | (1 << INTERCEPT_DR1_READ)
429 | (1 << INTERCEPT_DR2_READ)
430 | (1 << INTERCEPT_DR3_READ)
431 | (1 << INTERCEPT_DR4_READ)
432 | (1 << INTERCEPT_DR5_READ)
433 | (1 << INTERCEPT_DR6_READ)
434 | (1 << INTERCEPT_DR7_READ)
435 | (1 << INTERCEPT_DR0_WRITE)
436 | (1 << INTERCEPT_DR1_WRITE)
437 | (1 << INTERCEPT_DR2_WRITE)
438 | (1 << INTERCEPT_DR3_WRITE)
439 | (1 << INTERCEPT_DR4_WRITE)
440 | (1 << INTERCEPT_DR5_WRITE)
441 | (1 << INTERCEPT_DR6_WRITE)
442 | (1 << INTERCEPT_DR7_WRITE);
443
444 recalc_intercepts(svm);
445 }
446
447 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
448 {
449 struct vmcb *vmcb = get_host_vmcb(svm);
450
451 vmcb->control.intercept_dr = 0;
452
453 recalc_intercepts(svm);
454 }
455
456 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
457 {
458 struct vmcb *vmcb = get_host_vmcb(svm);
459
460 vmcb->control.intercept_exceptions |= (1U << bit);
461
462 recalc_intercepts(svm);
463 }
464
465 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
466 {
467 struct vmcb *vmcb = get_host_vmcb(svm);
468
469 vmcb->control.intercept_exceptions &= ~(1U << bit);
470
471 recalc_intercepts(svm);
472 }
473
474 static inline void set_intercept(struct vcpu_svm *svm, int bit)
475 {
476 struct vmcb *vmcb = get_host_vmcb(svm);
477
478 vmcb->control.intercept |= (1ULL << bit);
479
480 recalc_intercepts(svm);
481 }
482
483 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
484 {
485 struct vmcb *vmcb = get_host_vmcb(svm);
486
487 vmcb->control.intercept &= ~(1ULL << bit);
488
489 recalc_intercepts(svm);
490 }
491
492 static inline void enable_gif(struct vcpu_svm *svm)
493 {
494 svm->vcpu.arch.hflags |= HF_GIF_MASK;
495 }
496
497 static inline void disable_gif(struct vcpu_svm *svm)
498 {
499 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
500 }
501
502 static inline bool gif_set(struct vcpu_svm *svm)
503 {
504 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
505 }
506
507 static unsigned long iopm_base;
508
509 struct kvm_ldttss_desc {
510 u16 limit0;
511 u16 base0;
512 unsigned base1:8, type:5, dpl:2, p:1;
513 unsigned limit1:4, zero0:3, g:1, base2:8;
514 u32 base3;
515 u32 zero1;
516 } __attribute__((packed));
517
518 struct svm_cpu_data {
519 int cpu;
520
521 u64 asid_generation;
522 u32 max_asid;
523 u32 next_asid;
524 struct kvm_ldttss_desc *tss_desc;
525
526 struct page *save_area;
527 struct vmcb *current_vmcb;
528 };
529
530 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
531
532 struct svm_init_data {
533 int cpu;
534 int r;
535 };
536
537 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
538
539 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
540 #define MSRS_RANGE_SIZE 2048
541 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
542
543 static u32 svm_msrpm_offset(u32 msr)
544 {
545 u32 offset;
546 int i;
547
548 for (i = 0; i < NUM_MSR_MAPS; i++) {
549 if (msr < msrpm_ranges[i] ||
550 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
551 continue;
552
553 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
554 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
555
556 /* Now we have the u8 offset - but need the u32 offset */
557 return offset / 4;
558 }
559
560 /* MSR not in any range */
561 return MSR_INVALID;
562 }
563
564 #define MAX_INST_SIZE 15
565
566 static inline void clgi(void)
567 {
568 asm volatile (__ex(SVM_CLGI));
569 }
570
571 static inline void stgi(void)
572 {
573 asm volatile (__ex(SVM_STGI));
574 }
575
576 static inline void invlpga(unsigned long addr, u32 asid)
577 {
578 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
579 }
580
581 static int get_npt_level(void)
582 {
583 #ifdef CONFIG_X86_64
584 return PT64_ROOT_LEVEL;
585 #else
586 return PT32E_ROOT_LEVEL;
587 #endif
588 }
589
590 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
591 {
592 vcpu->arch.efer = efer;
593 if (!npt_enabled && !(efer & EFER_LMA))
594 efer &= ~EFER_LME;
595
596 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
597 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
598 }
599
600 static int is_external_interrupt(u32 info)
601 {
602 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
603 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
604 }
605
606 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
607 {
608 struct vcpu_svm *svm = to_svm(vcpu);
609 u32 ret = 0;
610
611 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
612 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
613 return ret;
614 }
615
616 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
617 {
618 struct vcpu_svm *svm = to_svm(vcpu);
619
620 if (mask == 0)
621 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
622 else
623 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
624
625 }
626
627 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
628 {
629 struct vcpu_svm *svm = to_svm(vcpu);
630
631 if (svm->vmcb->control.next_rip != 0) {
632 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
633 svm->next_rip = svm->vmcb->control.next_rip;
634 }
635
636 if (!svm->next_rip) {
637 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
638 EMULATE_DONE)
639 printk(KERN_DEBUG "%s: NOP\n", __func__);
640 return;
641 }
642 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
643 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
644 __func__, kvm_rip_read(vcpu), svm->next_rip);
645
646 kvm_rip_write(vcpu, svm->next_rip);
647 svm_set_interrupt_shadow(vcpu, 0);
648 }
649
650 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
651 bool has_error_code, u32 error_code,
652 bool reinject)
653 {
654 struct vcpu_svm *svm = to_svm(vcpu);
655
656 /*
657 * If we are within a nested VM we'd better #VMEXIT and let the guest
658 * handle the exception
659 */
660 if (!reinject &&
661 nested_svm_check_exception(svm, nr, has_error_code, error_code))
662 return;
663
664 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
665 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
666
667 /*
668 * For guest debugging where we have to reinject #BP if some
669 * INT3 is guest-owned:
670 * Emulate nRIP by moving RIP forward. Will fail if injection
671 * raises a fault that is not intercepted. Still better than
672 * failing in all cases.
673 */
674 skip_emulated_instruction(&svm->vcpu);
675 rip = kvm_rip_read(&svm->vcpu);
676 svm->int3_rip = rip + svm->vmcb->save.cs.base;
677 svm->int3_injected = rip - old_rip;
678 }
679
680 svm->vmcb->control.event_inj = nr
681 | SVM_EVTINJ_VALID
682 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
683 | SVM_EVTINJ_TYPE_EXEPT;
684 svm->vmcb->control.event_inj_err = error_code;
685 }
686
687 static void svm_init_erratum_383(void)
688 {
689 u32 low, high;
690 int err;
691 u64 val;
692
693 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
694 return;
695
696 /* Use _safe variants to not break nested virtualization */
697 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
698 if (err)
699 return;
700
701 val |= (1ULL << 47);
702
703 low = lower_32_bits(val);
704 high = upper_32_bits(val);
705
706 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
707
708 erratum_383_found = true;
709 }
710
711 static void svm_init_osvw(struct kvm_vcpu *vcpu)
712 {
713 /*
714 * Guests should see errata 400 and 415 as fixed (assuming that
715 * HLT and IO instructions are intercepted).
716 */
717 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
718 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
719
720 /*
721 * By increasing VCPU's osvw.length to 3 we are telling the guest that
722 * all osvw.status bits inside that length, including bit 0 (which is
723 * reserved for erratum 298), are valid. However, if host processor's
724 * osvw_len is 0 then osvw_status[0] carries no information. We need to
725 * be conservative here and therefore we tell the guest that erratum 298
726 * is present (because we really don't know).
727 */
728 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
729 vcpu->arch.osvw.status |= 1;
730 }
731
732 static int has_svm(void)
733 {
734 const char *msg;
735
736 if (!cpu_has_svm(&msg)) {
737 printk(KERN_INFO "has_svm: %s\n", msg);
738 return 0;
739 }
740
741 return 1;
742 }
743
744 static void svm_hardware_disable(void)
745 {
746 /* Make sure we clean up behind us */
747 if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
748 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
749
750 cpu_svm_disable();
751
752 amd_pmu_disable_virt();
753 }
754
755 static int svm_hardware_enable(void)
756 {
757
758 struct svm_cpu_data *sd;
759 uint64_t efer;
760 struct desc_ptr gdt_descr;
761 struct desc_struct *gdt;
762 int me = raw_smp_processor_id();
763
764 rdmsrl(MSR_EFER, efer);
765 if (efer & EFER_SVME)
766 return -EBUSY;
767
768 if (!has_svm()) {
769 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
770 return -EINVAL;
771 }
772 sd = per_cpu(svm_data, me);
773 if (!sd) {
774 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
775 return -EINVAL;
776 }
777
778 sd->asid_generation = 1;
779 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
780 sd->next_asid = sd->max_asid + 1;
781
782 native_store_gdt(&gdt_descr);
783 gdt = (struct desc_struct *)gdt_descr.address;
784 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
785
786 wrmsrl(MSR_EFER, efer | EFER_SVME);
787
788 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
789
790 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
791 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
792 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
793 }
794
795
796 /*
797 * Get OSVW bits.
798 *
799 * Note that it is possible to have a system with mixed processor
800 * revisions and therefore different OSVW bits. If bits are not the same
801 * on different processors then choose the worst case (i.e. if erratum
802 * is present on one processor and not on another then assume that the
803 * erratum is present everywhere).
804 */
805 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
806 uint64_t len, status = 0;
807 int err;
808
809 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
810 if (!err)
811 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
812 &err);
813
814 if (err)
815 osvw_status = osvw_len = 0;
816 else {
817 if (len < osvw_len)
818 osvw_len = len;
819 osvw_status |= status;
820 osvw_status &= (1ULL << osvw_len) - 1;
821 }
822 } else
823 osvw_status = osvw_len = 0;
824
825 svm_init_erratum_383();
826
827 amd_pmu_enable_virt();
828
829 return 0;
830 }
831
832 static void svm_cpu_uninit(int cpu)
833 {
834 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
835
836 if (!sd)
837 return;
838
839 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
840 __free_page(sd->save_area);
841 kfree(sd);
842 }
843
844 static int svm_cpu_init(int cpu)
845 {
846 struct svm_cpu_data *sd;
847 int r;
848
849 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
850 if (!sd)
851 return -ENOMEM;
852 sd->cpu = cpu;
853 sd->save_area = alloc_page(GFP_KERNEL);
854 r = -ENOMEM;
855 if (!sd->save_area)
856 goto err_1;
857
858 per_cpu(svm_data, cpu) = sd;
859
860 return 0;
861
862 err_1:
863 kfree(sd);
864 return r;
865
866 }
867
868 static bool valid_msr_intercept(u32 index)
869 {
870 int i;
871
872 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
873 if (direct_access_msrs[i].index == index)
874 return true;
875
876 return false;
877 }
878
879 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, unsigned msr)
880 {
881 u8 bit_write;
882 unsigned long tmp;
883 u32 offset;
884 u32 *msrpm;
885
886 msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
887 to_svm(vcpu)->msrpm;
888
889 offset = svm_msrpm_offset(msr);
890 bit_write = 2 * (msr & 0x0f) + 1;
891 tmp = msrpm[offset];
892
893 BUG_ON(offset == MSR_INVALID);
894
895 return !!test_bit(bit_write, &tmp);
896 }
897
898 static void set_msr_interception(u32 *msrpm, unsigned msr,
899 int read, int write)
900 {
901 u8 bit_read, bit_write;
902 unsigned long tmp;
903 u32 offset;
904
905 /*
906 * If this warning triggers extend the direct_access_msrs list at the
907 * beginning of the file
908 */
909 WARN_ON(!valid_msr_intercept(msr));
910
911 offset = svm_msrpm_offset(msr);
912 bit_read = 2 * (msr & 0x0f);
913 bit_write = 2 * (msr & 0x0f) + 1;
914 tmp = msrpm[offset];
915
916 BUG_ON(offset == MSR_INVALID);
917
918 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
919 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
920
921 msrpm[offset] = tmp;
922 }
923
924 static void svm_vcpu_init_msrpm(u32 *msrpm)
925 {
926 int i;
927
928 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
929
930 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
931 if (!direct_access_msrs[i].always)
932 continue;
933
934 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
935 }
936 }
937
938 static void add_msr_offset(u32 offset)
939 {
940 int i;
941
942 for (i = 0; i < MSRPM_OFFSETS; ++i) {
943
944 /* Offset already in list? */
945 if (msrpm_offsets[i] == offset)
946 return;
947
948 /* Slot used by another offset? */
949 if (msrpm_offsets[i] != MSR_INVALID)
950 continue;
951
952 /* Add offset to list */
953 msrpm_offsets[i] = offset;
954
955 return;
956 }
957
958 /*
959 * If this BUG triggers the msrpm_offsets table has an overflow. Just
960 * increase MSRPM_OFFSETS in this case.
961 */
962 BUG();
963 }
964
965 static void init_msrpm_offsets(void)
966 {
967 int i;
968
969 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
970
971 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
972 u32 offset;
973
974 offset = svm_msrpm_offset(direct_access_msrs[i].index);
975 BUG_ON(offset == MSR_INVALID);
976
977 add_msr_offset(offset);
978 }
979 }
980
981 static void svm_enable_lbrv(struct vcpu_svm *svm)
982 {
983 u32 *msrpm = svm->msrpm;
984
985 svm->vmcb->control.lbr_ctl = 1;
986 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
987 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
988 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
989 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
990 }
991
992 static void svm_disable_lbrv(struct vcpu_svm *svm)
993 {
994 u32 *msrpm = svm->msrpm;
995
996 svm->vmcb->control.lbr_ctl = 0;
997 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
998 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
999 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
1000 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
1001 }
1002
1003 /* Note:
1004 * This hash table is used to map VM_ID to a struct kvm_arch,
1005 * when handling AMD IOMMU GALOG notification to schedule in
1006 * a particular vCPU.
1007 */
1008 #define SVM_VM_DATA_HASH_BITS 8
1009 DECLARE_HASHTABLE(svm_vm_data_hash, SVM_VM_DATA_HASH_BITS);
1010 static spinlock_t svm_vm_data_hash_lock;
1011
1012 /* Note:
1013 * This function is called from IOMMU driver to notify
1014 * SVM to schedule in a particular vCPU of a particular VM.
1015 */
1016 static int avic_ga_log_notifier(u32 ga_tag)
1017 {
1018 unsigned long flags;
1019 struct kvm_arch *ka = NULL;
1020 struct kvm_vcpu *vcpu = NULL;
1021 u32 vm_id = AVIC_GATAG_TO_VMID(ga_tag);
1022 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(ga_tag);
1023
1024 pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__, vm_id, vcpu_id);
1025
1026 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1027 hash_for_each_possible(svm_vm_data_hash, ka, hnode, vm_id) {
1028 struct kvm *kvm = container_of(ka, struct kvm, arch);
1029 struct kvm_arch *vm_data = &kvm->arch;
1030
1031 if (vm_data->avic_vm_id != vm_id)
1032 continue;
1033 vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
1034 break;
1035 }
1036 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1037
1038 if (!vcpu)
1039 return 0;
1040
1041 /* Note:
1042 * At this point, the IOMMU should have already set the pending
1043 * bit in the vAPIC backing page. So, we just need to schedule
1044 * in the vcpu.
1045 */
1046 if (vcpu->mode == OUTSIDE_GUEST_MODE)
1047 kvm_vcpu_wake_up(vcpu);
1048
1049 return 0;
1050 }
1051
1052 static __init int svm_hardware_setup(void)
1053 {
1054 int cpu;
1055 struct page *iopm_pages;
1056 void *iopm_va;
1057 int r;
1058
1059 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
1060
1061 if (!iopm_pages)
1062 return -ENOMEM;
1063
1064 iopm_va = page_address(iopm_pages);
1065 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
1066 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
1067
1068 init_msrpm_offsets();
1069
1070 if (boot_cpu_has(X86_FEATURE_NX))
1071 kvm_enable_efer_bits(EFER_NX);
1072
1073 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
1074 kvm_enable_efer_bits(EFER_FFXSR);
1075
1076 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1077 kvm_has_tsc_control = true;
1078 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
1079 kvm_tsc_scaling_ratio_frac_bits = 32;
1080 }
1081
1082 if (nested) {
1083 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
1084 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
1085 }
1086
1087 for_each_possible_cpu(cpu) {
1088 r = svm_cpu_init(cpu);
1089 if (r)
1090 goto err;
1091 }
1092
1093 if (!boot_cpu_has(X86_FEATURE_NPT))
1094 npt_enabled = false;
1095
1096 if (npt_enabled && !npt) {
1097 printk(KERN_INFO "kvm: Nested Paging disabled\n");
1098 npt_enabled = false;
1099 }
1100
1101 if (npt_enabled) {
1102 printk(KERN_INFO "kvm: Nested Paging enabled\n");
1103 kvm_enable_tdp();
1104 } else
1105 kvm_disable_tdp();
1106
1107 if (avic) {
1108 if (!npt_enabled ||
1109 !boot_cpu_has(X86_FEATURE_AVIC) ||
1110 !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
1111 avic = false;
1112 } else {
1113 pr_info("AVIC enabled\n");
1114
1115 hash_init(svm_vm_data_hash);
1116 spin_lock_init(&svm_vm_data_hash_lock);
1117 amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1118 }
1119 }
1120
1121 return 0;
1122
1123 err:
1124 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
1125 iopm_base = 0;
1126 return r;
1127 }
1128
1129 static __exit void svm_hardware_unsetup(void)
1130 {
1131 int cpu;
1132
1133 for_each_possible_cpu(cpu)
1134 svm_cpu_uninit(cpu);
1135
1136 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
1137 iopm_base = 0;
1138 }
1139
1140 static void init_seg(struct vmcb_seg *seg)
1141 {
1142 seg->selector = 0;
1143 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1144 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1145 seg->limit = 0xffff;
1146 seg->base = 0;
1147 }
1148
1149 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1150 {
1151 seg->selector = 0;
1152 seg->attrib = SVM_SELECTOR_P_MASK | type;
1153 seg->limit = 0xffff;
1154 seg->base = 0;
1155 }
1156
1157 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1158 {
1159 struct vcpu_svm *svm = to_svm(vcpu);
1160 u64 g_tsc_offset = 0;
1161
1162 if (is_guest_mode(vcpu)) {
1163 g_tsc_offset = svm->vmcb->control.tsc_offset -
1164 svm->nested.hsave->control.tsc_offset;
1165 svm->nested.hsave->control.tsc_offset = offset;
1166 } else
1167 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1168 svm->vmcb->control.tsc_offset,
1169 offset);
1170
1171 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1172
1173 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1174 }
1175
1176 static void avic_init_vmcb(struct vcpu_svm *svm)
1177 {
1178 struct vmcb *vmcb = svm->vmcb;
1179 struct kvm_arch *vm_data = &svm->vcpu.kvm->arch;
1180 phys_addr_t bpa = page_to_phys(svm->avic_backing_page);
1181 phys_addr_t lpa = page_to_phys(vm_data->avic_logical_id_table_page);
1182 phys_addr_t ppa = page_to_phys(vm_data->avic_physical_id_table_page);
1183
1184 vmcb->control.avic_backing_page = bpa & AVIC_HPA_MASK;
1185 vmcb->control.avic_logical_id = lpa & AVIC_HPA_MASK;
1186 vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK;
1187 vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT;
1188 vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
1189 svm->vcpu.arch.apicv_active = true;
1190 }
1191
1192 static void init_vmcb(struct vcpu_svm *svm)
1193 {
1194 struct vmcb_control_area *control = &svm->vmcb->control;
1195 struct vmcb_save_area *save = &svm->vmcb->save;
1196
1197 svm->vcpu.fpu_active = 1;
1198 svm->vcpu.arch.hflags = 0;
1199
1200 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1201 set_cr_intercept(svm, INTERCEPT_CR3_READ);
1202 set_cr_intercept(svm, INTERCEPT_CR4_READ);
1203 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1204 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1205 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1206 if (!kvm_vcpu_apicv_active(&svm->vcpu))
1207 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1208
1209 set_dr_intercepts(svm);
1210
1211 set_exception_intercept(svm, PF_VECTOR);
1212 set_exception_intercept(svm, UD_VECTOR);
1213 set_exception_intercept(svm, MC_VECTOR);
1214 set_exception_intercept(svm, AC_VECTOR);
1215 set_exception_intercept(svm, DB_VECTOR);
1216
1217 set_intercept(svm, INTERCEPT_INTR);
1218 set_intercept(svm, INTERCEPT_NMI);
1219 set_intercept(svm, INTERCEPT_SMI);
1220 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1221 set_intercept(svm, INTERCEPT_RDPMC);
1222 set_intercept(svm, INTERCEPT_CPUID);
1223 set_intercept(svm, INTERCEPT_INVD);
1224 set_intercept(svm, INTERCEPT_HLT);
1225 set_intercept(svm, INTERCEPT_INVLPG);
1226 set_intercept(svm, INTERCEPT_INVLPGA);
1227 set_intercept(svm, INTERCEPT_IOIO_PROT);
1228 set_intercept(svm, INTERCEPT_MSR_PROT);
1229 set_intercept(svm, INTERCEPT_TASK_SWITCH);
1230 set_intercept(svm, INTERCEPT_SHUTDOWN);
1231 set_intercept(svm, INTERCEPT_VMRUN);
1232 set_intercept(svm, INTERCEPT_VMMCALL);
1233 set_intercept(svm, INTERCEPT_VMLOAD);
1234 set_intercept(svm, INTERCEPT_VMSAVE);
1235 set_intercept(svm, INTERCEPT_STGI);
1236 set_intercept(svm, INTERCEPT_CLGI);
1237 set_intercept(svm, INTERCEPT_SKINIT);
1238 set_intercept(svm, INTERCEPT_WBINVD);
1239 set_intercept(svm, INTERCEPT_MONITOR);
1240 set_intercept(svm, INTERCEPT_MWAIT);
1241 set_intercept(svm, INTERCEPT_XSETBV);
1242
1243 control->iopm_base_pa = iopm_base;
1244 control->msrpm_base_pa = __pa(svm->msrpm);
1245 control->int_ctl = V_INTR_MASKING_MASK;
1246
1247 init_seg(&save->es);
1248 init_seg(&save->ss);
1249 init_seg(&save->ds);
1250 init_seg(&save->fs);
1251 init_seg(&save->gs);
1252
1253 save->cs.selector = 0xf000;
1254 save->cs.base = 0xffff0000;
1255 /* Executable/Readable Code Segment */
1256 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1257 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1258 save->cs.limit = 0xffff;
1259
1260 save->gdtr.limit = 0xffff;
1261 save->idtr.limit = 0xffff;
1262
1263 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1264 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1265
1266 svm_set_efer(&svm->vcpu, 0);
1267 save->dr6 = 0xffff0ff0;
1268 kvm_set_rflags(&svm->vcpu, 2);
1269 save->rip = 0x0000fff0;
1270 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1271
1272 /*
1273 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1274 * It also updates the guest-visible cr0 value.
1275 */
1276 svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1277 kvm_mmu_reset_context(&svm->vcpu);
1278
1279 save->cr4 = X86_CR4_PAE;
1280 /* rdx = ?? */
1281
1282 if (npt_enabled) {
1283 /* Setup VMCB for Nested Paging */
1284 control->nested_ctl = 1;
1285 clr_intercept(svm, INTERCEPT_INVLPG);
1286 clr_exception_intercept(svm, PF_VECTOR);
1287 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1288 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1289 save->g_pat = svm->vcpu.arch.pat;
1290 save->cr3 = 0;
1291 save->cr4 = 0;
1292 }
1293 svm->asid_generation = 0;
1294
1295 svm->nested.vmcb = 0;
1296 svm->vcpu.arch.hflags = 0;
1297
1298 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1299 control->pause_filter_count = 3000;
1300 set_intercept(svm, INTERCEPT_PAUSE);
1301 }
1302
1303 if (avic)
1304 avic_init_vmcb(svm);
1305
1306 mark_all_dirty(svm->vmcb);
1307
1308 enable_gif(svm);
1309
1310 }
1311
1312 static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu, int index)
1313 {
1314 u64 *avic_physical_id_table;
1315 struct kvm_arch *vm_data = &vcpu->kvm->arch;
1316
1317 if (index >= AVIC_MAX_PHYSICAL_ID_COUNT)
1318 return NULL;
1319
1320 avic_physical_id_table = page_address(vm_data->avic_physical_id_table_page);
1321
1322 return &avic_physical_id_table[index];
1323 }
1324
1325 /**
1326 * Note:
1327 * AVIC hardware walks the nested page table to check permissions,
1328 * but does not use the SPA address specified in the leaf page
1329 * table entry since it uses address in the AVIC_BACKING_PAGE pointer
1330 * field of the VMCB. Therefore, we set up the
1331 * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here.
1332 */
1333 static int avic_init_access_page(struct kvm_vcpu *vcpu)
1334 {
1335 struct kvm *kvm = vcpu->kvm;
1336 int ret = 0;
1337
1338 mutex_lock(&kvm->slots_lock);
1339 if (kvm->arch.apic_access_page_done)
1340 goto out;
1341
1342 ret = __x86_set_memory_region(kvm,
1343 APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
1344 APIC_DEFAULT_PHYS_BASE,
1345 PAGE_SIZE);
1346 if (ret)
1347 goto out;
1348
1349 kvm->arch.apic_access_page_done = true;
1350 out:
1351 mutex_unlock(&kvm->slots_lock);
1352 return ret;
1353 }
1354
1355 static int avic_init_backing_page(struct kvm_vcpu *vcpu)
1356 {
1357 int ret;
1358 u64 *entry, new_entry;
1359 int id = vcpu->vcpu_id;
1360 struct vcpu_svm *svm = to_svm(vcpu);
1361
1362 ret = avic_init_access_page(vcpu);
1363 if (ret)
1364 return ret;
1365
1366 if (id >= AVIC_MAX_PHYSICAL_ID_COUNT)
1367 return -EINVAL;
1368
1369 if (!svm->vcpu.arch.apic->regs)
1370 return -EINVAL;
1371
1372 svm->avic_backing_page = virt_to_page(svm->vcpu.arch.apic->regs);
1373
1374 /* Setting AVIC backing page address in the phy APIC ID table */
1375 entry = avic_get_physical_id_entry(vcpu, id);
1376 if (!entry)
1377 return -EINVAL;
1378
1379 new_entry = READ_ONCE(*entry);
1380 new_entry = (page_to_phys(svm->avic_backing_page) &
1381 AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) |
1382 AVIC_PHYSICAL_ID_ENTRY_VALID_MASK;
1383 WRITE_ONCE(*entry, new_entry);
1384
1385 svm->avic_physical_id_cache = entry;
1386
1387 return 0;
1388 }
1389
1390 static inline int avic_get_next_vm_id(void)
1391 {
1392 int id;
1393
1394 spin_lock(&avic_vm_id_lock);
1395
1396 /* AVIC VM ID is one-based. */
1397 id = find_next_zero_bit(avic_vm_id_bitmap, AVIC_VM_ID_NR, 1);
1398 if (id <= AVIC_VM_ID_MASK)
1399 __set_bit(id, avic_vm_id_bitmap);
1400 else
1401 id = -EAGAIN;
1402
1403 spin_unlock(&avic_vm_id_lock);
1404 return id;
1405 }
1406
1407 static inline int avic_free_vm_id(int id)
1408 {
1409 if (id <= 0 || id > AVIC_VM_ID_MASK)
1410 return -EINVAL;
1411
1412 spin_lock(&avic_vm_id_lock);
1413 __clear_bit(id, avic_vm_id_bitmap);
1414 spin_unlock(&avic_vm_id_lock);
1415 return 0;
1416 }
1417
1418 static void avic_vm_destroy(struct kvm *kvm)
1419 {
1420 unsigned long flags;
1421 struct kvm_arch *vm_data = &kvm->arch;
1422
1423 if (!avic)
1424 return;
1425
1426 avic_free_vm_id(vm_data->avic_vm_id);
1427
1428 if (vm_data->avic_logical_id_table_page)
1429 __free_page(vm_data->avic_logical_id_table_page);
1430 if (vm_data->avic_physical_id_table_page)
1431 __free_page(vm_data->avic_physical_id_table_page);
1432
1433 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1434 hash_del(&vm_data->hnode);
1435 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1436 }
1437
1438 static int avic_vm_init(struct kvm *kvm)
1439 {
1440 unsigned long flags;
1441 int vm_id, err = -ENOMEM;
1442 struct kvm_arch *vm_data = &kvm->arch;
1443 struct page *p_page;
1444 struct page *l_page;
1445
1446 if (!avic)
1447 return 0;
1448
1449 vm_id = avic_get_next_vm_id();
1450 if (vm_id < 0)
1451 return vm_id;
1452 vm_data->avic_vm_id = (u32)vm_id;
1453
1454 /* Allocating physical APIC ID table (4KB) */
1455 p_page = alloc_page(GFP_KERNEL);
1456 if (!p_page)
1457 goto free_avic;
1458
1459 vm_data->avic_physical_id_table_page = p_page;
1460 clear_page(page_address(p_page));
1461
1462 /* Allocating logical APIC ID table (4KB) */
1463 l_page = alloc_page(GFP_KERNEL);
1464 if (!l_page)
1465 goto free_avic;
1466
1467 vm_data->avic_logical_id_table_page = l_page;
1468 clear_page(page_address(l_page));
1469
1470 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1471 hash_add(svm_vm_data_hash, &vm_data->hnode, vm_data->avic_vm_id);
1472 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1473
1474 return 0;
1475
1476 free_avic:
1477 avic_vm_destroy(kvm);
1478 return err;
1479 }
1480
1481 static inline int
1482 avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, bool r)
1483 {
1484 int ret = 0;
1485 unsigned long flags;
1486 struct amd_svm_iommu_ir *ir;
1487 struct vcpu_svm *svm = to_svm(vcpu);
1488
1489 if (!kvm_arch_has_assigned_device(vcpu->kvm))
1490 return 0;
1491
1492 /*
1493 * Here, we go through the per-vcpu ir_list to update all existing
1494 * interrupt remapping table entry targeting this vcpu.
1495 */
1496 spin_lock_irqsave(&svm->ir_list_lock, flags);
1497
1498 if (list_empty(&svm->ir_list))
1499 goto out;
1500
1501 list_for_each_entry(ir, &svm->ir_list, node) {
1502 ret = amd_iommu_update_ga(cpu, r, ir->data);
1503 if (ret)
1504 break;
1505 }
1506 out:
1507 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
1508 return ret;
1509 }
1510
1511 static void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1512 {
1513 u64 entry;
1514 /* ID = 0xff (broadcast), ID > 0xff (reserved) */
1515 int h_physical_id = kvm_cpu_get_apicid(cpu);
1516 struct vcpu_svm *svm = to_svm(vcpu);
1517
1518 if (!kvm_vcpu_apicv_active(vcpu))
1519 return;
1520
1521 /*
1522 * Since the host physical APIC id is 8 bits,
1523 * we can support host APIC ID upto 255.
1524 */
1525 if (WARN_ON(h_physical_id > AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK))
1526 return;
1527
1528 entry = READ_ONCE(*(svm->avic_physical_id_cache));
1529 WARN_ON(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
1530
1531 entry &= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK;
1532 entry |= (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK);
1533
1534 entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1535 if (svm->avic_is_running)
1536 entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1537
1538 WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
1539 avic_update_iommu_vcpu_affinity(vcpu, h_physical_id,
1540 svm->avic_is_running);
1541 }
1542
1543 static void avic_vcpu_put(struct kvm_vcpu *vcpu)
1544 {
1545 u64 entry;
1546 struct vcpu_svm *svm = to_svm(vcpu);
1547
1548 if (!kvm_vcpu_apicv_active(vcpu))
1549 return;
1550
1551 entry = READ_ONCE(*(svm->avic_physical_id_cache));
1552 if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK)
1553 avic_update_iommu_vcpu_affinity(vcpu, -1, 0);
1554
1555 entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1556 WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
1557 }
1558
1559 /**
1560 * This function is called during VCPU halt/unhalt.
1561 */
1562 static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run)
1563 {
1564 struct vcpu_svm *svm = to_svm(vcpu);
1565
1566 svm->avic_is_running = is_run;
1567 if (is_run)
1568 avic_vcpu_load(vcpu, vcpu->cpu);
1569 else
1570 avic_vcpu_put(vcpu);
1571 }
1572
1573 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1574 {
1575 struct vcpu_svm *svm = to_svm(vcpu);
1576 u32 dummy;
1577 u32 eax = 1;
1578
1579 vcpu->arch.microcode_version = 0x01000065;
1580 svm->spec_ctrl = 0;
1581 svm->virt_spec_ctrl = 0;
1582
1583 if (!init_event) {
1584 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1585 MSR_IA32_APICBASE_ENABLE;
1586 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
1587 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1588 }
1589 init_vmcb(svm);
1590
1591 kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy);
1592 kvm_register_write(vcpu, VCPU_REGS_RDX, eax);
1593
1594 if (kvm_vcpu_apicv_active(vcpu) && !init_event)
1595 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
1596 }
1597
1598 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1599 {
1600 struct vcpu_svm *svm;
1601 struct page *page;
1602 struct page *msrpm_pages;
1603 struct page *hsave_page;
1604 struct page *nested_msrpm_pages;
1605 int err;
1606
1607 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1608 if (!svm) {
1609 err = -ENOMEM;
1610 goto out;
1611 }
1612
1613 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1614 if (err)
1615 goto free_svm;
1616
1617 err = -ENOMEM;
1618 page = alloc_page(GFP_KERNEL);
1619 if (!page)
1620 goto uninit;
1621
1622 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1623 if (!msrpm_pages)
1624 goto free_page1;
1625
1626 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1627 if (!nested_msrpm_pages)
1628 goto free_page2;
1629
1630 hsave_page = alloc_page(GFP_KERNEL);
1631 if (!hsave_page)
1632 goto free_page3;
1633
1634 if (avic) {
1635 err = avic_init_backing_page(&svm->vcpu);
1636 if (err)
1637 goto free_page4;
1638
1639 INIT_LIST_HEAD(&svm->ir_list);
1640 spin_lock_init(&svm->ir_list_lock);
1641 }
1642
1643 /* We initialize this flag to true to make sure that the is_running
1644 * bit would be set the first time the vcpu is loaded.
1645 */
1646 svm->avic_is_running = true;
1647
1648 svm->nested.hsave = page_address(hsave_page);
1649
1650 svm->msrpm = page_address(msrpm_pages);
1651 svm_vcpu_init_msrpm(svm->msrpm);
1652
1653 svm->nested.msrpm = page_address(nested_msrpm_pages);
1654 svm_vcpu_init_msrpm(svm->nested.msrpm);
1655
1656 svm->vmcb = page_address(page);
1657 clear_page(svm->vmcb);
1658 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1659 svm->asid_generation = 0;
1660 init_vmcb(svm);
1661
1662 svm_init_osvw(&svm->vcpu);
1663
1664 return &svm->vcpu;
1665
1666 free_page4:
1667 __free_page(hsave_page);
1668 free_page3:
1669 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1670 free_page2:
1671 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1672 free_page1:
1673 __free_page(page);
1674 uninit:
1675 kvm_vcpu_uninit(&svm->vcpu);
1676 free_svm:
1677 kmem_cache_free(kvm_vcpu_cache, svm);
1678 out:
1679 return ERR_PTR(err);
1680 }
1681
1682 static void svm_clear_current_vmcb(struct vmcb *vmcb)
1683 {
1684 int i;
1685
1686 for_each_online_cpu(i)
1687 cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL);
1688 }
1689
1690 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1691 {
1692 struct vcpu_svm *svm = to_svm(vcpu);
1693
1694 /*
1695 * The vmcb page can be recycled, causing a false negative in
1696 * svm_vcpu_load(). So, ensure that no logical CPU has this
1697 * vmcb page recorded as its current vmcb.
1698 */
1699 svm_clear_current_vmcb(svm->vmcb);
1700
1701 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1702 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1703 __free_page(virt_to_page(svm->nested.hsave));
1704 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1705 kvm_vcpu_uninit(vcpu);
1706 kmem_cache_free(kvm_vcpu_cache, svm);
1707 }
1708
1709 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1710 {
1711 struct vcpu_svm *svm = to_svm(vcpu);
1712 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
1713 int i;
1714
1715 if (unlikely(cpu != vcpu->cpu)) {
1716 svm->asid_generation = 0;
1717 mark_all_dirty(svm->vmcb);
1718 }
1719
1720 #ifdef CONFIG_X86_64
1721 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1722 #endif
1723 savesegment(fs, svm->host.fs);
1724 savesegment(gs, svm->host.gs);
1725 svm->host.ldt = kvm_read_ldt();
1726
1727 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1728 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1729
1730 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1731 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
1732 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1733 __this_cpu_write(current_tsc_ratio, tsc_ratio);
1734 wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
1735 }
1736 }
1737 /* This assumes that the kernel never uses MSR_TSC_AUX */
1738 if (static_cpu_has(X86_FEATURE_RDTSCP))
1739 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
1740
1741 if (sd->current_vmcb != svm->vmcb) {
1742 sd->current_vmcb = svm->vmcb;
1743 indirect_branch_prediction_barrier();
1744 }
1745 avic_vcpu_load(vcpu, cpu);
1746 }
1747
1748 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1749 {
1750 struct vcpu_svm *svm = to_svm(vcpu);
1751 int i;
1752
1753 avic_vcpu_put(vcpu);
1754
1755 ++vcpu->stat.host_state_reload;
1756 kvm_load_ldt(svm->host.ldt);
1757 #ifdef CONFIG_X86_64
1758 loadsegment(fs, svm->host.fs);
1759 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
1760 load_gs_index(svm->host.gs);
1761 #else
1762 #ifdef CONFIG_X86_32_LAZY_GS
1763 loadsegment(gs, svm->host.gs);
1764 #endif
1765 #endif
1766 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1767 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1768 }
1769
1770 static void svm_vcpu_blocking(struct kvm_vcpu *vcpu)
1771 {
1772 avic_set_running(vcpu, false);
1773 }
1774
1775 static void svm_vcpu_unblocking(struct kvm_vcpu *vcpu)
1776 {
1777 avic_set_running(vcpu, true);
1778 }
1779
1780 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1781 {
1782 return to_svm(vcpu)->vmcb->save.rflags;
1783 }
1784
1785 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1786 {
1787 /*
1788 * Any change of EFLAGS.VM is accompanied by a reload of SS
1789 * (caused by either a task switch or an inter-privilege IRET),
1790 * so we do not need to update the CPL here.
1791 */
1792 to_svm(vcpu)->vmcb->save.rflags = rflags;
1793 }
1794
1795 static u32 svm_get_pkru(struct kvm_vcpu *vcpu)
1796 {
1797 return 0;
1798 }
1799
1800 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1801 {
1802 switch (reg) {
1803 case VCPU_EXREG_PDPTR:
1804 BUG_ON(!npt_enabled);
1805 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1806 break;
1807 default:
1808 BUG();
1809 }
1810 }
1811
1812 static void svm_set_vintr(struct vcpu_svm *svm)
1813 {
1814 set_intercept(svm, INTERCEPT_VINTR);
1815 }
1816
1817 static void svm_clear_vintr(struct vcpu_svm *svm)
1818 {
1819 clr_intercept(svm, INTERCEPT_VINTR);
1820 }
1821
1822 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1823 {
1824 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1825
1826 switch (seg) {
1827 case VCPU_SREG_CS: return &save->cs;
1828 case VCPU_SREG_DS: return &save->ds;
1829 case VCPU_SREG_ES: return &save->es;
1830 case VCPU_SREG_FS: return &save->fs;
1831 case VCPU_SREG_GS: return &save->gs;
1832 case VCPU_SREG_SS: return &save->ss;
1833 case VCPU_SREG_TR: return &save->tr;
1834 case VCPU_SREG_LDTR: return &save->ldtr;
1835 }
1836 BUG();
1837 return NULL;
1838 }
1839
1840 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1841 {
1842 struct vmcb_seg *s = svm_seg(vcpu, seg);
1843
1844 return s->base;
1845 }
1846
1847 static void svm_get_segment(struct kvm_vcpu *vcpu,
1848 struct kvm_segment *var, int seg)
1849 {
1850 struct vmcb_seg *s = svm_seg(vcpu, seg);
1851
1852 var->base = s->base;
1853 var->limit = s->limit;
1854 var->selector = s->selector;
1855 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1856 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1857 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1858 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1859 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1860 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1861 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1862
1863 /*
1864 * AMD CPUs circa 2014 track the G bit for all segments except CS.
1865 * However, the SVM spec states that the G bit is not observed by the
1866 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1867 * So let's synthesize a legal G bit for all segments, this helps
1868 * running KVM nested. It also helps cross-vendor migration, because
1869 * Intel's vmentry has a check on the 'G' bit.
1870 */
1871 var->g = s->limit > 0xfffff;
1872
1873 /*
1874 * AMD's VMCB does not have an explicit unusable field, so emulate it
1875 * for cross vendor migration purposes by "not present"
1876 */
1877 var->unusable = !var->present || (var->type == 0);
1878
1879 switch (seg) {
1880 case VCPU_SREG_TR:
1881 /*
1882 * Work around a bug where the busy flag in the tr selector
1883 * isn't exposed
1884 */
1885 var->type |= 0x2;
1886 break;
1887 case VCPU_SREG_DS:
1888 case VCPU_SREG_ES:
1889 case VCPU_SREG_FS:
1890 case VCPU_SREG_GS:
1891 /*
1892 * The accessed bit must always be set in the segment
1893 * descriptor cache, although it can be cleared in the
1894 * descriptor, the cached bit always remains at 1. Since
1895 * Intel has a check on this, set it here to support
1896 * cross-vendor migration.
1897 */
1898 if (!var->unusable)
1899 var->type |= 0x1;
1900 break;
1901 case VCPU_SREG_SS:
1902 /*
1903 * On AMD CPUs sometimes the DB bit in the segment
1904 * descriptor is left as 1, although the whole segment has
1905 * been made unusable. Clear it here to pass an Intel VMX
1906 * entry check when cross vendor migrating.
1907 */
1908 if (var->unusable)
1909 var->db = 0;
1910 /* This is symmetric with svm_set_segment() */
1911 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1912 break;
1913 }
1914 }
1915
1916 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1917 {
1918 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1919
1920 return save->cpl;
1921 }
1922
1923 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1924 {
1925 struct vcpu_svm *svm = to_svm(vcpu);
1926
1927 dt->size = svm->vmcb->save.idtr.limit;
1928 dt->address = svm->vmcb->save.idtr.base;
1929 }
1930
1931 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1932 {
1933 struct vcpu_svm *svm = to_svm(vcpu);
1934
1935 svm->vmcb->save.idtr.limit = dt->size;
1936 svm->vmcb->save.idtr.base = dt->address ;
1937 mark_dirty(svm->vmcb, VMCB_DT);
1938 }
1939
1940 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1941 {
1942 struct vcpu_svm *svm = to_svm(vcpu);
1943
1944 dt->size = svm->vmcb->save.gdtr.limit;
1945 dt->address = svm->vmcb->save.gdtr.base;
1946 }
1947
1948 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1949 {
1950 struct vcpu_svm *svm = to_svm(vcpu);
1951
1952 svm->vmcb->save.gdtr.limit = dt->size;
1953 svm->vmcb->save.gdtr.base = dt->address ;
1954 mark_dirty(svm->vmcb, VMCB_DT);
1955 }
1956
1957 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1958 {
1959 }
1960
1961 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
1962 {
1963 }
1964
1965 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1966 {
1967 }
1968
1969 static void update_cr0_intercept(struct vcpu_svm *svm)
1970 {
1971 ulong gcr0 = svm->vcpu.arch.cr0;
1972 u64 *hcr0 = &svm->vmcb->save.cr0;
1973
1974 if (!svm->vcpu.fpu_active)
1975 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1976 else
1977 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1978 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1979
1980 mark_dirty(svm->vmcb, VMCB_CR);
1981
1982 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1983 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1984 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1985 } else {
1986 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1987 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1988 }
1989 }
1990
1991 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1992 {
1993 struct vcpu_svm *svm = to_svm(vcpu);
1994
1995 #ifdef CONFIG_X86_64
1996 if (vcpu->arch.efer & EFER_LME) {
1997 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1998 vcpu->arch.efer |= EFER_LMA;
1999 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
2000 }
2001
2002 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
2003 vcpu->arch.efer &= ~EFER_LMA;
2004 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
2005 }
2006 }
2007 #endif
2008 vcpu->arch.cr0 = cr0;
2009
2010 if (!npt_enabled)
2011 cr0 |= X86_CR0_PG | X86_CR0_WP;
2012
2013 if (!vcpu->fpu_active)
2014 cr0 |= X86_CR0_TS;
2015 /*
2016 * re-enable caching here because the QEMU bios
2017 * does not do it - this results in some delay at
2018 * reboot
2019 */
2020 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
2021 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
2022 svm->vmcb->save.cr0 = cr0;
2023 mark_dirty(svm->vmcb, VMCB_CR);
2024 update_cr0_intercept(svm);
2025 }
2026
2027 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2028 {
2029 unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
2030 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
2031
2032 if (cr4 & X86_CR4_VMXE)
2033 return 1;
2034
2035 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
2036 svm_flush_tlb(vcpu);
2037
2038 vcpu->arch.cr4 = cr4;
2039 if (!npt_enabled)
2040 cr4 |= X86_CR4_PAE;
2041 cr4 |= host_cr4_mce;
2042 to_svm(vcpu)->vmcb->save.cr4 = cr4;
2043 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
2044 return 0;
2045 }
2046
2047 static void svm_set_segment(struct kvm_vcpu *vcpu,
2048 struct kvm_segment *var, int seg)
2049 {
2050 struct vcpu_svm *svm = to_svm(vcpu);
2051 struct vmcb_seg *s = svm_seg(vcpu, seg);
2052
2053 s->base = var->base;
2054 s->limit = var->limit;
2055 s->selector = var->selector;
2056 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
2057 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
2058 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
2059 s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
2060 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
2061 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
2062 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
2063 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
2064
2065 /*
2066 * This is always accurate, except if SYSRET returned to a segment
2067 * with SS.DPL != 3. Intel does not have this quirk, and always
2068 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
2069 * would entail passing the CPL to userspace and back.
2070 */
2071 if (seg == VCPU_SREG_SS)
2072 /* This is symmetric with svm_get_segment() */
2073 svm->vmcb->save.cpl = (var->dpl & 3);
2074
2075 mark_dirty(svm->vmcb, VMCB_SEG);
2076 }
2077
2078 static void update_bp_intercept(struct kvm_vcpu *vcpu)
2079 {
2080 struct vcpu_svm *svm = to_svm(vcpu);
2081
2082 clr_exception_intercept(svm, BP_VECTOR);
2083
2084 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
2085 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2086 set_exception_intercept(svm, BP_VECTOR);
2087 } else
2088 vcpu->guest_debug = 0;
2089 }
2090
2091 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
2092 {
2093 if (sd->next_asid > sd->max_asid) {
2094 ++sd->asid_generation;
2095 sd->next_asid = 1;
2096 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
2097 }
2098
2099 svm->asid_generation = sd->asid_generation;
2100 svm->vmcb->control.asid = sd->next_asid++;
2101
2102 mark_dirty(svm->vmcb, VMCB_ASID);
2103 }
2104
2105 static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
2106 {
2107 return to_svm(vcpu)->vmcb->save.dr6;
2108 }
2109
2110 static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
2111 {
2112 struct vcpu_svm *svm = to_svm(vcpu);
2113
2114 svm->vmcb->save.dr6 = value;
2115 mark_dirty(svm->vmcb, VMCB_DR);
2116 }
2117
2118 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
2119 {
2120 struct vcpu_svm *svm = to_svm(vcpu);
2121
2122 get_debugreg(vcpu->arch.db[0], 0);
2123 get_debugreg(vcpu->arch.db[1], 1);
2124 get_debugreg(vcpu->arch.db[2], 2);
2125 get_debugreg(vcpu->arch.db[3], 3);
2126 vcpu->arch.dr6 = svm_get_dr6(vcpu);
2127 vcpu->arch.dr7 = svm->vmcb->save.dr7;
2128
2129 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
2130 set_dr_intercepts(svm);
2131 }
2132
2133 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
2134 {
2135 struct vcpu_svm *svm = to_svm(vcpu);
2136
2137 svm->vmcb->save.dr7 = value;
2138 mark_dirty(svm->vmcb, VMCB_DR);
2139 }
2140
2141 static int pf_interception(struct vcpu_svm *svm)
2142 {
2143 u64 fault_address = svm->vmcb->control.exit_info_2;
2144 u32 error_code;
2145 int r = 1;
2146
2147 svm->vcpu.arch.l1tf_flush_l1d = true;
2148
2149 switch (svm->apf_reason) {
2150 default:
2151 error_code = svm->vmcb->control.exit_info_1;
2152
2153 trace_kvm_page_fault(fault_address, error_code);
2154 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
2155 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
2156 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
2157 svm->vmcb->control.insn_bytes,
2158 svm->vmcb->control.insn_len);
2159 break;
2160 case KVM_PV_REASON_PAGE_NOT_PRESENT:
2161 svm->apf_reason = 0;
2162 local_irq_disable();
2163 kvm_async_pf_task_wait(fault_address);
2164 local_irq_enable();
2165 break;
2166 case KVM_PV_REASON_PAGE_READY:
2167 svm->apf_reason = 0;
2168 local_irq_disable();
2169 kvm_async_pf_task_wake(fault_address);
2170 local_irq_enable();
2171 break;
2172 }
2173 return r;
2174 }
2175
2176 static int db_interception(struct vcpu_svm *svm)
2177 {
2178 struct kvm_run *kvm_run = svm->vcpu.run;
2179
2180 if (!(svm->vcpu.guest_debug &
2181 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
2182 !svm->nmi_singlestep) {
2183 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
2184 return 1;
2185 }
2186
2187 if (svm->nmi_singlestep) {
2188 svm->nmi_singlestep = false;
2189 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
2190 svm->vmcb->save.rflags &=
2191 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
2192 }
2193
2194 if (svm->vcpu.guest_debug &
2195 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
2196 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2197 kvm_run->debug.arch.pc =
2198 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2199 kvm_run->debug.arch.exception = DB_VECTOR;
2200 return 0;
2201 }
2202
2203 return 1;
2204 }
2205
2206 static int bp_interception(struct vcpu_svm *svm)
2207 {
2208 struct kvm_run *kvm_run = svm->vcpu.run;
2209
2210 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2211 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2212 kvm_run->debug.arch.exception = BP_VECTOR;
2213 return 0;
2214 }
2215
2216 static int ud_interception(struct vcpu_svm *svm)
2217 {
2218 int er;
2219
2220 er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
2221 if (er == EMULATE_USER_EXIT)
2222 return 0;
2223 if (er != EMULATE_DONE)
2224 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2225 return 1;
2226 }
2227
2228 static int ac_interception(struct vcpu_svm *svm)
2229 {
2230 kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
2231 return 1;
2232 }
2233
2234 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
2235 {
2236 struct vcpu_svm *svm = to_svm(vcpu);
2237
2238 clr_exception_intercept(svm, NM_VECTOR);
2239
2240 svm->vcpu.fpu_active = 1;
2241 update_cr0_intercept(svm);
2242 }
2243
2244 static int nm_interception(struct vcpu_svm *svm)
2245 {
2246 svm_fpu_activate(&svm->vcpu);
2247 return 1;
2248 }
2249
2250 static bool is_erratum_383(void)
2251 {
2252 int err, i;
2253 u64 value;
2254
2255 if (!erratum_383_found)
2256 return false;
2257
2258 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
2259 if (err)
2260 return false;
2261
2262 /* Bit 62 may or may not be set for this mce */
2263 value &= ~(1ULL << 62);
2264
2265 if (value != 0xb600000000010015ULL)
2266 return false;
2267
2268 /* Clear MCi_STATUS registers */
2269 for (i = 0; i < 6; ++i)
2270 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
2271
2272 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
2273 if (!err) {
2274 u32 low, high;
2275
2276 value &= ~(1ULL << 2);
2277 low = lower_32_bits(value);
2278 high = upper_32_bits(value);
2279
2280 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
2281 }
2282
2283 /* Flush tlb to evict multi-match entries */
2284 __flush_tlb_all();
2285
2286 return true;
2287 }
2288
2289 static void svm_handle_mce(struct vcpu_svm *svm)
2290 {
2291 if (is_erratum_383()) {
2292 /*
2293 * Erratum 383 triggered. Guest state is corrupt so kill the
2294 * guest.
2295 */
2296 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2297
2298 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
2299
2300 return;
2301 }
2302
2303 /*
2304 * On an #MC intercept the MCE handler is not called automatically in
2305 * the host. So do it by hand here.
2306 */
2307 asm volatile (
2308 "int $0x12\n");
2309 /* not sure if we ever come back to this point */
2310
2311 return;
2312 }
2313
2314 static int mc_interception(struct vcpu_svm *svm)
2315 {
2316 return 1;
2317 }
2318
2319 static int shutdown_interception(struct vcpu_svm *svm)
2320 {
2321 struct kvm_run *kvm_run = svm->vcpu.run;
2322
2323 /*
2324 * VMCB is undefined after a SHUTDOWN intercept
2325 * so reinitialize it.
2326 */
2327 clear_page(svm->vmcb);
2328 init_vmcb(svm);
2329
2330 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2331 return 0;
2332 }
2333
2334 static int io_interception(struct vcpu_svm *svm)
2335 {
2336 struct kvm_vcpu *vcpu = &svm->vcpu;
2337 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2338 int size, in, string;
2339 unsigned port;
2340
2341 ++svm->vcpu.stat.io_exits;
2342 string = (io_info & SVM_IOIO_STR_MASK) != 0;
2343 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2344 if (string || in)
2345 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
2346
2347 port = io_info >> 16;
2348 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2349 svm->next_rip = svm->vmcb->control.exit_info_2;
2350 skip_emulated_instruction(&svm->vcpu);
2351
2352 return kvm_fast_pio_out(vcpu, size, port);
2353 }
2354
2355 static int nmi_interception(struct vcpu_svm *svm)
2356 {
2357 return 1;
2358 }
2359
2360 static int intr_interception(struct vcpu_svm *svm)
2361 {
2362 ++svm->vcpu.stat.irq_exits;
2363 return 1;
2364 }
2365
2366 static int nop_on_interception(struct vcpu_svm *svm)
2367 {
2368 return 1;
2369 }
2370
2371 static int halt_interception(struct vcpu_svm *svm)
2372 {
2373 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
2374 return kvm_emulate_halt(&svm->vcpu);
2375 }
2376
2377 static int vmmcall_interception(struct vcpu_svm *svm)
2378 {
2379 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2380 return kvm_emulate_hypercall(&svm->vcpu);
2381 }
2382
2383 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
2384 {
2385 struct vcpu_svm *svm = to_svm(vcpu);
2386
2387 return svm->nested.nested_cr3;
2388 }
2389
2390 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
2391 {
2392 struct vcpu_svm *svm = to_svm(vcpu);
2393 u64 cr3 = svm->nested.nested_cr3;
2394 u64 pdpte;
2395 int ret;
2396
2397 ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(cr3), &pdpte,
2398 offset_in_page(cr3) + index * 8, 8);
2399 if (ret)
2400 return 0;
2401 return pdpte;
2402 }
2403
2404 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
2405 unsigned long root)
2406 {
2407 struct vcpu_svm *svm = to_svm(vcpu);
2408
2409 svm->vmcb->control.nested_cr3 = root;
2410 mark_dirty(svm->vmcb, VMCB_NPT);
2411 svm_flush_tlb(vcpu);
2412 }
2413
2414 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
2415 struct x86_exception *fault)
2416 {
2417 struct vcpu_svm *svm = to_svm(vcpu);
2418
2419 if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) {
2420 /*
2421 * TODO: track the cause of the nested page fault, and
2422 * correctly fill in the high bits of exit_info_1.
2423 */
2424 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
2425 svm->vmcb->control.exit_code_hi = 0;
2426 svm->vmcb->control.exit_info_1 = (1ULL << 32);
2427 svm->vmcb->control.exit_info_2 = fault->address;
2428 }
2429
2430 svm->vmcb->control.exit_info_1 &= ~0xffffffffULL;
2431 svm->vmcb->control.exit_info_1 |= fault->error_code;
2432
2433 /*
2434 * The present bit is always zero for page structure faults on real
2435 * hardware.
2436 */
2437 if (svm->vmcb->control.exit_info_1 & (2ULL << 32))
2438 svm->vmcb->control.exit_info_1 &= ~1;
2439
2440 nested_svm_vmexit(svm);
2441 }
2442
2443 static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
2444 {
2445 WARN_ON(mmu_is_nested(vcpu));
2446 kvm_init_shadow_mmu(vcpu);
2447 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
2448 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
2449 vcpu->arch.mmu.get_pdptr = nested_svm_get_tdp_pdptr;
2450 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
2451 vcpu->arch.mmu.shadow_root_level = get_npt_level();
2452 reset_shadow_zero_bits_mask(vcpu, &vcpu->arch.mmu);
2453 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
2454 }
2455
2456 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
2457 {
2458 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
2459 }
2460
2461 static int nested_svm_check_permissions(struct vcpu_svm *svm)
2462 {
2463 if (!(svm->vcpu.arch.efer & EFER_SVME)
2464 || !is_paging(&svm->vcpu)) {
2465 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2466 return 1;
2467 }
2468
2469 if (svm->vmcb->save.cpl) {
2470 kvm_inject_gp(&svm->vcpu, 0);
2471 return 1;
2472 }
2473
2474 return 0;
2475 }
2476
2477 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
2478 bool has_error_code, u32 error_code)
2479 {
2480 int vmexit;
2481
2482 if (!is_guest_mode(&svm->vcpu))
2483 return 0;
2484
2485 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
2486 svm->vmcb->control.exit_code_hi = 0;
2487 svm->vmcb->control.exit_info_1 = error_code;
2488 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
2489
2490 vmexit = nested_svm_intercept(svm);
2491 if (vmexit == NESTED_EXIT_DONE)
2492 svm->nested.exit_required = true;
2493
2494 return vmexit;
2495 }
2496
2497 /* This function returns true if it is save to enable the irq window */
2498 static inline bool nested_svm_intr(struct vcpu_svm *svm)
2499 {
2500 if (!is_guest_mode(&svm->vcpu))
2501 return true;
2502
2503 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2504 return true;
2505
2506 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
2507 return false;
2508
2509 /*
2510 * if vmexit was already requested (by intercepted exception
2511 * for instance) do not overwrite it with "external interrupt"
2512 * vmexit.
2513 */
2514 if (svm->nested.exit_required)
2515 return false;
2516
2517 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
2518 svm->vmcb->control.exit_info_1 = 0;
2519 svm->vmcb->control.exit_info_2 = 0;
2520
2521 if (svm->nested.intercept & 1ULL) {
2522 /*
2523 * The #vmexit can't be emulated here directly because this
2524 * code path runs with irqs and preemption disabled. A
2525 * #vmexit emulation might sleep. Only signal request for
2526 * the #vmexit here.
2527 */
2528 svm->nested.exit_required = true;
2529 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
2530 return false;
2531 }
2532
2533 return true;
2534 }
2535
2536 /* This function returns true if it is save to enable the nmi window */
2537 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
2538 {
2539 if (!is_guest_mode(&svm->vcpu))
2540 return true;
2541
2542 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
2543 return true;
2544
2545 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
2546 svm->nested.exit_required = true;
2547
2548 return false;
2549 }
2550
2551 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
2552 {
2553 struct page *page;
2554
2555 might_sleep();
2556
2557 page = kvm_vcpu_gfn_to_page(&svm->vcpu, gpa >> PAGE_SHIFT);
2558 if (is_error_page(page))
2559 goto error;
2560
2561 *_page = page;
2562
2563 return kmap(page);
2564
2565 error:
2566 kvm_inject_gp(&svm->vcpu, 0);
2567
2568 return NULL;
2569 }
2570
2571 static void nested_svm_unmap(struct page *page)
2572 {
2573 kunmap(page);
2574 kvm_release_page_dirty(page);
2575 }
2576
2577 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
2578 {
2579 unsigned port, size, iopm_len;
2580 u16 val, mask;
2581 u8 start_bit;
2582 u64 gpa;
2583
2584 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
2585 return NESTED_EXIT_HOST;
2586
2587 port = svm->vmcb->control.exit_info_1 >> 16;
2588 size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
2589 SVM_IOIO_SIZE_SHIFT;
2590 gpa = svm->nested.vmcb_iopm + (port / 8);
2591 start_bit = port % 8;
2592 iopm_len = (start_bit + size > 8) ? 2 : 1;
2593 mask = (0xf >> (4 - size)) << start_bit;
2594 val = 0;
2595
2596 if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len))
2597 return NESTED_EXIT_DONE;
2598
2599 return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2600 }
2601
2602 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
2603 {
2604 u32 offset, msr, value;
2605 int write, mask;
2606
2607 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2608 return NESTED_EXIT_HOST;
2609
2610 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2611 offset = svm_msrpm_offset(msr);
2612 write = svm->vmcb->control.exit_info_1 & 1;
2613 mask = 1 << ((2 * (msr & 0xf)) + write);
2614
2615 if (offset == MSR_INVALID)
2616 return NESTED_EXIT_DONE;
2617
2618 /* Offset is in 32 bit units but need in 8 bit units */
2619 offset *= 4;
2620
2621 if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4))
2622 return NESTED_EXIT_DONE;
2623
2624 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2625 }
2626
2627 static int nested_svm_exit_special(struct vcpu_svm *svm)
2628 {
2629 u32 exit_code = svm->vmcb->control.exit_code;
2630
2631 switch (exit_code) {
2632 case SVM_EXIT_INTR:
2633 case SVM_EXIT_NMI:
2634 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
2635 return NESTED_EXIT_HOST;
2636 case SVM_EXIT_NPF:
2637 /* For now we are always handling NPFs when using them */
2638 if (npt_enabled)
2639 return NESTED_EXIT_HOST;
2640 break;
2641 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
2642 /* When we're shadowing, trap PFs, but not async PF */
2643 if (!npt_enabled && svm->apf_reason == 0)
2644 return NESTED_EXIT_HOST;
2645 break;
2646 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
2647 nm_interception(svm);
2648 break;
2649 default:
2650 break;
2651 }
2652
2653 return NESTED_EXIT_CONTINUE;
2654 }
2655
2656 /*
2657 * If this function returns true, this #vmexit was already handled
2658 */
2659 static int nested_svm_intercept(struct vcpu_svm *svm)
2660 {
2661 u32 exit_code = svm->vmcb->control.exit_code;
2662 int vmexit = NESTED_EXIT_HOST;
2663
2664 switch (exit_code) {
2665 case SVM_EXIT_MSR:
2666 vmexit = nested_svm_exit_handled_msr(svm);
2667 break;
2668 case SVM_EXIT_IOIO:
2669 vmexit = nested_svm_intercept_ioio(svm);
2670 break;
2671 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2672 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2673 if (svm->nested.intercept_cr & bit)
2674 vmexit = NESTED_EXIT_DONE;
2675 break;
2676 }
2677 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2678 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2679 if (svm->nested.intercept_dr & bit)
2680 vmexit = NESTED_EXIT_DONE;
2681 break;
2682 }
2683 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2684 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2685 if (svm->nested.intercept_exceptions & excp_bits)
2686 vmexit = NESTED_EXIT_DONE;
2687 /* async page fault always cause vmexit */
2688 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2689 svm->apf_reason != 0)
2690 vmexit = NESTED_EXIT_DONE;
2691 break;
2692 }
2693 case SVM_EXIT_ERR: {
2694 vmexit = NESTED_EXIT_DONE;
2695 break;
2696 }
2697 default: {
2698 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2699 if (svm->nested.intercept & exit_bits)
2700 vmexit = NESTED_EXIT_DONE;
2701 }
2702 }
2703
2704 return vmexit;
2705 }
2706
2707 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2708 {
2709 int vmexit;
2710
2711 vmexit = nested_svm_intercept(svm);
2712
2713 if (vmexit == NESTED_EXIT_DONE)
2714 nested_svm_vmexit(svm);
2715
2716 return vmexit;
2717 }
2718
2719 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2720 {
2721 struct vmcb_control_area *dst = &dst_vmcb->control;
2722 struct vmcb_control_area *from = &from_vmcb->control;
2723
2724 dst->intercept_cr = from->intercept_cr;
2725 dst->intercept_dr = from->intercept_dr;
2726 dst->intercept_exceptions = from->intercept_exceptions;
2727 dst->intercept = from->intercept;
2728 dst->iopm_base_pa = from->iopm_base_pa;
2729 dst->msrpm_base_pa = from->msrpm_base_pa;
2730 dst->tsc_offset = from->tsc_offset;
2731 dst->asid = from->asid;
2732 dst->tlb_ctl = from->tlb_ctl;
2733 dst->int_ctl = from->int_ctl;
2734 dst->int_vector = from->int_vector;
2735 dst->int_state = from->int_state;
2736 dst->exit_code = from->exit_code;
2737 dst->exit_code_hi = from->exit_code_hi;
2738 dst->exit_info_1 = from->exit_info_1;
2739 dst->exit_info_2 = from->exit_info_2;
2740 dst->exit_int_info = from->exit_int_info;
2741 dst->exit_int_info_err = from->exit_int_info_err;
2742 dst->nested_ctl = from->nested_ctl;
2743 dst->event_inj = from->event_inj;
2744 dst->event_inj_err = from->event_inj_err;
2745 dst->nested_cr3 = from->nested_cr3;
2746 dst->lbr_ctl = from->lbr_ctl;
2747 }
2748
2749 static int nested_svm_vmexit(struct vcpu_svm *svm)
2750 {
2751 struct vmcb *nested_vmcb;
2752 struct vmcb *hsave = svm->nested.hsave;
2753 struct vmcb *vmcb = svm->vmcb;
2754 struct page *page;
2755
2756 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2757 vmcb->control.exit_info_1,
2758 vmcb->control.exit_info_2,
2759 vmcb->control.exit_int_info,
2760 vmcb->control.exit_int_info_err,
2761 KVM_ISA_SVM);
2762
2763 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2764 if (!nested_vmcb)
2765 return 1;
2766
2767 /* Exit Guest-Mode */
2768 leave_guest_mode(&svm->vcpu);
2769 svm->nested.vmcb = 0;
2770
2771 /* Give the current vmcb to the guest */
2772 disable_gif(svm);
2773
2774 nested_vmcb->save.es = vmcb->save.es;
2775 nested_vmcb->save.cs = vmcb->save.cs;
2776 nested_vmcb->save.ss = vmcb->save.ss;
2777 nested_vmcb->save.ds = vmcb->save.ds;
2778 nested_vmcb->save.gdtr = vmcb->save.gdtr;
2779 nested_vmcb->save.idtr = vmcb->save.idtr;
2780 nested_vmcb->save.efer = svm->vcpu.arch.efer;
2781 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2782 nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu);
2783 nested_vmcb->save.cr2 = vmcb->save.cr2;
2784 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
2785 nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
2786 nested_vmcb->save.rip = vmcb->save.rip;
2787 nested_vmcb->save.rsp = vmcb->save.rsp;
2788 nested_vmcb->save.rax = vmcb->save.rax;
2789 nested_vmcb->save.dr7 = vmcb->save.dr7;
2790 nested_vmcb->save.dr6 = vmcb->save.dr6;
2791 nested_vmcb->save.cpl = vmcb->save.cpl;
2792
2793 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
2794 nested_vmcb->control.int_vector = vmcb->control.int_vector;
2795 nested_vmcb->control.int_state = vmcb->control.int_state;
2796 nested_vmcb->control.exit_code = vmcb->control.exit_code;
2797 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
2798 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
2799 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
2800 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
2801 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2802
2803 if (svm->nrips_enabled)
2804 nested_vmcb->control.next_rip = vmcb->control.next_rip;
2805
2806 /*
2807 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2808 * to make sure that we do not lose injected events. So check event_inj
2809 * here and copy it to exit_int_info if it is valid.
2810 * Exit_int_info and event_inj can't be both valid because the case
2811 * below only happens on a VMRUN instruction intercept which has
2812 * no valid exit_int_info set.
2813 */
2814 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2815 struct vmcb_control_area *nc = &nested_vmcb->control;
2816
2817 nc->exit_int_info = vmcb->control.event_inj;
2818 nc->exit_int_info_err = vmcb->control.event_inj_err;
2819 }
2820
2821 nested_vmcb->control.tlb_ctl = 0;
2822 nested_vmcb->control.event_inj = 0;
2823 nested_vmcb->control.event_inj_err = 0;
2824
2825 /* We always set V_INTR_MASKING and remember the old value in hflags */
2826 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2827 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2828
2829 /* Restore the original control entries */
2830 copy_vmcb_control_area(vmcb, hsave);
2831
2832 kvm_clear_exception_queue(&svm->vcpu);
2833 kvm_clear_interrupt_queue(&svm->vcpu);
2834
2835 svm->nested.nested_cr3 = 0;
2836
2837 /* Restore selected save entries */
2838 svm->vmcb->save.es = hsave->save.es;
2839 svm->vmcb->save.cs = hsave->save.cs;
2840 svm->vmcb->save.ss = hsave->save.ss;
2841 svm->vmcb->save.ds = hsave->save.ds;
2842 svm->vmcb->save.gdtr = hsave->save.gdtr;
2843 svm->vmcb->save.idtr = hsave->save.idtr;
2844 kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
2845 svm_set_efer(&svm->vcpu, hsave->save.efer);
2846 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2847 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2848 if (npt_enabled) {
2849 svm->vmcb->save.cr3 = hsave->save.cr3;
2850 svm->vcpu.arch.cr3 = hsave->save.cr3;
2851 } else {
2852 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2853 }
2854 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2855 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2856 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2857 svm->vmcb->save.dr7 = 0;
2858 svm->vmcb->save.cpl = 0;
2859 svm->vmcb->control.exit_int_info = 0;
2860
2861 mark_all_dirty(svm->vmcb);
2862
2863 nested_svm_unmap(page);
2864
2865 nested_svm_uninit_mmu_context(&svm->vcpu);
2866 kvm_mmu_reset_context(&svm->vcpu);
2867 kvm_mmu_load(&svm->vcpu);
2868
2869 /*
2870 * Drop what we picked up for L2 via svm_complete_interrupts() so it
2871 * doesn't end up in L1.
2872 */
2873 svm->vcpu.arch.nmi_injected = false;
2874 kvm_clear_exception_queue(&svm->vcpu);
2875 kvm_clear_interrupt_queue(&svm->vcpu);
2876
2877 return 0;
2878 }
2879
2880 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2881 {
2882 /*
2883 * This function merges the msr permission bitmaps of kvm and the
2884 * nested vmcb. It is optimized in that it only merges the parts where
2885 * the kvm msr permission bitmap may contain zero bits
2886 */
2887 int i;
2888
2889 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2890 return true;
2891
2892 for (i = 0; i < MSRPM_OFFSETS; i++) {
2893 u32 value, p;
2894 u64 offset;
2895
2896 if (msrpm_offsets[i] == 0xffffffff)
2897 break;
2898
2899 p = msrpm_offsets[i];
2900 offset = svm->nested.vmcb_msrpm + (p * 4);
2901
2902 if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4))
2903 return false;
2904
2905 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2906 }
2907
2908 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2909
2910 return true;
2911 }
2912
2913 static bool nested_vmcb_checks(struct vmcb *vmcb)
2914 {
2915 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2916 return false;
2917
2918 if (vmcb->control.asid == 0)
2919 return false;
2920
2921 if (vmcb->control.nested_ctl && !npt_enabled)
2922 return false;
2923
2924 return true;
2925 }
2926
2927 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2928 {
2929 struct vmcb *nested_vmcb;
2930 struct vmcb *hsave = svm->nested.hsave;
2931 struct vmcb *vmcb = svm->vmcb;
2932 struct page *page;
2933 u64 vmcb_gpa;
2934
2935 vmcb_gpa = svm->vmcb->save.rax;
2936
2937 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2938 if (!nested_vmcb)
2939 return false;
2940
2941 if (!nested_vmcb_checks(nested_vmcb)) {
2942 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2943 nested_vmcb->control.exit_code_hi = 0;
2944 nested_vmcb->control.exit_info_1 = 0;
2945 nested_vmcb->control.exit_info_2 = 0;
2946
2947 nested_svm_unmap(page);
2948
2949 return false;
2950 }
2951
2952 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2953 nested_vmcb->save.rip,
2954 nested_vmcb->control.int_ctl,
2955 nested_vmcb->control.event_inj,
2956 nested_vmcb->control.nested_ctl);
2957
2958 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2959 nested_vmcb->control.intercept_cr >> 16,
2960 nested_vmcb->control.intercept_exceptions,
2961 nested_vmcb->control.intercept);
2962
2963 /* Clear internal status */
2964 kvm_clear_exception_queue(&svm->vcpu);
2965 kvm_clear_interrupt_queue(&svm->vcpu);
2966
2967 /*
2968 * Save the old vmcb, so we don't need to pick what we save, but can
2969 * restore everything when a VMEXIT occurs
2970 */
2971 hsave->save.es = vmcb->save.es;
2972 hsave->save.cs = vmcb->save.cs;
2973 hsave->save.ss = vmcb->save.ss;
2974 hsave->save.ds = vmcb->save.ds;
2975 hsave->save.gdtr = vmcb->save.gdtr;
2976 hsave->save.idtr = vmcb->save.idtr;
2977 hsave->save.efer = svm->vcpu.arch.efer;
2978 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
2979 hsave->save.cr4 = svm->vcpu.arch.cr4;
2980 hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
2981 hsave->save.rip = kvm_rip_read(&svm->vcpu);
2982 hsave->save.rsp = vmcb->save.rsp;
2983 hsave->save.rax = vmcb->save.rax;
2984 if (npt_enabled)
2985 hsave->save.cr3 = vmcb->save.cr3;
2986 else
2987 hsave->save.cr3 = kvm_read_cr3(&svm->vcpu);
2988
2989 copy_vmcb_control_area(hsave, vmcb);
2990
2991 if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
2992 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2993 else
2994 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2995
2996 if (nested_vmcb->control.nested_ctl) {
2997 kvm_mmu_unload(&svm->vcpu);
2998 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2999 nested_svm_init_mmu_context(&svm->vcpu);
3000 }
3001
3002 /* Load the nested guest state */
3003 svm->vmcb->save.es = nested_vmcb->save.es;
3004 svm->vmcb->save.cs = nested_vmcb->save.cs;
3005 svm->vmcb->save.ss = nested_vmcb->save.ss;
3006 svm->vmcb->save.ds = nested_vmcb->save.ds;
3007 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
3008 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
3009 kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
3010 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
3011 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
3012 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
3013 if (npt_enabled) {
3014 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
3015 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
3016 } else
3017 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
3018
3019 /* Guest paging mode is active - reset mmu */
3020 kvm_mmu_reset_context(&svm->vcpu);
3021
3022 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3023 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
3024 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
3025 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
3026
3027 /* In case we don't even reach vcpu_run, the fields are not updated */
3028 svm->vmcb->save.rax = nested_vmcb->save.rax;
3029 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
3030 svm->vmcb->save.rip = nested_vmcb->save.rip;
3031 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
3032 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
3033 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
3034
3035 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
3036 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
3037
3038 /* cache intercepts */
3039 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
3040 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
3041 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
3042 svm->nested.intercept = nested_vmcb->control.intercept;
3043
3044 svm_flush_tlb(&svm->vcpu);
3045 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3046 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
3047 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
3048 else
3049 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
3050
3051 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
3052 /* We only want the cr8 intercept bits of the guest */
3053 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
3054 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3055 }
3056
3057 /* We don't want to see VMMCALLs from a nested guest */
3058 clr_intercept(svm, INTERCEPT_VMMCALL);
3059
3060 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
3061 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
3062 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
3063 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
3064 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
3065 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
3066
3067 nested_svm_unmap(page);
3068
3069 /* Enter Guest-Mode */
3070 enter_guest_mode(&svm->vcpu);
3071
3072 /*
3073 * Merge guest and host intercepts - must be called with vcpu in
3074 * guest-mode to take affect here
3075 */
3076 recalc_intercepts(svm);
3077
3078 svm->nested.vmcb = vmcb_gpa;
3079
3080 enable_gif(svm);
3081
3082 mark_all_dirty(svm->vmcb);
3083
3084 return true;
3085 }
3086
3087 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
3088 {
3089 to_vmcb->save.fs = from_vmcb->save.fs;
3090 to_vmcb->save.gs = from_vmcb->save.gs;
3091 to_vmcb->save.tr = from_vmcb->save.tr;
3092 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
3093 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
3094 to_vmcb->save.star = from_vmcb->save.star;
3095 to_vmcb->save.lstar = from_vmcb->save.lstar;
3096 to_vmcb->save.cstar = from_vmcb->save.cstar;
3097 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
3098 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
3099 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
3100 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
3101 }
3102
3103 static int vmload_interception(struct vcpu_svm *svm)
3104 {
3105 struct vmcb *nested_vmcb;
3106 struct page *page;
3107
3108 if (nested_svm_check_permissions(svm))
3109 return 1;
3110
3111 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3112 if (!nested_vmcb)
3113 return 1;
3114
3115 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3116 skip_emulated_instruction(&svm->vcpu);
3117
3118 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
3119 nested_svm_unmap(page);
3120
3121 return 1;
3122 }
3123
3124 static int vmsave_interception(struct vcpu_svm *svm)
3125 {
3126 struct vmcb *nested_vmcb;
3127 struct page *page;
3128
3129 if (nested_svm_check_permissions(svm))
3130 return 1;
3131
3132 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3133 if (!nested_vmcb)
3134 return 1;
3135
3136 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3137 skip_emulated_instruction(&svm->vcpu);
3138
3139 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
3140 nested_svm_unmap(page);
3141
3142 return 1;
3143 }
3144
3145 static int vmrun_interception(struct vcpu_svm *svm)
3146 {
3147 if (nested_svm_check_permissions(svm))
3148 return 1;
3149
3150 /* Save rip after vmrun instruction */
3151 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
3152
3153 if (!nested_svm_vmrun(svm))
3154 return 1;
3155
3156 if (!nested_svm_vmrun_msrpm(svm))
3157 goto failed;
3158
3159 return 1;
3160
3161 failed:
3162
3163 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
3164 svm->vmcb->control.exit_code_hi = 0;
3165 svm->vmcb->control.exit_info_1 = 0;
3166 svm->vmcb->control.exit_info_2 = 0;
3167
3168 nested_svm_vmexit(svm);
3169
3170 return 1;
3171 }
3172
3173 static int stgi_interception(struct vcpu_svm *svm)
3174 {
3175 if (nested_svm_check_permissions(svm))
3176 return 1;
3177
3178 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3179 skip_emulated_instruction(&svm->vcpu);
3180 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3181
3182 enable_gif(svm);
3183
3184 return 1;
3185 }
3186
3187 static int clgi_interception(struct vcpu_svm *svm)
3188 {
3189 if (nested_svm_check_permissions(svm))
3190 return 1;
3191
3192 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3193 skip_emulated_instruction(&svm->vcpu);
3194
3195 disable_gif(svm);
3196
3197 /* After a CLGI no interrupts should come */
3198 if (!kvm_vcpu_apicv_active(&svm->vcpu)) {
3199 svm_clear_vintr(svm);
3200 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3201 mark_dirty(svm->vmcb, VMCB_INTR);
3202 }
3203
3204 return 1;
3205 }
3206
3207 static int invlpga_interception(struct vcpu_svm *svm)
3208 {
3209 struct kvm_vcpu *vcpu = &svm->vcpu;
3210
3211 trace_kvm_invlpga(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RCX),
3212 kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3213
3214 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
3215 kvm_mmu_invlpg(vcpu, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3216
3217 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3218 skip_emulated_instruction(&svm->vcpu);
3219 return 1;
3220 }
3221
3222 static int skinit_interception(struct vcpu_svm *svm)
3223 {
3224 trace_kvm_skinit(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3225
3226 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3227 return 1;
3228 }
3229
3230 static int wbinvd_interception(struct vcpu_svm *svm)
3231 {
3232 kvm_emulate_wbinvd(&svm->vcpu);
3233 return 1;
3234 }
3235
3236 static int xsetbv_interception(struct vcpu_svm *svm)
3237 {
3238 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
3239 u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3240
3241 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
3242 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3243 skip_emulated_instruction(&svm->vcpu);
3244 }
3245
3246 return 1;
3247 }
3248
3249 static int task_switch_interception(struct vcpu_svm *svm)
3250 {
3251 u16 tss_selector;
3252 int reason;
3253 int int_type = svm->vmcb->control.exit_int_info &
3254 SVM_EXITINTINFO_TYPE_MASK;
3255 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
3256 uint32_t type =
3257 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
3258 uint32_t idt_v =
3259 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
3260 bool has_error_code = false;
3261 u32 error_code = 0;
3262
3263 tss_selector = (u16)svm->vmcb->control.exit_info_1;
3264
3265 if (svm->vmcb->control.exit_info_2 &
3266 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
3267 reason = TASK_SWITCH_IRET;
3268 else if (svm->vmcb->control.exit_info_2 &
3269 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
3270 reason = TASK_SWITCH_JMP;
3271 else if (idt_v)
3272 reason = TASK_SWITCH_GATE;
3273 else
3274 reason = TASK_SWITCH_CALL;
3275
3276 if (reason == TASK_SWITCH_GATE) {
3277 switch (type) {
3278 case SVM_EXITINTINFO_TYPE_NMI:
3279 svm->vcpu.arch.nmi_injected = false;
3280 break;
3281 case SVM_EXITINTINFO_TYPE_EXEPT:
3282 if (svm->vmcb->control.exit_info_2 &
3283 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
3284 has_error_code = true;
3285 error_code =
3286 (u32)svm->vmcb->control.exit_info_2;
3287 }
3288 kvm_clear_exception_queue(&svm->vcpu);
3289 break;
3290 case SVM_EXITINTINFO_TYPE_INTR:
3291 kvm_clear_interrupt_queue(&svm->vcpu);
3292 break;
3293 default:
3294 break;
3295 }
3296 }
3297
3298 if (reason != TASK_SWITCH_GATE ||
3299 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
3300 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
3301 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
3302 skip_emulated_instruction(&svm->vcpu);
3303
3304 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
3305 int_vec = -1;
3306
3307 if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
3308 has_error_code, error_code) == EMULATE_FAIL) {
3309 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3310 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3311 svm->vcpu.run->internal.ndata = 0;
3312 return 0;
3313 }
3314 return 1;
3315 }
3316
3317 static int cpuid_interception(struct vcpu_svm *svm)
3318 {
3319 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3320 kvm_emulate_cpuid(&svm->vcpu);
3321 return 1;
3322 }
3323
3324 static int iret_interception(struct vcpu_svm *svm)
3325 {
3326 ++svm->vcpu.stat.nmi_window_exits;
3327 clr_intercept(svm, INTERCEPT_IRET);
3328 svm->vcpu.arch.hflags |= HF_IRET_MASK;
3329 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
3330 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3331 return 1;
3332 }
3333
3334 static int invlpg_interception(struct vcpu_svm *svm)
3335 {
3336 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3337 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3338
3339 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
3340 skip_emulated_instruction(&svm->vcpu);
3341 return 1;
3342 }
3343
3344 static int emulate_on_interception(struct vcpu_svm *svm)
3345 {
3346 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3347 }
3348
3349 static int rdpmc_interception(struct vcpu_svm *svm)
3350 {
3351 int err;
3352
3353 if (!static_cpu_has(X86_FEATURE_NRIPS))
3354 return emulate_on_interception(svm);
3355
3356 err = kvm_rdpmc(&svm->vcpu);
3357 kvm_complete_insn_gp(&svm->vcpu, err);
3358
3359 return 1;
3360 }
3361
3362 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
3363 unsigned long val)
3364 {
3365 unsigned long cr0 = svm->vcpu.arch.cr0;
3366 bool ret = false;
3367 u64 intercept;
3368
3369 intercept = svm->nested.intercept;
3370
3371 if (!is_guest_mode(&svm->vcpu) ||
3372 (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
3373 return false;
3374
3375 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
3376 val &= ~SVM_CR0_SELECTIVE_MASK;
3377
3378 if (cr0 ^ val) {
3379 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3380 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
3381 }
3382
3383 return ret;
3384 }
3385
3386 #define CR_VALID (1ULL << 63)
3387
3388 static int cr_interception(struct vcpu_svm *svm)
3389 {
3390 int reg, cr;
3391 unsigned long val;
3392 int err;
3393
3394 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3395 return emulate_on_interception(svm);
3396
3397 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
3398 return emulate_on_interception(svm);
3399
3400 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3401 if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
3402 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
3403 else
3404 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
3405
3406 err = 0;
3407 if (cr >= 16) { /* mov to cr */
3408 cr -= 16;
3409 val = kvm_register_read(&svm->vcpu, reg);
3410 switch (cr) {
3411 case 0:
3412 if (!check_selective_cr0_intercepted(svm, val))
3413 err = kvm_set_cr0(&svm->vcpu, val);
3414 else
3415 return 1;
3416
3417 break;
3418 case 3:
3419 err = kvm_set_cr3(&svm->vcpu, val);
3420 break;
3421 case 4:
3422 err = kvm_set_cr4(&svm->vcpu, val);
3423 break;
3424 case 8:
3425 err = kvm_set_cr8(&svm->vcpu, val);
3426 break;
3427 default:
3428 WARN(1, "unhandled write to CR%d", cr);
3429 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3430 return 1;
3431 }
3432 } else { /* mov from cr */
3433 switch (cr) {
3434 case 0:
3435 val = kvm_read_cr0(&svm->vcpu);
3436 break;
3437 case 2:
3438 val = svm->vcpu.arch.cr2;
3439 break;
3440 case 3:
3441 val = kvm_read_cr3(&svm->vcpu);
3442 break;
3443 case 4:
3444 val = kvm_read_cr4(&svm->vcpu);
3445 break;
3446 case 8:
3447 val = kvm_get_cr8(&svm->vcpu);
3448 break;
3449 default:
3450 WARN(1, "unhandled read from CR%d", cr);
3451 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3452 return 1;
3453 }
3454 kvm_register_write(&svm->vcpu, reg, val);
3455 }
3456 kvm_complete_insn_gp(&svm->vcpu, err);
3457
3458 return 1;
3459 }
3460
3461 static int dr_interception(struct vcpu_svm *svm)
3462 {
3463 int reg, dr;
3464 unsigned long val;
3465
3466 if (svm->vcpu.guest_debug == 0) {
3467 /*
3468 * No more DR vmexits; force a reload of the debug registers
3469 * and reenter on this instruction. The next vmexit will
3470 * retrieve the full state of the debug registers.
3471 */
3472 clr_dr_intercepts(svm);
3473 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
3474 return 1;
3475 }
3476
3477 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
3478 return emulate_on_interception(svm);
3479
3480 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3481 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
3482
3483 if (dr >= 16) { /* mov to DRn */
3484 if (!kvm_require_dr(&svm->vcpu, dr - 16))
3485 return 1;
3486 val = kvm_register_read(&svm->vcpu, reg);
3487 kvm_set_dr(&svm->vcpu, dr - 16, val);
3488 } else {
3489 if (!kvm_require_dr(&svm->vcpu, dr))
3490 return 1;
3491 kvm_get_dr(&svm->vcpu, dr, &val);
3492 kvm_register_write(&svm->vcpu, reg, val);
3493 }
3494
3495 skip_emulated_instruction(&svm->vcpu);
3496
3497 return 1;
3498 }
3499
3500 static int cr8_write_interception(struct vcpu_svm *svm)
3501 {
3502 struct kvm_run *kvm_run = svm->vcpu.run;
3503 int r;
3504
3505 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
3506 /* instruction emulation calls kvm_set_cr8() */
3507 r = cr_interception(svm);
3508 if (lapic_in_kernel(&svm->vcpu))
3509 return r;
3510 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
3511 return r;
3512 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
3513 return 0;
3514 }
3515
3516 static int svm_get_msr_feature(struct kvm_msr_entry *msr)
3517 {
3518 msr->data = 0;
3519
3520 switch (msr->index) {
3521 case MSR_F10H_DECFG:
3522 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
3523 msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
3524 break;
3525 default:
3526 return 1;
3527 }
3528
3529 return 0;
3530 }
3531
3532 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3533 {
3534 struct vcpu_svm *svm = to_svm(vcpu);
3535
3536 switch (msr_info->index) {
3537 case MSR_IA32_TSC: {
3538 msr_info->data = svm->vmcb->control.tsc_offset +
3539 kvm_scale_tsc(vcpu, rdtsc());
3540
3541 break;
3542 }
3543 case MSR_STAR:
3544 msr_info->data = svm->vmcb->save.star;
3545 break;
3546 #ifdef CONFIG_X86_64
3547 case MSR_LSTAR:
3548 msr_info->data = svm->vmcb->save.lstar;
3549 break;
3550 case MSR_CSTAR:
3551 msr_info->data = svm->vmcb->save.cstar;
3552 break;
3553 case MSR_KERNEL_GS_BASE:
3554 msr_info->data = svm->vmcb->save.kernel_gs_base;
3555 break;
3556 case MSR_SYSCALL_MASK:
3557 msr_info->data = svm->vmcb->save.sfmask;
3558 break;
3559 #endif
3560 case MSR_IA32_SYSENTER_CS:
3561 msr_info->data = svm->vmcb->save.sysenter_cs;
3562 break;
3563 case MSR_IA32_SYSENTER_EIP:
3564 msr_info->data = svm->sysenter_eip;
3565 break;
3566 case MSR_IA32_SYSENTER_ESP:
3567 msr_info->data = svm->sysenter_esp;
3568 break;
3569 case MSR_TSC_AUX:
3570 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
3571 return 1;
3572 msr_info->data = svm->tsc_aux;
3573 break;
3574 /*
3575 * Nobody will change the following 5 values in the VMCB so we can
3576 * safely return them on rdmsr. They will always be 0 until LBRV is
3577 * implemented.
3578 */
3579 case MSR_IA32_DEBUGCTLMSR:
3580 msr_info->data = svm->vmcb->save.dbgctl;
3581 break;
3582 case MSR_IA32_LASTBRANCHFROMIP:
3583 msr_info->data = svm->vmcb->save.br_from;
3584 break;
3585 case MSR_IA32_LASTBRANCHTOIP:
3586 msr_info->data = svm->vmcb->save.br_to;
3587 break;
3588 case MSR_IA32_LASTINTFROMIP:
3589 msr_info->data = svm->vmcb->save.last_excp_from;
3590 break;
3591 case MSR_IA32_LASTINTTOIP:
3592 msr_info->data = svm->vmcb->save.last_excp_to;
3593 break;
3594 case MSR_VM_HSAVE_PA:
3595 msr_info->data = svm->nested.hsave_msr;
3596 break;
3597 case MSR_VM_CR:
3598 msr_info->data = svm->nested.vm_cr_msr;
3599 break;
3600 case MSR_IA32_SPEC_CTRL:
3601 if (!msr_info->host_initiated &&
3602 !guest_cpuid_has_spec_ctrl(vcpu))
3603 return 1;
3604
3605 msr_info->data = svm->spec_ctrl;
3606 break;
3607 case MSR_AMD64_VIRT_SPEC_CTRL:
3608 if (!msr_info->host_initiated &&
3609 !guest_cpuid_has_virt_ssbd(vcpu))
3610 return 1;
3611
3612 msr_info->data = svm->virt_spec_ctrl;
3613 break;
3614 case MSR_F15H_IC_CFG: {
3615
3616 int family, model;
3617
3618 family = guest_cpuid_family(vcpu);
3619 model = guest_cpuid_model(vcpu);
3620
3621 if (family < 0 || model < 0)
3622 return kvm_get_msr_common(vcpu, msr_info);
3623
3624 msr_info->data = 0;
3625
3626 if (family == 0x15 &&
3627 (model >= 0x2 && model < 0x20))
3628 msr_info->data = 0x1E;
3629 }
3630 break;
3631 case MSR_F10H_DECFG:
3632 msr_info->data = svm->msr_decfg;
3633 break;
3634 default:
3635 return kvm_get_msr_common(vcpu, msr_info);
3636 }
3637 return 0;
3638 }
3639
3640 static int rdmsr_interception(struct vcpu_svm *svm)
3641 {
3642 u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3643 struct msr_data msr_info;
3644
3645 msr_info.index = ecx;
3646 msr_info.host_initiated = false;
3647 if (svm_get_msr(&svm->vcpu, &msr_info)) {
3648 trace_kvm_msr_read_ex(ecx);
3649 kvm_inject_gp(&svm->vcpu, 0);
3650 } else {
3651 trace_kvm_msr_read(ecx, msr_info.data);
3652
3653 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX,
3654 msr_info.data & 0xffffffff);
3655 kvm_register_write(&svm->vcpu, VCPU_REGS_RDX,
3656 msr_info.data >> 32);
3657 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3658 skip_emulated_instruction(&svm->vcpu);
3659 }
3660 return 1;
3661 }
3662
3663 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
3664 {
3665 struct vcpu_svm *svm = to_svm(vcpu);
3666 int svm_dis, chg_mask;
3667
3668 if (data & ~SVM_VM_CR_VALID_MASK)
3669 return 1;
3670
3671 chg_mask = SVM_VM_CR_VALID_MASK;
3672
3673 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
3674 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
3675
3676 svm->nested.vm_cr_msr &= ~chg_mask;
3677 svm->nested.vm_cr_msr |= (data & chg_mask);
3678
3679 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
3680
3681 /* check for svm_disable while efer.svme is set */
3682 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
3683 return 1;
3684
3685 return 0;
3686 }
3687
3688 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
3689 {
3690 struct vcpu_svm *svm = to_svm(vcpu);
3691
3692 u32 ecx = msr->index;
3693 u64 data = msr->data;
3694 switch (ecx) {
3695 case MSR_IA32_CR_PAT:
3696 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3697 return 1;
3698 vcpu->arch.pat = data;
3699 svm->vmcb->save.g_pat = data;
3700 mark_dirty(svm->vmcb, VMCB_NPT);
3701 break;
3702 case MSR_IA32_TSC:
3703 kvm_write_tsc(vcpu, msr);
3704 break;
3705 case MSR_IA32_SPEC_CTRL:
3706 if (!msr->host_initiated &&
3707 !guest_cpuid_has_spec_ctrl(vcpu))
3708 return 1;
3709
3710 /* The STIBP bit doesn't fault even if it's not advertised */
3711 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
3712 return 1;
3713
3714 svm->spec_ctrl = data;
3715
3716 if (!data)
3717 break;
3718
3719 /*
3720 * For non-nested:
3721 * When it's written (to non-zero) for the first time, pass
3722 * it through.
3723 *
3724 * For nested:
3725 * The handling of the MSR bitmap for L2 guests is done in
3726 * nested_svm_vmrun_msrpm.
3727 * We update the L1 MSR bit as well since it will end up
3728 * touching the MSR anyway now.
3729 */
3730 set_msr_interception(svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
3731 break;
3732 case MSR_IA32_PRED_CMD:
3733 if (!msr->host_initiated &&
3734 !guest_cpuid_has_ibpb(vcpu))
3735 return 1;
3736
3737 if (data & ~PRED_CMD_IBPB)
3738 return 1;
3739
3740 if (!data)
3741 break;
3742
3743 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
3744 if (is_guest_mode(vcpu))
3745 break;
3746 set_msr_interception(svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
3747 break;
3748 case MSR_AMD64_VIRT_SPEC_CTRL:
3749 if (!msr->host_initiated &&
3750 !guest_cpuid_has_virt_ssbd(vcpu))
3751 return 1;
3752
3753 if (data & ~SPEC_CTRL_SSBD)
3754 return 1;
3755
3756 svm->virt_spec_ctrl = data;
3757 break;
3758 case MSR_STAR:
3759 svm->vmcb->save.star = data;
3760 break;
3761 #ifdef CONFIG_X86_64
3762 case MSR_LSTAR:
3763 svm->vmcb->save.lstar = data;
3764 break;
3765 case MSR_CSTAR:
3766 svm->vmcb->save.cstar = data;
3767 break;
3768 case MSR_KERNEL_GS_BASE:
3769 svm->vmcb->save.kernel_gs_base = data;
3770 break;
3771 case MSR_SYSCALL_MASK:
3772 svm->vmcb->save.sfmask = data;
3773 break;
3774 #endif
3775 case MSR_IA32_SYSENTER_CS:
3776 svm->vmcb->save.sysenter_cs = data;
3777 break;
3778 case MSR_IA32_SYSENTER_EIP:
3779 svm->sysenter_eip = data;
3780 svm->vmcb->save.sysenter_eip = data;
3781 break;
3782 case MSR_IA32_SYSENTER_ESP:
3783 svm->sysenter_esp = data;
3784 svm->vmcb->save.sysenter_esp = data;
3785 break;
3786 case MSR_TSC_AUX:
3787 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
3788 return 1;
3789
3790 /*
3791 * This is rare, so we update the MSR here instead of using
3792 * direct_access_msrs. Doing that would require a rdmsr in
3793 * svm_vcpu_put.
3794 */
3795 svm->tsc_aux = data;
3796 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
3797 break;
3798 case MSR_IA32_DEBUGCTLMSR:
3799 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
3800 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3801 __func__, data);
3802 break;
3803 }
3804 if (data & DEBUGCTL_RESERVED_BITS)
3805 return 1;
3806
3807 svm->vmcb->save.dbgctl = data;
3808 mark_dirty(svm->vmcb, VMCB_LBR);
3809 if (data & (1ULL<<0))
3810 svm_enable_lbrv(svm);
3811 else
3812 svm_disable_lbrv(svm);
3813 break;
3814 case MSR_VM_HSAVE_PA:
3815 svm->nested.hsave_msr = data;
3816 break;
3817 case MSR_VM_CR:
3818 return svm_set_vm_cr(vcpu, data);
3819 case MSR_VM_IGNNE:
3820 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3821 break;
3822 case MSR_F10H_DECFG: {
3823 struct kvm_msr_entry msr_entry;
3824
3825 msr_entry.index = msr->index;
3826 if (svm_get_msr_feature(&msr_entry))
3827 return 1;
3828
3829 /* Check the supported bits */
3830 if (data & ~msr_entry.data)
3831 return 1;
3832
3833 /* Don't allow the guest to change a bit, #GP */
3834 if (!msr->host_initiated && (data ^ msr_entry.data))
3835 return 1;
3836
3837 svm->msr_decfg = data;
3838 break;
3839 }
3840 case MSR_IA32_APICBASE:
3841 if (kvm_vcpu_apicv_active(vcpu))
3842 avic_update_vapic_bar(to_svm(vcpu), data);
3843 /* Follow through */
3844 default:
3845 return kvm_set_msr_common(vcpu, msr);
3846 }
3847 return 0;
3848 }
3849
3850 static int wrmsr_interception(struct vcpu_svm *svm)
3851 {
3852 struct msr_data msr;
3853 u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3854 u64 data = kvm_read_edx_eax(&svm->vcpu);
3855
3856 msr.data = data;
3857 msr.index = ecx;
3858 msr.host_initiated = false;
3859
3860 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3861 if (kvm_set_msr(&svm->vcpu, &msr)) {
3862 trace_kvm_msr_write_ex(ecx, data);
3863 kvm_inject_gp(&svm->vcpu, 0);
3864 } else {
3865 trace_kvm_msr_write(ecx, data);
3866 skip_emulated_instruction(&svm->vcpu);
3867 }
3868 return 1;
3869 }
3870
3871 static int msr_interception(struct vcpu_svm *svm)
3872 {
3873 if (svm->vmcb->control.exit_info_1)
3874 return wrmsr_interception(svm);
3875 else
3876 return rdmsr_interception(svm);
3877 }
3878
3879 static int interrupt_window_interception(struct vcpu_svm *svm)
3880 {
3881 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3882 svm_clear_vintr(svm);
3883 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3884 mark_dirty(svm->vmcb, VMCB_INTR);
3885 ++svm->vcpu.stat.irq_window_exits;
3886 return 1;
3887 }
3888
3889 static int pause_interception(struct vcpu_svm *svm)
3890 {
3891 kvm_vcpu_on_spin(&(svm->vcpu));
3892 return 1;
3893 }
3894
3895 static int nop_interception(struct vcpu_svm *svm)
3896 {
3897 skip_emulated_instruction(&(svm->vcpu));
3898 return 1;
3899 }
3900
3901 static int monitor_interception(struct vcpu_svm *svm)
3902 {
3903 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
3904 return nop_interception(svm);
3905 }
3906
3907 static int mwait_interception(struct vcpu_svm *svm)
3908 {
3909 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
3910 return nop_interception(svm);
3911 }
3912
3913 enum avic_ipi_failure_cause {
3914 AVIC_IPI_FAILURE_INVALID_INT_TYPE,
3915 AVIC_IPI_FAILURE_TARGET_NOT_RUNNING,
3916 AVIC_IPI_FAILURE_INVALID_TARGET,
3917 AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,
3918 };
3919
3920 static int avic_incomplete_ipi_interception(struct vcpu_svm *svm)
3921 {
3922 u32 icrh = svm->vmcb->control.exit_info_1 >> 32;
3923 u32 icrl = svm->vmcb->control.exit_info_1;
3924 u32 id = svm->vmcb->control.exit_info_2 >> 32;
3925 u32 index = svm->vmcb->control.exit_info_2 & 0xFF;
3926 struct kvm_lapic *apic = svm->vcpu.arch.apic;
3927
3928 trace_kvm_avic_incomplete_ipi(svm->vcpu.vcpu_id, icrh, icrl, id, index);
3929
3930 switch (id) {
3931 case AVIC_IPI_FAILURE_INVALID_INT_TYPE:
3932 /*
3933 * AVIC hardware handles the generation of
3934 * IPIs when the specified Message Type is Fixed
3935 * (also known as fixed delivery mode) and
3936 * the Trigger Mode is edge-triggered. The hardware
3937 * also supports self and broadcast delivery modes
3938 * specified via the Destination Shorthand(DSH)
3939 * field of the ICRL. Logical and physical APIC ID
3940 * formats are supported. All other IPI types cause
3941 * a #VMEXIT, which needs to emulated.
3942 */
3943 kvm_lapic_reg_write(apic, APIC_ICR2, icrh);
3944 kvm_lapic_reg_write(apic, APIC_ICR, icrl);
3945 break;
3946 case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING: {
3947 int i;
3948 struct kvm_vcpu *vcpu;
3949 struct kvm *kvm = svm->vcpu.kvm;
3950 struct kvm_lapic *apic = svm->vcpu.arch.apic;
3951
3952 /*
3953 * At this point, we expect that the AVIC HW has already
3954 * set the appropriate IRR bits on the valid target
3955 * vcpus. So, we just need to kick the appropriate vcpu.
3956 */
3957 kvm_for_each_vcpu(i, vcpu, kvm) {
3958 bool m = kvm_apic_match_dest(vcpu, apic,
3959 icrl & KVM_APIC_SHORT_MASK,
3960 GET_APIC_DEST_FIELD(icrh),
3961 icrl & KVM_APIC_DEST_MASK);
3962
3963 if (m && !avic_vcpu_is_running(vcpu))
3964 kvm_vcpu_wake_up(vcpu);
3965 }
3966 break;
3967 }
3968 case AVIC_IPI_FAILURE_INVALID_TARGET:
3969 break;
3970 case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE:
3971 WARN_ONCE(1, "Invalid backing page\n");
3972 break;
3973 default:
3974 pr_err("Unknown IPI interception\n");
3975 }
3976
3977 return 1;
3978 }
3979
3980 static u32 *avic_get_logical_id_entry(struct kvm_vcpu *vcpu, u32 ldr, bool flat)
3981 {
3982 struct kvm_arch *vm_data = &vcpu->kvm->arch;
3983 int index;
3984 u32 *logical_apic_id_table;
3985 int dlid = GET_APIC_LOGICAL_ID(ldr);
3986
3987 if (!dlid)
3988 return NULL;
3989
3990 if (flat) { /* flat */
3991 index = ffs(dlid) - 1;
3992 if (index > 7)
3993 return NULL;
3994 } else { /* cluster */
3995 int cluster = (dlid & 0xf0) >> 4;
3996 int apic = ffs(dlid & 0x0f) - 1;
3997
3998 if ((apic < 0) || (apic > 7) ||
3999 (cluster >= 0xf))
4000 return NULL;
4001 index = (cluster << 2) + apic;
4002 }
4003
4004 logical_apic_id_table = (u32 *) page_address(vm_data->avic_logical_id_table_page);
4005
4006 return &logical_apic_id_table[index];
4007 }
4008
4009 static int avic_ldr_write(struct kvm_vcpu *vcpu, u8 g_physical_id, u32 ldr,
4010 bool valid)
4011 {
4012 bool flat;
4013 u32 *entry, new_entry;
4014
4015 flat = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR) == APIC_DFR_FLAT;
4016 entry = avic_get_logical_id_entry(vcpu, ldr, flat);
4017 if (!entry)
4018 return -EINVAL;
4019
4020 new_entry = READ_ONCE(*entry);
4021 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK;
4022 new_entry |= (g_physical_id & AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK);
4023 if (valid)
4024 new_entry |= AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
4025 else
4026 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
4027 WRITE_ONCE(*entry, new_entry);
4028
4029 return 0;
4030 }
4031
4032 static int avic_handle_ldr_update(struct kvm_vcpu *vcpu)
4033 {
4034 int ret;
4035 struct vcpu_svm *svm = to_svm(vcpu);
4036 u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR);
4037
4038 if (!ldr)
4039 return 1;
4040
4041 ret = avic_ldr_write(vcpu, vcpu->vcpu_id, ldr, true);
4042 if (ret && svm->ldr_reg) {
4043 avic_ldr_write(vcpu, 0, svm->ldr_reg, false);
4044 svm->ldr_reg = 0;
4045 } else {
4046 svm->ldr_reg = ldr;
4047 }
4048 return ret;
4049 }
4050
4051 static int avic_handle_apic_id_update(struct kvm_vcpu *vcpu)
4052 {
4053 u64 *old, *new;
4054 struct vcpu_svm *svm = to_svm(vcpu);
4055 u32 apic_id_reg = kvm_lapic_get_reg(vcpu->arch.apic, APIC_ID);
4056 u32 id = (apic_id_reg >> 24) & 0xff;
4057
4058 if (vcpu->vcpu_id == id)
4059 return 0;
4060
4061 old = avic_get_physical_id_entry(vcpu, vcpu->vcpu_id);
4062 new = avic_get_physical_id_entry(vcpu, id);
4063 if (!new || !old)
4064 return 1;
4065
4066 /* We need to move physical_id_entry to new offset */
4067 *new = *old;
4068 *old = 0ULL;
4069 to_svm(vcpu)->avic_physical_id_cache = new;
4070
4071 /*
4072 * Also update the guest physical APIC ID in the logical
4073 * APIC ID table entry if already setup the LDR.
4074 */
4075 if (svm->ldr_reg)
4076 avic_handle_ldr_update(vcpu);
4077
4078 return 0;
4079 }
4080
4081 static int avic_handle_dfr_update(struct kvm_vcpu *vcpu)
4082 {
4083 struct vcpu_svm *svm = to_svm(vcpu);
4084 struct kvm_arch *vm_data = &vcpu->kvm->arch;
4085 u32 dfr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR);
4086 u32 mod = (dfr >> 28) & 0xf;
4087
4088 /*
4089 * We assume that all local APICs are using the same type.
4090 * If this changes, we need to flush the AVIC logical
4091 * APID id table.
4092 */
4093 if (vm_data->ldr_mode == mod)
4094 return 0;
4095
4096 clear_page(page_address(vm_data->avic_logical_id_table_page));
4097 vm_data->ldr_mode = mod;
4098
4099 if (svm->ldr_reg)
4100 avic_handle_ldr_update(vcpu);
4101 return 0;
4102 }
4103
4104 static int avic_unaccel_trap_write(struct vcpu_svm *svm)
4105 {
4106 struct kvm_lapic *apic = svm->vcpu.arch.apic;
4107 u32 offset = svm->vmcb->control.exit_info_1 &
4108 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4109
4110 switch (offset) {
4111 case APIC_ID:
4112 if (avic_handle_apic_id_update(&svm->vcpu))
4113 return 0;
4114 break;
4115 case APIC_LDR:
4116 if (avic_handle_ldr_update(&svm->vcpu))
4117 return 0;
4118 break;
4119 case APIC_DFR:
4120 avic_handle_dfr_update(&svm->vcpu);
4121 break;
4122 default:
4123 break;
4124 }
4125
4126 kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset));
4127
4128 return 1;
4129 }
4130
4131 static bool is_avic_unaccelerated_access_trap(u32 offset)
4132 {
4133 bool ret = false;
4134
4135 switch (offset) {
4136 case APIC_ID:
4137 case APIC_EOI:
4138 case APIC_RRR:
4139 case APIC_LDR:
4140 case APIC_DFR:
4141 case APIC_SPIV:
4142 case APIC_ESR:
4143 case APIC_ICR:
4144 case APIC_LVTT:
4145 case APIC_LVTTHMR:
4146 case APIC_LVTPC:
4147 case APIC_LVT0:
4148 case APIC_LVT1:
4149 case APIC_LVTERR:
4150 case APIC_TMICT:
4151 case APIC_TDCR:
4152 ret = true;
4153 break;
4154 default:
4155 break;
4156 }
4157 return ret;
4158 }
4159
4160 static int avic_unaccelerated_access_interception(struct vcpu_svm *svm)
4161 {
4162 int ret = 0;
4163 u32 offset = svm->vmcb->control.exit_info_1 &
4164 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4165 u32 vector = svm->vmcb->control.exit_info_2 &
4166 AVIC_UNACCEL_ACCESS_VECTOR_MASK;
4167 bool write = (svm->vmcb->control.exit_info_1 >> 32) &
4168 AVIC_UNACCEL_ACCESS_WRITE_MASK;
4169 bool trap = is_avic_unaccelerated_access_trap(offset);
4170
4171 trace_kvm_avic_unaccelerated_access(svm->vcpu.vcpu_id, offset,
4172 trap, write, vector);
4173 if (trap) {
4174 /* Handling Trap */
4175 WARN_ONCE(!write, "svm: Handling trap read.\n");
4176 ret = avic_unaccel_trap_write(svm);
4177 } else {
4178 /* Handling Fault */
4179 ret = (emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE);
4180 }
4181
4182 return ret;
4183 }
4184
4185 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
4186 [SVM_EXIT_READ_CR0] = cr_interception,
4187 [SVM_EXIT_READ_CR3] = cr_interception,
4188 [SVM_EXIT_READ_CR4] = cr_interception,
4189 [SVM_EXIT_READ_CR8] = cr_interception,
4190 [SVM_EXIT_CR0_SEL_WRITE] = cr_interception,
4191 [SVM_EXIT_WRITE_CR0] = cr_interception,
4192 [SVM_EXIT_WRITE_CR3] = cr_interception,
4193 [SVM_EXIT_WRITE_CR4] = cr_interception,
4194 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
4195 [SVM_EXIT_READ_DR0] = dr_interception,
4196 [SVM_EXIT_READ_DR1] = dr_interception,
4197 [SVM_EXIT_READ_DR2] = dr_interception,
4198 [SVM_EXIT_READ_DR3] = dr_interception,
4199 [SVM_EXIT_READ_DR4] = dr_interception,
4200 [SVM_EXIT_READ_DR5] = dr_interception,
4201 [SVM_EXIT_READ_DR6] = dr_interception,
4202 [SVM_EXIT_READ_DR7] = dr_interception,
4203 [SVM_EXIT_WRITE_DR0] = dr_interception,
4204 [SVM_EXIT_WRITE_DR1] = dr_interception,
4205 [SVM_EXIT_WRITE_DR2] = dr_interception,
4206 [SVM_EXIT_WRITE_DR3] = dr_interception,
4207 [SVM_EXIT_WRITE_DR4] = dr_interception,
4208 [SVM_EXIT_WRITE_DR5] = dr_interception,
4209 [SVM_EXIT_WRITE_DR6] = dr_interception,
4210 [SVM_EXIT_WRITE_DR7] = dr_interception,
4211 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
4212 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
4213 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
4214 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
4215 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
4216 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
4217 [SVM_EXIT_EXCP_BASE + AC_VECTOR] = ac_interception,
4218 [SVM_EXIT_INTR] = intr_interception,
4219 [SVM_EXIT_NMI] = nmi_interception,
4220 [SVM_EXIT_SMI] = nop_on_interception,
4221 [SVM_EXIT_INIT] = nop_on_interception,
4222 [SVM_EXIT_VINTR] = interrupt_window_interception,
4223 [SVM_EXIT_RDPMC] = rdpmc_interception,
4224 [SVM_EXIT_CPUID] = cpuid_interception,
4225 [SVM_EXIT_IRET] = iret_interception,
4226 [SVM_EXIT_INVD] = emulate_on_interception,
4227 [SVM_EXIT_PAUSE] = pause_interception,
4228 [SVM_EXIT_HLT] = halt_interception,
4229 [SVM_EXIT_INVLPG] = invlpg_interception,
4230 [SVM_EXIT_INVLPGA] = invlpga_interception,
4231 [SVM_EXIT_IOIO] = io_interception,
4232 [SVM_EXIT_MSR] = msr_interception,
4233 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
4234 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
4235 [SVM_EXIT_VMRUN] = vmrun_interception,
4236 [SVM_EXIT_VMMCALL] = vmmcall_interception,
4237 [SVM_EXIT_VMLOAD] = vmload_interception,
4238 [SVM_EXIT_VMSAVE] = vmsave_interception,
4239 [SVM_EXIT_STGI] = stgi_interception,
4240 [SVM_EXIT_CLGI] = clgi_interception,
4241 [SVM_EXIT_SKINIT] = skinit_interception,
4242 [SVM_EXIT_WBINVD] = wbinvd_interception,
4243 [SVM_EXIT_MONITOR] = monitor_interception,
4244 [SVM_EXIT_MWAIT] = mwait_interception,
4245 [SVM_EXIT_XSETBV] = xsetbv_interception,
4246 [SVM_EXIT_NPF] = pf_interception,
4247 [SVM_EXIT_RSM] = emulate_on_interception,
4248 [SVM_EXIT_AVIC_INCOMPLETE_IPI] = avic_incomplete_ipi_interception,
4249 [SVM_EXIT_AVIC_UNACCELERATED_ACCESS] = avic_unaccelerated_access_interception,
4250 };
4251
4252 static void dump_vmcb(struct kvm_vcpu *vcpu)
4253 {
4254 struct vcpu_svm *svm = to_svm(vcpu);
4255 struct vmcb_control_area *control = &svm->vmcb->control;
4256 struct vmcb_save_area *save = &svm->vmcb->save;
4257
4258 pr_err("VMCB Control Area:\n");
4259 pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
4260 pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
4261 pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
4262 pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
4263 pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
4264 pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
4265 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
4266 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
4267 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
4268 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
4269 pr_err("%-20s%d\n", "asid:", control->asid);
4270 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
4271 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
4272 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
4273 pr_err("%-20s%08x\n", "int_state:", control->int_state);
4274 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
4275 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
4276 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
4277 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
4278 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
4279 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
4280 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
4281 pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
4282 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
4283 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
4284 pr_err("%-20s%lld\n", "lbr_ctl:", control->lbr_ctl);
4285 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
4286 pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
4287 pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
4288 pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
4289 pr_err("VMCB State Save Area:\n");
4290 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4291 "es:",
4292 save->es.selector, save->es.attrib,
4293 save->es.limit, save->es.base);
4294 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4295 "cs:",
4296 save->cs.selector, save->cs.attrib,
4297 save->cs.limit, save->cs.base);
4298 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4299 "ss:",
4300 save->ss.selector, save->ss.attrib,
4301 save->ss.limit, save->ss.base);
4302 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4303 "ds:",
4304 save->ds.selector, save->ds.attrib,
4305 save->ds.limit, save->ds.base);
4306 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4307 "fs:",
4308 save->fs.selector, save->fs.attrib,
4309 save->fs.limit, save->fs.base);
4310 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4311 "gs:",
4312 save->gs.selector, save->gs.attrib,
4313 save->gs.limit, save->gs.base);
4314 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4315 "gdtr:",
4316 save->gdtr.selector, save->gdtr.attrib,
4317 save->gdtr.limit, save->gdtr.base);
4318 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4319 "ldtr:",
4320 save->ldtr.selector, save->ldtr.attrib,
4321 save->ldtr.limit, save->ldtr.base);
4322 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4323 "idtr:",
4324 save->idtr.selector, save->idtr.attrib,
4325 save->idtr.limit, save->idtr.base);
4326 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4327 "tr:",
4328 save->tr.selector, save->tr.attrib,
4329 save->tr.limit, save->tr.base);
4330 pr_err("cpl: %d efer: %016llx\n",
4331 save->cpl, save->efer);
4332 pr_err("%-15s %016llx %-13s %016llx\n",
4333 "cr0:", save->cr0, "cr2:", save->cr2);
4334 pr_err("%-15s %016llx %-13s %016llx\n",
4335 "cr3:", save->cr3, "cr4:", save->cr4);
4336 pr_err("%-15s %016llx %-13s %016llx\n",
4337 "dr6:", save->dr6, "dr7:", save->dr7);
4338 pr_err("%-15s %016llx %-13s %016llx\n",
4339 "rip:", save->rip, "rflags:", save->rflags);
4340 pr_err("%-15s %016llx %-13s %016llx\n",
4341 "rsp:", save->rsp, "rax:", save->rax);
4342 pr_err("%-15s %016llx %-13s %016llx\n",
4343 "star:", save->star, "lstar:", save->lstar);
4344 pr_err("%-15s %016llx %-13s %016llx\n",
4345 "cstar:", save->cstar, "sfmask:", save->sfmask);
4346 pr_err("%-15s %016llx %-13s %016llx\n",
4347 "kernel_gs_base:", save->kernel_gs_base,
4348 "sysenter_cs:", save->sysenter_cs);
4349 pr_err("%-15s %016llx %-13s %016llx\n",
4350 "sysenter_esp:", save->sysenter_esp,
4351 "sysenter_eip:", save->sysenter_eip);
4352 pr_err("%-15s %016llx %-13s %016llx\n",
4353 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
4354 pr_err("%-15s %016llx %-13s %016llx\n",
4355 "br_from:", save->br_from, "br_to:", save->br_to);
4356 pr_err("%-15s %016llx %-13s %016llx\n",
4357 "excp_from:", save->last_excp_from,
4358 "excp_to:", save->last_excp_to);
4359 }
4360
4361 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
4362 {
4363 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
4364
4365 *info1 = control->exit_info_1;
4366 *info2 = control->exit_info_2;
4367 }
4368
4369 static int handle_exit(struct kvm_vcpu *vcpu)
4370 {
4371 struct vcpu_svm *svm = to_svm(vcpu);
4372 struct kvm_run *kvm_run = vcpu->run;
4373 u32 exit_code = svm->vmcb->control.exit_code;
4374
4375 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
4376
4377 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
4378 vcpu->arch.cr0 = svm->vmcb->save.cr0;
4379 if (npt_enabled)
4380 vcpu->arch.cr3 = svm->vmcb->save.cr3;
4381
4382 if (unlikely(svm->nested.exit_required)) {
4383 nested_svm_vmexit(svm);
4384 svm->nested.exit_required = false;
4385
4386 return 1;
4387 }
4388
4389 if (is_guest_mode(vcpu)) {
4390 int vmexit;
4391
4392 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
4393 svm->vmcb->control.exit_info_1,
4394 svm->vmcb->control.exit_info_2,
4395 svm->vmcb->control.exit_int_info,
4396 svm->vmcb->control.exit_int_info_err,
4397 KVM_ISA_SVM);
4398
4399 vmexit = nested_svm_exit_special(svm);
4400
4401 if (vmexit == NESTED_EXIT_CONTINUE)
4402 vmexit = nested_svm_exit_handled(svm);
4403
4404 if (vmexit == NESTED_EXIT_DONE)
4405 return 1;
4406 }
4407
4408 svm_complete_interrupts(svm);
4409
4410 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
4411 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
4412 kvm_run->fail_entry.hardware_entry_failure_reason
4413 = svm->vmcb->control.exit_code;
4414 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
4415 dump_vmcb(vcpu);
4416 return 0;
4417 }
4418
4419 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
4420 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
4421 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
4422 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
4423 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
4424 "exit_code 0x%x\n",
4425 __func__, svm->vmcb->control.exit_int_info,
4426 exit_code);
4427
4428 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
4429 || !svm_exit_handlers[exit_code]) {
4430 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code);
4431 kvm_queue_exception(vcpu, UD_VECTOR);
4432 return 1;
4433 }
4434
4435 return svm_exit_handlers[exit_code](svm);
4436 }
4437
4438 static void reload_tss(struct kvm_vcpu *vcpu)
4439 {
4440 int cpu = raw_smp_processor_id();
4441
4442 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4443 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
4444 load_TR_desc();
4445 }
4446
4447 static void pre_svm_run(struct vcpu_svm *svm)
4448 {
4449 int cpu = raw_smp_processor_id();
4450
4451 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4452
4453 /* FIXME: handle wraparound of asid_generation */
4454 if (svm->asid_generation != sd->asid_generation)
4455 new_asid(svm, sd);
4456 }
4457
4458 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
4459 {
4460 struct vcpu_svm *svm = to_svm(vcpu);
4461
4462 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
4463 vcpu->arch.hflags |= HF_NMI_MASK;
4464 set_intercept(svm, INTERCEPT_IRET);
4465 ++vcpu->stat.nmi_injections;
4466 }
4467
4468 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
4469 {
4470 struct vmcb_control_area *control;
4471
4472 /* The following fields are ignored when AVIC is enabled */
4473 control = &svm->vmcb->control;
4474 control->int_vector = irq;
4475 control->int_ctl &= ~V_INTR_PRIO_MASK;
4476 control->int_ctl |= V_IRQ_MASK |
4477 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
4478 mark_dirty(svm->vmcb, VMCB_INTR);
4479 }
4480
4481 static void svm_set_irq(struct kvm_vcpu *vcpu)
4482 {
4483 struct vcpu_svm *svm = to_svm(vcpu);
4484
4485 BUG_ON(!(gif_set(svm)));
4486
4487 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
4488 ++vcpu->stat.irq_injections;
4489
4490 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
4491 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
4492 }
4493
4494 static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu *vcpu)
4495 {
4496 return is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK);
4497 }
4498
4499 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
4500 {
4501 struct vcpu_svm *svm = to_svm(vcpu);
4502
4503 if (svm_nested_virtualize_tpr(vcpu) ||
4504 kvm_vcpu_apicv_active(vcpu))
4505 return;
4506
4507 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
4508
4509 if (irr == -1)
4510 return;
4511
4512 if (tpr >= irr)
4513 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
4514 }
4515
4516 static void svm_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
4517 {
4518 return;
4519 }
4520
4521 static bool svm_get_enable_apicv(void)
4522 {
4523 return avic;
4524 }
4525
4526 static void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
4527 {
4528 }
4529
4530 static void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
4531 {
4532 }
4533
4534 /* Note: Currently only used by Hyper-V. */
4535 static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4536 {
4537 struct vcpu_svm *svm = to_svm(vcpu);
4538 struct vmcb *vmcb = svm->vmcb;
4539
4540 if (!avic)
4541 return;
4542
4543 vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK;
4544 mark_dirty(vmcb, VMCB_INTR);
4545 }
4546
4547 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
4548 {
4549 return;
4550 }
4551
4552 static void svm_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4553 {
4554 return;
4555 }
4556
4557 static void svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec)
4558 {
4559 kvm_lapic_set_irr(vec, vcpu->arch.apic);
4560 smp_mb__after_atomic();
4561
4562 if (avic_vcpu_is_running(vcpu))
4563 wrmsrl(SVM_AVIC_DOORBELL,
4564 kvm_cpu_get_apicid(vcpu->cpu));
4565 else
4566 kvm_vcpu_wake_up(vcpu);
4567 }
4568
4569 static void svm_ir_list_del(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
4570 {
4571 unsigned long flags;
4572 struct amd_svm_iommu_ir *cur;
4573
4574 spin_lock_irqsave(&svm->ir_list_lock, flags);
4575 list_for_each_entry(cur, &svm->ir_list, node) {
4576 if (cur->data != pi->ir_data)
4577 continue;
4578 list_del(&cur->node);
4579 kfree(cur);
4580 break;
4581 }
4582 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
4583 }
4584
4585 static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
4586 {
4587 int ret = 0;
4588 unsigned long flags;
4589 struct amd_svm_iommu_ir *ir;
4590
4591 /**
4592 * In some cases, the existing irte is updaed and re-set,
4593 * so we need to check here if it's already been * added
4594 * to the ir_list.
4595 */
4596 if (pi->ir_data && (pi->prev_ga_tag != 0)) {
4597 struct kvm *kvm = svm->vcpu.kvm;
4598 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(pi->prev_ga_tag);
4599 struct kvm_vcpu *prev_vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
4600 struct vcpu_svm *prev_svm;
4601
4602 if (!prev_vcpu) {
4603 ret = -EINVAL;
4604 goto out;
4605 }
4606
4607 prev_svm = to_svm(prev_vcpu);
4608 svm_ir_list_del(prev_svm, pi);
4609 }
4610
4611 /**
4612 * Allocating new amd_iommu_pi_data, which will get
4613 * add to the per-vcpu ir_list.
4614 */
4615 ir = kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_KERNEL);
4616 if (!ir) {
4617 ret = -ENOMEM;
4618 goto out;
4619 }
4620 ir->data = pi->ir_data;
4621
4622 spin_lock_irqsave(&svm->ir_list_lock, flags);
4623 list_add(&ir->node, &svm->ir_list);
4624 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
4625 out:
4626 return ret;
4627 }
4628
4629 /**
4630 * Note:
4631 * The HW cannot support posting multicast/broadcast
4632 * interrupts to a vCPU. So, we still use legacy interrupt
4633 * remapping for these kind of interrupts.
4634 *
4635 * For lowest-priority interrupts, we only support
4636 * those with single CPU as the destination, e.g. user
4637 * configures the interrupts via /proc/irq or uses
4638 * irqbalance to make the interrupts single-CPU.
4639 */
4640 static int
4641 get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e,
4642 struct vcpu_data *vcpu_info, struct vcpu_svm **svm)
4643 {
4644 struct kvm_lapic_irq irq;
4645 struct kvm_vcpu *vcpu = NULL;
4646
4647 kvm_set_msi_irq(kvm, e, &irq);
4648
4649 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
4650 pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n",
4651 __func__, irq.vector);
4652 return -1;
4653 }
4654
4655 pr_debug("SVM: %s: use GA mode for irq %u\n", __func__,
4656 irq.vector);
4657 *svm = to_svm(vcpu);
4658 vcpu_info->pi_desc_addr = page_to_phys((*svm)->avic_backing_page);
4659 vcpu_info->vector = irq.vector;
4660
4661 return 0;
4662 }
4663
4664 /*
4665 * svm_update_pi_irte - set IRTE for Posted-Interrupts
4666 *
4667 * @kvm: kvm
4668 * @host_irq: host irq of the interrupt
4669 * @guest_irq: gsi of the interrupt
4670 * @set: set or unset PI
4671 * returns 0 on success, < 0 on failure
4672 */
4673 static int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
4674 uint32_t guest_irq, bool set)
4675 {
4676 struct kvm_kernel_irq_routing_entry *e;
4677 struct kvm_irq_routing_table *irq_rt;
4678 int idx, ret = -EINVAL;
4679
4680 if (!kvm_arch_has_assigned_device(kvm) ||
4681 !irq_remapping_cap(IRQ_POSTING_CAP))
4682 return 0;
4683
4684 pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n",
4685 __func__, host_irq, guest_irq, set);
4686
4687 idx = srcu_read_lock(&kvm->irq_srcu);
4688 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
4689 WARN_ON(guest_irq >= irq_rt->nr_rt_entries);
4690
4691 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
4692 struct vcpu_data vcpu_info;
4693 struct vcpu_svm *svm = NULL;
4694
4695 if (e->type != KVM_IRQ_ROUTING_MSI)
4696 continue;
4697
4698 /**
4699 * Here, we setup with legacy mode in the following cases:
4700 * 1. When cannot target interrupt to a specific vcpu.
4701 * 2. Unsetting posted interrupt.
4702 * 3. APIC virtialization is disabled for the vcpu.
4703 */
4704 if (!get_pi_vcpu_info(kvm, e, &vcpu_info, &svm) && set &&
4705 kvm_vcpu_apicv_active(&svm->vcpu)) {
4706 struct amd_iommu_pi_data pi;
4707
4708 /* Try to enable guest_mode in IRTE */
4709 pi.base = page_to_phys(svm->avic_backing_page) & AVIC_HPA_MASK;
4710 pi.ga_tag = AVIC_GATAG(kvm->arch.avic_vm_id,
4711 svm->vcpu.vcpu_id);
4712 pi.is_guest_mode = true;
4713 pi.vcpu_data = &vcpu_info;
4714 ret = irq_set_vcpu_affinity(host_irq, &pi);
4715
4716 /**
4717 * Here, we successfully setting up vcpu affinity in
4718 * IOMMU guest mode. Now, we need to store the posted
4719 * interrupt information in a per-vcpu ir_list so that
4720 * we can reference to them directly when we update vcpu
4721 * scheduling information in IOMMU irte.
4722 */
4723 if (!ret && pi.is_guest_mode)
4724 svm_ir_list_add(svm, &pi);
4725 } else {
4726 /* Use legacy mode in IRTE */
4727 struct amd_iommu_pi_data pi;
4728
4729 /**
4730 * Here, pi is used to:
4731 * - Tell IOMMU to use legacy mode for this interrupt.
4732 * - Retrieve ga_tag of prior interrupt remapping data.
4733 */
4734 pi.is_guest_mode = false;
4735 ret = irq_set_vcpu_affinity(host_irq, &pi);
4736
4737 /**
4738 * Check if the posted interrupt was previously
4739 * setup with the guest_mode by checking if the ga_tag
4740 * was cached. If so, we need to clean up the per-vcpu
4741 * ir_list.
4742 */
4743 if (!ret && pi.prev_ga_tag) {
4744 int id = AVIC_GATAG_TO_VCPUID(pi.prev_ga_tag);
4745 struct kvm_vcpu *vcpu;
4746
4747 vcpu = kvm_get_vcpu_by_id(kvm, id);
4748 if (vcpu)
4749 svm_ir_list_del(to_svm(vcpu), &pi);
4750 }
4751 }
4752
4753 if (!ret && svm) {
4754 trace_kvm_pi_irte_update(svm->vcpu.vcpu_id,
4755 host_irq, e->gsi,
4756 vcpu_info.vector,
4757 vcpu_info.pi_desc_addr, set);
4758 }
4759
4760 if (ret < 0) {
4761 pr_err("%s: failed to update PI IRTE\n", __func__);
4762 goto out;
4763 }
4764 }
4765
4766 ret = 0;
4767 out:
4768 srcu_read_unlock(&kvm->irq_srcu, idx);
4769 return ret;
4770 }
4771
4772 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
4773 {
4774 struct vcpu_svm *svm = to_svm(vcpu);
4775 struct vmcb *vmcb = svm->vmcb;
4776 int ret;
4777 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
4778 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
4779 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
4780
4781 return ret;
4782 }
4783
4784 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
4785 {
4786 struct vcpu_svm *svm = to_svm(vcpu);
4787
4788 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
4789 }
4790
4791 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4792 {
4793 struct vcpu_svm *svm = to_svm(vcpu);
4794
4795 if (masked) {
4796 svm->vcpu.arch.hflags |= HF_NMI_MASK;
4797 set_intercept(svm, INTERCEPT_IRET);
4798 } else {
4799 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
4800 clr_intercept(svm, INTERCEPT_IRET);
4801 }
4802 }
4803
4804 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
4805 {
4806 struct vcpu_svm *svm = to_svm(vcpu);
4807 struct vmcb *vmcb = svm->vmcb;
4808 int ret;
4809
4810 if (!gif_set(svm) ||
4811 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
4812 return 0;
4813
4814 ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
4815
4816 if (is_guest_mode(vcpu))
4817 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
4818
4819 return ret;
4820 }
4821
4822 static void enable_irq_window(struct kvm_vcpu *vcpu)
4823 {
4824 struct vcpu_svm *svm = to_svm(vcpu);
4825
4826 if (kvm_vcpu_apicv_active(vcpu))
4827 return;
4828
4829 /*
4830 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
4831 * 1, because that's a separate STGI/VMRUN intercept. The next time we
4832 * get that intercept, this function will be called again though and
4833 * we'll get the vintr intercept.
4834 */
4835 if (gif_set(svm) && nested_svm_intr(svm)) {
4836 svm_set_vintr(svm);
4837 svm_inject_irq(svm, 0x0);
4838 }
4839 }
4840
4841 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4842 {
4843 struct vcpu_svm *svm = to_svm(vcpu);
4844
4845 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
4846 == HF_NMI_MASK)
4847 return; /* IRET will cause a vm exit */
4848
4849 /*
4850 * Something prevents NMI from been injected. Single step over possible
4851 * problem (IRET or exception injection or interrupt shadow)
4852 */
4853 svm->nmi_singlestep = true;
4854 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
4855 }
4856
4857 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
4858 {
4859 return 0;
4860 }
4861
4862 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
4863 {
4864 struct vcpu_svm *svm = to_svm(vcpu);
4865
4866 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
4867 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
4868 else
4869 svm->asid_generation--;
4870 }
4871
4872 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
4873 {
4874 }
4875
4876 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
4877 {
4878 struct vcpu_svm *svm = to_svm(vcpu);
4879
4880 if (svm_nested_virtualize_tpr(vcpu))
4881 return;
4882
4883 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
4884 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
4885 kvm_set_cr8(vcpu, cr8);
4886 }
4887 }
4888
4889 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
4890 {
4891 struct vcpu_svm *svm = to_svm(vcpu);
4892 u64 cr8;
4893
4894 if (svm_nested_virtualize_tpr(vcpu) ||
4895 kvm_vcpu_apicv_active(vcpu))
4896 return;
4897
4898 cr8 = kvm_get_cr8(vcpu);
4899 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
4900 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
4901 }
4902
4903 static void svm_complete_interrupts(struct vcpu_svm *svm)
4904 {
4905 u8 vector;
4906 int type;
4907 u32 exitintinfo = svm->vmcb->control.exit_int_info;
4908 unsigned int3_injected = svm->int3_injected;
4909
4910 svm->int3_injected = 0;
4911
4912 /*
4913 * If we've made progress since setting HF_IRET_MASK, we've
4914 * executed an IRET and can allow NMI injection.
4915 */
4916 if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
4917 && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
4918 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
4919 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4920 }
4921
4922 svm->vcpu.arch.nmi_injected = false;
4923 kvm_clear_exception_queue(&svm->vcpu);
4924 kvm_clear_interrupt_queue(&svm->vcpu);
4925
4926 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
4927 return;
4928
4929 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4930
4931 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
4932 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
4933
4934 switch (type) {
4935 case SVM_EXITINTINFO_TYPE_NMI:
4936 svm->vcpu.arch.nmi_injected = true;
4937 break;
4938 case SVM_EXITINTINFO_TYPE_EXEPT:
4939 /*
4940 * In case of software exceptions, do not reinject the vector,
4941 * but re-execute the instruction instead. Rewind RIP first
4942 * if we emulated INT3 before.
4943 */
4944 if (kvm_exception_is_soft(vector)) {
4945 if (vector == BP_VECTOR && int3_injected &&
4946 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
4947 kvm_rip_write(&svm->vcpu,
4948 kvm_rip_read(&svm->vcpu) -
4949 int3_injected);
4950 break;
4951 }
4952 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
4953 u32 err = svm->vmcb->control.exit_int_info_err;
4954 kvm_requeue_exception_e(&svm->vcpu, vector, err);
4955
4956 } else
4957 kvm_requeue_exception(&svm->vcpu, vector);
4958 break;
4959 case SVM_EXITINTINFO_TYPE_INTR:
4960 kvm_queue_interrupt(&svm->vcpu, vector, false);
4961 break;
4962 default:
4963 break;
4964 }
4965 }
4966
4967 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
4968 {
4969 struct vcpu_svm *svm = to_svm(vcpu);
4970 struct vmcb_control_area *control = &svm->vmcb->control;
4971
4972 control->exit_int_info = control->event_inj;
4973 control->exit_int_info_err = control->event_inj_err;
4974 control->event_inj = 0;
4975 svm_complete_interrupts(svm);
4976 }
4977
4978 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
4979 {
4980 struct vcpu_svm *svm = to_svm(vcpu);
4981
4982 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
4983 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
4984 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
4985
4986 /*
4987 * A vmexit emulation is required before the vcpu can be executed
4988 * again.
4989 */
4990 if (unlikely(svm->nested.exit_required))
4991 return;
4992
4993 pre_svm_run(svm);
4994
4995 sync_lapic_to_cr8(vcpu);
4996
4997 svm->vmcb->save.cr2 = vcpu->arch.cr2;
4998
4999 clgi();
5000
5001 /*
5002 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
5003 * it's non-zero. Since vmentry is serialising on affected CPUs, there
5004 * is no need to worry about the conditional branch over the wrmsr
5005 * being speculatively taken.
5006 */
5007 x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
5008
5009 local_irq_enable();
5010
5011 asm volatile (
5012 "push %%" _ASM_BP "; \n\t"
5013 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
5014 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
5015 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
5016 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
5017 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
5018 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
5019 #ifdef CONFIG_X86_64
5020 "mov %c[r8](%[svm]), %%r8 \n\t"
5021 "mov %c[r9](%[svm]), %%r9 \n\t"
5022 "mov %c[r10](%[svm]), %%r10 \n\t"
5023 "mov %c[r11](%[svm]), %%r11 \n\t"
5024 "mov %c[r12](%[svm]), %%r12 \n\t"
5025 "mov %c[r13](%[svm]), %%r13 \n\t"
5026 "mov %c[r14](%[svm]), %%r14 \n\t"
5027 "mov %c[r15](%[svm]), %%r15 \n\t"
5028 #endif
5029
5030 /* Enter guest mode */
5031 "push %%" _ASM_AX " \n\t"
5032 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
5033 __ex(SVM_VMLOAD) "\n\t"
5034 __ex(SVM_VMRUN) "\n\t"
5035 __ex(SVM_VMSAVE) "\n\t"
5036 "pop %%" _ASM_AX " \n\t"
5037
5038 /* Save guest registers, load host registers */
5039 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
5040 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
5041 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
5042 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
5043 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
5044 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
5045 #ifdef CONFIG_X86_64
5046 "mov %%r8, %c[r8](%[svm]) \n\t"
5047 "mov %%r9, %c[r9](%[svm]) \n\t"
5048 "mov %%r10, %c[r10](%[svm]) \n\t"
5049 "mov %%r11, %c[r11](%[svm]) \n\t"
5050 "mov %%r12, %c[r12](%[svm]) \n\t"
5051 "mov %%r13, %c[r13](%[svm]) \n\t"
5052 "mov %%r14, %c[r14](%[svm]) \n\t"
5053 "mov %%r15, %c[r15](%[svm]) \n\t"
5054 #endif
5055 /*
5056 * Clear host registers marked as clobbered to prevent
5057 * speculative use.
5058 */
5059 "xor %%" _ASM_BX ", %%" _ASM_BX " \n\t"
5060 "xor %%" _ASM_CX ", %%" _ASM_CX " \n\t"
5061 "xor %%" _ASM_DX ", %%" _ASM_DX " \n\t"
5062 "xor %%" _ASM_SI ", %%" _ASM_SI " \n\t"
5063 "xor %%" _ASM_DI ", %%" _ASM_DI " \n\t"
5064 #ifdef CONFIG_X86_64
5065 "xor %%r8, %%r8 \n\t"
5066 "xor %%r9, %%r9 \n\t"
5067 "xor %%r10, %%r10 \n\t"
5068 "xor %%r11, %%r11 \n\t"
5069 "xor %%r12, %%r12 \n\t"
5070 "xor %%r13, %%r13 \n\t"
5071 "xor %%r14, %%r14 \n\t"
5072 "xor %%r15, %%r15 \n\t"
5073 #endif
5074 "pop %%" _ASM_BP
5075 :
5076 : [svm]"a"(svm),
5077 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
5078 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
5079 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
5080 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
5081 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
5082 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
5083 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
5084 #ifdef CONFIG_X86_64
5085 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
5086 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
5087 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
5088 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
5089 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
5090 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
5091 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
5092 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
5093 #endif
5094 : "cc", "memory"
5095 #ifdef CONFIG_X86_64
5096 , "rbx", "rcx", "rdx", "rsi", "rdi"
5097 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
5098 #else
5099 , "ebx", "ecx", "edx", "esi", "edi"
5100 #endif
5101 );
5102
5103 /* Eliminate branch target predictions from guest mode */
5104 vmexit_fill_RSB();
5105
5106 #ifdef CONFIG_X86_64
5107 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
5108 #else
5109 loadsegment(fs, svm->host.fs);
5110 #ifndef CONFIG_X86_32_LAZY_GS
5111 loadsegment(gs, svm->host.gs);
5112 #endif
5113 #endif
5114
5115 /*
5116 * We do not use IBRS in the kernel. If this vCPU has used the
5117 * SPEC_CTRL MSR it may have left it on; save the value and
5118 * turn it off. This is much more efficient than blindly adding
5119 * it to the atomic save/restore list. Especially as the former
5120 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
5121 *
5122 * For non-nested case:
5123 * If the L01 MSR bitmap does not intercept the MSR, then we need to
5124 * save it.
5125 *
5126 * For nested case:
5127 * If the L02 MSR bitmap does not intercept the MSR, then we need to
5128 * save it.
5129 */
5130 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
5131 svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
5132
5133 reload_tss(vcpu);
5134
5135 local_irq_disable();
5136
5137 x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl);
5138
5139 vcpu->arch.cr2 = svm->vmcb->save.cr2;
5140 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
5141 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
5142 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
5143
5144 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
5145 kvm_before_handle_nmi(&svm->vcpu);
5146
5147 stgi();
5148
5149 /* Any pending NMI will happen here */
5150
5151 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
5152 kvm_after_handle_nmi(&svm->vcpu);
5153
5154 sync_cr8_to_lapic(vcpu);
5155
5156 svm->next_rip = 0;
5157
5158 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
5159
5160 /* if exit due to PF check for async PF */
5161 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
5162 svm->apf_reason = kvm_read_and_reset_pf_reason();
5163
5164 if (npt_enabled) {
5165 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
5166 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
5167 }
5168
5169 /*
5170 * We need to handle MC intercepts here before the vcpu has a chance to
5171 * change the physical cpu
5172 */
5173 if (unlikely(svm->vmcb->control.exit_code ==
5174 SVM_EXIT_EXCP_BASE + MC_VECTOR))
5175 svm_handle_mce(svm);
5176
5177 mark_all_clean(svm->vmcb);
5178 }
5179 STACK_FRAME_NON_STANDARD(svm_vcpu_run);
5180
5181 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5182 {
5183 struct vcpu_svm *svm = to_svm(vcpu);
5184
5185 svm->vmcb->save.cr3 = root;
5186 mark_dirty(svm->vmcb, VMCB_CR);
5187 svm_flush_tlb(vcpu);
5188 }
5189
5190 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5191 {
5192 struct vcpu_svm *svm = to_svm(vcpu);
5193
5194 svm->vmcb->control.nested_cr3 = root;
5195 mark_dirty(svm->vmcb, VMCB_NPT);
5196
5197 /* Also sync guest cr3 here in case we live migrate */
5198 svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
5199 mark_dirty(svm->vmcb, VMCB_CR);
5200
5201 svm_flush_tlb(vcpu);
5202 }
5203
5204 static int is_disabled(void)
5205 {
5206 u64 vm_cr;
5207
5208 rdmsrl(MSR_VM_CR, vm_cr);
5209 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
5210 return 1;
5211
5212 return 0;
5213 }
5214
5215 static void
5216 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5217 {
5218 /*
5219 * Patch in the VMMCALL instruction:
5220 */
5221 hypercall[0] = 0x0f;
5222 hypercall[1] = 0x01;
5223 hypercall[2] = 0xd9;
5224 }
5225
5226 static void svm_check_processor_compat(void *rtn)
5227 {
5228 *(int *)rtn = 0;
5229 }
5230
5231 static bool svm_cpu_has_accelerated_tpr(void)
5232 {
5233 return false;
5234 }
5235
5236 static bool svm_has_emulated_msr(int index)
5237 {
5238 switch (index) {
5239 case MSR_IA32_MCG_EXT_CTL:
5240 return false;
5241 default:
5242 break;
5243 }
5244
5245 return true;
5246 }
5247
5248 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
5249 {
5250 return 0;
5251 }
5252
5253 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
5254 {
5255 struct vcpu_svm *svm = to_svm(vcpu);
5256 struct kvm_cpuid_entry2 *entry;
5257
5258 /* Update nrips enabled cache */
5259 svm->nrips_enabled = !!guest_cpuid_has_nrips(&svm->vcpu);
5260
5261 if (!kvm_vcpu_apicv_active(vcpu))
5262 return;
5263
5264 entry = kvm_find_cpuid_entry(vcpu, 1, 0);
5265 if (entry)
5266 entry->ecx &= ~bit(X86_FEATURE_X2APIC);
5267 }
5268
5269 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
5270 {
5271 switch (func) {
5272 case 0x1:
5273 if (avic)
5274 entry->ecx &= ~bit(X86_FEATURE_X2APIC);
5275 break;
5276 case 0x80000001:
5277 if (nested)
5278 entry->ecx |= (1 << 2); /* Set SVM bit */
5279 break;
5280 case 0x8000000A:
5281 entry->eax = 1; /* SVM revision 1 */
5282 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
5283 ASID emulation to nested SVM */
5284 entry->ecx = 0; /* Reserved */
5285 entry->edx = 0; /* Per default do not support any
5286 additional features */
5287
5288 /* Support next_rip if host supports it */
5289 if (boot_cpu_has(X86_FEATURE_NRIPS))
5290 entry->edx |= SVM_FEATURE_NRIP;
5291
5292 /* Support NPT for the guest if enabled */
5293 if (npt_enabled)
5294 entry->edx |= SVM_FEATURE_NPT;
5295
5296 break;
5297 }
5298 }
5299
5300 static int svm_get_lpage_level(void)
5301 {
5302 return PT_PDPE_LEVEL;
5303 }
5304
5305 static bool svm_rdtscp_supported(void)
5306 {
5307 return boot_cpu_has(X86_FEATURE_RDTSCP);
5308 }
5309
5310 static bool svm_invpcid_supported(void)
5311 {
5312 return false;
5313 }
5314
5315 static bool svm_mpx_supported(void)
5316 {
5317 return false;
5318 }
5319
5320 static bool svm_xsaves_supported(void)
5321 {
5322 return false;
5323 }
5324
5325 static bool svm_has_wbinvd_exit(void)
5326 {
5327 return true;
5328 }
5329
5330 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
5331 {
5332 struct vcpu_svm *svm = to_svm(vcpu);
5333
5334 set_exception_intercept(svm, NM_VECTOR);
5335 update_cr0_intercept(svm);
5336 }
5337
5338 #define PRE_EX(exit) { .exit_code = (exit), \
5339 .stage = X86_ICPT_PRE_EXCEPT, }
5340 #define POST_EX(exit) { .exit_code = (exit), \
5341 .stage = X86_ICPT_POST_EXCEPT, }
5342 #define POST_MEM(exit) { .exit_code = (exit), \
5343 .stage = X86_ICPT_POST_MEMACCESS, }
5344
5345 static const struct __x86_intercept {
5346 u32 exit_code;
5347 enum x86_intercept_stage stage;
5348 } x86_intercept_map[] = {
5349 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
5350 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
5351 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
5352 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
5353 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
5354 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
5355 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
5356 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
5357 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
5358 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
5359 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
5360 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
5361 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
5362 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
5363 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
5364 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
5365 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
5366 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
5367 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
5368 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
5369 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
5370 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
5371 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
5372 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
5373 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
5374 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
5375 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
5376 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
5377 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
5378 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
5379 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
5380 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
5381 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
5382 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
5383 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
5384 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
5385 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
5386 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
5387 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
5388 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
5389 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
5390 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
5391 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
5392 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
5393 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
5394 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
5395 };
5396
5397 #undef PRE_EX
5398 #undef POST_EX
5399 #undef POST_MEM
5400
5401 static int svm_check_intercept(struct kvm_vcpu *vcpu,
5402 struct x86_instruction_info *info,
5403 enum x86_intercept_stage stage)
5404 {
5405 struct vcpu_svm *svm = to_svm(vcpu);
5406 int vmexit, ret = X86EMUL_CONTINUE;
5407 struct __x86_intercept icpt_info;
5408 struct vmcb *vmcb = svm->vmcb;
5409
5410 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
5411 goto out;
5412
5413 icpt_info = x86_intercept_map[info->intercept];
5414
5415 if (stage != icpt_info.stage)
5416 goto out;
5417
5418 switch (icpt_info.exit_code) {
5419 case SVM_EXIT_READ_CR0:
5420 if (info->intercept == x86_intercept_cr_read)
5421 icpt_info.exit_code += info->modrm_reg;
5422 break;
5423 case SVM_EXIT_WRITE_CR0: {
5424 unsigned long cr0, val;
5425 u64 intercept;
5426
5427 if (info->intercept == x86_intercept_cr_write)
5428 icpt_info.exit_code += info->modrm_reg;
5429
5430 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
5431 info->intercept == x86_intercept_clts)
5432 break;
5433
5434 intercept = svm->nested.intercept;
5435
5436 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
5437 break;
5438
5439 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
5440 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
5441
5442 if (info->intercept == x86_intercept_lmsw) {
5443 cr0 &= 0xfUL;
5444 val &= 0xfUL;
5445 /* lmsw can't clear PE - catch this here */
5446 if (cr0 & X86_CR0_PE)
5447 val |= X86_CR0_PE;
5448 }
5449
5450 if (cr0 ^ val)
5451 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
5452
5453 break;
5454 }
5455 case SVM_EXIT_READ_DR0:
5456 case SVM_EXIT_WRITE_DR0:
5457 icpt_info.exit_code += info->modrm_reg;
5458 break;
5459 case SVM_EXIT_MSR:
5460 if (info->intercept == x86_intercept_wrmsr)
5461 vmcb->control.exit_info_1 = 1;
5462 else
5463 vmcb->control.exit_info_1 = 0;
5464 break;
5465 case SVM_EXIT_PAUSE:
5466 /*
5467 * We get this for NOP only, but pause
5468 * is rep not, check this here
5469 */
5470 if (info->rep_prefix != REPE_PREFIX)
5471 goto out;
5472 case SVM_EXIT_IOIO: {
5473 u64 exit_info;
5474 u32 bytes;
5475
5476 if (info->intercept == x86_intercept_in ||
5477 info->intercept == x86_intercept_ins) {
5478 exit_info = ((info->src_val & 0xffff) << 16) |
5479 SVM_IOIO_TYPE_MASK;
5480 bytes = info->dst_bytes;
5481 } else {
5482 exit_info = (info->dst_val & 0xffff) << 16;
5483 bytes = info->src_bytes;
5484 }
5485
5486 if (info->intercept == x86_intercept_outs ||
5487 info->intercept == x86_intercept_ins)
5488 exit_info |= SVM_IOIO_STR_MASK;
5489
5490 if (info->rep_prefix)
5491 exit_info |= SVM_IOIO_REP_MASK;
5492
5493 bytes = min(bytes, 4u);
5494
5495 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
5496
5497 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
5498
5499 vmcb->control.exit_info_1 = exit_info;
5500 vmcb->control.exit_info_2 = info->next_rip;
5501
5502 break;
5503 }
5504 default:
5505 break;
5506 }
5507
5508 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
5509 if (static_cpu_has(X86_FEATURE_NRIPS))
5510 vmcb->control.next_rip = info->next_rip;
5511 vmcb->control.exit_code = icpt_info.exit_code;
5512 vmexit = nested_svm_exit_handled(svm);
5513
5514 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
5515 : X86EMUL_CONTINUE;
5516
5517 out:
5518 return ret;
5519 }
5520
5521 static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
5522 {
5523 local_irq_enable();
5524 /*
5525 * We must have an instruction with interrupts enabled, so
5526 * the timer interrupt isn't delayed by the interrupt shadow.
5527 */
5528 asm("nop");
5529 local_irq_disable();
5530 }
5531
5532 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
5533 {
5534 }
5535
5536 static inline void avic_post_state_restore(struct kvm_vcpu *vcpu)
5537 {
5538 if (avic_handle_apic_id_update(vcpu) != 0)
5539 return;
5540 if (avic_handle_dfr_update(vcpu) != 0)
5541 return;
5542 avic_handle_ldr_update(vcpu);
5543 }
5544
5545 static void svm_setup_mce(struct kvm_vcpu *vcpu)
5546 {
5547 /* [63:9] are reserved. */
5548 vcpu->arch.mcg_cap &= 0x1ff;
5549 }
5550
5551 static struct kvm_x86_ops svm_x86_ops __ro_after_init = {
5552 .cpu_has_kvm_support = has_svm,
5553 .disabled_by_bios = is_disabled,
5554 .hardware_setup = svm_hardware_setup,
5555 .hardware_unsetup = svm_hardware_unsetup,
5556 .check_processor_compatibility = svm_check_processor_compat,
5557 .hardware_enable = svm_hardware_enable,
5558 .hardware_disable = svm_hardware_disable,
5559 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
5560 .has_emulated_msr = svm_has_emulated_msr,
5561
5562 .vcpu_create = svm_create_vcpu,
5563 .vcpu_free = svm_free_vcpu,
5564 .vcpu_reset = svm_vcpu_reset,
5565
5566 .vm_init = avic_vm_init,
5567 .vm_destroy = avic_vm_destroy,
5568
5569 .prepare_guest_switch = svm_prepare_guest_switch,
5570 .vcpu_load = svm_vcpu_load,
5571 .vcpu_put = svm_vcpu_put,
5572 .vcpu_blocking = svm_vcpu_blocking,
5573 .vcpu_unblocking = svm_vcpu_unblocking,
5574
5575 .update_bp_intercept = update_bp_intercept,
5576 .get_msr_feature = svm_get_msr_feature,
5577 .get_msr = svm_get_msr,
5578 .set_msr = svm_set_msr,
5579 .get_segment_base = svm_get_segment_base,
5580 .get_segment = svm_get_segment,
5581 .set_segment = svm_set_segment,
5582 .get_cpl = svm_get_cpl,
5583 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
5584 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
5585 .decache_cr3 = svm_decache_cr3,
5586 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
5587 .set_cr0 = svm_set_cr0,
5588 .set_cr3 = svm_set_cr3,
5589 .set_cr4 = svm_set_cr4,
5590 .set_efer = svm_set_efer,
5591 .get_idt = svm_get_idt,
5592 .set_idt = svm_set_idt,
5593 .get_gdt = svm_get_gdt,
5594 .set_gdt = svm_set_gdt,
5595 .get_dr6 = svm_get_dr6,
5596 .set_dr6 = svm_set_dr6,
5597 .set_dr7 = svm_set_dr7,
5598 .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
5599 .cache_reg = svm_cache_reg,
5600 .get_rflags = svm_get_rflags,
5601 .set_rflags = svm_set_rflags,
5602
5603 .get_pkru = svm_get_pkru,
5604
5605 .fpu_activate = svm_fpu_activate,
5606 .fpu_deactivate = svm_fpu_deactivate,
5607
5608 .tlb_flush = svm_flush_tlb,
5609
5610 .run = svm_vcpu_run,
5611 .handle_exit = handle_exit,
5612 .skip_emulated_instruction = skip_emulated_instruction,
5613 .set_interrupt_shadow = svm_set_interrupt_shadow,
5614 .get_interrupt_shadow = svm_get_interrupt_shadow,
5615 .patch_hypercall = svm_patch_hypercall,
5616 .set_irq = svm_set_irq,
5617 .set_nmi = svm_inject_nmi,
5618 .queue_exception = svm_queue_exception,
5619 .cancel_injection = svm_cancel_injection,
5620 .interrupt_allowed = svm_interrupt_allowed,
5621 .nmi_allowed = svm_nmi_allowed,
5622 .get_nmi_mask = svm_get_nmi_mask,
5623 .set_nmi_mask = svm_set_nmi_mask,
5624 .enable_nmi_window = enable_nmi_window,
5625 .enable_irq_window = enable_irq_window,
5626 .update_cr8_intercept = update_cr8_intercept,
5627 .set_virtual_x2apic_mode = svm_set_virtual_x2apic_mode,
5628 .get_enable_apicv = svm_get_enable_apicv,
5629 .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
5630 .load_eoi_exitmap = svm_load_eoi_exitmap,
5631 .sync_pir_to_irr = svm_sync_pir_to_irr,
5632 .hwapic_irr_update = svm_hwapic_irr_update,
5633 .hwapic_isr_update = svm_hwapic_isr_update,
5634 .apicv_post_state_restore = avic_post_state_restore,
5635
5636 .set_tss_addr = svm_set_tss_addr,
5637 .get_tdp_level = get_npt_level,
5638 .get_mt_mask = svm_get_mt_mask,
5639
5640 .get_exit_info = svm_get_exit_info,
5641
5642 .get_lpage_level = svm_get_lpage_level,
5643
5644 .cpuid_update = svm_cpuid_update,
5645
5646 .rdtscp_supported = svm_rdtscp_supported,
5647 .invpcid_supported = svm_invpcid_supported,
5648 .mpx_supported = svm_mpx_supported,
5649 .xsaves_supported = svm_xsaves_supported,
5650
5651 .set_supported_cpuid = svm_set_supported_cpuid,
5652
5653 .has_wbinvd_exit = svm_has_wbinvd_exit,
5654
5655 .write_tsc_offset = svm_write_tsc_offset,
5656
5657 .set_tdp_cr3 = set_tdp_cr3,
5658
5659 .check_intercept = svm_check_intercept,
5660 .handle_external_intr = svm_handle_external_intr,
5661
5662 .sched_in = svm_sched_in,
5663
5664 .pmu_ops = &amd_pmu_ops,
5665 .deliver_posted_interrupt = svm_deliver_avic_intr,
5666 .update_pi_irte = svm_update_pi_irte,
5667 .setup_mce = svm_setup_mce,
5668 };
5669
5670 static int __init svm_init(void)
5671 {
5672 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
5673 __alignof__(struct vcpu_svm), THIS_MODULE);
5674 }
5675
5676 static void __exit svm_exit(void)
5677 {
5678 kvm_exit();
5679 }
5680
5681 module_init(svm_init)
5682 module_exit(svm_exit)
Linux with added FPC-III support