?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
NFC: pn533: Fix wrong GFP flag usage
[linux/fpc-iii.git] / drivers / i2c / busses / i2c-mt65xx.c
blob1e57f58fcb00151e9ef274e25e3adf22f2c197b8
1 /*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Xudong Chen <xudong.chen@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15 #include <linux/clk.h>
16 #include <linux/completion.h>
17 #include <linux/delay.h>
18 #include <linux/device.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/err.h>
21 #include <linux/errno.h>
22 #include <linux/i2c.h>
23 #include <linux/init.h>
24 #include <linux/interrupt.h>
25 #include <linux/io.h>
26 #include <linux/kernel.h>
27 #include <linux/mm.h>
28 #include <linux/module.h>
29 #include <linux/of_address.h>
30 #include <linux/of_device.h>
31 #include <linux/of_irq.h>
32 #include <linux/platform_device.h>
33 #include <linux/scatterlist.h>
34 #include <linux/sched.h>
35 #include <linux/slab.h>
36
37 #define I2C_RS_TRANSFER (1 << 4)
38 #define I2C_HS_NACKERR (1 << 2)
39 #define I2C_ACKERR (1 << 1)
40 #define I2C_TRANSAC_COMP (1 << 0)
41 #define I2C_TRANSAC_START (1 << 0)
42 #define I2C_RS_MUL_CNFG (1 << 15)
43 #define I2C_RS_MUL_TRIG (1 << 14)
44 #define I2C_DCM_DISABLE 0x0000
45 #define I2C_IO_CONFIG_OPEN_DRAIN 0x0003
46 #define I2C_IO_CONFIG_PUSH_PULL 0x0000
47 #define I2C_SOFT_RST 0x0001
48 #define I2C_FIFO_ADDR_CLR 0x0001
49 #define I2C_DELAY_LEN 0x0002
50 #define I2C_ST_START_CON 0x8001
51 #define I2C_FS_START_CON 0x1800
52 #define I2C_TIME_CLR_VALUE 0x0000
53 #define I2C_TIME_DEFAULT_VALUE 0x0003
54 #define I2C_WRRD_TRANAC_VALUE 0x0002
55 #define I2C_RD_TRANAC_VALUE 0x0001
56
57 #define I2C_DMA_CON_TX 0x0000
58 #define I2C_DMA_CON_RX 0x0001
59 #define I2C_DMA_START_EN 0x0001
60 #define I2C_DMA_INT_FLAG_NONE 0x0000
61 #define I2C_DMA_CLR_FLAG 0x0000
62 #define I2C_DMA_HARD_RST 0x0002
63 #define I2C_DMA_4G_MODE 0x0001
64
65 #define I2C_DEFAULT_CLK_DIV 5
66 #define I2C_DEFAULT_SPEED 100000 /* hz */
67 #define MAX_FS_MODE_SPEED 400000
68 #define MAX_HS_MODE_SPEED 3400000
69 #define MAX_SAMPLE_CNT_DIV 8
70 #define MAX_STEP_CNT_DIV 64
71 #define MAX_HS_STEP_CNT_DIV 8
72
73 #define I2C_CONTROL_RS (0x1 << 1)
74 #define I2C_CONTROL_DMA_EN (0x1 << 2)
75 #define I2C_CONTROL_CLK_EXT_EN (0x1 << 3)
76 #define I2C_CONTROL_DIR_CHANGE (0x1 << 4)
77 #define I2C_CONTROL_ACKERR_DET_EN (0x1 << 5)
78 #define I2C_CONTROL_TRANSFER_LEN_CHANGE (0x1 << 6)
79 #define I2C_CONTROL_WRAPPER (0x1 << 0)
80
81 #define I2C_DRV_NAME "i2c-mt65xx"
82
83 enum DMA_REGS_OFFSET {
84 OFFSET_INT_FLAG = 0x0,
85 OFFSET_INT_EN = 0x04,
86 OFFSET_EN = 0x08,
87 OFFSET_RST = 0x0c,
88 OFFSET_CON = 0x18,
89 OFFSET_TX_MEM_ADDR = 0x1c,
90 OFFSET_RX_MEM_ADDR = 0x20,
91 OFFSET_TX_LEN = 0x24,
92 OFFSET_RX_LEN = 0x28,
93 OFFSET_TX_4G_MODE = 0x54,
94 OFFSET_RX_4G_MODE = 0x58,
95 };
96
97 enum i2c_trans_st_rs {
98 I2C_TRANS_STOP = 0,
99 I2C_TRANS_REPEATED_START,
100 };
101
102 enum mtk_trans_op {
103 I2C_MASTER_WR = 1,
104 I2C_MASTER_RD,
105 I2C_MASTER_WRRD,
106 };
107
108 enum I2C_REGS_OFFSET {
109 OFFSET_DATA_PORT = 0x0,
110 OFFSET_SLAVE_ADDR = 0x04,
111 OFFSET_INTR_MASK = 0x08,
112 OFFSET_INTR_STAT = 0x0c,
113 OFFSET_CONTROL = 0x10,
114 OFFSET_TRANSFER_LEN = 0x14,
115 OFFSET_TRANSAC_LEN = 0x18,
116 OFFSET_DELAY_LEN = 0x1c,
117 OFFSET_TIMING = 0x20,
118 OFFSET_START = 0x24,
119 OFFSET_EXT_CONF = 0x28,
120 OFFSET_FIFO_STAT = 0x30,
121 OFFSET_FIFO_THRESH = 0x34,
122 OFFSET_FIFO_ADDR_CLR = 0x38,
123 OFFSET_IO_CONFIG = 0x40,
124 OFFSET_RSV_DEBUG = 0x44,
125 OFFSET_HS = 0x48,
126 OFFSET_SOFTRESET = 0x50,
127 OFFSET_DCM_EN = 0x54,
128 OFFSET_PATH_DIR = 0x60,
129 OFFSET_DEBUGSTAT = 0x64,
130 OFFSET_DEBUGCTRL = 0x68,
131 OFFSET_TRANSFER_LEN_AUX = 0x6c,
132 OFFSET_CLOCK_DIV = 0x70,
133 };
134
135 struct mtk_i2c_compatible {
136 const struct i2c_adapter_quirks *quirks;
137 unsigned char pmic_i2c: 1;
138 unsigned char dcm: 1;
139 unsigned char auto_restart: 1;
140 unsigned char aux_len_reg: 1;
141 unsigned char support_33bits: 1;
142 unsigned char timing_adjust: 1;
143 };
144
145 struct mtk_i2c {
146 struct i2c_adapter adap; /* i2c host adapter */
147 struct device *dev;
148 struct completion msg_complete;
149
150 /* set in i2c probe */
151 void __iomem *base; /* i2c base addr */
152 void __iomem *pdmabase; /* dma base address*/
153 struct clk *clk_main; /* main clock for i2c bus */
154 struct clk *clk_dma; /* DMA clock for i2c via DMA */
155 struct clk *clk_pmic; /* PMIC clock for i2c from PMIC */
156 bool have_pmic; /* can use i2c pins from PMIC */
157 bool use_push_pull; /* IO config push-pull mode */
158
159 u16 irq_stat; /* interrupt status */
160 unsigned int clk_src_div;
161 unsigned int speed_hz; /* The speed in transfer */
162 enum mtk_trans_op op;
163 u16 timing_reg;
164 u16 high_speed_reg;
165 unsigned char auto_restart;
166 bool ignore_restart_irq;
167 const struct mtk_i2c_compatible *dev_comp;
168 };
169
170 static const struct i2c_adapter_quirks mt6577_i2c_quirks = {
171 .flags = I2C_AQ_COMB_WRITE_THEN_READ,
172 .max_num_msgs = 1,
173 .max_write_len = 255,
174 .max_read_len = 255,
175 .max_comb_1st_msg_len = 255,
176 .max_comb_2nd_msg_len = 31,
177 };
178
179 static const struct i2c_adapter_quirks mt7622_i2c_quirks = {
180 .max_num_msgs = 255,
181 };
182
183 static const struct mtk_i2c_compatible mt2712_compat = {
184 .pmic_i2c = 0,
185 .dcm = 1,
186 .auto_restart = 1,
187 .aux_len_reg = 1,
188 .support_33bits = 1,
189 .timing_adjust = 1,
190 };
191
192 static const struct mtk_i2c_compatible mt6577_compat = {
193 .quirks = &mt6577_i2c_quirks,
194 .pmic_i2c = 0,
195 .dcm = 1,
196 .auto_restart = 0,
197 .aux_len_reg = 0,
198 .support_33bits = 0,
199 .timing_adjust = 0,
200 };
201
202 static const struct mtk_i2c_compatible mt6589_compat = {
203 .quirks = &mt6577_i2c_quirks,
204 .pmic_i2c = 1,
205 .dcm = 0,
206 .auto_restart = 0,
207 .aux_len_reg = 0,
208 .support_33bits = 0,
209 .timing_adjust = 0,
210 };
211
212 static const struct mtk_i2c_compatible mt7622_compat = {
213 .quirks = &mt7622_i2c_quirks,
214 .pmic_i2c = 0,
215 .dcm = 1,
216 .auto_restart = 1,
217 .aux_len_reg = 1,
218 .support_33bits = 0,
219 .timing_adjust = 0,
220 };
221
222 static const struct mtk_i2c_compatible mt8173_compat = {
223 .pmic_i2c = 0,
224 .dcm = 1,
225 .auto_restart = 1,
226 .aux_len_reg = 1,
227 .support_33bits = 1,
228 .timing_adjust = 0,
229 };
230
231 static const struct of_device_id mtk_i2c_of_match[] = {
232 { .compatible = "mediatek,mt2712-i2c", .data = &mt2712_compat },
233 { .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat },
234 { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat },
235 { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat },
236 { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat },
237 {}
238 };
239 MODULE_DEVICE_TABLE(of, mtk_i2c_of_match);
240
241 static int mtk_i2c_clock_enable(struct mtk_i2c *i2c)
242 {
243 int ret;
244
245 ret = clk_prepare_enable(i2c->clk_dma);
246 if (ret)
247 return ret;
248
249 ret = clk_prepare_enable(i2c->clk_main);
250 if (ret)
251 goto err_main;
252
253 if (i2c->have_pmic) {
254 ret = clk_prepare_enable(i2c->clk_pmic);
255 if (ret)
256 goto err_pmic;
257 }
258 return 0;
259
260 err_pmic:
261 clk_disable_unprepare(i2c->clk_main);
262 err_main:
263 clk_disable_unprepare(i2c->clk_dma);
264
265 return ret;
266 }
267
268 static void mtk_i2c_clock_disable(struct mtk_i2c *i2c)
269 {
270 if (i2c->have_pmic)
271 clk_disable_unprepare(i2c->clk_pmic);
272
273 clk_disable_unprepare(i2c->clk_main);
274 clk_disable_unprepare(i2c->clk_dma);
275 }
276
277 static void mtk_i2c_init_hw(struct mtk_i2c *i2c)
278 {
279 u16 control_reg;
280
281 writew(I2C_SOFT_RST, i2c->base + OFFSET_SOFTRESET);
282
283 /* Set ioconfig */
284 if (i2c->use_push_pull)
285 writew(I2C_IO_CONFIG_PUSH_PULL, i2c->base + OFFSET_IO_CONFIG);
286 else
287 writew(I2C_IO_CONFIG_OPEN_DRAIN, i2c->base + OFFSET_IO_CONFIG);
288
289 if (i2c->dev_comp->dcm)
290 writew(I2C_DCM_DISABLE, i2c->base + OFFSET_DCM_EN);
291
292 if (i2c->dev_comp->timing_adjust)
293 writew(I2C_DEFAULT_CLK_DIV - 1, i2c->base + OFFSET_CLOCK_DIV);
294
295 writew(i2c->timing_reg, i2c->base + OFFSET_TIMING);
296 writew(i2c->high_speed_reg, i2c->base + OFFSET_HS);
297
298 /* If use i2c pin from PMIC mt6397 side, need set PATH_DIR first */
299 if (i2c->have_pmic)
300 writew(I2C_CONTROL_WRAPPER, i2c->base + OFFSET_PATH_DIR);
301
302 control_reg = I2C_CONTROL_ACKERR_DET_EN |
303 I2C_CONTROL_CLK_EXT_EN | I2C_CONTROL_DMA_EN;
304 writew(control_reg, i2c->base + OFFSET_CONTROL);
305 writew(I2C_DELAY_LEN, i2c->base + OFFSET_DELAY_LEN);
306
307 writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST);
308 udelay(50);
309 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
310 }
311
312 /*
313 * Calculate i2c port speed
314 *
315 * Hardware design:
316 * i2c_bus_freq = parent_clk / (clock_div * 2 * sample_cnt * step_cnt)
317 * clock_div: fixed in hardware, but may be various in different SoCs
318 *
319 * The calculation want to pick the highest bus frequency that is still
320 * less than or equal to i2c->speed_hz. The calculation try to get
321 * sample_cnt and step_cn
322 */
323 static int mtk_i2c_calculate_speed(struct mtk_i2c *i2c, unsigned int clk_src,
324 unsigned int target_speed,
325 unsigned int *timing_step_cnt,
326 unsigned int *timing_sample_cnt)
327 {
328 unsigned int step_cnt;
329 unsigned int sample_cnt;
330 unsigned int max_step_cnt;
331 unsigned int base_sample_cnt = MAX_SAMPLE_CNT_DIV;
332 unsigned int base_step_cnt;
333 unsigned int opt_div;
334 unsigned int best_mul;
335 unsigned int cnt_mul;
336
337 if (target_speed > MAX_HS_MODE_SPEED)
338 target_speed = MAX_HS_MODE_SPEED;
339
340 if (target_speed > MAX_FS_MODE_SPEED)
341 max_step_cnt = MAX_HS_STEP_CNT_DIV;
342 else
343 max_step_cnt = MAX_STEP_CNT_DIV;
344
345 base_step_cnt = max_step_cnt;
346 /* Find the best combination */
347 opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed);
348 best_mul = MAX_SAMPLE_CNT_DIV * max_step_cnt;
349
350 /* Search for the best pair (sample_cnt, step_cnt) with
351 * 0 < sample_cnt < MAX_SAMPLE_CNT_DIV
352 * 0 < step_cnt < max_step_cnt
353 * sample_cnt * step_cnt >= opt_div
354 * optimizing for sample_cnt * step_cnt being minimal
355 */
356 for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) {
357 step_cnt = DIV_ROUND_UP(opt_div, sample_cnt);
358 cnt_mul = step_cnt * sample_cnt;
359 if (step_cnt > max_step_cnt)
360 continue;
361
362 if (cnt_mul < best_mul) {
363 best_mul = cnt_mul;
364 base_sample_cnt = sample_cnt;
365 base_step_cnt = step_cnt;
366 if (best_mul == opt_div)
367 break;
368 }
369 }
370
371 sample_cnt = base_sample_cnt;
372 step_cnt = base_step_cnt;
373
374 if ((clk_src / (2 * sample_cnt * step_cnt)) > target_speed) {
375 /* In this case, hardware can't support such
376 * low i2c_bus_freq
377 */
378 dev_dbg(i2c->dev, "Unsupported speed (%uhz)\n", target_speed);
379 return -EINVAL;
380 }
381
382 *timing_step_cnt = step_cnt - 1;
383 *timing_sample_cnt = sample_cnt - 1;
384
385 return 0;
386 }
387
388 static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk)
389 {
390 unsigned int clk_src;
391 unsigned int step_cnt;
392 unsigned int sample_cnt;
393 unsigned int target_speed;
394 int ret;
395
396 clk_src = parent_clk / i2c->clk_src_div;
397 target_speed = i2c->speed_hz;
398
399 if (target_speed > MAX_FS_MODE_SPEED) {
400 /* Set master code speed register */
401 ret = mtk_i2c_calculate_speed(i2c, clk_src, MAX_FS_MODE_SPEED,
402 &step_cnt, &sample_cnt);
403 if (ret < 0)
404 return ret;
405
406 i2c->timing_reg = (sample_cnt << 8) | step_cnt;
407
408 /* Set the high speed mode register */
409 ret = mtk_i2c_calculate_speed(i2c, clk_src, target_speed,
410 &step_cnt, &sample_cnt);
411 if (ret < 0)
412 return ret;
413
414 i2c->high_speed_reg = I2C_TIME_DEFAULT_VALUE |
415 (sample_cnt << 12) | (step_cnt << 8);
416 } else {
417 ret = mtk_i2c_calculate_speed(i2c, clk_src, target_speed,
418 &step_cnt, &sample_cnt);
419 if (ret < 0)
420 return ret;
421
422 i2c->timing_reg = (sample_cnt << 8) | step_cnt;
423
424 /* Disable the high speed transaction */
425 i2c->high_speed_reg = I2C_TIME_CLR_VALUE;
426 }
427
428 return 0;
429 }
430
431 static inline u32 mtk_i2c_set_4g_mode(dma_addr_t addr)
432 {
433 return (addr & BIT_ULL(32)) ? I2C_DMA_4G_MODE : I2C_DMA_CLR_FLAG;
434 }
435
436 static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
437 int num, int left_num)
438 {
439 u16 addr_reg;
440 u16 start_reg;
441 u16 control_reg;
442 u16 restart_flag = 0;
443 u32 reg_4g_mode;
444 dma_addr_t rpaddr = 0;
445 dma_addr_t wpaddr = 0;
446 int ret;
447
448 i2c->irq_stat = 0;
449
450 if (i2c->auto_restart)
451 restart_flag = I2C_RS_TRANSFER;
452
453 reinit_completion(&i2c->msg_complete);
454
455 control_reg = readw(i2c->base + OFFSET_CONTROL) &
456 ~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS);
457 if ((i2c->speed_hz > 400000) || (left_num >= 1))
458 control_reg |= I2C_CONTROL_RS;
459
460 if (i2c->op == I2C_MASTER_WRRD)
461 control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS;
462
463 writew(control_reg, i2c->base + OFFSET_CONTROL);
464
465 /* set start condition */
466 if (i2c->speed_hz <= 100000)
467 writew(I2C_ST_START_CON, i2c->base + OFFSET_EXT_CONF);
468 else
469 writew(I2C_FS_START_CON, i2c->base + OFFSET_EXT_CONF);
470
471 addr_reg = i2c_8bit_addr_from_msg(msgs);
472 writew(addr_reg, i2c->base + OFFSET_SLAVE_ADDR);
473
474 /* Clear interrupt status */
475 writew(restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
476 I2C_TRANSAC_COMP, i2c->base + OFFSET_INTR_STAT);
477 writew(I2C_FIFO_ADDR_CLR, i2c->base + OFFSET_FIFO_ADDR_CLR);
478
479 /* Enable interrupt */
480 writew(restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
481 I2C_TRANSAC_COMP, i2c->base + OFFSET_INTR_MASK);
482
483 /* Set transfer and transaction len */
484 if (i2c->op == I2C_MASTER_WRRD) {
485 if (i2c->dev_comp->aux_len_reg) {
486 writew(msgs->len, i2c->base + OFFSET_TRANSFER_LEN);
487 writew((msgs + 1)->len, i2c->base +
488 OFFSET_TRANSFER_LEN_AUX);
489 } else {
490 writew(msgs->len | ((msgs + 1)->len) << 8,
491 i2c->base + OFFSET_TRANSFER_LEN);
492 }
493 writew(I2C_WRRD_TRANAC_VALUE, i2c->base + OFFSET_TRANSAC_LEN);
494 } else {
495 writew(msgs->len, i2c->base + OFFSET_TRANSFER_LEN);
496 writew(num, i2c->base + OFFSET_TRANSAC_LEN);
497 }
498
499 /* Prepare buffer data to start transfer */
500 if (i2c->op == I2C_MASTER_RD) {
501 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
502 writel(I2C_DMA_CON_RX, i2c->pdmabase + OFFSET_CON);
503 rpaddr = dma_map_single(i2c->dev, msgs->buf,
504 msgs->len, DMA_FROM_DEVICE);
505 if (dma_mapping_error(i2c->dev, rpaddr))
506 return -ENOMEM;
507
508 if (i2c->dev_comp->support_33bits) {
509 reg_4g_mode = mtk_i2c_set_4g_mode(rpaddr);
510 writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
511 }
512
513 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR);
514 writel(msgs->len, i2c->pdmabase + OFFSET_RX_LEN);
515 } else if (i2c->op == I2C_MASTER_WR) {
516 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
517 writel(I2C_DMA_CON_TX, i2c->pdmabase + OFFSET_CON);
518 wpaddr = dma_map_single(i2c->dev, msgs->buf,
519 msgs->len, DMA_TO_DEVICE);
520 if (dma_mapping_error(i2c->dev, wpaddr))
521 return -ENOMEM;
522
523 if (i2c->dev_comp->support_33bits) {
524 reg_4g_mode = mtk_i2c_set_4g_mode(wpaddr);
525 writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
526 }
527
528 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR);
529 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN);
530 } else {
531 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_INT_FLAG);
532 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_CON);
533 wpaddr = dma_map_single(i2c->dev, msgs->buf,
534 msgs->len, DMA_TO_DEVICE);
535 if (dma_mapping_error(i2c->dev, wpaddr))
536 return -ENOMEM;
537 rpaddr = dma_map_single(i2c->dev, (msgs + 1)->buf,
538 (msgs + 1)->len,
539 DMA_FROM_DEVICE);
540 if (dma_mapping_error(i2c->dev, rpaddr)) {
541 dma_unmap_single(i2c->dev, wpaddr,
542 msgs->len, DMA_TO_DEVICE);
543 return -ENOMEM;
544 }
545
546 if (i2c->dev_comp->support_33bits) {
547 reg_4g_mode = mtk_i2c_set_4g_mode(wpaddr);
548 writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
549
550 reg_4g_mode = mtk_i2c_set_4g_mode(rpaddr);
551 writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
552 }
553
554 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR);
555 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR);
556 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN);
557 writel((msgs + 1)->len, i2c->pdmabase + OFFSET_RX_LEN);
558 }
559
560 writel(I2C_DMA_START_EN, i2c->pdmabase + OFFSET_EN);
561
562 if (!i2c->auto_restart) {
563 start_reg = I2C_TRANSAC_START;
564 } else {
565 start_reg = I2C_TRANSAC_START | I2C_RS_MUL_TRIG;
566 if (left_num >= 1)
567 start_reg |= I2C_RS_MUL_CNFG;
568 }
569 writew(start_reg, i2c->base + OFFSET_START);
570
571 ret = wait_for_completion_timeout(&i2c->msg_complete,
572 i2c->adap.timeout);
573
574 /* Clear interrupt mask */
575 writew(~(restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
576 I2C_TRANSAC_COMP), i2c->base + OFFSET_INTR_MASK);
577
578 if (i2c->op == I2C_MASTER_WR) {
579 dma_unmap_single(i2c->dev, wpaddr,
580 msgs->len, DMA_TO_DEVICE);
581 } else if (i2c->op == I2C_MASTER_RD) {
582 dma_unmap_single(i2c->dev, rpaddr,
583 msgs->len, DMA_FROM_DEVICE);
584 } else {
585 dma_unmap_single(i2c->dev, wpaddr, msgs->len,
586 DMA_TO_DEVICE);
587 dma_unmap_single(i2c->dev, rpaddr, (msgs + 1)->len,
588 DMA_FROM_DEVICE);
589 }
590
591 if (ret == 0) {
592 dev_dbg(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr);
593 mtk_i2c_init_hw(i2c);
594 return -ETIMEDOUT;
595 }
596
597 completion_done(&i2c->msg_complete);
598
599 if (i2c->irq_stat & (I2C_HS_NACKERR | I2C_ACKERR)) {
600 dev_dbg(i2c->dev, "addr: %x, transfer ACK error\n", msgs->addr);
601 mtk_i2c_init_hw(i2c);
602 return -ENXIO;
603 }
604
605 return 0;
606 }
607
608 static int mtk_i2c_transfer(struct i2c_adapter *adap,
609 struct i2c_msg msgs[], int num)
610 {
611 int ret;
612 int left_num = num;
613 struct mtk_i2c *i2c = i2c_get_adapdata(adap);
614
615 ret = mtk_i2c_clock_enable(i2c);
616 if (ret)
617 return ret;
618
619 i2c->auto_restart = i2c->dev_comp->auto_restart;
620
621 /* checking if we can skip restart and optimize using WRRD mode */
622 if (i2c->auto_restart && num == 2) {
623 if (!(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD) &&
624 msgs[0].addr == msgs[1].addr) {
625 i2c->auto_restart = 0;
626 }
627 }
628
629 if (i2c->auto_restart && num >= 2 && i2c->speed_hz > MAX_FS_MODE_SPEED)
630 /* ignore the first restart irq after the master code,
631 * otherwise the first transfer will be discarded.
632 */
633 i2c->ignore_restart_irq = true;
634 else
635 i2c->ignore_restart_irq = false;
636
637 while (left_num--) {
638 if (!msgs->buf) {
639 dev_dbg(i2c->dev, "data buffer is NULL.\n");
640 ret = -EINVAL;
641 goto err_exit;
642 }
643
644 if (msgs->flags & I2C_M_RD)
645 i2c->op = I2C_MASTER_RD;
646 else
647 i2c->op = I2C_MASTER_WR;
648
649 if (!i2c->auto_restart) {
650 if (num > 1) {
651 /* combined two messages into one transaction */
652 i2c->op = I2C_MASTER_WRRD;
653 left_num--;
654 }
655 }
656
657 /* always use DMA mode. */
658 ret = mtk_i2c_do_transfer(i2c, msgs, num, left_num);
659 if (ret < 0)
660 goto err_exit;
661
662 msgs++;
663 }
664 /* the return value is number of executed messages */
665 ret = num;
666
667 err_exit:
668 mtk_i2c_clock_disable(i2c);
669 return ret;
670 }
671
672 static irqreturn_t mtk_i2c_irq(int irqno, void *dev_id)
673 {
674 struct mtk_i2c *i2c = dev_id;
675 u16 restart_flag = 0;
676 u16 intr_stat;
677
678 if (i2c->auto_restart)
679 restart_flag = I2C_RS_TRANSFER;
680
681 intr_stat = readw(i2c->base + OFFSET_INTR_STAT);
682 writew(intr_stat, i2c->base + OFFSET_INTR_STAT);
683
684 /*
685 * when occurs ack error, i2c controller generate two interrupts
686 * first is the ack error interrupt, then the complete interrupt
687 * i2c->irq_stat need keep the two interrupt value.
688 */
689 i2c->irq_stat |= intr_stat;
690
691 if (i2c->ignore_restart_irq && (i2c->irq_stat & restart_flag)) {
692 i2c->ignore_restart_irq = false;
693 i2c->irq_stat = 0;
694 writew(I2C_RS_MUL_CNFG | I2C_RS_MUL_TRIG | I2C_TRANSAC_START,
695 i2c->base + OFFSET_START);
696 } else {
697 if (i2c->irq_stat & (I2C_TRANSAC_COMP | restart_flag))
698 complete(&i2c->msg_complete);
699 }
700
701 return IRQ_HANDLED;
702 }
703
704 static u32 mtk_i2c_functionality(struct i2c_adapter *adap)
705 {
706 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
707 }
708
709 static const struct i2c_algorithm mtk_i2c_algorithm = {
710 .master_xfer = mtk_i2c_transfer,
711 .functionality = mtk_i2c_functionality,
712 };
713
714 static int mtk_i2c_parse_dt(struct device_node *np, struct mtk_i2c *i2c)
715 {
716 int ret;
717
718 ret = of_property_read_u32(np, "clock-frequency", &i2c->speed_hz);
719 if (ret < 0)
720 i2c->speed_hz = I2C_DEFAULT_SPEED;
721
722 ret = of_property_read_u32(np, "clock-div", &i2c->clk_src_div);
723 if (ret < 0)
724 return ret;
725
726 if (i2c->clk_src_div == 0)
727 return -EINVAL;
728
729 i2c->have_pmic = of_property_read_bool(np, "mediatek,have-pmic");
730 i2c->use_push_pull =
731 of_property_read_bool(np, "mediatek,use-push-pull");
732
733 return 0;
734 }
735
736 static int mtk_i2c_probe(struct platform_device *pdev)
737 {
738 int ret = 0;
739 struct mtk_i2c *i2c;
740 struct clk *clk;
741 struct resource *res;
742 int irq;
743
744 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
745 if (!i2c)
746 return -ENOMEM;
747
748 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
749 i2c->base = devm_ioremap_resource(&pdev->dev, res);
750 if (IS_ERR(i2c->base))
751 return PTR_ERR(i2c->base);
752
753 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
754 i2c->pdmabase = devm_ioremap_resource(&pdev->dev, res);
755 if (IS_ERR(i2c->pdmabase))
756 return PTR_ERR(i2c->pdmabase);
757
758 irq = platform_get_irq(pdev, 0);
759 if (irq <= 0)
760 return irq;
761
762 init_completion(&i2c->msg_complete);
763
764 i2c->dev_comp = of_device_get_match_data(&pdev->dev);
765 i2c->adap.dev.of_node = pdev->dev.of_node;
766 i2c->dev = &pdev->dev;
767 i2c->adap.dev.parent = &pdev->dev;
768 i2c->adap.owner = THIS_MODULE;
769 i2c->adap.algo = &mtk_i2c_algorithm;
770 i2c->adap.quirks = i2c->dev_comp->quirks;
771 i2c->adap.timeout = 2 * HZ;
772 i2c->adap.retries = 1;
773
774 ret = mtk_i2c_parse_dt(pdev->dev.of_node, i2c);
775 if (ret)
776 return -EINVAL;
777
778 if (i2c->dev_comp->timing_adjust)
779 i2c->clk_src_div *= I2C_DEFAULT_CLK_DIV;
780
781 if (i2c->have_pmic && !i2c->dev_comp->pmic_i2c)
782 return -EINVAL;
783
784 i2c->clk_main = devm_clk_get(&pdev->dev, "main");
785 if (IS_ERR(i2c->clk_main)) {
786 dev_err(&pdev->dev, "cannot get main clock\n");
787 return PTR_ERR(i2c->clk_main);
788 }
789
790 i2c->clk_dma = devm_clk_get(&pdev->dev, "dma");
791 if (IS_ERR(i2c->clk_dma)) {
792 dev_err(&pdev->dev, "cannot get dma clock\n");
793 return PTR_ERR(i2c->clk_dma);
794 }
795
796 clk = i2c->clk_main;
797 if (i2c->have_pmic) {
798 i2c->clk_pmic = devm_clk_get(&pdev->dev, "pmic");
799 if (IS_ERR(i2c->clk_pmic)) {
800 dev_err(&pdev->dev, "cannot get pmic clock\n");
801 return PTR_ERR(i2c->clk_pmic);
802 }
803 clk = i2c->clk_pmic;
804 }
805
806 strlcpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name));
807
808 ret = mtk_i2c_set_speed(i2c, clk_get_rate(clk));
809 if (ret) {
810 dev_err(&pdev->dev, "Failed to set the speed.\n");
811 return -EINVAL;
812 }
813
814 if (i2c->dev_comp->support_33bits) {
815 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(33));
816 if (ret) {
817 dev_err(&pdev->dev, "dma_set_mask return error.\n");
818 return ret;
819 }
820 }
821
822 ret = mtk_i2c_clock_enable(i2c);
823 if (ret) {
824 dev_err(&pdev->dev, "clock enable failed!\n");
825 return ret;
826 }
827 mtk_i2c_init_hw(i2c);
828 mtk_i2c_clock_disable(i2c);
829
830 ret = devm_request_irq(&pdev->dev, irq, mtk_i2c_irq,
831 IRQF_TRIGGER_NONE, I2C_DRV_NAME, i2c);
832 if (ret < 0) {
833 dev_err(&pdev->dev,
834 "Request I2C IRQ %d fail\n", irq);
835 return ret;
836 }
837
838 i2c_set_adapdata(&i2c->adap, i2c);
839 ret = i2c_add_adapter(&i2c->adap);
840 if (ret)
841 return ret;
842
843 platform_set_drvdata(pdev, i2c);
844
845 return 0;
846 }
847
848 static int mtk_i2c_remove(struct platform_device *pdev)
849 {
850 struct mtk_i2c *i2c = platform_get_drvdata(pdev);
851
852 i2c_del_adapter(&i2c->adap);
853
854 return 0;
855 }
856
857 #ifdef CONFIG_PM_SLEEP
858 static int mtk_i2c_resume(struct device *dev)
859 {
860 int ret;
861 struct mtk_i2c *i2c = dev_get_drvdata(dev);
862
863 ret = mtk_i2c_clock_enable(i2c);
864 if (ret) {
865 dev_err(dev, "clock enable failed!\n");
866 return ret;
867 }
868
869 mtk_i2c_init_hw(i2c);
870
871 mtk_i2c_clock_disable(i2c);
872
873 return 0;
874 }
875 #endif
876
877 static const struct dev_pm_ops mtk_i2c_pm = {
878 SET_SYSTEM_SLEEP_PM_OPS(NULL, mtk_i2c_resume)
879 };
880
881 static struct platform_driver mtk_i2c_driver = {
882 .probe = mtk_i2c_probe,
883 .remove = mtk_i2c_remove,
884 .driver = {
885 .name = I2C_DRV_NAME,
886 .pm = &mtk_i2c_pm,
887 .of_match_table = of_match_ptr(mtk_i2c_of_match),
888 },
889 };
890
891 module_platform_driver(mtk_i2c_driver);
892
893 MODULE_LICENSE("GPL v2");
894 MODULE_DESCRIPTION("MediaTek I2C Bus Driver");
895 MODULE_AUTHOR("Xudong Chen <xudong.chen@mediatek.com>");
Linux with added FPC-III support