drivers/ata/pata_hpt366.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Libata driver for the highpoint 366 and 368 UDMA66 ATA controllers.
   4  *
   5  * This driver is heavily based upon:
   6  *
   7  * linux/drivers/ide/pci/hpt366.c               Version 0.36    April 25, 2003
   8  *
   9  * Copyright (C) 1999-2003              Andre Hedrick <andre@linux-ide.org>
  10  * Portions Copyright (C) 2001          Sun Microsystems, Inc.
  11  * Portions Copyright (C) 2003          Red Hat Inc
  12  *
  13  *
  14  * TODO
  15  *      Look into engine reset on timeout errors. Should not be required.
  16  */
  17
  18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  19
  20 #include <linux/kernel.h>
  21 #include <linux/module.h>
  22 #include <linux/pci.h>
  23 #include <linux/blkdev.h>
  24 #include <linux/delay.h>
  25 #include <scsi/scsi_host.h>
  26 #include <linux/libata.h>
  27
  28 #define DRV_NAME        "pata_hpt366"
  29 #define DRV_VERSION     "0.6.11"
  30
  31 struct hpt_clock {
  32         u8      xfer_mode;
  33         u32     timing;
  34 };
  35
  36 /* key for bus clock timings
  37  * bit
  38  * 0:3    data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
  39  *        cycles = value + 1
  40  * 4:7    data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
  41  *        cycles = value + 1
  42  * 8:11   cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
  43  *        register access.
  44  * 12:15  cmd_low_time. Active time of DIOW_/DIOR_ during task file
  45  *        register access.
  46  * 16:18  udma_cycle_time. Clock cycles for UDMA xfer?
  47  * 19:21  pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer.
  48  * 22:24  cmd_pre_high_time. Time to initialize 1st PIO cycle for task file
  49  *        register access.
  50  * 28     UDMA enable.
  51  * 29     DMA  enable.
  52  * 30     PIO_MST enable. If set, the chip is in bus master mode during
  53  *        PIO xfer.
  54  * 31     FIFO enable.
  55  */
  56
  57 static const struct hpt_clock hpt366_40[] = {
  58         {       XFER_UDMA_4,    0x900fd943      },
  59         {       XFER_UDMA_3,    0x900ad943      },
  60         {       XFER_UDMA_2,    0x900bd943      },
  61         {       XFER_UDMA_1,    0x9008d943      },
  62         {       XFER_UDMA_0,    0x9008d943      },
  63
  64         {       XFER_MW_DMA_2,  0xa008d943      },
  65         {       XFER_MW_DMA_1,  0xa010d955      },
  66         {       XFER_MW_DMA_0,  0xa010d9fc      },
  67
  68         {       XFER_PIO_4,     0xc008d963      },
  69         {       XFER_PIO_3,     0xc010d974      },
  70         {       XFER_PIO_2,     0xc010d997      },
  71         {       XFER_PIO_1,     0xc010d9c7      },
  72         {       XFER_PIO_0,     0xc018d9d9      },
  73         {       0,              0x0120d9d9      }
  74 };
  75
  76 static const struct hpt_clock hpt366_33[] = {
  77         {       XFER_UDMA_4,    0x90c9a731      },
  78         {       XFER_UDMA_3,    0x90cfa731      },
  79         {       XFER_UDMA_2,    0x90caa731      },
  80         {       XFER_UDMA_1,    0x90cba731      },
  81         {       XFER_UDMA_0,    0x90c8a731      },
  82
  83         {       XFER_MW_DMA_2,  0xa0c8a731      },
  84         {       XFER_MW_DMA_1,  0xa0c8a732      },      /* 0xa0c8a733 */
  85         {       XFER_MW_DMA_0,  0xa0c8a797      },
  86
  87         {       XFER_PIO_4,     0xc0c8a731      },
  88         {       XFER_PIO_3,     0xc0c8a742      },
  89         {       XFER_PIO_2,     0xc0d0a753      },
  90         {       XFER_PIO_1,     0xc0d0a7a3      },      /* 0xc0d0a793 */
  91         {       XFER_PIO_0,     0xc0d0a7aa      },      /* 0xc0d0a7a7 */
  92         {       0,              0x0120a7a7      }
  93 };
  94
  95 static const struct hpt_clock hpt366_25[] = {
  96         {       XFER_UDMA_4,    0x90c98521      },
  97         {       XFER_UDMA_3,    0x90cf8521      },
  98         {       XFER_UDMA_2,    0x90cf8521      },
  99         {       XFER_UDMA_1,    0x90cb8521      },
 100         {       XFER_UDMA_0,    0x90cb8521      },
 101
 102         {       XFER_MW_DMA_2,  0xa0ca8521      },
 103         {       XFER_MW_DMA_1,  0xa0ca8532      },
 104         {       XFER_MW_DMA_0,  0xa0ca8575      },
 105
 106         {       XFER_PIO_4,     0xc0ca8521      },
 107         {       XFER_PIO_3,     0xc0ca8532      },
 108         {       XFER_PIO_2,     0xc0ca8542      },
 109         {       XFER_PIO_1,     0xc0d08572      },
 110         {       XFER_PIO_0,     0xc0d08585      },
 111         {       0,              0x01208585      }
 112 };
 113
 114 /**
 115  *      hpt36x_find_mode        -       find the hpt36x timing
 116  *      @ap: ATA port
 117  *      @speed: transfer mode
 118  *
 119  *      Return the 32bit register programming information for this channel
 120  *      that matches the speed provided.
 121  */
 122
 123 static u32 hpt36x_find_mode(struct ata_port *ap, int speed)
 124 {
 125         struct hpt_clock *clocks = ap->host->private_data;
 126
 127         while (clocks->xfer_mode) {
 128                 if (clocks->xfer_mode == speed)
 129                         return clocks->timing;
 130                 clocks++;
 131         }
 132         BUG();
 133         return 0xffffffffU;     /* silence compiler warning */
 134 }
 135
 136 static const char * const bad_ata33[] = {
 137         "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3",
 138         "Maxtor 90845U3", "Maxtor 90650U2",
 139         "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5",
 140         "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
 141         "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6",
 142         "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
 143         "Maxtor 90510D4",
 144         "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
 145         "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7",
 146         "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
 147         "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5",
 148         "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
 149         NULL
 150 };
 151
 152 static const char * const bad_ata66_4[] = {
 153         "IBM-DTLA-307075",
 154         "IBM-DTLA-307060",
 155         "IBM-DTLA-307045",
 156         "IBM-DTLA-307030",
 157         "IBM-DTLA-307020",
 158         "IBM-DTLA-307015",
 159         "IBM-DTLA-305040",
 160         "IBM-DTLA-305030",
 161         "IBM-DTLA-305020",
 162         "IC35L010AVER07-0",
 163         "IC35L020AVER07-0",
 164         "IC35L030AVER07-0",
 165         "IC35L040AVER07-0",
 166         "IC35L060AVER07-0",
 167         "WDC AC310200R",
 168         NULL
 169 };
 170
 171 static const char * const bad_ata66_3[] = {
 172         "WDC AC310200R",
 173         NULL
 174 };
 175
 176 static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr,
 177                                const char * const list[])
 178 {
 179         unsigned char model_num[ATA_ID_PROD_LEN + 1];
 180         int i;
 181
 182         ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
 183
 184         i = match_string(list, -1, model_num);
 185         if (i >= 0) {
 186                 pr_warn("%s is not supported for %s\n", modestr, list[i]);
 187                 return 1;
 188         }
 189         return 0;
 190 }
 191
 192 /**
 193  *      hpt366_filter   -       mode selection filter
 194  *      @adev: ATA device
 195  *
 196  *      Block UDMA on devices that cause trouble with this controller.
 197  */
 198
 199 static unsigned long hpt366_filter(struct ata_device *adev, unsigned long mask)
 200 {
 201         if (adev->class == ATA_DEV_ATA) {
 202                 if (hpt_dma_blacklisted(adev, "UDMA",  bad_ata33))
 203                         mask &= ~ATA_MASK_UDMA;
 204                 if (hpt_dma_blacklisted(adev, "UDMA3", bad_ata66_3))
 205                         mask &= ~(0xF8 << ATA_SHIFT_UDMA);
 206                 if (hpt_dma_blacklisted(adev, "UDMA4", bad_ata66_4))
 207                         mask &= ~(0xF0 << ATA_SHIFT_UDMA);
 208         } else if (adev->class == ATA_DEV_ATAPI)
 209                 mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
 210
 211         return mask;
 212 }
 213
 214 static int hpt36x_cable_detect(struct ata_port *ap)
 215 {
 216         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 217         u8 ata66;
 218
 219         /*
 220          * Each channel of pata_hpt366 occupies separate PCI function
 221          * as the primary channel and bit1 indicates the cable type.
 222          */
 223         pci_read_config_byte(pdev, 0x5A, &ata66);
 224         if (ata66 & 2)
 225                 return ATA_CBL_PATA40;
 226         return ATA_CBL_PATA80;
 227 }
 228
 229 static void hpt366_set_mode(struct ata_port *ap, struct ata_device *adev,
 230                             u8 mode)
 231 {
 232         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 233         u32 addr = 0x40 + 4 * adev->devno;
 234         u32 mask, reg, t;
 235
 236         /* determine timing mask and find matching clock entry */
 237         if (mode < XFER_MW_DMA_0)
 238                 mask = 0xc1f8ffff;
 239         else if (mode < XFER_UDMA_0)
 240                 mask = 0x303800ff;
 241         else
 242                 mask = 0x30070000;
 243
 244         t = hpt36x_find_mode(ap, mode);
 245
 246         /*
 247          * Combine new mode bits with old config bits and disable
 248          * on-chip PIO FIFO/buffer (and PIO MST mode as well) to avoid
 249          * problems handling I/O errors later.
 250          */
 251         pci_read_config_dword(pdev, addr, &reg);
 252         reg = ((reg & ~mask) | (t & mask)) & ~0xc0000000;
 253         pci_write_config_dword(pdev, addr, reg);
 254 }
 255
 256 /**
 257  *      hpt366_set_piomode              -       PIO setup
 258  *      @ap: ATA interface
 259  *      @adev: device on the interface
 260  *
 261  *      Perform PIO mode setup.
 262  */
 263
 264 static void hpt366_set_piomode(struct ata_port *ap, struct ata_device *adev)
 265 {
 266         hpt366_set_mode(ap, adev, adev->pio_mode);
 267 }
 268
 269 /**
 270  *      hpt366_set_dmamode              -       DMA timing setup
 271  *      @ap: ATA interface
 272  *      @adev: Device being configured
 273  *
 274  *      Set up the channel for MWDMA or UDMA modes. Much the same as with
 275  *      PIO, load the mode number and then set MWDMA or UDMA flag.
 276  */
 277
 278 static void hpt366_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 279 {
 280         hpt366_set_mode(ap, adev, adev->dma_mode);
 281 }
 282
 283 static struct scsi_host_template hpt36x_sht = {
 284         ATA_BMDMA_SHT(DRV_NAME),
 285 };
 286
 287 /*
 288  *      Configuration for HPT366/68
 289  */
 290
 291 static struct ata_port_operations hpt366_port_ops = {
 292         .inherits       = &ata_bmdma_port_ops,
 293         .cable_detect   = hpt36x_cable_detect,
 294         .mode_filter    = hpt366_filter,
 295         .set_piomode    = hpt366_set_piomode,
 296         .set_dmamode    = hpt366_set_dmamode,
 297 };
 298
 299 /**
 300  *      hpt36x_init_chipset     -       common chip setup
 301  *      @dev: PCI device
 302  *
 303  *      Perform the chip setup work that must be done at both init and
 304  *      resume time
 305  */
 306
 307 static void hpt36x_init_chipset(struct pci_dev *dev)
 308 {
 309         u8 drive_fast;
 310
 311         pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
 312         pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
 313         pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
 314         pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
 315
 316         pci_read_config_byte(dev, 0x51, &drive_fast);
 317         if (drive_fast & 0x80)
 318                 pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
 319 }
 320
 321 /**
 322  *      hpt36x_init_one         -       Initialise an HPT366/368
 323  *      @dev: PCI device
 324  *      @id: Entry in match table
 325  *
 326  *      Initialise an HPT36x device. There are some interesting complications
 327  *      here. Firstly the chip may report 366 and be one of several variants.
 328  *      Secondly all the timings depend on the clock for the chip which we must
 329  *      detect and look up
 330  *
 331  *      This is the known chip mappings. It may be missing a couple of later
 332  *      releases.
 333  *
 334  *      Chip version            PCI             Rev     Notes
 335  *      HPT366                  4 (HPT366)      0       UDMA66
 336  *      HPT366                  4 (HPT366)      1       UDMA66
 337  *      HPT368                  4 (HPT366)      2       UDMA66
 338  *      HPT37x/30x              4 (HPT366)      3+      Other driver
 339  *
 340  */
 341
 342 static int hpt36x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 343 {
 344         static const struct ata_port_info info_hpt366 = {
 345                 .flags = ATA_FLAG_SLAVE_POSS,
 346                 .pio_mask = ATA_PIO4,
 347                 .mwdma_mask = ATA_MWDMA2,
 348                 .udma_mask = ATA_UDMA4,
 349                 .port_ops = &hpt366_port_ops
 350         };
 351         const struct ata_port_info *ppi[] = { &info_hpt366, NULL };
 352
 353         const void *hpriv = NULL;
 354         u32 reg1;
 355         int rc;
 356
 357         rc = pcim_enable_device(dev);
 358         if (rc)
 359                 return rc;
 360
 361         /* May be a later chip in disguise. Check */
 362         /* Newer chips are not in the HPT36x driver. Ignore them */
 363         if (dev->revision > 2)
 364                 return -ENODEV;
 365
 366         hpt36x_init_chipset(dev);
 367
 368         pci_read_config_dword(dev, 0x40,  &reg1);
 369
 370         /* PCI clocking determines the ATA timing values to use */
 371         /* info_hpt366 is safe against re-entry so we can scribble on it */
 372         switch ((reg1 & 0xf00) >> 8) {
 373         case 9:
 374                 hpriv = &hpt366_40;
 375                 break;
 376         case 5:
 377                 hpriv = &hpt366_25;
 378                 break;
 379         default:
 380                 hpriv = &hpt366_33;
 381                 break;
 382         }
 383         /* Now kick off ATA set up */
 384         return ata_pci_bmdma_init_one(dev, ppi, &hpt36x_sht, (void *)hpriv, 0);
 385 }
 386
 387 #ifdef CONFIG_PM_SLEEP
 388 static int hpt36x_reinit_one(struct pci_dev *dev)
 389 {
 390         struct ata_host *host = pci_get_drvdata(dev);
 391         int rc;
 392
 393         rc = ata_pci_device_do_resume(dev);
 394         if (rc)
 395                 return rc;
 396         hpt36x_init_chipset(dev);
 397         ata_host_resume(host);
 398         return 0;
 399 }
 400 #endif
 401
 402 static const struct pci_device_id hpt36x[] = {
 403         { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
 404         { },
 405 };
 406
 407 static struct pci_driver hpt36x_pci_driver = {
 408         .name           = DRV_NAME,
 409         .id_table       = hpt36x,
 410         .probe          = hpt36x_init_one,
 411         .remove         = ata_pci_remove_one,
 412 #ifdef CONFIG_PM_SLEEP
 413         .suspend        = ata_pci_device_suspend,
 414         .resume         = hpt36x_reinit_one,
 415 #endif
 416 };
 417
 418 module_pci_driver(hpt36x_pci_driver);
 419
 420 MODULE_AUTHOR("Alan Cox");
 421 MODULE_DESCRIPTION("low-level driver for the Highpoint HPT366/368");
 422 MODULE_LICENSE("GPL");
 423 MODULE_DEVICE_TABLE(pci, hpt36x);
 424 MODULE_VERSION(DRV_VERSION);