1 // SPDX-License-Identifier: GPL-2.0-only
3 * Libata based driver for Apple "macio" family of PATA controllers
5 * Copyright 2008/2009 Benjamin Herrenschmidt, IBM Corp
6 * <benh@kernel.crashing.org>
8 * Some bits and pieces from drivers/ide/ppc/pmac.c
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/init.h>
18 #include <linux/blkdev.h>
19 #include <linux/ata.h>
20 #include <linux/libata.h>
21 #include <linux/adb.h>
22 #include <linux/pmu.h>
23 #include <linux/scatterlist.h>
25 #include <linux/gfp.h>
26 #include <linux/pci.h>
28 #include <scsi/scsi.h>
29 #include <scsi/scsi_host.h>
30 #include <scsi/scsi_device.h>
32 #include <asm/macio.h>
34 #include <asm/dbdma.h>
35 #include <asm/machdep.h>
36 #include <asm/pmac_feature.h>
37 #include <asm/mediabay.h>
40 #define dev_dbgdma(dev, format, arg...) \
41 dev_printk(KERN_DEBUG , dev , format , ## arg)
43 #define dev_dbgdma(dev, format, arg...) \
44 ({ if (0) dev_printk(KERN_DEBUG, dev, format, ##arg); 0; })
47 #define DRV_NAME "pata_macio"
48 #define DRV_VERSION "0.9"
50 /* Models of macio ATA controller */
52 controller_ohare
, /* OHare based */
53 controller_heathrow
, /* Heathrow/Paddington */
54 controller_kl_ata3
, /* KeyLargo ATA-3 */
55 controller_kl_ata4
, /* KeyLargo ATA-4 */
56 controller_un_ata6
, /* UniNorth2 ATA-6 */
57 controller_k2_ata6
, /* K2 ATA-6 */
58 controller_sh_ata6
, /* Shasta ATA-6 */
61 static const char* macio_ata_names
[] = {
62 "OHare ATA", /* OHare based */
63 "Heathrow ATA", /* Heathrow/Paddington */
64 "KeyLargo ATA-3", /* KeyLargo ATA-3 (MDMA only) */
65 "KeyLargo ATA-4", /* KeyLargo ATA-4 (UDMA/66) */
66 "UniNorth ATA-6", /* UniNorth2 ATA-6 (UDMA/100) */
67 "K2 ATA-6", /* K2 ATA-6 (UDMA/100) */
68 "Shasta ATA-6", /* Shasta ATA-6 (UDMA/133) */
72 * Extra registers, both 32-bit little-endian
74 #define IDE_TIMING_CONFIG 0x200
75 #define IDE_INTERRUPT 0x300
77 /* Kauai (U2) ATA has different register setup */
78 #define IDE_KAUAI_PIO_CONFIG 0x200
79 #define IDE_KAUAI_ULTRA_CONFIG 0x210
80 #define IDE_KAUAI_POLL_CONFIG 0x220
83 * Timing configuration register definitions
86 /* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */
87 #define SYSCLK_TICKS(t) (((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS)
88 #define SYSCLK_TICKS_66(t) (((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS)
89 #define IDE_SYSCLK_NS 30 /* 33Mhz cell */
90 #define IDE_SYSCLK_66_NS 15 /* 66Mhz cell */
92 /* 133Mhz cell, found in shasta.
93 * See comments about 100 Mhz Uninorth 2...
94 * Note that PIO_MASK and MDMA_MASK seem to overlap, that's just
95 * weird and I don't now why .. at this stage
97 #define TR_133_PIOREG_PIO_MASK 0xff000fff
98 #define TR_133_PIOREG_MDMA_MASK 0x00fff800
99 #define TR_133_UDMAREG_UDMA_MASK 0x0003ffff
100 #define TR_133_UDMAREG_UDMA_EN 0x00000001
102 /* 100Mhz cell, found in Uninorth 2 and K2. It appears as a pci device
103 * (106b/0033) on uninorth or K2 internal PCI bus and it's clock is
104 * controlled like gem or fw. It appears to be an evolution of keylargo
105 * ATA4 with a timing register extended to 2x32bits registers (one
106 * for PIO & MWDMA and one for UDMA, and a similar DBDMA channel.
107 * It has it's own local feature control register as well.
109 * After scratching my mind over the timing values, at least for PIO
110 * and MDMA, I think I've figured the format of the timing register,
111 * though I use pre-calculated tables for UDMA as usual...
113 #define TR_100_PIO_ADDRSETUP_MASK 0xff000000 /* Size of field unknown */
114 #define TR_100_PIO_ADDRSETUP_SHIFT 24
115 #define TR_100_MDMA_MASK 0x00fff000
116 #define TR_100_MDMA_RECOVERY_MASK 0x00fc0000
117 #define TR_100_MDMA_RECOVERY_SHIFT 18
118 #define TR_100_MDMA_ACCESS_MASK 0x0003f000
119 #define TR_100_MDMA_ACCESS_SHIFT 12
120 #define TR_100_PIO_MASK 0xff000fff
121 #define TR_100_PIO_RECOVERY_MASK 0x00000fc0
122 #define TR_100_PIO_RECOVERY_SHIFT 6
123 #define TR_100_PIO_ACCESS_MASK 0x0000003f
124 #define TR_100_PIO_ACCESS_SHIFT 0
126 #define TR_100_UDMAREG_UDMA_MASK 0x0000ffff
127 #define TR_100_UDMAREG_UDMA_EN 0x00000001
130 /* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on
131 * 40 connector cable and to 4 on 80 connector one.
132 * Clock unit is 15ns (66Mhz)
134 * 3 Values can be programmed:
135 * - Write data setup, which appears to match the cycle time. They
136 * also call it DIOW setup.
137 * - Ready to pause time (from spec)
138 * - Address setup. That one is weird. I don't see where exactly
139 * it fits in UDMA cycles, I got it's name from an obscure piece
140 * of commented out code in Darwin. They leave it to 0, we do as
141 * well, despite a comment that would lead to think it has a
143 * Apple also add 60ns to the write data setup (or cycle time ?) on
146 #define TR_66_UDMA_MASK 0xfff00000
147 #define TR_66_UDMA_EN 0x00100000 /* Enable Ultra mode for DMA */
148 #define TR_66_PIO_ADDRSETUP_MASK 0xe0000000 /* Address setup */
149 #define TR_66_PIO_ADDRSETUP_SHIFT 29
150 #define TR_66_UDMA_RDY2PAUS_MASK 0x1e000000 /* Ready 2 pause time */
151 #define TR_66_UDMA_RDY2PAUS_SHIFT 25
152 #define TR_66_UDMA_WRDATASETUP_MASK 0x01e00000 /* Write data setup time */
153 #define TR_66_UDMA_WRDATASETUP_SHIFT 21
154 #define TR_66_MDMA_MASK 0x000ffc00
155 #define TR_66_MDMA_RECOVERY_MASK 0x000f8000
156 #define TR_66_MDMA_RECOVERY_SHIFT 15
157 #define TR_66_MDMA_ACCESS_MASK 0x00007c00
158 #define TR_66_MDMA_ACCESS_SHIFT 10
159 #define TR_66_PIO_MASK 0xe00003ff
160 #define TR_66_PIO_RECOVERY_MASK 0x000003e0
161 #define TR_66_PIO_RECOVERY_SHIFT 5
162 #define TR_66_PIO_ACCESS_MASK 0x0000001f
163 #define TR_66_PIO_ACCESS_SHIFT 0
165 /* 33Mhz cell, found in OHare, Heathrow (& Paddington) and KeyLargo
166 * Can do pio & mdma modes, clock unit is 30ns (33Mhz)
168 * The access time and recovery time can be programmed. Some older
169 * Darwin code base limit OHare to 150ns cycle time. I decided to do
170 * the same here fore safety against broken old hardware ;)
171 * The HalfTick bit, when set, adds half a clock (15ns) to the access
172 * time and removes one from recovery. It's not supported on KeyLargo
173 * implementation afaik. The E bit appears to be set for PIO mode 0 and
174 * is used to reach long timings used in this mode.
176 #define TR_33_MDMA_MASK 0x003ff800
177 #define TR_33_MDMA_RECOVERY_MASK 0x001f0000
178 #define TR_33_MDMA_RECOVERY_SHIFT 16
179 #define TR_33_MDMA_ACCESS_MASK 0x0000f800
180 #define TR_33_MDMA_ACCESS_SHIFT 11
181 #define TR_33_MDMA_HALFTICK 0x00200000
182 #define TR_33_PIO_MASK 0x000007ff
183 #define TR_33_PIO_E 0x00000400
184 #define TR_33_PIO_RECOVERY_MASK 0x000003e0
185 #define TR_33_PIO_RECOVERY_SHIFT 5
186 #define TR_33_PIO_ACCESS_MASK 0x0000001f
187 #define TR_33_PIO_ACCESS_SHIFT 0
190 * Interrupt register definitions. Only present on newer cells
191 * (Keylargo and later afaik) so we don't use it.
193 #define IDE_INTR_DMA 0x80000000
194 #define IDE_INTR_DEVICE 0x40000000
197 * FCR Register on Kauai. Not sure what bit 0x4 is ...
199 #define KAUAI_FCR_UATA_MAGIC 0x00000004
200 #define KAUAI_FCR_UATA_RESET_N 0x00000002
201 #define KAUAI_FCR_UATA_ENABLE 0x00000001
204 /* Allow up to 256 DBDMA commands per xfer */
205 #define MAX_DCMDS 256
207 /* Don't let a DMA segment go all the way to 64K */
208 #define MAX_DBDMA_SEG 0xff00
212 * Wait 1s for disk to answer on IDE bus after a hard reset
213 * of the device (via GPIO/FCR).
215 * Some devices seem to "pollute" the bus even after dropping
216 * the BSY bit (typically some combo drives slave on the UDMA
217 * bus) after a hard reset. Since we hard reset all drives on
218 * KeyLargo ATA66, we have to keep that delay around. I may end
219 * up not hard resetting anymore on these and keep the delay only
220 * for older interfaces instead (we have to reset when coming
221 * from MacOS...) --BenH.
223 #define IDE_WAKEUP_DELAY_MS 1000
225 struct pata_macio_timing
;
227 struct pata_macio_priv
{
231 struct device_node
*node
;
232 struct macio_dev
*mdev
;
233 struct pci_dev
*pdev
;
237 void __iomem
*tfregs
;
238 void __iomem
*kauai_fcr
;
239 struct dbdma_cmd
* dma_table_cpu
;
240 dma_addr_t dma_table_dma
;
241 struct ata_host
*host
;
242 const struct pata_macio_timing
*timings
;
245 /* Previous variants of this driver used to calculate timings
246 * for various variants of the chip and use tables for others.
248 * Not only was this confusing, but in addition, it isn't clear
249 * whether our calculation code was correct. It didn't entirely
250 * match the darwin code and whatever documentation I could find
253 * I decided to entirely rely on a table instead for this version
254 * of the driver. Also, because I don't really care about derated
255 * modes and really old HW other than making it work, I'm not going
256 * to calculate / snoop timing values for something else than the
259 struct pata_macio_timing
{
261 u32 reg1
; /* Bits to set in first timing reg */
262 u32 reg2
; /* Bits to set in second timing reg */
265 static const struct pata_macio_timing pata_macio_ohare_timings
[] = {
266 { XFER_PIO_0
, 0x00000526, 0, },
267 { XFER_PIO_1
, 0x00000085, 0, },
268 { XFER_PIO_2
, 0x00000025, 0, },
269 { XFER_PIO_3
, 0x00000025, 0, },
270 { XFER_PIO_4
, 0x00000025, 0, },
271 { XFER_MW_DMA_0
, 0x00074000, 0, },
272 { XFER_MW_DMA_1
, 0x00221000, 0, },
273 { XFER_MW_DMA_2
, 0x00211000, 0, },
277 static const struct pata_macio_timing pata_macio_heathrow_timings
[] = {
278 { XFER_PIO_0
, 0x00000526, 0, },
279 { XFER_PIO_1
, 0x00000085, 0, },
280 { XFER_PIO_2
, 0x00000025, 0, },
281 { XFER_PIO_3
, 0x00000025, 0, },
282 { XFER_PIO_4
, 0x00000025, 0, },
283 { XFER_MW_DMA_0
, 0x00074000, 0, },
284 { XFER_MW_DMA_1
, 0x00221000, 0, },
285 { XFER_MW_DMA_2
, 0x00211000, 0, },
289 static const struct pata_macio_timing pata_macio_kl33_timings
[] = {
290 { XFER_PIO_0
, 0x00000526, 0, },
291 { XFER_PIO_1
, 0x00000085, 0, },
292 { XFER_PIO_2
, 0x00000025, 0, },
293 { XFER_PIO_3
, 0x00000025, 0, },
294 { XFER_PIO_4
, 0x00000025, 0, },
295 { XFER_MW_DMA_0
, 0x00084000, 0, },
296 { XFER_MW_DMA_1
, 0x00021800, 0, },
297 { XFER_MW_DMA_2
, 0x00011800, 0, },
301 static const struct pata_macio_timing pata_macio_kl66_timings
[] = {
302 { XFER_PIO_0
, 0x0000038c, 0, },
303 { XFER_PIO_1
, 0x0000020a, 0, },
304 { XFER_PIO_2
, 0x00000127, 0, },
305 { XFER_PIO_3
, 0x000000c6, 0, },
306 { XFER_PIO_4
, 0x00000065, 0, },
307 { XFER_MW_DMA_0
, 0x00084000, 0, },
308 { XFER_MW_DMA_1
, 0x00029800, 0, },
309 { XFER_MW_DMA_2
, 0x00019400, 0, },
310 { XFER_UDMA_0
, 0x19100000, 0, },
311 { XFER_UDMA_1
, 0x14d00000, 0, },
312 { XFER_UDMA_2
, 0x10900000, 0, },
313 { XFER_UDMA_3
, 0x0c700000, 0, },
314 { XFER_UDMA_4
, 0x0c500000, 0, },
318 static const struct pata_macio_timing pata_macio_kauai_timings
[] = {
319 { XFER_PIO_0
, 0x08000a92, 0, },
320 { XFER_PIO_1
, 0x0800060f, 0, },
321 { XFER_PIO_2
, 0x0800038b, 0, },
322 { XFER_PIO_3
, 0x05000249, 0, },
323 { XFER_PIO_4
, 0x04000148, 0, },
324 { XFER_MW_DMA_0
, 0x00618000, 0, },
325 { XFER_MW_DMA_1
, 0x00209000, 0, },
326 { XFER_MW_DMA_2
, 0x00148000, 0, },
327 { XFER_UDMA_0
, 0, 0x000070c1, },
328 { XFER_UDMA_1
, 0, 0x00005d81, },
329 { XFER_UDMA_2
, 0, 0x00004a61, },
330 { XFER_UDMA_3
, 0, 0x00003a51, },
331 { XFER_UDMA_4
, 0, 0x00002a31, },
332 { XFER_UDMA_5
, 0, 0x00002921, },
336 static const struct pata_macio_timing pata_macio_shasta_timings
[] = {
337 { XFER_PIO_0
, 0x0a000c97, 0, },
338 { XFER_PIO_1
, 0x07000712, 0, },
339 { XFER_PIO_2
, 0x040003cd, 0, },
340 { XFER_PIO_3
, 0x0500028b, 0, },
341 { XFER_PIO_4
, 0x0400010a, 0, },
342 { XFER_MW_DMA_0
, 0x00820800, 0, },
343 { XFER_MW_DMA_1
, 0x0028b000, 0, },
344 { XFER_MW_DMA_2
, 0x001ca000, 0, },
345 { XFER_UDMA_0
, 0, 0x00035901, },
346 { XFER_UDMA_1
, 0, 0x000348b1, },
347 { XFER_UDMA_2
, 0, 0x00033881, },
348 { XFER_UDMA_3
, 0, 0x00033861, },
349 { XFER_UDMA_4
, 0, 0x00033841, },
350 { XFER_UDMA_5
, 0, 0x00033031, },
351 { XFER_UDMA_6
, 0, 0x00033021, },
355 static const struct pata_macio_timing
*pata_macio_find_timing(
356 struct pata_macio_priv
*priv
,
361 for (i
= 0; priv
->timings
[i
].mode
> 0; i
++) {
362 if (priv
->timings
[i
].mode
== mode
)
363 return &priv
->timings
[i
];
369 static void pata_macio_apply_timings(struct ata_port
*ap
, unsigned int device
)
371 struct pata_macio_priv
*priv
= ap
->private_data
;
372 void __iomem
*rbase
= ap
->ioaddr
.cmd_addr
;
374 if (priv
->kind
== controller_sh_ata6
||
375 priv
->kind
== controller_un_ata6
||
376 priv
->kind
== controller_k2_ata6
) {
377 writel(priv
->treg
[device
][0], rbase
+ IDE_KAUAI_PIO_CONFIG
);
378 writel(priv
->treg
[device
][1], rbase
+ IDE_KAUAI_ULTRA_CONFIG
);
380 writel(priv
->treg
[device
][0], rbase
+ IDE_TIMING_CONFIG
);
383 static void pata_macio_dev_select(struct ata_port
*ap
, unsigned int device
)
385 ata_sff_dev_select(ap
, device
);
388 pata_macio_apply_timings(ap
, device
);
391 static void pata_macio_set_timings(struct ata_port
*ap
,
392 struct ata_device
*adev
)
394 struct pata_macio_priv
*priv
= ap
->private_data
;
395 const struct pata_macio_timing
*t
;
397 dev_dbg(priv
->dev
, "Set timings: DEV=%d,PIO=0x%x (%s),DMA=0x%x (%s)\n",
400 ata_mode_string(ata_xfer_mode2mask(adev
->pio_mode
)),
402 ata_mode_string(ata_xfer_mode2mask(adev
->dma_mode
)));
404 /* First clear timings */
405 priv
->treg
[adev
->devno
][0] = priv
->treg
[adev
->devno
][1] = 0;
407 /* Now get the PIO timings */
408 t
= pata_macio_find_timing(priv
, adev
->pio_mode
);
410 dev_warn(priv
->dev
, "Invalid PIO timing requested: 0x%x\n",
412 t
= pata_macio_find_timing(priv
, XFER_PIO_0
);
416 /* PIO timings only ever use the first treg */
417 priv
->treg
[adev
->devno
][0] |= t
->reg1
;
419 /* Now get DMA timings */
420 t
= pata_macio_find_timing(priv
, adev
->dma_mode
);
421 if (t
== NULL
|| (t
->reg1
== 0 && t
->reg2
== 0)) {
422 dev_dbg(priv
->dev
, "DMA timing not set yet, using MW_DMA_0\n");
423 t
= pata_macio_find_timing(priv
, XFER_MW_DMA_0
);
427 /* DMA timings can use both tregs */
428 priv
->treg
[adev
->devno
][0] |= t
->reg1
;
429 priv
->treg
[adev
->devno
][1] |= t
->reg2
;
431 dev_dbg(priv
->dev
, " -> %08x %08x\n",
432 priv
->treg
[adev
->devno
][0],
433 priv
->treg
[adev
->devno
][1]);
435 /* Apply to hardware */
436 pata_macio_apply_timings(ap
, adev
->devno
);
440 * Blast some well known "safe" values to the timing registers at init or
441 * wakeup from sleep time, before we do real calculation
443 static void pata_macio_default_timings(struct pata_macio_priv
*priv
)
445 unsigned int value
, value2
= 0;
448 case controller_sh_ata6
:
452 case controller_un_ata6
:
453 case controller_k2_ata6
:
457 case controller_kl_ata4
:
460 case controller_kl_ata3
:
463 case controller_heathrow
:
464 case controller_ohare
:
469 priv
->treg
[0][0] = priv
->treg
[1][0] = value
;
470 priv
->treg
[0][1] = priv
->treg
[1][1] = value2
;
473 static int pata_macio_cable_detect(struct ata_port
*ap
)
475 struct pata_macio_priv
*priv
= ap
->private_data
;
477 /* Get cable type from device-tree */
478 if (priv
->kind
== controller_kl_ata4
||
479 priv
->kind
== controller_un_ata6
||
480 priv
->kind
== controller_k2_ata6
||
481 priv
->kind
== controller_sh_ata6
) {
482 const char* cable
= of_get_property(priv
->node
, "cable-type",
484 struct device_node
*root
= of_find_node_by_path("/");
485 const char *model
= of_get_property(root
, "model", NULL
);
489 if (cable
&& !strncmp(cable
, "80-", 3)) {
490 /* Some drives fail to detect 80c cable in PowerBook
491 * These machine use proprietary short IDE cable
494 if (!strncmp(model
, "PowerBook", 9))
495 return ATA_CBL_PATA40_SHORT
;
497 return ATA_CBL_PATA80
;
501 /* G5's seem to have incorrect cable type in device-tree.
502 * Let's assume they always have a 80 conductor cable, this seem to
503 * be always the case unless the user mucked around
505 if (of_device_is_compatible(priv
->node
, "K2-UATA") ||
506 of_device_is_compatible(priv
->node
, "shasta-ata"))
507 return ATA_CBL_PATA80
;
509 /* Anything else is 40 connectors */
510 return ATA_CBL_PATA40
;
513 static enum ata_completion_errors
pata_macio_qc_prep(struct ata_queued_cmd
*qc
)
515 unsigned int write
= (qc
->tf
.flags
& ATA_TFLAG_WRITE
);
516 struct ata_port
*ap
= qc
->ap
;
517 struct pata_macio_priv
*priv
= ap
->private_data
;
518 struct scatterlist
*sg
;
519 struct dbdma_cmd
*table
;
522 dev_dbgdma(priv
->dev
, "%s: qc %p flags %lx, write %d dev %d\n",
523 __func__
, qc
, qc
->flags
, write
, qc
->dev
->devno
);
525 if (!(qc
->flags
& ATA_QCFLAG_DMAMAP
))
528 table
= (struct dbdma_cmd
*) priv
->dma_table_cpu
;
531 for_each_sg(qc
->sg
, sg
, qc
->n_elem
, si
) {
532 u32 addr
, sg_len
, len
;
534 /* determine if physical DMA addr spans 64K boundary.
535 * Note h/w doesn't support 64-bit, so we unconditionally
536 * truncate dma_addr_t to u32.
538 addr
= (u32
) sg_dma_address(sg
);
539 sg_len
= sg_dma_len(sg
);
542 /* table overflow should never happen */
543 BUG_ON (pi
++ >= MAX_DCMDS
);
545 len
= (sg_len
< MAX_DBDMA_SEG
) ? sg_len
: MAX_DBDMA_SEG
;
546 table
->command
= cpu_to_le16(write
? OUTPUT_MORE
: INPUT_MORE
);
547 table
->req_count
= cpu_to_le16(len
);
548 table
->phy_addr
= cpu_to_le32(addr
);
550 table
->xfer_status
= 0;
551 table
->res_count
= 0;
558 /* Should never happen according to Tejun */
561 /* Convert the last command to an input/output */
563 table
->command
= cpu_to_le16(write
? OUTPUT_LAST
: INPUT_LAST
);
566 /* Add the stop command to the end of the list */
567 memset(table
, 0, sizeof(struct dbdma_cmd
));
568 table
->command
= cpu_to_le16(DBDMA_STOP
);
570 dev_dbgdma(priv
->dev
, "%s: %d DMA list entries\n", __func__
, pi
);
576 static void pata_macio_freeze(struct ata_port
*ap
)
578 struct dbdma_regs __iomem
*dma_regs
= ap
->ioaddr
.bmdma_addr
;
581 unsigned int timeout
= 1000000;
583 /* Make sure DMA controller is stopped */
584 writel((RUN
|PAUSE
|FLUSH
|WAKE
|DEAD
) << 16, &dma_regs
->control
);
585 while (--timeout
&& (readl(&dma_regs
->status
) & RUN
))
593 static void pata_macio_bmdma_setup(struct ata_queued_cmd
*qc
)
595 struct ata_port
*ap
= qc
->ap
;
596 struct pata_macio_priv
*priv
= ap
->private_data
;
597 struct dbdma_regs __iomem
*dma_regs
= ap
->ioaddr
.bmdma_addr
;
598 int dev
= qc
->dev
->devno
;
600 dev_dbgdma(priv
->dev
, "%s: qc %p\n", __func__
, qc
);
602 /* Make sure DMA commands updates are visible */
603 writel(priv
->dma_table_dma
, &dma_regs
->cmdptr
);
605 /* On KeyLargo 66Mhz cell, we need to add 60ns to wrDataSetup on
608 if (priv
->kind
== controller_kl_ata4
&&
609 (priv
->treg
[dev
][0] & TR_66_UDMA_EN
)) {
610 void __iomem
*rbase
= ap
->ioaddr
.cmd_addr
;
611 u32 reg
= priv
->treg
[dev
][0];
613 if (!(qc
->tf
.flags
& ATA_TFLAG_WRITE
))
615 writel(reg
, rbase
+ IDE_TIMING_CONFIG
);
618 /* issue r/w command */
619 ap
->ops
->sff_exec_command(ap
, &qc
->tf
);
622 static void pata_macio_bmdma_start(struct ata_queued_cmd
*qc
)
624 struct ata_port
*ap
= qc
->ap
;
625 struct pata_macio_priv
*priv
= ap
->private_data
;
626 struct dbdma_regs __iomem
*dma_regs
= ap
->ioaddr
.bmdma_addr
;
628 dev_dbgdma(priv
->dev
, "%s: qc %p\n", __func__
, qc
);
630 writel((RUN
<< 16) | RUN
, &dma_regs
->control
);
631 /* Make sure it gets to the controller right now */
632 (void)readl(&dma_regs
->control
);
635 static void pata_macio_bmdma_stop(struct ata_queued_cmd
*qc
)
637 struct ata_port
*ap
= qc
->ap
;
638 struct pata_macio_priv
*priv
= ap
->private_data
;
639 struct dbdma_regs __iomem
*dma_regs
= ap
->ioaddr
.bmdma_addr
;
640 unsigned int timeout
= 1000000;
642 dev_dbgdma(priv
->dev
, "%s: qc %p\n", __func__
, qc
);
644 /* Stop the DMA engine and wait for it to full halt */
645 writel (((RUN
|WAKE
|DEAD
) << 16), &dma_regs
->control
);
646 while (--timeout
&& (readl(&dma_regs
->status
) & RUN
))
650 static u8
pata_macio_bmdma_status(struct ata_port
*ap
)
652 struct pata_macio_priv
*priv
= ap
->private_data
;
653 struct dbdma_regs __iomem
*dma_regs
= ap
->ioaddr
.bmdma_addr
;
654 u32 dstat
, rstat
= ATA_DMA_INTR
;
655 unsigned long timeout
= 0;
657 dstat
= readl(&dma_regs
->status
);
659 dev_dbgdma(priv
->dev
, "%s: dstat=%x\n", __func__
, dstat
);
661 /* We have two things to deal with here:
663 * - The dbdma won't stop if the command was started
664 * but completed with an error without transferring all
665 * datas. This happens when bad blocks are met during
666 * a multi-block transfer.
668 * - The dbdma fifo hasn't yet finished flushing to
669 * to system memory when the disk interrupt occurs.
673 /* First check for errors */
674 if ((dstat
& (RUN
|DEAD
)) != RUN
)
675 rstat
|= ATA_DMA_ERR
;
677 /* If ACTIVE is cleared, the STOP command has been hit and
678 * the transfer is complete. If not, we have to flush the
681 if ((dstat
& ACTIVE
) == 0)
684 dev_dbgdma(priv
->dev
, "%s: DMA still active, flushing...\n", __func__
);
686 /* If dbdma didn't execute the STOP command yet, the
687 * active bit is still set. We consider that we aren't
688 * sharing interrupts (which is hopefully the case with
689 * those controllers) and so we just try to flush the
690 * channel for pending data in the fifo
693 writel((FLUSH
<< 16) | FLUSH
, &dma_regs
->control
);
696 dstat
= readl(&dma_regs
->status
);
697 if ((dstat
& FLUSH
) == 0)
699 if (++timeout
> 1000) {
700 dev_warn(priv
->dev
, "timeout flushing DMA\n");
701 rstat
|= ATA_DMA_ERR
;
708 /* port_start is when we allocate the DMA command list */
709 static int pata_macio_port_start(struct ata_port
*ap
)
711 struct pata_macio_priv
*priv
= ap
->private_data
;
713 if (ap
->ioaddr
.bmdma_addr
== NULL
)
716 /* Allocate space for the DBDMA commands.
718 * The +2 is +1 for the stop command and +1 to allow for
719 * aligning the start address to a multiple of 16 bytes.
721 priv
->dma_table_cpu
=
722 dmam_alloc_coherent(priv
->dev
,
723 (MAX_DCMDS
+ 2) * sizeof(struct dbdma_cmd
),
724 &priv
->dma_table_dma
, GFP_KERNEL
);
725 if (priv
->dma_table_cpu
== NULL
) {
726 dev_err(priv
->dev
, "Unable to allocate DMA command list\n");
727 ap
->ioaddr
.bmdma_addr
= NULL
;
734 static void pata_macio_irq_clear(struct ata_port
*ap
)
736 struct pata_macio_priv
*priv
= ap
->private_data
;
738 /* Nothing to do here */
740 dev_dbgdma(priv
->dev
, "%s\n", __func__
);
743 static void pata_macio_reset_hw(struct pata_macio_priv
*priv
, int resume
)
745 dev_dbg(priv
->dev
, "Enabling & resetting... \n");
750 if (priv
->kind
== controller_ohare
&& !resume
) {
751 /* The code below is having trouble on some ohare machines
752 * (timing related ?). Until I can put my hand on one of these
753 * units, I keep the old way
755 ppc_md
.feature_call(PMAC_FTR_IDE_ENABLE
, priv
->node
, 0, 1);
759 /* Reset and enable controller */
760 rc
= ppc_md
.feature_call(PMAC_FTR_IDE_RESET
,
761 priv
->node
, priv
->aapl_bus_id
, 1);
762 ppc_md
.feature_call(PMAC_FTR_IDE_ENABLE
,
763 priv
->node
, priv
->aapl_bus_id
, 1);
765 /* Only bother waiting if there's a reset control */
767 ppc_md
.feature_call(PMAC_FTR_IDE_RESET
,
768 priv
->node
, priv
->aapl_bus_id
, 0);
769 msleep(IDE_WAKEUP_DELAY_MS
);
773 /* If resuming a PCI device, restore the config space here */
774 if (priv
->pdev
&& resume
) {
777 pci_restore_state(priv
->pdev
);
778 rc
= pcim_enable_device(priv
->pdev
);
780 dev_err(&priv
->pdev
->dev
,
781 "Failed to enable device after resume (%d)\n",
784 pci_set_master(priv
->pdev
);
787 /* On Kauai, initialize the FCR. We don't perform a reset, doesn't really
788 * seem necessary and speeds up the boot process
791 writel(KAUAI_FCR_UATA_MAGIC
|
792 KAUAI_FCR_UATA_RESET_N
|
793 KAUAI_FCR_UATA_ENABLE
, priv
->kauai_fcr
);
796 /* Hook the standard slave config to fixup some HW related alignment
799 static int pata_macio_slave_config(struct scsi_device
*sdev
)
801 struct ata_port
*ap
= ata_shost_to_port(sdev
->host
);
802 struct pata_macio_priv
*priv
= ap
->private_data
;
803 struct ata_device
*dev
;
807 /* First call original */
808 rc
= ata_scsi_slave_config(sdev
);
812 /* This is lifted from sata_nv */
813 dev
= &ap
->link
.device
[sdev
->id
];
815 /* OHare has issues with non cache aligned DMA on some chipsets */
816 if (priv
->kind
== controller_ohare
) {
817 blk_queue_update_dma_alignment(sdev
->request_queue
, 31);
818 blk_queue_update_dma_pad(sdev
->request_queue
, 31);
820 /* Tell the world about it */
821 ata_dev_info(dev
, "OHare alignment limits applied\n");
825 /* We only have issues with ATAPI */
826 if (dev
->class != ATA_DEV_ATAPI
)
829 /* Shasta and K2 seem to have "issues" with reads ... */
830 if (priv
->kind
== controller_sh_ata6
|| priv
->kind
== controller_k2_ata6
) {
831 /* Allright these are bad, apply restrictions */
832 blk_queue_update_dma_alignment(sdev
->request_queue
, 15);
833 blk_queue_update_dma_pad(sdev
->request_queue
, 15);
835 /* We enable MWI and hack cache line size directly here, this
836 * is specific to this chipset and not normal values, we happen
837 * to somewhat know what we are doing here (which is basically
838 * to do the same Apple does and pray they did not get it wrong :-)
841 pci_write_config_byte(priv
->pdev
, PCI_CACHE_LINE_SIZE
, 0x08);
842 pci_read_config_word(priv
->pdev
, PCI_COMMAND
, &cmd
);
843 pci_write_config_word(priv
->pdev
, PCI_COMMAND
,
844 cmd
| PCI_COMMAND_INVALIDATE
);
846 /* Tell the world about it */
847 ata_dev_info(dev
, "K2/Shasta alignment limits applied\n");
853 #ifdef CONFIG_PM_SLEEP
854 static int pata_macio_do_suspend(struct pata_macio_priv
*priv
, pm_message_t mesg
)
858 /* First, core libata suspend to do most of the work */
859 rc
= ata_host_suspend(priv
->host
, mesg
);
863 /* Restore to default timings */
864 pata_macio_default_timings(priv
);
866 /* Mask interrupt. Not strictly necessary but old driver did
867 * it and I'd rather not change that here */
868 disable_irq(priv
->irq
);
870 /* The media bay will handle itself just fine */
874 /* Kauai has bus control FCRs directly here */
875 if (priv
->kauai_fcr
) {
876 u32 fcr
= readl(priv
->kauai_fcr
);
877 fcr
&= ~(KAUAI_FCR_UATA_RESET_N
| KAUAI_FCR_UATA_ENABLE
);
878 writel(fcr
, priv
->kauai_fcr
);
881 /* For PCI, save state and disable DMA. No need to call
882 * pci_set_power_state(), the HW doesn't do D states that
883 * way, the platform code will take care of suspending the
887 pci_save_state(priv
->pdev
);
888 pci_disable_device(priv
->pdev
);
891 /* Disable the bus on older machines and the cell on kauai */
892 ppc_md
.feature_call(PMAC_FTR_IDE_ENABLE
, priv
->node
,
893 priv
->aapl_bus_id
, 0);
898 static int pata_macio_do_resume(struct pata_macio_priv
*priv
)
900 /* Reset and re-enable the HW */
901 pata_macio_reset_hw(priv
, 1);
903 /* Sanitize drive timings */
904 pata_macio_apply_timings(priv
->host
->ports
[0], 0);
906 /* We want our IRQ back ! */
907 enable_irq(priv
->irq
);
909 /* Let the libata core take it from there */
910 ata_host_resume(priv
->host
);
914 #endif /* CONFIG_PM_SLEEP */
916 static struct scsi_host_template pata_macio_sht
= {
917 ATA_BASE_SHT(DRV_NAME
),
918 .sg_tablesize
= MAX_DCMDS
,
919 /* We may not need that strict one */
920 .dma_boundary
= ATA_DMA_BOUNDARY
,
921 /* Not sure what the real max is but we know it's less than 64K, let's
924 .max_segment_size
= MAX_DBDMA_SEG
,
925 .slave_configure
= pata_macio_slave_config
,
928 static struct ata_port_operations pata_macio_ops
= {
929 .inherits
= &ata_bmdma_port_ops
,
931 .freeze
= pata_macio_freeze
,
932 .set_piomode
= pata_macio_set_timings
,
933 .set_dmamode
= pata_macio_set_timings
,
934 .cable_detect
= pata_macio_cable_detect
,
935 .sff_dev_select
= pata_macio_dev_select
,
936 .qc_prep
= pata_macio_qc_prep
,
937 .bmdma_setup
= pata_macio_bmdma_setup
,
938 .bmdma_start
= pata_macio_bmdma_start
,
939 .bmdma_stop
= pata_macio_bmdma_stop
,
940 .bmdma_status
= pata_macio_bmdma_status
,
941 .port_start
= pata_macio_port_start
,
942 .sff_irq_clear
= pata_macio_irq_clear
,
945 static void pata_macio_invariants(struct pata_macio_priv
*priv
)
949 /* Identify the type of controller */
950 if (of_device_is_compatible(priv
->node
, "shasta-ata")) {
951 priv
->kind
= controller_sh_ata6
;
952 priv
->timings
= pata_macio_shasta_timings
;
953 } else if (of_device_is_compatible(priv
->node
, "kauai-ata")) {
954 priv
->kind
= controller_un_ata6
;
955 priv
->timings
= pata_macio_kauai_timings
;
956 } else if (of_device_is_compatible(priv
->node
, "K2-UATA")) {
957 priv
->kind
= controller_k2_ata6
;
958 priv
->timings
= pata_macio_kauai_timings
;
959 } else if (of_device_is_compatible(priv
->node
, "keylargo-ata")) {
960 if (of_node_name_eq(priv
->node
, "ata-4")) {
961 priv
->kind
= controller_kl_ata4
;
962 priv
->timings
= pata_macio_kl66_timings
;
964 priv
->kind
= controller_kl_ata3
;
965 priv
->timings
= pata_macio_kl33_timings
;
967 } else if (of_device_is_compatible(priv
->node
, "heathrow-ata")) {
968 priv
->kind
= controller_heathrow
;
969 priv
->timings
= pata_macio_heathrow_timings
;
971 priv
->kind
= controller_ohare
;
972 priv
->timings
= pata_macio_ohare_timings
;
975 /* XXX FIXME --- setup priv->mediabay here */
977 /* Get Apple bus ID (for clock and ASIC control) */
978 bidp
= of_get_property(priv
->node
, "AAPL,bus-id", NULL
);
979 priv
->aapl_bus_id
= bidp
? *bidp
: 0;
981 /* Fixup missing Apple bus ID in case of media-bay */
982 if (priv
->mediabay
&& !bidp
)
983 priv
->aapl_bus_id
= 1;
986 static void pata_macio_setup_ios(struct ata_ioports
*ioaddr
,
987 void __iomem
* base
, void __iomem
* dma
)
989 /* cmd_addr is the base of regs for that port */
990 ioaddr
->cmd_addr
= base
;
992 /* taskfile registers */
993 ioaddr
->data_addr
= base
+ (ATA_REG_DATA
<< 4);
994 ioaddr
->error_addr
= base
+ (ATA_REG_ERR
<< 4);
995 ioaddr
->feature_addr
= base
+ (ATA_REG_FEATURE
<< 4);
996 ioaddr
->nsect_addr
= base
+ (ATA_REG_NSECT
<< 4);
997 ioaddr
->lbal_addr
= base
+ (ATA_REG_LBAL
<< 4);
998 ioaddr
->lbam_addr
= base
+ (ATA_REG_LBAM
<< 4);
999 ioaddr
->lbah_addr
= base
+ (ATA_REG_LBAH
<< 4);
1000 ioaddr
->device_addr
= base
+ (ATA_REG_DEVICE
<< 4);
1001 ioaddr
->status_addr
= base
+ (ATA_REG_STATUS
<< 4);
1002 ioaddr
->command_addr
= base
+ (ATA_REG_CMD
<< 4);
1003 ioaddr
->altstatus_addr
= base
+ 0x160;
1004 ioaddr
->ctl_addr
= base
+ 0x160;
1005 ioaddr
->bmdma_addr
= dma
;
1008 static void pmac_macio_calc_timing_masks(struct pata_macio_priv
*priv
,
1009 struct ata_port_info
*pinfo
)
1013 pinfo
->pio_mask
= 0;
1014 pinfo
->mwdma_mask
= 0;
1015 pinfo
->udma_mask
= 0;
1017 while (priv
->timings
[i
].mode
> 0) {
1018 unsigned int mask
= 1U << (priv
->timings
[i
].mode
& 0x0f);
1019 switch(priv
->timings
[i
].mode
& 0xf0) {
1020 case 0x00: /* PIO */
1021 pinfo
->pio_mask
|= (mask
>> 8);
1023 case 0x20: /* MWDMA */
1024 pinfo
->mwdma_mask
|= mask
;
1026 case 0x40: /* UDMA */
1027 pinfo
->udma_mask
|= mask
;
1032 dev_dbg(priv
->dev
, "Supported masks: PIO=%lx, MWDMA=%lx, UDMA=%lx\n",
1033 pinfo
->pio_mask
, pinfo
->mwdma_mask
, pinfo
->udma_mask
);
1036 static int pata_macio_common_init(struct pata_macio_priv
*priv
,
1037 resource_size_t tfregs
,
1038 resource_size_t dmaregs
,
1039 resource_size_t fcregs
,
1042 struct ata_port_info pinfo
;
1043 const struct ata_port_info
*ppi
[] = { &pinfo
, NULL
};
1044 void __iomem
*dma_regs
= NULL
;
1046 /* Fill up privates with various invariants collected from the
1049 pata_macio_invariants(priv
);
1051 /* Make sure we have sane initial timings in the cache */
1052 pata_macio_default_timings(priv
);
1054 /* Allocate libata host for 1 port */
1055 memset(&pinfo
, 0, sizeof(struct ata_port_info
));
1056 pmac_macio_calc_timing_masks(priv
, &pinfo
);
1057 pinfo
.flags
= ATA_FLAG_SLAVE_POSS
;
1058 pinfo
.port_ops
= &pata_macio_ops
;
1059 pinfo
.private_data
= priv
;
1061 priv
->host
= ata_host_alloc_pinfo(priv
->dev
, ppi
, 1);
1062 if (priv
->host
== NULL
) {
1063 dev_err(priv
->dev
, "Failed to allocate ATA port structure\n");
1067 /* Setup the private data in host too */
1068 priv
->host
->private_data
= priv
;
1070 /* Map base registers */
1071 priv
->tfregs
= devm_ioremap(priv
->dev
, tfregs
, 0x100);
1072 if (priv
->tfregs
== NULL
) {
1073 dev_err(priv
->dev
, "Failed to map ATA ports\n");
1076 priv
->host
->iomap
= &priv
->tfregs
;
1080 dma_regs
= devm_ioremap(priv
->dev
, dmaregs
,
1081 sizeof(struct dbdma_regs
));
1082 if (dma_regs
== NULL
)
1083 dev_warn(priv
->dev
, "Failed to map ATA DMA registers\n");
1086 /* If chip has local feature control, map those regs too */
1088 priv
->kauai_fcr
= devm_ioremap(priv
->dev
, fcregs
, 4);
1089 if (priv
->kauai_fcr
== NULL
) {
1090 dev_err(priv
->dev
, "Failed to map ATA FCR register\n");
1095 /* Setup port data structure */
1096 pata_macio_setup_ios(&priv
->host
->ports
[0]->ioaddr
,
1097 priv
->tfregs
, dma_regs
);
1098 priv
->host
->ports
[0]->private_data
= priv
;
1100 /* hard-reset the controller */
1101 pata_macio_reset_hw(priv
, 0);
1102 pata_macio_apply_timings(priv
->host
->ports
[0], 0);
1104 /* Enable bus master if necessary */
1105 if (priv
->pdev
&& dma_regs
)
1106 pci_set_master(priv
->pdev
);
1108 dev_info(priv
->dev
, "Activating pata-macio chipset %s, Apple bus ID %d\n",
1109 macio_ata_names
[priv
->kind
], priv
->aapl_bus_id
);
1113 return ata_host_activate(priv
->host
, irq
, ata_bmdma_interrupt
, 0,
1117 static int pata_macio_attach(struct macio_dev
*mdev
,
1118 const struct of_device_id
*match
)
1120 struct pata_macio_priv
*priv
;
1121 resource_size_t tfregs
, dmaregs
= 0;
1125 /* Check for broken device-trees */
1126 if (macio_resource_count(mdev
) == 0) {
1127 dev_err(&mdev
->ofdev
.dev
,
1128 "No addresses for controller\n");
1132 /* Enable managed resources */
1133 macio_enable_devres(mdev
);
1135 /* Allocate and init private data structure */
1136 priv
= devm_kzalloc(&mdev
->ofdev
.dev
,
1137 sizeof(struct pata_macio_priv
), GFP_KERNEL
);
1141 priv
->node
= of_node_get(mdev
->ofdev
.dev
.of_node
);
1143 priv
->dev
= &mdev
->ofdev
.dev
;
1145 /* Request memory resource for taskfile registers */
1146 if (macio_request_resource(mdev
, 0, "pata-macio")) {
1147 dev_err(&mdev
->ofdev
.dev
,
1148 "Cannot obtain taskfile resource\n");
1151 tfregs
= macio_resource_start(mdev
, 0);
1153 /* Request resources for DMA registers if any */
1154 if (macio_resource_count(mdev
) >= 2) {
1155 if (macio_request_resource(mdev
, 1, "pata-macio-dma"))
1156 dev_err(&mdev
->ofdev
.dev
,
1157 "Cannot obtain DMA resource\n");
1159 dmaregs
= macio_resource_start(mdev
, 1);
1163 * Fixup missing IRQ for some old implementations with broken
1166 * This is a bit bogus, it should be fixed in the device-tree itself,
1167 * via the existing macio fixups, based on the type of interrupt
1168 * controller in the machine. However, I have no test HW for this case,
1169 * and this trick works well enough on those old machines...
1171 if (macio_irq_count(mdev
) == 0) {
1172 dev_warn(&mdev
->ofdev
.dev
,
1173 "No interrupts for controller, using 13\n");
1174 irq
= irq_create_mapping(NULL
, 13);
1176 irq
= macio_irq(mdev
, 0);
1178 /* Prevvent media bay callbacks until fully registered */
1179 lock_media_bay(priv
->mdev
->media_bay
);
1181 /* Get register addresses and call common initialization */
1182 rc
= pata_macio_common_init(priv
,
1183 tfregs
, /* Taskfile regs */
1184 dmaregs
, /* DBDMA regs */
1185 0, /* Feature control */
1187 unlock_media_bay(priv
->mdev
->media_bay
);
1192 static int pata_macio_detach(struct macio_dev
*mdev
)
1194 struct ata_host
*host
= macio_get_drvdata(mdev
);
1195 struct pata_macio_priv
*priv
= host
->private_data
;
1197 lock_media_bay(priv
->mdev
->media_bay
);
1199 /* Make sure the mediabay callback doesn't try to access
1202 priv
->host
->private_data
= NULL
;
1204 ata_host_detach(host
);
1206 unlock_media_bay(priv
->mdev
->media_bay
);
1211 #ifdef CONFIG_PM_SLEEP
1212 static int pata_macio_suspend(struct macio_dev
*mdev
, pm_message_t mesg
)
1214 struct ata_host
*host
= macio_get_drvdata(mdev
);
1216 return pata_macio_do_suspend(host
->private_data
, mesg
);
1219 static int pata_macio_resume(struct macio_dev
*mdev
)
1221 struct ata_host
*host
= macio_get_drvdata(mdev
);
1223 return pata_macio_do_resume(host
->private_data
);
1225 #endif /* CONFIG_PM_SLEEP */
1227 #ifdef CONFIG_PMAC_MEDIABAY
1228 static void pata_macio_mb_event(struct macio_dev
* mdev
, int mb_state
)
1230 struct ata_host
*host
= macio_get_drvdata(mdev
);
1231 struct ata_port
*ap
;
1232 struct ata_eh_info
*ehi
;
1233 struct ata_device
*dev
;
1234 unsigned long flags
;
1236 if (!host
|| !host
->private_data
)
1238 ap
= host
->ports
[0];
1239 spin_lock_irqsave(ap
->lock
, flags
);
1240 ehi
= &ap
->link
.eh_info
;
1241 if (mb_state
== MB_CD
) {
1242 ata_ehi_push_desc(ehi
, "mediabay plug");
1243 ata_ehi_hotplugged(ehi
);
1244 ata_port_freeze(ap
);
1246 ata_ehi_push_desc(ehi
, "mediabay unplug");
1247 ata_for_each_dev(dev
, &ap
->link
, ALL
)
1248 dev
->flags
|= ATA_DFLAG_DETACH
;
1251 spin_unlock_irqrestore(ap
->lock
, flags
);
1254 #endif /* CONFIG_PMAC_MEDIABAY */
1257 static int pata_macio_pci_attach(struct pci_dev
*pdev
,
1258 const struct pci_device_id
*id
)
1260 struct pata_macio_priv
*priv
;
1261 struct device_node
*np
;
1262 resource_size_t rbase
;
1264 /* We cannot use a MacIO controller without its OF device node */
1265 np
= pci_device_to_OF_node(pdev
);
1268 "Cannot find OF device node for controller\n");
1272 /* Check that it can be enabled */
1273 if (pcim_enable_device(pdev
)) {
1275 "Cannot enable controller PCI device\n");
1279 /* Allocate and init private data structure */
1280 priv
= devm_kzalloc(&pdev
->dev
,
1281 sizeof(struct pata_macio_priv
), GFP_KERNEL
);
1285 priv
->node
= of_node_get(np
);
1287 priv
->dev
= &pdev
->dev
;
1289 /* Get MMIO regions */
1290 if (pci_request_regions(pdev
, "pata-macio")) {
1292 "Cannot obtain PCI resources\n");
1296 /* Get register addresses and call common initialization */
1297 rbase
= pci_resource_start(pdev
, 0);
1298 if (pata_macio_common_init(priv
,
1299 rbase
+ 0x2000, /* Taskfile regs */
1300 rbase
+ 0x1000, /* DBDMA regs */
1301 rbase
, /* Feature control */
1308 static void pata_macio_pci_detach(struct pci_dev
*pdev
)
1310 struct ata_host
*host
= pci_get_drvdata(pdev
);
1312 ata_host_detach(host
);
1315 #ifdef CONFIG_PM_SLEEP
1316 static int pata_macio_pci_suspend(struct pci_dev
*pdev
, pm_message_t mesg
)
1318 struct ata_host
*host
= pci_get_drvdata(pdev
);
1320 return pata_macio_do_suspend(host
->private_data
, mesg
);
1323 static int pata_macio_pci_resume(struct pci_dev
*pdev
)
1325 struct ata_host
*host
= pci_get_drvdata(pdev
);
1327 return pata_macio_do_resume(host
->private_data
);
1329 #endif /* CONFIG_PM_SLEEP */
1331 static const struct of_device_id pata_macio_match
[] =
1347 MODULE_DEVICE_TABLE(of
, pata_macio_match
);
1349 static struct macio_driver pata_macio_driver
=
1352 .name
= "pata-macio",
1353 .owner
= THIS_MODULE
,
1354 .of_match_table
= pata_macio_match
,
1356 .probe
= pata_macio_attach
,
1357 .remove
= pata_macio_detach
,
1358 #ifdef CONFIG_PM_SLEEP
1359 .suspend
= pata_macio_suspend
,
1360 .resume
= pata_macio_resume
,
1362 #ifdef CONFIG_PMAC_MEDIABAY
1363 .mediabay_event
= pata_macio_mb_event
,
1367 static const struct pci_device_id pata_macio_pci_match
[] = {
1368 { PCI_VDEVICE(APPLE
, PCI_DEVICE_ID_APPLE_UNI_N_ATA
), 0 },
1369 { PCI_VDEVICE(APPLE
, PCI_DEVICE_ID_APPLE_IPID_ATA100
), 0 },
1370 { PCI_VDEVICE(APPLE
, PCI_DEVICE_ID_APPLE_K2_ATA100
), 0 },
1371 { PCI_VDEVICE(APPLE
, PCI_DEVICE_ID_APPLE_SH_ATA
), 0 },
1372 { PCI_VDEVICE(APPLE
, PCI_DEVICE_ID_APPLE_IPID2_ATA
), 0 },
1376 static struct pci_driver pata_macio_pci_driver
= {
1377 .name
= "pata-pci-macio",
1378 .id_table
= pata_macio_pci_match
,
1379 .probe
= pata_macio_pci_attach
,
1380 .remove
= pata_macio_pci_detach
,
1381 #ifdef CONFIG_PM_SLEEP
1382 .suspend
= pata_macio_pci_suspend
,
1383 .resume
= pata_macio_pci_resume
,
1386 .owner
= THIS_MODULE
,
1389 MODULE_DEVICE_TABLE(pci
, pata_macio_pci_match
);
1392 static int __init
pata_macio_init(void)
1396 if (!machine_is(powermac
))
1399 rc
= pci_register_driver(&pata_macio_pci_driver
);
1402 rc
= macio_register_driver(&pata_macio_driver
);
1404 pci_unregister_driver(&pata_macio_pci_driver
);
1410 static void __exit
pata_macio_exit(void)
1412 macio_unregister_driver(&pata_macio_driver
);
1413 pci_unregister_driver(&pata_macio_pci_driver
);
1416 module_init(pata_macio_init
);
1417 module_exit(pata_macio_exit
);
1419 MODULE_AUTHOR("Benjamin Herrenschmidt");
1420 MODULE_DESCRIPTION("Apple MacIO PATA driver");
1421 MODULE_LICENSE("GPL");
1422 MODULE_VERSION(DRV_VERSION
);