drivers/ata/pata_serverworks.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * pata_serverworks.c   - Serverworks PATA for new ATA layer
   4  *                        (C) 2005 Red Hat Inc
   5  *                        (C) 2010 Bartlomiej Zolnierkiewicz
   6  *
   7  * based upon
   8  *
   9  * serverworks.c
  10  *
  11  * Copyright (C) 1998-2000 Michel Aubry
  12  * Copyright (C) 1998-2000 Andrzej Krzysztofowicz
  13  * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
  14  * Portions copyright (c) 2001 Sun Microsystems
  15  *
  16  *
  17  * RCC/ServerWorks IDE driver for Linux
  18  *
  19  *   OSB4: `Open South Bridge' IDE Interface (fn 1)
  20  *         supports UDMA mode 2 (33 MB/s)
  21  *
  22  *   CSB5: `Champion South Bridge' IDE Interface (fn 1)
  23  *         all revisions support UDMA mode 4 (66 MB/s)
  24  *         revision A2.0 and up support UDMA mode 5 (100 MB/s)
  25  *
  26  *         *** The CSB5 does not provide ANY register ***
  27  *         *** to detect 80-conductor cable presence. ***
  28  *
  29  *   CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
  30  *
  31  * Documentation:
  32  *      Available under NDA only. Errata info very hard to get.
  33  */
  34
  35 #include <linux/kernel.h>
  36 #include <linux/module.h>
  37 #include <linux/pci.h>
  38 #include <linux/blkdev.h>
  39 #include <linux/delay.h>
  40 #include <scsi/scsi_host.h>
  41 #include <linux/libata.h>
  42
  43 #define DRV_NAME "pata_serverworks"
  44 #define DRV_VERSION "0.4.3"
  45
  46 #define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
  47 #define SVWKS_CSB6_REVISION     0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */
  48
  49 /* Seagate Barracuda ATA IV Family drives in UDMA mode 5
  50  * can overrun their FIFOs when used with the CSB5 */
  51
  52 static const char *csb_bad_ata100[] = {
  53         "ST320011A",
  54         "ST340016A",
  55         "ST360021A",
  56         "ST380021A",
  57         NULL
  58 };
  59
  60 /**
  61  *      oem_cable       -       Dell/Sun serverworks cable detection
  62  *      @ap: ATA port to do cable detect
  63  *
  64  *      Dell PowerEdge and Sun Cobalt 'Alpine' hide the 40/80 pin select
  65  *      for their interfaces in the top two bits of the subsystem ID.
  66  */
  67
  68 static int oem_cable(struct ata_port *ap)
  69 {
  70         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  71
  72         if (pdev->subsystem_device & (1 << (ap->port_no + 14)))
  73                 return ATA_CBL_PATA80;
  74         return ATA_CBL_PATA40;
  75 }
  76
  77 struct sv_cable_table {
  78         int device;
  79         int subvendor;
  80         int (*cable_detect)(struct ata_port *ap);
  81 };
  82
  83 static struct sv_cable_table cable_detect[] = {
  84         { PCI_DEVICE_ID_SERVERWORKS_CSB5IDE,   PCI_VENDOR_ID_DELL, oem_cable },
  85         { PCI_DEVICE_ID_SERVERWORKS_CSB6IDE,   PCI_VENDOR_ID_DELL, oem_cable },
  86         { PCI_DEVICE_ID_SERVERWORKS_CSB5IDE,   PCI_VENDOR_ID_SUN,  oem_cable },
  87         { PCI_DEVICE_ID_SERVERWORKS_OSB4IDE,   PCI_ANY_ID, ata_cable_40wire  },
  88         { PCI_DEVICE_ID_SERVERWORKS_CSB5IDE,   PCI_ANY_ID, ata_cable_unknown },
  89         { PCI_DEVICE_ID_SERVERWORKS_CSB6IDE,   PCI_ANY_ID, ata_cable_unknown },
  90         { PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2,  PCI_ANY_ID, ata_cable_unknown },
  91         { PCI_DEVICE_ID_SERVERWORKS_HT1000IDE, PCI_ANY_ID, ata_cable_unknown },
  92         { }
  93 };
  94
  95 /**
  96  *      serverworks_cable_detect        -       cable detection
  97  *      @ap: ATA port
  98  *
  99  *      Perform cable detection according to the device and subvendor
 100  *      identifications
 101  */
 102
 103 static int serverworks_cable_detect(struct ata_port *ap)
 104 {
 105         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 106         struct sv_cable_table *cb = cable_detect;
 107
 108         while(cb->device) {
 109                 if (cb->device == pdev->device &&
 110                     (cb->subvendor == pdev->subsystem_vendor ||
 111                       cb->subvendor == PCI_ANY_ID)) {
 112                         return cb->cable_detect(ap);
 113                 }
 114                 cb++;
 115         }
 116
 117         BUG();
 118         return -1;      /* kill compiler warning */
 119 }
 120
 121 /**
 122  *      serverworks_is_csb      -       Check for CSB or OSB
 123  *      @pdev: PCI device to check
 124  *
 125  *      Returns true if the device being checked is known to be a CSB
 126  *      series device.
 127  */
 128
 129 static u8 serverworks_is_csb(struct pci_dev *pdev)
 130 {
 131         switch (pdev->device) {
 132                 case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
 133                 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
 134                 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
 135                 case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
 136                         return 1;
 137                 default:
 138                         break;
 139         }
 140         return 0;
 141 }
 142
 143 /**
 144  *      serverworks_osb4_filter -       mode selection filter
 145  *      @adev: ATA device
 146  *      @mask: Mask of proposed modes
 147  *
 148  *      Filter the offered modes for the device to apply controller
 149  *      specific rules. OSB4 requires no UDMA for disks due to a FIFO
 150  *      bug we hit.
 151  */
 152
 153 static unsigned long serverworks_osb4_filter(struct ata_device *adev, unsigned long mask)
 154 {
 155         if (adev->class == ATA_DEV_ATA)
 156                 mask &= ~ATA_MASK_UDMA;
 157         return mask;
 158 }
 159
 160
 161 /**
 162  *      serverworks_csb_filter  -       mode selection filter
 163  *      @adev: ATA device
 164  *      @mask: Mask of proposed modes
 165  *
 166  *      Check the blacklist and disable UDMA5 if matched
 167  */
 168
 169 static unsigned long serverworks_csb_filter(struct ata_device *adev, unsigned long mask)
 170 {
 171         const char *p;
 172         char model_num[ATA_ID_PROD_LEN + 1];
 173         int i;
 174
 175         /* Disk, UDMA */
 176         if (adev->class != ATA_DEV_ATA)
 177                 return mask;
 178
 179         /* Actually do need to check */
 180         ata_id_c_string(adev->id, model_num, ATA_ID_PROD, sizeof(model_num));
 181
 182         for (i = 0; (p = csb_bad_ata100[i]) != NULL; i++) {
 183                 if (!strcmp(p, model_num))
 184                         mask &= ~(0xE0 << ATA_SHIFT_UDMA);
 185         }
 186         return mask;
 187 }
 188
 189 /**
 190  *      serverworks_set_piomode -       set initial PIO mode data
 191  *      @ap: ATA interface
 192  *      @adev: ATA device
 193  *
 194  *      Program the OSB4/CSB5 timing registers for PIO. The PIO register
 195  *      load is done as a simple lookup.
 196  */
 197 static void serverworks_set_piomode(struct ata_port *ap, struct ata_device *adev)
 198 {
 199         static const u8 pio_mode[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
 200         int offset = 1 + 2 * ap->port_no - adev->devno;
 201         int devbits = (2 * ap->port_no + adev->devno) * 4;
 202         u16 csb5_pio;
 203         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 204         int pio = adev->pio_mode - XFER_PIO_0;
 205
 206         pci_write_config_byte(pdev, 0x40 + offset, pio_mode[pio]);
 207
 208         /* The OSB4 just requires the timing but the CSB series want the
 209            mode number as well */
 210         if (serverworks_is_csb(pdev)) {
 211                 pci_read_config_word(pdev, 0x4A, &csb5_pio);
 212                 csb5_pio &= ~(0x0F << devbits);
 213                 pci_write_config_word(pdev, 0x4A, csb5_pio | (pio << devbits));
 214         }
 215 }
 216
 217 /**
 218  *      serverworks_set_dmamode -       set initial DMA mode data
 219  *      @ap: ATA interface
 220  *      @adev: ATA device
 221  *
 222  *      Program the MWDMA/UDMA modes for the serverworks OSB4/CSB5
 223  *      chipset. The MWDMA mode values are pulled from a lookup table
 224  *      while the chipset uses mode number for UDMA.
 225  */
 226
 227 static void serverworks_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 228 {
 229         static const u8 dma_mode[] = { 0x77, 0x21, 0x20 };
 230         int offset = 1 + 2 * ap->port_no - adev->devno;
 231         int devbits = 2 * ap->port_no + adev->devno;
 232         u8 ultra;
 233         u8 ultra_cfg;
 234         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 235
 236         pci_read_config_byte(pdev, 0x54, &ultra_cfg);
 237         pci_read_config_byte(pdev, 0x56 + ap->port_no, &ultra);
 238         ultra &= ~(0x0F << (adev->devno * 4));
 239
 240         if (adev->dma_mode >= XFER_UDMA_0) {
 241                 pci_write_config_byte(pdev, 0x44 + offset,  0x20);
 242
 243                 ultra |= (adev->dma_mode - XFER_UDMA_0)
 244                                         << (adev->devno * 4);
 245                 ultra_cfg |=  (1 << devbits);
 246         } else {
 247                 pci_write_config_byte(pdev, 0x44 + offset,
 248                         dma_mode[adev->dma_mode - XFER_MW_DMA_0]);
 249                 ultra_cfg &= ~(1 << devbits);
 250         }
 251         pci_write_config_byte(pdev, 0x56 + ap->port_no, ultra);
 252         pci_write_config_byte(pdev, 0x54, ultra_cfg);
 253 }
 254
 255 static struct scsi_host_template serverworks_osb4_sht = {
 256         ATA_BMDMA_SHT(DRV_NAME),
 257         .sg_tablesize   = LIBATA_DUMB_MAX_PRD,
 258 };
 259
 260 static struct scsi_host_template serverworks_csb_sht = {
 261         ATA_BMDMA_SHT(DRV_NAME),
 262 };
 263
 264 static struct ata_port_operations serverworks_osb4_port_ops = {
 265         .inherits       = &ata_bmdma_port_ops,
 266         .qc_prep        = ata_bmdma_dumb_qc_prep,
 267         .cable_detect   = serverworks_cable_detect,
 268         .mode_filter    = serverworks_osb4_filter,
 269         .set_piomode    = serverworks_set_piomode,
 270         .set_dmamode    = serverworks_set_dmamode,
 271 };
 272
 273 static struct ata_port_operations serverworks_csb_port_ops = {
 274         .inherits       = &serverworks_osb4_port_ops,
 275         .qc_prep        = ata_bmdma_qc_prep,
 276         .mode_filter    = serverworks_csb_filter,
 277 };
 278
 279 static int serverworks_fixup_osb4(struct pci_dev *pdev)
 280 {
 281         u32 reg;
 282         struct pci_dev *isa_dev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
 283                   PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
 284         if (isa_dev) {
 285                 pci_read_config_dword(isa_dev, 0x64, &reg);
 286                 reg &= ~0x00002000; /* disable 600ns interrupt mask */
 287                 if (!(reg & 0x00004000))
 288                         printk(KERN_DEBUG DRV_NAME ": UDMA not BIOS enabled.\n");
 289                 reg |=  0x00004000; /* enable UDMA/33 support */
 290                 pci_write_config_dword(isa_dev, 0x64, reg);
 291                 pci_dev_put(isa_dev);
 292                 return 0;
 293         }
 294         printk(KERN_WARNING DRV_NAME ": Unable to find bridge.\n");
 295         return -ENODEV;
 296 }
 297
 298 static int serverworks_fixup_csb(struct pci_dev *pdev)
 299 {
 300         u8 btr;
 301
 302         /* Third Channel Test */
 303         if (!(PCI_FUNC(pdev->devfn) & 1)) {
 304                 struct pci_dev * findev = NULL;
 305                 u32 reg4c = 0;
 306                 findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
 307                         PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL);
 308                 if (findev) {
 309                         pci_read_config_dword(findev, 0x4C, &reg4c);
 310                         reg4c &= ~0x000007FF;
 311                         reg4c |=  0x00000040;
 312                         reg4c |=  0x00000020;
 313                         pci_write_config_dword(findev, 0x4C, reg4c);
 314                         pci_dev_put(findev);
 315                 }
 316         } else {
 317                 struct pci_dev * findev = NULL;
 318                 u8 reg41 = 0;
 319
 320                 findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
 321                                 PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL);
 322                 if (findev) {
 323                         pci_read_config_byte(findev, 0x41, &reg41);
 324                         reg41 &= ~0x40;
 325                         pci_write_config_byte(findev, 0x41, reg41);
 326                         pci_dev_put(findev);
 327                 }
 328         }
 329         /* setup the UDMA Control register
 330          *
 331          * 1. clear bit 6 to enable DMA
 332          * 2. enable DMA modes with bits 0-1
 333          *      00 : legacy
 334          *      01 : udma2
 335          *      10 : udma2/udma4
 336          *      11 : udma2/udma4/udma5
 337          */
 338         pci_read_config_byte(pdev, 0x5A, &btr);
 339         btr &= ~0x40;
 340         if (!(PCI_FUNC(pdev->devfn) & 1))
 341                 btr |= 0x2;
 342         else
 343                 btr |= (pdev->revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
 344         pci_write_config_byte(pdev, 0x5A, btr);
 345
 346         return btr;
 347 }
 348
 349 static void serverworks_fixup_ht1000(struct pci_dev *pdev)
 350 {
 351         u8 btr;
 352         /* Setup HT1000 SouthBridge Controller - Single Channel Only */
 353         pci_read_config_byte(pdev, 0x5A, &btr);
 354         btr &= ~0x40;
 355         btr |= 0x3;
 356         pci_write_config_byte(pdev, 0x5A, btr);
 357 }
 358
 359 static int serverworks_fixup(struct pci_dev *pdev)
 360 {
 361         int rc = 0;
 362
 363         /* Force master latency timer to 64 PCI clocks */
 364         pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x40);
 365
 366         switch (pdev->device) {
 367         case PCI_DEVICE_ID_SERVERWORKS_OSB4IDE:
 368                 rc = serverworks_fixup_osb4(pdev);
 369                 break;
 370         case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
 371                 ata_pci_bmdma_clear_simplex(pdev);
 372                 fallthrough;
 373         case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
 374         case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
 375                 rc = serverworks_fixup_csb(pdev);
 376                 break;
 377         case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
 378                 serverworks_fixup_ht1000(pdev);
 379                 break;
 380         }
 381
 382         return rc;
 383 }
 384
 385 static int serverworks_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
 386 {
 387         static const struct ata_port_info info[4] = {
 388                 { /* OSB4 */
 389                         .flags = ATA_FLAG_SLAVE_POSS,
 390                         .pio_mask = ATA_PIO4,
 391                         .mwdma_mask = ATA_MWDMA2,
 392                         .udma_mask = ATA_UDMA2,
 393                         .port_ops = &serverworks_osb4_port_ops
 394                 }, { /* OSB4 no UDMA */
 395                         .flags = ATA_FLAG_SLAVE_POSS,
 396                         .pio_mask = ATA_PIO4,
 397                         .mwdma_mask = ATA_MWDMA2,
 398                         /* No UDMA */
 399                         .port_ops = &serverworks_osb4_port_ops
 400                 }, { /* CSB5 */
 401                         .flags = ATA_FLAG_SLAVE_POSS,
 402                         .pio_mask = ATA_PIO4,
 403                         .mwdma_mask = ATA_MWDMA2,
 404                         .udma_mask = ATA_UDMA4,
 405                         .port_ops = &serverworks_csb_port_ops
 406                 }, { /* CSB5 - later revisions*/
 407                         .flags = ATA_FLAG_SLAVE_POSS,
 408                         .pio_mask = ATA_PIO4,
 409                         .mwdma_mask = ATA_MWDMA2,
 410                         .udma_mask = ATA_UDMA5,
 411                         .port_ops = &serverworks_csb_port_ops
 412                 }
 413         };
 414         const struct ata_port_info *ppi[] = { &info[id->driver_data], NULL };
 415         struct scsi_host_template *sht = &serverworks_csb_sht;
 416         int rc;
 417
 418         rc = pcim_enable_device(pdev);
 419         if (rc)
 420                 return rc;
 421
 422         rc = serverworks_fixup(pdev);
 423
 424         /* OSB4 : South Bridge and IDE */
 425         if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
 426                 /* Select non UDMA capable OSB4 if we can't do fixups */
 427                 if (rc < 0)
 428                         ppi[0] = &info[1];
 429                 sht = &serverworks_osb4_sht;
 430         }
 431         /* setup CSB5/CSB6 : South Bridge and IDE option RAID */
 432         else if ((pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) ||
 433                  (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
 434                  (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
 435
 436                  /* If the returned btr is the newer revision then
 437                     select the right info block */
 438                  if (rc == 3)
 439                         ppi[0] = &info[3];
 440
 441                 /* Is this the 3rd channel CSB6 IDE ? */
 442                 if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)
 443                         ppi[1] = &ata_dummy_port_info;
 444         }
 445
 446         return ata_pci_bmdma_init_one(pdev, ppi, sht, NULL, 0);
 447 }
 448
 449 #ifdef CONFIG_PM_SLEEP
 450 static int serverworks_reinit_one(struct pci_dev *pdev)
 451 {
 452         struct ata_host *host = pci_get_drvdata(pdev);
 453         int rc;
 454
 455         rc = ata_pci_device_do_resume(pdev);
 456         if (rc)
 457                 return rc;
 458
 459         (void)serverworks_fixup(pdev);
 460
 461         ata_host_resume(host);
 462         return 0;
 463 }
 464 #endif
 465
 466 static const struct pci_device_id serverworks[] = {
 467         { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE), 0},
 468         { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE), 2},
 469         { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE), 2},
 470         { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2), 2},
 471         { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE), 2},
 472
 473         { },
 474 };
 475
 476 static struct pci_driver serverworks_pci_driver = {
 477         .name           = DRV_NAME,
 478         .id_table       = serverworks,
 479         .probe          = serverworks_init_one,
 480         .remove         = ata_pci_remove_one,
 481 #ifdef CONFIG_PM_SLEEP
 482         .suspend        = ata_pci_device_suspend,
 483         .resume         = serverworks_reinit_one,
 484 #endif
 485 };
 486
 487 module_pci_driver(serverworks_pci_driver);
 488
 489 MODULE_AUTHOR("Alan Cox");
 490 MODULE_DESCRIPTION("low-level driver for Serverworks OSB4/CSB5/CSB6");
 491 MODULE_LICENSE("GPL");
 492 MODULE_DEVICE_TABLE(pci, serverworks);
 493 MODULE_VERSION(DRV_VERSION);