1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * sata_promise.c - Promise SATA
5 * Maintained by: Tejun Heo <tj@kernel.org>
7 * Please ALWAYS copy linux-ide@vger.kernel.org
10 * Copyright 2003-2004 Red Hat, Inc.
12 * libata documentation is available via 'make {ps|pdf}docs',
13 * as Documentation/driver-api/libata.rst
15 * Hardware information only available under NDA.
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/gfp.h>
21 #include <linux/pci.h>
22 #include <linux/blkdev.h>
23 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/device.h>
26 #include <scsi/scsi.h>
27 #include <scsi/scsi_host.h>
28 #include <scsi/scsi_cmnd.h>
29 #include <linux/libata.h>
30 #include "sata_promise.h"
32 #define DRV_NAME "sata_promise"
33 #define DRV_VERSION "2.12"
38 PDC_MAX_PRD
= LIBATA_MAX_PRD
- 1, /* -1 for ASIC PRD bug workaround */
40 /* host register offsets (from host->iomap[PDC_MMIO_BAR]) */
41 PDC_INT_SEQMASK
= 0x40, /* Mask of asserted SEQ INTs */
42 PDC_FLASH_CTL
= 0x44, /* Flash control register */
43 PDC_PCI_CTL
= 0x48, /* PCI control/status reg */
44 PDC_SATA_PLUG_CSR
= 0x6C, /* SATA Plug control/status reg */
45 PDC2_SATA_PLUG_CSR
= 0x60, /* SATAII Plug control/status reg */
46 PDC_TBG_MODE
= 0x41C, /* TBG mode (not SATAII) */
47 PDC_SLEW_CTL
= 0x470, /* slew rate control reg (not SATAII) */
49 /* per-port ATA register offsets (from ap->ioaddr.cmd_addr) */
50 PDC_FEATURE
= 0x04, /* Feature/Error reg (per port) */
51 PDC_SECTOR_COUNT
= 0x08, /* Sector count reg (per port) */
52 PDC_SECTOR_NUMBER
= 0x0C, /* Sector number reg (per port) */
53 PDC_CYLINDER_LOW
= 0x10, /* Cylinder low reg (per port) */
54 PDC_CYLINDER_HIGH
= 0x14, /* Cylinder high reg (per port) */
55 PDC_DEVICE
= 0x18, /* Device/Head reg (per port) */
56 PDC_COMMAND
= 0x1C, /* Command/status reg (per port) */
57 PDC_ALTSTATUS
= 0x38, /* Alternate-status/device-control reg (per port) */
58 PDC_PKT_SUBMIT
= 0x40, /* Command packet pointer addr */
59 PDC_GLOBAL_CTL
= 0x48, /* Global control/status (per port) */
60 PDC_CTLSTAT
= 0x60, /* IDE control and status (per port) */
62 /* per-port SATA register offsets (from ap->ioaddr.scr_addr) */
63 PDC_SATA_ERROR
= 0x04,
65 PDC_LINK_LAYER_ERRORS
= 0x6C,
66 PDC_FPDMA_CTLSTAT
= 0xD8,
67 PDC_INTERNAL_DEBUG_1
= 0xF8, /* also used for PATA */
68 PDC_INTERNAL_DEBUG_2
= 0xFC, /* also used for PATA */
70 /* PDC_FPDMA_CTLSTAT bit definitions */
71 PDC_FPDMA_CTLSTAT_RESET
= 1 << 3,
72 PDC_FPDMA_CTLSTAT_DMASETUP_INT_FLAG
= 1 << 10,
73 PDC_FPDMA_CTLSTAT_SETDB_INT_FLAG
= 1 << 11,
75 /* PDC_GLOBAL_CTL bit definitions */
76 PDC_PH_ERR
= (1 << 8), /* PCI error while loading packet */
77 PDC_SH_ERR
= (1 << 9), /* PCI error while loading S/G table */
78 PDC_DH_ERR
= (1 << 10), /* PCI error while loading data */
79 PDC2_HTO_ERR
= (1 << 12), /* host bus timeout */
80 PDC2_ATA_HBA_ERR
= (1 << 13), /* error during SATA DATA FIS transmission */
81 PDC2_ATA_DMA_CNT_ERR
= (1 << 14), /* DMA DATA FIS size differs from S/G count */
82 PDC_OVERRUN_ERR
= (1 << 19), /* S/G byte count larger than HD requires */
83 PDC_UNDERRUN_ERR
= (1 << 20), /* S/G byte count less than HD requires */
84 PDC_DRIVE_ERR
= (1 << 21), /* drive error */
85 PDC_PCI_SYS_ERR
= (1 << 22), /* PCI system error */
86 PDC1_PCI_PARITY_ERR
= (1 << 23), /* PCI parity error (from SATA150 driver) */
87 PDC1_ERR_MASK
= PDC1_PCI_PARITY_ERR
,
88 PDC2_ERR_MASK
= PDC2_HTO_ERR
| PDC2_ATA_HBA_ERR
|
90 PDC_ERR_MASK
= PDC_PH_ERR
| PDC_SH_ERR
| PDC_DH_ERR
|
91 PDC_OVERRUN_ERR
| PDC_UNDERRUN_ERR
|
92 PDC_DRIVE_ERR
| PDC_PCI_SYS_ERR
|
93 PDC1_ERR_MASK
| PDC2_ERR_MASK
,
95 board_2037x
= 0, /* FastTrak S150 TX2plus */
96 board_2037x_pata
= 1, /* FastTrak S150 TX2plus PATA port */
97 board_20319
= 2, /* FastTrak S150 TX4 */
98 board_20619
= 3, /* FastTrak TX4000 */
99 board_2057x
= 4, /* SATAII150 Tx2plus */
100 board_2057x_pata
= 5, /* SATAII150 Tx2plus PATA port */
101 board_40518
= 6, /* SATAII150 Tx4 */
103 PDC_HAS_PATA
= (1 << 1), /* PDC20375/20575 has PATA */
105 /* Sequence counter control registers bit definitions */
106 PDC_SEQCNTRL_INT_MASK
= (1 << 5), /* Sequence Interrupt Mask */
108 /* Feature register values */
109 PDC_FEATURE_ATAPI_PIO
= 0x00, /* ATAPI data xfer by PIO */
110 PDC_FEATURE_ATAPI_DMA
= 0x01, /* ATAPI data xfer by DMA */
112 /* Device/Head register values */
113 PDC_DEVICE_SATA
= 0xE0, /* Device/Head value for SATA devices */
115 /* PDC_CTLSTAT bit definitions */
116 PDC_DMA_ENABLE
= (1 << 7),
117 PDC_IRQ_DISABLE
= (1 << 10),
118 PDC_RESET
= (1 << 11), /* HDMA reset */
120 PDC_COMMON_FLAGS
= ATA_FLAG_PIO_POLLING
,
123 PDC_FLAG_GEN_II
= (1 << 24),
124 PDC_FLAG_SATA_PATA
= (1 << 25), /* supports SATA + PATA */
125 PDC_FLAG_4_PORTS
= (1 << 26), /* 4 ports */
128 struct pdc_port_priv
{
133 struct pdc_host_priv
{
134 spinlock_t hard_reset_lock
;
137 static int pdc_sata_scr_read(struct ata_link
*link
, unsigned int sc_reg
, u32
*val
);
138 static int pdc_sata_scr_write(struct ata_link
*link
, unsigned int sc_reg
, u32 val
);
139 static int pdc_ata_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
);
140 static int pdc_common_port_start(struct ata_port
*ap
);
141 static int pdc_sata_port_start(struct ata_port
*ap
);
142 static enum ata_completion_errors
pdc_qc_prep(struct ata_queued_cmd
*qc
);
143 static void pdc_tf_load_mmio(struct ata_port
*ap
, const struct ata_taskfile
*tf
);
144 static void pdc_exec_command_mmio(struct ata_port
*ap
, const struct ata_taskfile
*tf
);
145 static int pdc_check_atapi_dma(struct ata_queued_cmd
*qc
);
146 static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd
*qc
);
147 static void pdc_irq_clear(struct ata_port
*ap
);
148 static unsigned int pdc_qc_issue(struct ata_queued_cmd
*qc
);
149 static void pdc_freeze(struct ata_port
*ap
);
150 static void pdc_sata_freeze(struct ata_port
*ap
);
151 static void pdc_thaw(struct ata_port
*ap
);
152 static void pdc_sata_thaw(struct ata_port
*ap
);
153 static int pdc_pata_softreset(struct ata_link
*link
, unsigned int *class,
154 unsigned long deadline
);
155 static int pdc_sata_hardreset(struct ata_link
*link
, unsigned int *class,
156 unsigned long deadline
);
157 static void pdc_error_handler(struct ata_port
*ap
);
158 static void pdc_post_internal_cmd(struct ata_queued_cmd
*qc
);
159 static int pdc_pata_cable_detect(struct ata_port
*ap
);
161 static struct scsi_host_template pdc_ata_sht
= {
162 ATA_BASE_SHT(DRV_NAME
),
163 .sg_tablesize
= PDC_MAX_PRD
,
164 .dma_boundary
= ATA_DMA_BOUNDARY
,
167 static const struct ata_port_operations pdc_common_ops
= {
168 .inherits
= &ata_sff_port_ops
,
170 .sff_tf_load
= pdc_tf_load_mmio
,
171 .sff_exec_command
= pdc_exec_command_mmio
,
172 .check_atapi_dma
= pdc_check_atapi_dma
,
173 .qc_prep
= pdc_qc_prep
,
174 .qc_issue
= pdc_qc_issue
,
176 .sff_irq_clear
= pdc_irq_clear
,
177 .lost_interrupt
= ATA_OP_NULL
,
179 .post_internal_cmd
= pdc_post_internal_cmd
,
180 .error_handler
= pdc_error_handler
,
183 static struct ata_port_operations pdc_sata_ops
= {
184 .inherits
= &pdc_common_ops
,
185 .cable_detect
= ata_cable_sata
,
186 .freeze
= pdc_sata_freeze
,
187 .thaw
= pdc_sata_thaw
,
188 .scr_read
= pdc_sata_scr_read
,
189 .scr_write
= pdc_sata_scr_write
,
190 .port_start
= pdc_sata_port_start
,
191 .hardreset
= pdc_sata_hardreset
,
194 /* First-generation chips need a more restrictive ->check_atapi_dma op,
195 and ->freeze/thaw that ignore the hotplug controls. */
196 static struct ata_port_operations pdc_old_sata_ops
= {
197 .inherits
= &pdc_sata_ops
,
198 .freeze
= pdc_freeze
,
200 .check_atapi_dma
= pdc_old_sata_check_atapi_dma
,
203 static struct ata_port_operations pdc_pata_ops
= {
204 .inherits
= &pdc_common_ops
,
205 .cable_detect
= pdc_pata_cable_detect
,
206 .freeze
= pdc_freeze
,
208 .port_start
= pdc_common_port_start
,
209 .softreset
= pdc_pata_softreset
,
212 static const struct ata_port_info pdc_port_info
[] = {
215 .flags
= PDC_COMMON_FLAGS
| ATA_FLAG_SATA
|
217 .pio_mask
= ATA_PIO4
,
218 .mwdma_mask
= ATA_MWDMA2
,
219 .udma_mask
= ATA_UDMA6
,
220 .port_ops
= &pdc_old_sata_ops
,
225 .flags
= PDC_COMMON_FLAGS
| ATA_FLAG_SLAVE_POSS
,
226 .pio_mask
= ATA_PIO4
,
227 .mwdma_mask
= ATA_MWDMA2
,
228 .udma_mask
= ATA_UDMA6
,
229 .port_ops
= &pdc_pata_ops
,
234 .flags
= PDC_COMMON_FLAGS
| ATA_FLAG_SATA
|
236 .pio_mask
= ATA_PIO4
,
237 .mwdma_mask
= ATA_MWDMA2
,
238 .udma_mask
= ATA_UDMA6
,
239 .port_ops
= &pdc_old_sata_ops
,
244 .flags
= PDC_COMMON_FLAGS
| ATA_FLAG_SLAVE_POSS
|
246 .pio_mask
= ATA_PIO4
,
247 .mwdma_mask
= ATA_MWDMA2
,
248 .udma_mask
= ATA_UDMA6
,
249 .port_ops
= &pdc_pata_ops
,
254 .flags
= PDC_COMMON_FLAGS
| ATA_FLAG_SATA
|
255 PDC_FLAG_GEN_II
| PDC_FLAG_SATA_PATA
,
256 .pio_mask
= ATA_PIO4
,
257 .mwdma_mask
= ATA_MWDMA2
,
258 .udma_mask
= ATA_UDMA6
,
259 .port_ops
= &pdc_sata_ops
,
264 .flags
= PDC_COMMON_FLAGS
| ATA_FLAG_SLAVE_POSS
|
266 .pio_mask
= ATA_PIO4
,
267 .mwdma_mask
= ATA_MWDMA2
,
268 .udma_mask
= ATA_UDMA6
,
269 .port_ops
= &pdc_pata_ops
,
274 .flags
= PDC_COMMON_FLAGS
| ATA_FLAG_SATA
|
275 PDC_FLAG_GEN_II
| PDC_FLAG_4_PORTS
,
276 .pio_mask
= ATA_PIO4
,
277 .mwdma_mask
= ATA_MWDMA2
,
278 .udma_mask
= ATA_UDMA6
,
279 .port_ops
= &pdc_sata_ops
,
283 static const struct pci_device_id pdc_ata_pci_tbl
[] = {
284 { PCI_VDEVICE(PROMISE
, 0x3371), board_2037x
},
285 { PCI_VDEVICE(PROMISE
, 0x3373), board_2037x
},
286 { PCI_VDEVICE(PROMISE
, 0x3375), board_2037x
},
287 { PCI_VDEVICE(PROMISE
, 0x3376), board_2037x
},
288 { PCI_VDEVICE(PROMISE
, 0x3570), board_2057x
},
289 { PCI_VDEVICE(PROMISE
, 0x3571), board_2057x
},
290 { PCI_VDEVICE(PROMISE
, 0x3574), board_2057x
},
291 { PCI_VDEVICE(PROMISE
, 0x3577), board_2057x
},
292 { PCI_VDEVICE(PROMISE
, 0x3d73), board_2057x
},
293 { PCI_VDEVICE(PROMISE
, 0x3d75), board_2057x
},
295 { PCI_VDEVICE(PROMISE
, 0x3318), board_20319
},
296 { PCI_VDEVICE(PROMISE
, 0x3319), board_20319
},
297 { PCI_VDEVICE(PROMISE
, 0x3515), board_40518
},
298 { PCI_VDEVICE(PROMISE
, 0x3519), board_40518
},
299 { PCI_VDEVICE(PROMISE
, 0x3d17), board_40518
},
300 { PCI_VDEVICE(PROMISE
, 0x3d18), board_40518
},
302 { PCI_VDEVICE(PROMISE
, 0x6629), board_20619
},
304 { } /* terminate list */
307 static struct pci_driver pdc_ata_pci_driver
= {
309 .id_table
= pdc_ata_pci_tbl
,
310 .probe
= pdc_ata_init_one
,
311 .remove
= ata_pci_remove_one
,
314 static int pdc_common_port_start(struct ata_port
*ap
)
316 struct device
*dev
= ap
->host
->dev
;
317 struct pdc_port_priv
*pp
;
320 /* we use the same prd table as bmdma, allocate it */
321 rc
= ata_bmdma_port_start(ap
);
325 pp
= devm_kzalloc(dev
, sizeof(*pp
), GFP_KERNEL
);
329 pp
->pkt
= dmam_alloc_coherent(dev
, 128, &pp
->pkt_dma
, GFP_KERNEL
);
333 ap
->private_data
= pp
;
338 static int pdc_sata_port_start(struct ata_port
*ap
)
342 rc
= pdc_common_port_start(ap
);
346 /* fix up PHYMODE4 align timing */
347 if (ap
->flags
& PDC_FLAG_GEN_II
) {
348 void __iomem
*sata_mmio
= ap
->ioaddr
.scr_addr
;
351 tmp
= readl(sata_mmio
+ PDC_PHYMODE4
);
352 tmp
= (tmp
& ~3) | 1; /* set bits 1:0 = 0:1 */
353 writel(tmp
, sata_mmio
+ PDC_PHYMODE4
);
359 static void pdc_fpdma_clear_interrupt_flag(struct ata_port
*ap
)
361 void __iomem
*sata_mmio
= ap
->ioaddr
.scr_addr
;
364 tmp
= readl(sata_mmio
+ PDC_FPDMA_CTLSTAT
);
365 tmp
|= PDC_FPDMA_CTLSTAT_DMASETUP_INT_FLAG
;
366 tmp
|= PDC_FPDMA_CTLSTAT_SETDB_INT_FLAG
;
368 /* It's not allowed to write to the entire FPDMA_CTLSTAT register
369 when NCQ is running. So do a byte-sized write to bits 10 and 11. */
370 writeb(tmp
>> 8, sata_mmio
+ PDC_FPDMA_CTLSTAT
+ 1);
371 readb(sata_mmio
+ PDC_FPDMA_CTLSTAT
+ 1); /* flush */
374 static void pdc_fpdma_reset(struct ata_port
*ap
)
376 void __iomem
*sata_mmio
= ap
->ioaddr
.scr_addr
;
379 tmp
= (u8
)readl(sata_mmio
+ PDC_FPDMA_CTLSTAT
);
381 tmp
|= PDC_FPDMA_CTLSTAT_RESET
;
382 writeb(tmp
, sata_mmio
+ PDC_FPDMA_CTLSTAT
);
383 readl(sata_mmio
+ PDC_FPDMA_CTLSTAT
); /* flush */
385 tmp
&= ~PDC_FPDMA_CTLSTAT_RESET
;
386 writeb(tmp
, sata_mmio
+ PDC_FPDMA_CTLSTAT
);
387 readl(sata_mmio
+ PDC_FPDMA_CTLSTAT
); /* flush */
389 pdc_fpdma_clear_interrupt_flag(ap
);
392 static void pdc_not_at_command_packet_phase(struct ata_port
*ap
)
394 void __iomem
*sata_mmio
= ap
->ioaddr
.scr_addr
;
398 /* check not at ASIC packet command phase */
399 for (i
= 0; i
< 100; ++i
) {
400 writel(0, sata_mmio
+ PDC_INTERNAL_DEBUG_1
);
401 tmp
= readl(sata_mmio
+ PDC_INTERNAL_DEBUG_2
);
402 if ((tmp
& 0xF) != 1)
408 static void pdc_clear_internal_debug_record_error_register(struct ata_port
*ap
)
410 void __iomem
*sata_mmio
= ap
->ioaddr
.scr_addr
;
412 writel(0xffffffff, sata_mmio
+ PDC_SATA_ERROR
);
413 writel(0xffff0000, sata_mmio
+ PDC_LINK_LAYER_ERRORS
);
416 static void pdc_reset_port(struct ata_port
*ap
)
418 void __iomem
*ata_ctlstat_mmio
= ap
->ioaddr
.cmd_addr
+ PDC_CTLSTAT
;
422 if (ap
->flags
& PDC_FLAG_GEN_II
)
423 pdc_not_at_command_packet_phase(ap
);
425 tmp
= readl(ata_ctlstat_mmio
);
427 writel(tmp
, ata_ctlstat_mmio
);
429 for (i
= 11; i
> 0; i
--) {
430 tmp
= readl(ata_ctlstat_mmio
);
437 writel(tmp
, ata_ctlstat_mmio
);
441 writel(tmp
, ata_ctlstat_mmio
);
442 readl(ata_ctlstat_mmio
); /* flush */
444 if (sata_scr_valid(&ap
->link
) && (ap
->flags
& PDC_FLAG_GEN_II
)) {
446 pdc_clear_internal_debug_record_error_register(ap
);
450 static int pdc_pata_cable_detect(struct ata_port
*ap
)
453 void __iomem
*ata_mmio
= ap
->ioaddr
.cmd_addr
;
455 tmp
= readb(ata_mmio
+ PDC_CTLSTAT
+ 3);
457 return ATA_CBL_PATA40
;
458 return ATA_CBL_PATA80
;
461 static int pdc_sata_scr_read(struct ata_link
*link
,
462 unsigned int sc_reg
, u32
*val
)
464 if (sc_reg
> SCR_CONTROL
)
466 *val
= readl(link
->ap
->ioaddr
.scr_addr
+ (sc_reg
* 4));
470 static int pdc_sata_scr_write(struct ata_link
*link
,
471 unsigned int sc_reg
, u32 val
)
473 if (sc_reg
> SCR_CONTROL
)
475 writel(val
, link
->ap
->ioaddr
.scr_addr
+ (sc_reg
* 4));
479 static void pdc_atapi_pkt(struct ata_queued_cmd
*qc
)
481 struct ata_port
*ap
= qc
->ap
;
482 dma_addr_t sg_table
= ap
->bmdma_prd_dma
;
483 unsigned int cdb_len
= qc
->dev
->cdb_len
;
485 struct pdc_port_priv
*pp
= ap
->private_data
;
487 __le32
*buf32
= (__le32
*) buf
;
488 unsigned int dev_sel
, feature
;
490 /* set control bits (byte 0), zero delay seq id (byte 3),
491 * and seq id (byte 2)
493 switch (qc
->tf
.protocol
) {
495 if (!(qc
->tf
.flags
& ATA_TFLAG_WRITE
))
496 buf32
[0] = cpu_to_le32(PDC_PKT_READ
);
500 case ATAPI_PROT_NODATA
:
501 buf32
[0] = cpu_to_le32(PDC_PKT_NODATA
);
507 buf32
[1] = cpu_to_le32(sg_table
); /* S/G table addr */
508 buf32
[2] = 0; /* no next-packet */
511 if (sata_scr_valid(&ap
->link
))
512 dev_sel
= PDC_DEVICE_SATA
;
514 dev_sel
= qc
->tf
.device
;
516 buf
[12] = (1 << 5) | ATA_REG_DEVICE
;
518 buf
[14] = (1 << 5) | ATA_REG_DEVICE
| PDC_PKT_CLEAR_BSY
;
519 buf
[15] = dev_sel
; /* once more, waiting for BSY to clear */
521 buf
[16] = (1 << 5) | ATA_REG_NSECT
;
522 buf
[17] = qc
->tf
.nsect
;
523 buf
[18] = (1 << 5) | ATA_REG_LBAL
;
524 buf
[19] = qc
->tf
.lbal
;
526 /* set feature and byte counter registers */
527 if (qc
->tf
.protocol
!= ATAPI_PROT_DMA
)
528 feature
= PDC_FEATURE_ATAPI_PIO
;
530 feature
= PDC_FEATURE_ATAPI_DMA
;
532 buf
[20] = (1 << 5) | ATA_REG_FEATURE
;
534 buf
[22] = (1 << 5) | ATA_REG_BYTEL
;
535 buf
[23] = qc
->tf
.lbam
;
536 buf
[24] = (1 << 5) | ATA_REG_BYTEH
;
537 buf
[25] = qc
->tf
.lbah
;
539 /* send ATAPI packet command 0xA0 */
540 buf
[26] = (1 << 5) | ATA_REG_CMD
;
541 buf
[27] = qc
->tf
.command
;
543 /* select drive and check DRQ */
544 buf
[28] = (1 << 5) | ATA_REG_DEVICE
| PDC_PKT_WAIT_DRDY
;
547 /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */
548 BUG_ON(cdb_len
& ~0x1E);
550 /* append the CDB as the final part */
551 buf
[30] = (((cdb_len
>> 1) & 7) << 5) | ATA_REG_DATA
| PDC_LAST_REG
;
552 memcpy(buf
+31, cdb
, cdb_len
);
556 * pdc_fill_sg - Fill PCI IDE PRD table
557 * @qc: Metadata associated with taskfile to be transferred
559 * Fill PCI IDE PRD (scatter-gather) table with segments
560 * associated with the current disk command.
561 * Make sure hardware does not choke on it.
564 * spin_lock_irqsave(host lock)
567 static void pdc_fill_sg(struct ata_queued_cmd
*qc
)
569 struct ata_port
*ap
= qc
->ap
;
570 struct ata_bmdma_prd
*prd
= ap
->bmdma_prd
;
571 struct scatterlist
*sg
;
572 const u32 SG_COUNT_ASIC_BUG
= 41*4;
573 unsigned int si
, idx
;
576 if (!(qc
->flags
& ATA_QCFLAG_DMAMAP
))
580 for_each_sg(qc
->sg
, sg
, qc
->n_elem
, si
) {
584 /* determine if physical DMA addr spans 64K boundary.
585 * Note h/w doesn't support 64-bit, so we unconditionally
586 * truncate dma_addr_t to u32.
588 addr
= (u32
) sg_dma_address(sg
);
589 sg_len
= sg_dma_len(sg
);
592 offset
= addr
& 0xffff;
594 if ((offset
+ sg_len
) > 0x10000)
595 len
= 0x10000 - offset
;
597 prd
[idx
].addr
= cpu_to_le32(addr
);
598 prd
[idx
].flags_len
= cpu_to_le32(len
& 0xffff);
599 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx
, addr
, len
);
607 len
= le32_to_cpu(prd
[idx
- 1].flags_len
);
609 if (len
> SG_COUNT_ASIC_BUG
) {
612 VPRINTK("Splitting last PRD.\n");
614 addr
= le32_to_cpu(prd
[idx
- 1].addr
);
615 prd
[idx
- 1].flags_len
= cpu_to_le32(len
- SG_COUNT_ASIC_BUG
);
616 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx
- 1, addr
, SG_COUNT_ASIC_BUG
);
618 addr
= addr
+ len
- SG_COUNT_ASIC_BUG
;
619 len
= SG_COUNT_ASIC_BUG
;
620 prd
[idx
].addr
= cpu_to_le32(addr
);
621 prd
[idx
].flags_len
= cpu_to_le32(len
);
622 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx
, addr
, len
);
627 prd
[idx
- 1].flags_len
|= cpu_to_le32(ATA_PRD_EOT
);
630 static enum ata_completion_errors
pdc_qc_prep(struct ata_queued_cmd
*qc
)
632 struct pdc_port_priv
*pp
= qc
->ap
->private_data
;
637 switch (qc
->tf
.protocol
) {
641 case ATA_PROT_NODATA
:
642 i
= pdc_pkt_header(&qc
->tf
, qc
->ap
->bmdma_prd_dma
,
643 qc
->dev
->devno
, pp
->pkt
);
644 if (qc
->tf
.flags
& ATA_TFLAG_LBA48
)
645 i
= pdc_prep_lba48(&qc
->tf
, pp
->pkt
, i
);
647 i
= pdc_prep_lba28(&qc
->tf
, pp
->pkt
, i
);
648 pdc_pkt_footer(&qc
->tf
, pp
->pkt
, i
);
656 case ATAPI_PROT_NODATA
:
666 static int pdc_is_sataii_tx4(unsigned long flags
)
668 const unsigned long mask
= PDC_FLAG_GEN_II
| PDC_FLAG_4_PORTS
;
669 return (flags
& mask
) == mask
;
672 static unsigned int pdc_port_no_to_ata_no(unsigned int port_no
,
675 static const unsigned char sataii_tx4_port_remap
[4] = { 3, 1, 0, 2};
676 return is_sataii_tx4
? sataii_tx4_port_remap
[port_no
] : port_no
;
679 static unsigned int pdc_sata_nr_ports(const struct ata_port
*ap
)
681 return (ap
->flags
& PDC_FLAG_4_PORTS
) ? 4 : 2;
684 static unsigned int pdc_sata_ata_port_to_ata_no(const struct ata_port
*ap
)
686 const struct ata_host
*host
= ap
->host
;
687 unsigned int nr_ports
= pdc_sata_nr_ports(ap
);
690 for (i
= 0; i
< nr_ports
&& host
->ports
[i
] != ap
; ++i
)
692 BUG_ON(i
>= nr_ports
);
693 return pdc_port_no_to_ata_no(i
, pdc_is_sataii_tx4(ap
->flags
));
696 static void pdc_freeze(struct ata_port
*ap
)
698 void __iomem
*ata_mmio
= ap
->ioaddr
.cmd_addr
;
701 tmp
= readl(ata_mmio
+ PDC_CTLSTAT
);
702 tmp
|= PDC_IRQ_DISABLE
;
703 tmp
&= ~PDC_DMA_ENABLE
;
704 writel(tmp
, ata_mmio
+ PDC_CTLSTAT
);
705 readl(ata_mmio
+ PDC_CTLSTAT
); /* flush */
708 static void pdc_sata_freeze(struct ata_port
*ap
)
710 struct ata_host
*host
= ap
->host
;
711 void __iomem
*host_mmio
= host
->iomap
[PDC_MMIO_BAR
];
712 unsigned int hotplug_offset
= PDC2_SATA_PLUG_CSR
;
713 unsigned int ata_no
= pdc_sata_ata_port_to_ata_no(ap
);
716 /* Disable hotplug events on this port.
719 * 1) hotplug register accesses must be serialised via host->lock
720 * 2) ap->lock == &ap->host->lock
721 * 3) ->freeze() and ->thaw() are called with ap->lock held
723 hotplug_status
= readl(host_mmio
+ hotplug_offset
);
724 hotplug_status
|= 0x11 << (ata_no
+ 16);
725 writel(hotplug_status
, host_mmio
+ hotplug_offset
);
726 readl(host_mmio
+ hotplug_offset
); /* flush */
731 static void pdc_thaw(struct ata_port
*ap
)
733 void __iomem
*ata_mmio
= ap
->ioaddr
.cmd_addr
;
737 readl(ata_mmio
+ PDC_COMMAND
);
739 /* turn IRQ back on */
740 tmp
= readl(ata_mmio
+ PDC_CTLSTAT
);
741 tmp
&= ~PDC_IRQ_DISABLE
;
742 writel(tmp
, ata_mmio
+ PDC_CTLSTAT
);
743 readl(ata_mmio
+ PDC_CTLSTAT
); /* flush */
746 static void pdc_sata_thaw(struct ata_port
*ap
)
748 struct ata_host
*host
= ap
->host
;
749 void __iomem
*host_mmio
= host
->iomap
[PDC_MMIO_BAR
];
750 unsigned int hotplug_offset
= PDC2_SATA_PLUG_CSR
;
751 unsigned int ata_no
= pdc_sata_ata_port_to_ata_no(ap
);
756 /* Enable hotplug events on this port.
757 * Locking: see pdc_sata_freeze().
759 hotplug_status
= readl(host_mmio
+ hotplug_offset
);
760 hotplug_status
|= 0x11 << ata_no
;
761 hotplug_status
&= ~(0x11 << (ata_no
+ 16));
762 writel(hotplug_status
, host_mmio
+ hotplug_offset
);
763 readl(host_mmio
+ hotplug_offset
); /* flush */
766 static int pdc_pata_softreset(struct ata_link
*link
, unsigned int *class,
767 unsigned long deadline
)
769 pdc_reset_port(link
->ap
);
770 return ata_sff_softreset(link
, class, deadline
);
773 static unsigned int pdc_ata_port_to_ata_no(const struct ata_port
*ap
)
775 void __iomem
*ata_mmio
= ap
->ioaddr
.cmd_addr
;
776 void __iomem
*host_mmio
= ap
->host
->iomap
[PDC_MMIO_BAR
];
778 /* ata_mmio == host_mmio + 0x200 + ata_no * 0x80 */
779 return (ata_mmio
- host_mmio
- 0x200) / 0x80;
782 static void pdc_hard_reset_port(struct ata_port
*ap
)
784 void __iomem
*host_mmio
= ap
->host
->iomap
[PDC_MMIO_BAR
];
785 void __iomem
*pcictl_b1_mmio
= host_mmio
+ PDC_PCI_CTL
+ 1;
786 unsigned int ata_no
= pdc_ata_port_to_ata_no(ap
);
787 struct pdc_host_priv
*hpriv
= ap
->host
->private_data
;
790 spin_lock(&hpriv
->hard_reset_lock
);
792 tmp
= readb(pcictl_b1_mmio
);
793 tmp
&= ~(0x10 << ata_no
);
794 writeb(tmp
, pcictl_b1_mmio
);
795 readb(pcictl_b1_mmio
); /* flush */
797 tmp
|= (0x10 << ata_no
);
798 writeb(tmp
, pcictl_b1_mmio
);
799 readb(pcictl_b1_mmio
); /* flush */
801 spin_unlock(&hpriv
->hard_reset_lock
);
804 static int pdc_sata_hardreset(struct ata_link
*link
, unsigned int *class,
805 unsigned long deadline
)
807 if (link
->ap
->flags
& PDC_FLAG_GEN_II
)
808 pdc_not_at_command_packet_phase(link
->ap
);
809 /* hotplug IRQs should have been masked by pdc_sata_freeze() */
810 pdc_hard_reset_port(link
->ap
);
811 pdc_reset_port(link
->ap
);
813 /* sata_promise can't reliably acquire the first D2H Reg FIS
814 * after hardreset. Do non-waiting hardreset and request
817 return sata_std_hardreset(link
, class, deadline
);
820 static void pdc_error_handler(struct ata_port
*ap
)
822 if (!(ap
->pflags
& ATA_PFLAG_FROZEN
))
825 ata_sff_error_handler(ap
);
828 static void pdc_post_internal_cmd(struct ata_queued_cmd
*qc
)
830 struct ata_port
*ap
= qc
->ap
;
832 /* make DMA engine forget about the failed command */
833 if (qc
->flags
& ATA_QCFLAG_FAILED
)
837 static void pdc_error_intr(struct ata_port
*ap
, struct ata_queued_cmd
*qc
,
838 u32 port_status
, u32 err_mask
)
840 struct ata_eh_info
*ehi
= &ap
->link
.eh_info
;
841 unsigned int ac_err_mask
= 0;
843 ata_ehi_clear_desc(ehi
);
844 ata_ehi_push_desc(ehi
, "port_status 0x%08x", port_status
);
845 port_status
&= err_mask
;
847 if (port_status
& PDC_DRIVE_ERR
)
848 ac_err_mask
|= AC_ERR_DEV
;
849 if (port_status
& (PDC_OVERRUN_ERR
| PDC_UNDERRUN_ERR
))
850 ac_err_mask
|= AC_ERR_OTHER
;
851 if (port_status
& (PDC2_ATA_HBA_ERR
| PDC2_ATA_DMA_CNT_ERR
))
852 ac_err_mask
|= AC_ERR_ATA_BUS
;
853 if (port_status
& (PDC_PH_ERR
| PDC_SH_ERR
| PDC_DH_ERR
| PDC2_HTO_ERR
854 | PDC_PCI_SYS_ERR
| PDC1_PCI_PARITY_ERR
))
855 ac_err_mask
|= AC_ERR_HOST_BUS
;
857 if (sata_scr_valid(&ap
->link
)) {
860 pdc_sata_scr_read(&ap
->link
, SCR_ERROR
, &serror
);
861 ehi
->serror
|= serror
;
864 qc
->err_mask
|= ac_err_mask
;
871 static unsigned int pdc_host_intr(struct ata_port
*ap
,
872 struct ata_queued_cmd
*qc
)
874 unsigned int handled
= 0;
875 void __iomem
*ata_mmio
= ap
->ioaddr
.cmd_addr
;
876 u32 port_status
, err_mask
;
878 err_mask
= PDC_ERR_MASK
;
879 if (ap
->flags
& PDC_FLAG_GEN_II
)
880 err_mask
&= ~PDC1_ERR_MASK
;
882 err_mask
&= ~PDC2_ERR_MASK
;
883 port_status
= readl(ata_mmio
+ PDC_GLOBAL_CTL
);
884 if (unlikely(port_status
& err_mask
)) {
885 pdc_error_intr(ap
, qc
, port_status
, err_mask
);
889 switch (qc
->tf
.protocol
) {
891 case ATA_PROT_NODATA
:
893 case ATAPI_PROT_NODATA
:
894 qc
->err_mask
|= ac_err_mask(ata_wait_idle(ap
));
899 ap
->stats
.idle_irq
++;
906 static void pdc_irq_clear(struct ata_port
*ap
)
908 void __iomem
*ata_mmio
= ap
->ioaddr
.cmd_addr
;
910 readl(ata_mmio
+ PDC_COMMAND
);
913 static irqreturn_t
pdc_interrupt(int irq
, void *dev_instance
)
915 struct ata_host
*host
= dev_instance
;
919 unsigned int handled
= 0;
920 void __iomem
*host_mmio
;
921 unsigned int hotplug_offset
, ata_no
;
927 if (!host
|| !host
->iomap
[PDC_MMIO_BAR
]) {
928 VPRINTK("QUICK EXIT\n");
932 host_mmio
= host
->iomap
[PDC_MMIO_BAR
];
934 spin_lock(&host
->lock
);
936 /* read and clear hotplug flags for all ports */
937 if (host
->ports
[0]->flags
& PDC_FLAG_GEN_II
) {
938 hotplug_offset
= PDC2_SATA_PLUG_CSR
;
939 hotplug_status
= readl(host_mmio
+ hotplug_offset
);
940 if (hotplug_status
& 0xff)
941 writel(hotplug_status
| 0xff, host_mmio
+ hotplug_offset
);
942 hotplug_status
&= 0xff; /* clear uninteresting bits */
946 /* reading should also clear interrupts */
947 mask
= readl(host_mmio
+ PDC_INT_SEQMASK
);
949 if (mask
== 0xffffffff && hotplug_status
== 0) {
950 VPRINTK("QUICK EXIT 2\n");
954 mask
&= 0xffff; /* only 16 SEQIDs possible */
955 if (mask
== 0 && hotplug_status
== 0) {
956 VPRINTK("QUICK EXIT 3\n");
960 writel(mask
, host_mmio
+ PDC_INT_SEQMASK
);
962 is_sataii_tx4
= pdc_is_sataii_tx4(host
->ports
[0]->flags
);
964 for (i
= 0; i
< host
->n_ports
; i
++) {
965 VPRINTK("port %u\n", i
);
968 /* check for a plug or unplug event */
969 ata_no
= pdc_port_no_to_ata_no(i
, is_sataii_tx4
);
970 tmp
= hotplug_status
& (0x11 << ata_no
);
972 struct ata_eh_info
*ehi
= &ap
->link
.eh_info
;
973 ata_ehi_clear_desc(ehi
);
974 ata_ehi_hotplugged(ehi
);
975 ata_ehi_push_desc(ehi
, "hotplug_status %#x", tmp
);
981 /* check for a packet interrupt */
982 tmp
= mask
& (1 << (i
+ 1));
984 struct ata_queued_cmd
*qc
;
986 qc
= ata_qc_from_tag(ap
, ap
->link
.active_tag
);
987 if (qc
&& (!(qc
->tf
.flags
& ATA_TFLAG_POLLING
)))
988 handled
+= pdc_host_intr(ap
, qc
);
995 spin_unlock(&host
->lock
);
996 return IRQ_RETVAL(handled
);
999 static void pdc_packet_start(struct ata_queued_cmd
*qc
)
1001 struct ata_port
*ap
= qc
->ap
;
1002 struct pdc_port_priv
*pp
= ap
->private_data
;
1003 void __iomem
*host_mmio
= ap
->host
->iomap
[PDC_MMIO_BAR
];
1004 void __iomem
*ata_mmio
= ap
->ioaddr
.cmd_addr
;
1005 unsigned int port_no
= ap
->port_no
;
1006 u8 seq
= (u8
) (port_no
+ 1);
1008 VPRINTK("ENTER, ap %p\n", ap
);
1010 writel(0x00000001, host_mmio
+ (seq
* 4));
1011 readl(host_mmio
+ (seq
* 4)); /* flush */
1014 wmb(); /* flush PRD, pkt writes */
1015 writel(pp
->pkt_dma
, ata_mmio
+ PDC_PKT_SUBMIT
);
1016 readl(ata_mmio
+ PDC_PKT_SUBMIT
); /* flush */
1019 static unsigned int pdc_qc_issue(struct ata_queued_cmd
*qc
)
1021 switch (qc
->tf
.protocol
) {
1022 case ATAPI_PROT_NODATA
:
1023 if (qc
->dev
->flags
& ATA_DFLAG_CDB_INTR
)
1026 case ATA_PROT_NODATA
:
1027 if (qc
->tf
.flags
& ATA_TFLAG_POLLING
)
1030 case ATAPI_PROT_DMA
:
1032 pdc_packet_start(qc
);
1037 return ata_sff_qc_issue(qc
);
1040 static void pdc_tf_load_mmio(struct ata_port
*ap
, const struct ata_taskfile
*tf
)
1042 WARN_ON(tf
->protocol
== ATA_PROT_DMA
|| tf
->protocol
== ATAPI_PROT_DMA
);
1043 ata_sff_tf_load(ap
, tf
);
1046 static void pdc_exec_command_mmio(struct ata_port
*ap
,
1047 const struct ata_taskfile
*tf
)
1049 WARN_ON(tf
->protocol
== ATA_PROT_DMA
|| tf
->protocol
== ATAPI_PROT_DMA
);
1050 ata_sff_exec_command(ap
, tf
);
1053 static int pdc_check_atapi_dma(struct ata_queued_cmd
*qc
)
1055 u8
*scsicmd
= qc
->scsicmd
->cmnd
;
1056 int pio
= 1; /* atapi dma off by default */
1058 /* Whitelist commands that may use DMA. */
1059 switch (scsicmd
[0]) {
1066 case 0xad: /* READ_DVD_STRUCTURE */
1067 case 0xbe: /* READ_CD */
1070 /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */
1071 if (scsicmd
[0] == WRITE_10
) {
1073 (scsicmd
[2] << 24) |
1074 (scsicmd
[3] << 16) |
1077 if (lba
>= 0xFFFF4FA2)
1083 static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd
*qc
)
1085 /* First generation chips cannot use ATAPI DMA on SATA ports */
1089 static void pdc_ata_setup_port(struct ata_port
*ap
,
1090 void __iomem
*base
, void __iomem
*scr_addr
)
1092 ap
->ioaddr
.cmd_addr
= base
;
1093 ap
->ioaddr
.data_addr
= base
;
1094 ap
->ioaddr
.feature_addr
=
1095 ap
->ioaddr
.error_addr
= base
+ 0x4;
1096 ap
->ioaddr
.nsect_addr
= base
+ 0x8;
1097 ap
->ioaddr
.lbal_addr
= base
+ 0xc;
1098 ap
->ioaddr
.lbam_addr
= base
+ 0x10;
1099 ap
->ioaddr
.lbah_addr
= base
+ 0x14;
1100 ap
->ioaddr
.device_addr
= base
+ 0x18;
1101 ap
->ioaddr
.command_addr
=
1102 ap
->ioaddr
.status_addr
= base
+ 0x1c;
1103 ap
->ioaddr
.altstatus_addr
=
1104 ap
->ioaddr
.ctl_addr
= base
+ 0x38;
1105 ap
->ioaddr
.scr_addr
= scr_addr
;
1108 static void pdc_host_init(struct ata_host
*host
)
1110 void __iomem
*host_mmio
= host
->iomap
[PDC_MMIO_BAR
];
1111 int is_gen2
= host
->ports
[0]->flags
& PDC_FLAG_GEN_II
;
1116 hotplug_offset
= PDC2_SATA_PLUG_CSR
;
1118 hotplug_offset
= PDC_SATA_PLUG_CSR
;
1121 * Except for the hotplug stuff, this is voodoo from the
1122 * Promise driver. Label this entire section
1123 * "TODO: figure out why we do this"
1126 /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */
1127 tmp
= readl(host_mmio
+ PDC_FLASH_CTL
);
1128 tmp
|= 0x02000; /* bit 13 (enable bmr burst) */
1130 tmp
|= 0x10000; /* bit 16 (fifo threshold at 8 dw) */
1131 writel(tmp
, host_mmio
+ PDC_FLASH_CTL
);
1133 /* clear plug/unplug flags for all ports */
1134 tmp
= readl(host_mmio
+ hotplug_offset
);
1135 writel(tmp
| 0xff, host_mmio
+ hotplug_offset
);
1137 tmp
= readl(host_mmio
+ hotplug_offset
);
1138 if (is_gen2
) /* unmask plug/unplug ints */
1139 writel(tmp
& ~0xff0000, host_mmio
+ hotplug_offset
);
1140 else /* mask plug/unplug ints */
1141 writel(tmp
| 0xff0000, host_mmio
+ hotplug_offset
);
1143 /* don't initialise TBG or SLEW on 2nd generation chips */
1147 /* reduce TBG clock to 133 Mhz. */
1148 tmp
= readl(host_mmio
+ PDC_TBG_MODE
);
1149 tmp
&= ~0x30000; /* clear bit 17, 16*/
1150 tmp
|= 0x10000; /* set bit 17:16 = 0:1 */
1151 writel(tmp
, host_mmio
+ PDC_TBG_MODE
);
1153 readl(host_mmio
+ PDC_TBG_MODE
); /* flush */
1156 /* adjust slew rate control register. */
1157 tmp
= readl(host_mmio
+ PDC_SLEW_CTL
);
1158 tmp
&= 0xFFFFF03F; /* clear bit 11 ~ 6 */
1159 tmp
|= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
1160 writel(tmp
, host_mmio
+ PDC_SLEW_CTL
);
1163 static int pdc_ata_init_one(struct pci_dev
*pdev
,
1164 const struct pci_device_id
*ent
)
1166 const struct ata_port_info
*pi
= &pdc_port_info
[ent
->driver_data
];
1167 const struct ata_port_info
*ppi
[PDC_MAX_PORTS
];
1168 struct ata_host
*host
;
1169 struct pdc_host_priv
*hpriv
;
1170 void __iomem
*host_mmio
;
1174 ata_print_version_once(&pdev
->dev
, DRV_VERSION
);
1176 /* enable and acquire resources */
1177 rc
= pcim_enable_device(pdev
);
1181 rc
= pcim_iomap_regions(pdev
, 1 << PDC_MMIO_BAR
, DRV_NAME
);
1183 pcim_pin_device(pdev
);
1186 host_mmio
= pcim_iomap_table(pdev
)[PDC_MMIO_BAR
];
1188 /* determine port configuration and setup host */
1190 if (pi
->flags
& PDC_FLAG_4_PORTS
)
1192 for (i
= 0; i
< n_ports
; i
++)
1195 if (pi
->flags
& PDC_FLAG_SATA_PATA
) {
1196 u8 tmp
= readb(host_mmio
+ PDC_FLASH_CTL
+ 1);
1198 ppi
[n_ports
++] = pi
+ 1;
1201 host
= ata_host_alloc_pinfo(&pdev
->dev
, ppi
, n_ports
);
1203 dev_err(&pdev
->dev
, "failed to allocate host\n");
1206 hpriv
= devm_kzalloc(&pdev
->dev
, sizeof *hpriv
, GFP_KERNEL
);
1209 spin_lock_init(&hpriv
->hard_reset_lock
);
1210 host
->private_data
= hpriv
;
1211 host
->iomap
= pcim_iomap_table(pdev
);
1213 is_sataii_tx4
= pdc_is_sataii_tx4(pi
->flags
);
1214 for (i
= 0; i
< host
->n_ports
; i
++) {
1215 struct ata_port
*ap
= host
->ports
[i
];
1216 unsigned int ata_no
= pdc_port_no_to_ata_no(i
, is_sataii_tx4
);
1217 unsigned int ata_offset
= 0x200 + ata_no
* 0x80;
1218 unsigned int scr_offset
= 0x400 + ata_no
* 0x100;
1220 pdc_ata_setup_port(ap
, host_mmio
+ ata_offset
, host_mmio
+ scr_offset
);
1222 ata_port_pbar_desc(ap
, PDC_MMIO_BAR
, -1, "mmio");
1223 ata_port_pbar_desc(ap
, PDC_MMIO_BAR
, ata_offset
, "ata");
1226 /* initialize adapter */
1227 pdc_host_init(host
);
1229 rc
= dma_set_mask_and_coherent(&pdev
->dev
, ATA_DMA_MASK
);
1233 /* start host, request IRQ and attach */
1234 pci_set_master(pdev
);
1235 return ata_host_activate(host
, pdev
->irq
, pdc_interrupt
, IRQF_SHARED
,
1239 module_pci_driver(pdc_ata_pci_driver
);
1241 MODULE_AUTHOR("Jeff Garzik");
1242 MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
1243 MODULE_LICENSE("GPL");
1244 MODULE_DEVICE_TABLE(pci
, pdc_ata_pci_tbl
);
1245 MODULE_VERSION(DRV_VERSION
);