drivers/ata/sata_sis.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *  sata_sis.c - Silicon Integrated Systems SATA
   4  *
   5  *  Maintained by:  Uwe Koziolek
   6  *                  Please ALWAYS copy linux-ide@vger.kernel.org
   7  *                  on emails.
   8  *
   9  *  Copyright 2004 Uwe Koziolek
  10  *
  11  *  libata documentation is available via 'make {ps|pdf}docs',
  12  *  as Documentation/driver-api/libata.rst
  13  *
  14  *  Hardware documentation available under NDA.
  15  */
  16
  17 #include <linux/kernel.h>
  18 #include <linux/module.h>
  19 #include <linux/pci.h>
  20 #include <linux/blkdev.h>
  21 #include <linux/delay.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/device.h>
  24 #include <scsi/scsi_host.h>
  25 #include <linux/libata.h>
  26 #include "sis.h"
  27
  28 #define DRV_NAME        "sata_sis"
  29 #define DRV_VERSION     "1.0"
  30
  31 enum {
  32         sis_180                 = 0,
  33         SIS_SCR_PCI_BAR         = 5,
  34
  35         /* PCI configuration registers */
  36         SIS_GENCTL              = 0x54, /* IDE General Control register */
  37         SIS_SCR_BASE            = 0xc0, /* sata0 phy SCR registers */
  38         SIS180_SATA1_OFS        = 0x10, /* offset from sata0->sata1 phy regs */
  39         SIS182_SATA1_OFS        = 0x20, /* offset from sata0->sata1 phy regs */
  40         SIS_PMR                 = 0x90, /* port mapping register */
  41         SIS_PMR_COMBINED        = 0x30,
  42
  43         /* random bits */
  44         SIS_FLAG_CFGSCR         = (1 << 30), /* host flag: SCRs via PCI cfg */
  45
  46         GENCTL_IOMAPPED_SCR     = (1 << 26), /* if set, SCRs are in IO space */
  47 };
  48
  49 static int sis_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
  50 static int sis_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
  51 static int sis_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
  52
  53 static const struct pci_device_id sis_pci_tbl[] = {
  54         { PCI_VDEVICE(SI, 0x0180), sis_180 },   /* SiS 964/180 */
  55         { PCI_VDEVICE(SI, 0x0181), sis_180 },   /* SiS 964/180 */
  56         { PCI_VDEVICE(SI, 0x0182), sis_180 },   /* SiS 965/965L */
  57         { PCI_VDEVICE(SI, 0x0183), sis_180 },   /* SiS 965/965L */
  58         { PCI_VDEVICE(SI, 0x1182), sis_180 },   /* SiS 966/680 */
  59         { PCI_VDEVICE(SI, 0x1183), sis_180 },   /* SiS 966/966L/968/680 */
  60
  61         { }     /* terminate list */
  62 };
  63
  64 static struct pci_driver sis_pci_driver = {
  65         .name                   = DRV_NAME,
  66         .id_table               = sis_pci_tbl,
  67         .probe                  = sis_init_one,
  68         .remove                 = ata_pci_remove_one,
  69 #ifdef CONFIG_PM_SLEEP
  70         .suspend                = ata_pci_device_suspend,
  71         .resume                 = ata_pci_device_resume,
  72 #endif
  73 };
  74
  75 static struct scsi_host_template sis_sht = {
  76         ATA_BMDMA_SHT(DRV_NAME),
  77 };
  78
  79 static struct ata_port_operations sis_ops = {
  80         .inherits               = &ata_bmdma_port_ops,
  81         .scr_read               = sis_scr_read,
  82         .scr_write              = sis_scr_write,
  83 };
  84
  85 static const struct ata_port_info sis_port_info = {
  86         .flags          = ATA_FLAG_SATA,
  87         .pio_mask       = ATA_PIO4,
  88         .mwdma_mask     = ATA_MWDMA2,
  89         .udma_mask      = ATA_UDMA6,
  90         .port_ops       = &sis_ops,
  91 };
  92
  93 MODULE_AUTHOR("Uwe Koziolek");
  94 MODULE_DESCRIPTION("low-level driver for Silicon Integrated Systems SATA controller");
  95 MODULE_LICENSE("GPL");
  96 MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
  97 MODULE_VERSION(DRV_VERSION);
  98
  99 static unsigned int get_scr_cfg_addr(struct ata_link *link, unsigned int sc_reg)
 100 {
 101         struct ata_port *ap = link->ap;
 102         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 103         unsigned int addr = SIS_SCR_BASE + (4 * sc_reg);
 104         u8 pmr;
 105
 106         if (ap->port_no)  {
 107                 switch (pdev->device) {
 108                 case 0x0180:
 109                 case 0x0181:
 110                         pci_read_config_byte(pdev, SIS_PMR, &pmr);
 111                         if ((pmr & SIS_PMR_COMBINED) == 0)
 112                                 addr += SIS180_SATA1_OFS;
 113                         break;
 114
 115                 case 0x0182:
 116                 case 0x0183:
 117                 case 0x1182:
 118                         addr += SIS182_SATA1_OFS;
 119                         break;
 120                 }
 121         }
 122         if (link->pmp)
 123                 addr += 0x10;
 124
 125         return addr;
 126 }
 127
 128 static u32 sis_scr_cfg_read(struct ata_link *link,
 129                             unsigned int sc_reg, u32 *val)
 130 {
 131         struct pci_dev *pdev = to_pci_dev(link->ap->host->dev);
 132         unsigned int cfg_addr = get_scr_cfg_addr(link, sc_reg);
 133
 134         if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
 135                 return -EINVAL;
 136
 137         pci_read_config_dword(pdev, cfg_addr, val);
 138         return 0;
 139 }
 140
 141 static int sis_scr_cfg_write(struct ata_link *link,
 142                              unsigned int sc_reg, u32 val)
 143 {
 144         struct pci_dev *pdev = to_pci_dev(link->ap->host->dev);
 145         unsigned int cfg_addr = get_scr_cfg_addr(link, sc_reg);
 146
 147         pci_write_config_dword(pdev, cfg_addr, val);
 148         return 0;
 149 }
 150
 151 static int sis_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
 152 {
 153         struct ata_port *ap = link->ap;
 154         void __iomem *base = ap->ioaddr.scr_addr + link->pmp * 0x10;
 155
 156         if (sc_reg > SCR_CONTROL)
 157                 return -EINVAL;
 158
 159         if (ap->flags & SIS_FLAG_CFGSCR)
 160                 return sis_scr_cfg_read(link, sc_reg, val);
 161
 162         *val = ioread32(base + sc_reg * 4);
 163         return 0;
 164 }
 165
 166 static int sis_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
 167 {
 168         struct ata_port *ap = link->ap;
 169         void __iomem *base = ap->ioaddr.scr_addr + link->pmp * 0x10;
 170
 171         if (sc_reg > SCR_CONTROL)
 172                 return -EINVAL;
 173
 174         if (ap->flags & SIS_FLAG_CFGSCR)
 175                 return sis_scr_cfg_write(link, sc_reg, val);
 176
 177         iowrite32(val, base + (sc_reg * 4));
 178         return 0;
 179 }
 180
 181 static int sis_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
 182 {
 183         struct ata_port_info pi = sis_port_info;
 184         const struct ata_port_info *ppi[] = { &pi, &pi };
 185         struct ata_host *host;
 186         u32 genctl, val;
 187         u8 pmr;
 188         u8 port2_start = 0x20;
 189         int i, rc;
 190
 191         ata_print_version_once(&pdev->dev, DRV_VERSION);
 192
 193         rc = pcim_enable_device(pdev);
 194         if (rc)
 195                 return rc;
 196
 197         /* check and see if the SCRs are in IO space or PCI cfg space */
 198         pci_read_config_dword(pdev, SIS_GENCTL, &genctl);
 199         if ((genctl & GENCTL_IOMAPPED_SCR) == 0)
 200                 pi.flags |= SIS_FLAG_CFGSCR;
 201
 202         /* if hardware thinks SCRs are in IO space, but there are
 203          * no IO resources assigned, change to PCI cfg space.
 204          */
 205         if ((!(pi.flags & SIS_FLAG_CFGSCR)) &&
 206             ((pci_resource_start(pdev, SIS_SCR_PCI_BAR) == 0) ||
 207              (pci_resource_len(pdev, SIS_SCR_PCI_BAR) < 128))) {
 208                 genctl &= ~GENCTL_IOMAPPED_SCR;
 209                 pci_write_config_dword(pdev, SIS_GENCTL, genctl);
 210                 pi.flags |= SIS_FLAG_CFGSCR;
 211         }
 212
 213         pci_read_config_byte(pdev, SIS_PMR, &pmr);
 214         switch (ent->device) {
 215         case 0x0180:
 216         case 0x0181:
 217
 218                 /* The PATA-handling is provided by pata_sis */
 219                 switch (pmr & 0x30) {
 220                 case 0x10:
 221                         ppi[1] = &sis_info133_for_sata;
 222                         break;
 223
 224                 case 0x30:
 225                         ppi[0] = &sis_info133_for_sata;
 226                         break;
 227                 }
 228                 if ((pmr & SIS_PMR_COMBINED) == 0) {
 229                         dev_info(&pdev->dev,
 230                                  "Detected SiS 180/181/964 chipset in SATA mode\n");
 231                         port2_start = 64;
 232                 } else {
 233                         dev_info(&pdev->dev,
 234                                  "Detected SiS 180/181 chipset in combined mode\n");
 235                         port2_start = 0;
 236                         pi.flags |= ATA_FLAG_SLAVE_POSS;
 237                 }
 238                 break;
 239
 240         case 0x0182:
 241         case 0x0183:
 242                 pci_read_config_dword(pdev, 0x6C, &val);
 243                 if (val & (1L << 31)) {
 244                         dev_info(&pdev->dev, "Detected SiS 182/965 chipset\n");
 245                         pi.flags |= ATA_FLAG_SLAVE_POSS;
 246                 } else {
 247                         dev_info(&pdev->dev, "Detected SiS 182/965L chipset\n");
 248                 }
 249                 break;
 250
 251         case 0x1182:
 252                 dev_info(&pdev->dev,
 253                          "Detected SiS 1182/966/680 SATA controller\n");
 254                 pi.flags |= ATA_FLAG_SLAVE_POSS;
 255                 break;
 256
 257         case 0x1183:
 258                 dev_info(&pdev->dev,
 259                          "Detected SiS 1183/966/966L/968/680 controller in PATA mode\n");
 260                 ppi[0] = &sis_info133_for_sata;
 261                 ppi[1] = &sis_info133_for_sata;
 262                 break;
 263         }
 264
 265         rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
 266         if (rc)
 267                 return rc;
 268
 269         for (i = 0; i < 2; i++) {
 270                 struct ata_port *ap = host->ports[i];
 271
 272                 if (ap->flags & ATA_FLAG_SATA &&
 273                     ap->flags & ATA_FLAG_SLAVE_POSS) {
 274                         rc = ata_slave_link_init(ap);
 275                         if (rc)
 276                                 return rc;
 277                 }
 278         }
 279
 280         if (!(pi.flags & SIS_FLAG_CFGSCR)) {
 281                 void __iomem *mmio;
 282
 283                 rc = pcim_iomap_regions(pdev, 1 << SIS_SCR_PCI_BAR, DRV_NAME);
 284                 if (rc)
 285                         return rc;
 286                 mmio = host->iomap[SIS_SCR_PCI_BAR];
 287
 288                 host->ports[0]->ioaddr.scr_addr = mmio;
 289                 host->ports[1]->ioaddr.scr_addr = mmio + port2_start;
 290         }
 291
 292         pci_set_master(pdev);
 293         pci_intx(pdev, 1);
 294         return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
 295                                  IRQF_SHARED, &sis_sht);
 296 }
 297
 298 module_pci_driver(sis_pci_driver);