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Merge tag 'block-5.11-2021-01-10' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / atm / nicstar.c
blob5c7e4df159b9128d6bda914c1e6365f3fe6e6bb1
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * nicstar.c
4 *
5 * Device driver supporting CBR for IDT 77201/77211 "NICStAR" based cards.
6 *
7 * IMPORTANT: The included file nicstarmac.c was NOT WRITTEN BY ME.
8 * It was taken from the frle-0.22 device driver.
9 * As the file doesn't have a copyright notice, in the file
10 * nicstarmac.copyright I put the copyright notice from the
11 * frle-0.22 device driver.
12 * Some code is based on the nicstar driver by M. Welsh.
13 *
14 * Author: Rui Prior (rprior@inescn.pt)
15 * PowerPC support by Jay Talbott (jay_talbott@mcg.mot.com) April 1999
16 *
17 *
18 * (C) INESC 1999
19 */
20
21 /*
22 * IMPORTANT INFORMATION
23 *
24 * There are currently three types of spinlocks:
25 *
26 * 1 - Per card interrupt spinlock (to protect structures and such)
27 * 2 - Per SCQ scq spinlock
28 * 3 - Per card resource spinlock (to access registers, etc.)
29 *
30 * These must NEVER be grabbed in reverse order.
31 *
32 */
33
34 /* Header files */
35
36 #include <linux/module.h>
37 #include <linux/kernel.h>
38 #include <linux/skbuff.h>
39 #include <linux/atmdev.h>
40 #include <linux/atm.h>
41 #include <linux/pci.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/types.h>
44 #include <linux/string.h>
45 #include <linux/delay.h>
46 #include <linux/init.h>
47 #include <linux/sched.h>
48 #include <linux/timer.h>
49 #include <linux/interrupt.h>
50 #include <linux/bitops.h>
51 #include <linux/slab.h>
52 #include <linux/idr.h>
53 #include <asm/io.h>
54 #include <linux/uaccess.h>
55 #include <linux/atomic.h>
56 #include <linux/etherdevice.h>
57 #include "nicstar.h"
58 #ifdef CONFIG_ATM_NICSTAR_USE_SUNI
59 #include "suni.h"
60 #endif /* CONFIG_ATM_NICSTAR_USE_SUNI */
61 #ifdef CONFIG_ATM_NICSTAR_USE_IDT77105
62 #include "idt77105.h"
63 #endif /* CONFIG_ATM_NICSTAR_USE_IDT77105 */
64
65 /* Additional code */
66
67 #include "nicstarmac.c"
68
69 /* Configurable parameters */
70
71 #undef PHY_LOOPBACK
72 #undef TX_DEBUG
73 #undef RX_DEBUG
74 #undef GENERAL_DEBUG
75 #undef EXTRA_DEBUG
76
77 /* Do not touch these */
78
79 #ifdef TX_DEBUG
80 #define TXPRINTK(args...) printk(args)
81 #else
82 #define TXPRINTK(args...)
83 #endif /* TX_DEBUG */
84
85 #ifdef RX_DEBUG
86 #define RXPRINTK(args...) printk(args)
87 #else
88 #define RXPRINTK(args...)
89 #endif /* RX_DEBUG */
90
91 #ifdef GENERAL_DEBUG
92 #define PRINTK(args...) printk(args)
93 #else
94 #define PRINTK(args...) do {} while (0)
95 #endif /* GENERAL_DEBUG */
96
97 #ifdef EXTRA_DEBUG
98 #define XPRINTK(args...) printk(args)
99 #else
100 #define XPRINTK(args...)
101 #endif /* EXTRA_DEBUG */
102
103 /* Macros */
104
105 #define CMD_BUSY(card) (readl((card)->membase + STAT) & NS_STAT_CMDBZ)
106
107 #define NS_DELAY mdelay(1)
108
109 #define PTR_DIFF(a, b) ((u32)((unsigned long)(a) - (unsigned long)(b)))
110
111 #ifndef ATM_SKB
112 #define ATM_SKB(s) (&(s)->atm)
113 #endif
114
115 #define scq_virt_to_bus(scq, p) \
116 (scq->dma + ((unsigned long)(p) - (unsigned long)(scq)->org))
117
118 /* Function declarations */
119
120 static u32 ns_read_sram(ns_dev * card, u32 sram_address);
121 static void ns_write_sram(ns_dev * card, u32 sram_address, u32 * value,
122 int count);
123 static int ns_init_card(int i, struct pci_dev *pcidev);
124 static void ns_init_card_error(ns_dev * card, int error);
125 static scq_info *get_scq(ns_dev *card, int size, u32 scd);
126 static void free_scq(ns_dev *card, scq_info * scq, struct atm_vcc *vcc);
127 static void push_rxbufs(ns_dev *, struct sk_buff *);
128 static irqreturn_t ns_irq_handler(int irq, void *dev_id);
129 static int ns_open(struct atm_vcc *vcc);
130 static void ns_close(struct atm_vcc *vcc);
131 static void fill_tst(ns_dev * card, int n, vc_map * vc);
132 static int ns_send(struct atm_vcc *vcc, struct sk_buff *skb);
133 static int ns_send_bh(struct atm_vcc *vcc, struct sk_buff *skb);
134 static int push_scqe(ns_dev * card, vc_map * vc, scq_info * scq, ns_scqe * tbd,
135 struct sk_buff *skb, bool may_sleep);
136 static void process_tsq(ns_dev * card);
137 static void drain_scq(ns_dev * card, scq_info * scq, int pos);
138 static void process_rsq(ns_dev * card);
139 static void dequeue_rx(ns_dev * card, ns_rsqe * rsqe);
140 static void recycle_rx_buf(ns_dev * card, struct sk_buff *skb);
141 static void recycle_iovec_rx_bufs(ns_dev * card, struct iovec *iov, int count);
142 static void recycle_iov_buf(ns_dev * card, struct sk_buff *iovb);
143 static void dequeue_sm_buf(ns_dev * card, struct sk_buff *sb);
144 static void dequeue_lg_buf(ns_dev * card, struct sk_buff *lb);
145 static int ns_proc_read(struct atm_dev *dev, loff_t * pos, char *page);
146 static int ns_ioctl(struct atm_dev *dev, unsigned int cmd, void __user * arg);
147 #ifdef EXTRA_DEBUG
148 static void which_list(ns_dev * card, struct sk_buff *skb);
149 #endif
150 static void ns_poll(struct timer_list *unused);
151 static void ns_phy_put(struct atm_dev *dev, unsigned char value,
152 unsigned long addr);
153 static unsigned char ns_phy_get(struct atm_dev *dev, unsigned long addr);
154
155 /* Global variables */
156
157 static struct ns_dev *cards[NS_MAX_CARDS];
158 static unsigned num_cards;
159 static const struct atmdev_ops atm_ops = {
160 .open = ns_open,
161 .close = ns_close,
162 .ioctl = ns_ioctl,
163 .send = ns_send,
164 .send_bh = ns_send_bh,
165 .phy_put = ns_phy_put,
166 .phy_get = ns_phy_get,
167 .proc_read = ns_proc_read,
168 .owner = THIS_MODULE,
169 };
170
171 static struct timer_list ns_timer;
172 static char *mac[NS_MAX_CARDS];
173 module_param_array(mac, charp, NULL, 0);
174 MODULE_LICENSE("GPL");
175
176 /* Functions */
177
178 static int nicstar_init_one(struct pci_dev *pcidev,
179 const struct pci_device_id *ent)
180 {
181 static int index = -1;
182 unsigned int error;
183
184 index++;
185 cards[index] = NULL;
186
187 error = ns_init_card(index, pcidev);
188 if (error) {
189 cards[index--] = NULL; /* don't increment index */
190 goto err_out;
191 }
192
193 return 0;
194 err_out:
195 return -ENODEV;
196 }
197
198 static void nicstar_remove_one(struct pci_dev *pcidev)
199 {
200 int i, j;
201 ns_dev *card = pci_get_drvdata(pcidev);
202 struct sk_buff *hb;
203 struct sk_buff *iovb;
204 struct sk_buff *lb;
205 struct sk_buff *sb;
206
207 i = card->index;
208
209 if (cards[i] == NULL)
210 return;
211
212 if (card->atmdev->phy && card->atmdev->phy->stop)
213 card->atmdev->phy->stop(card->atmdev);
214
215 /* Stop everything */
216 writel(0x00000000, card->membase + CFG);
217
218 /* De-register device */
219 atm_dev_deregister(card->atmdev);
220
221 /* Disable PCI device */
222 pci_disable_device(pcidev);
223
224 /* Free up resources */
225 j = 0;
226 PRINTK("nicstar%d: freeing %d huge buffers.\n", i, card->hbpool.count);
227 while ((hb = skb_dequeue(&card->hbpool.queue)) != NULL) {
228 dev_kfree_skb_any(hb);
229 j++;
230 }
231 PRINTK("nicstar%d: %d huge buffers freed.\n", i, j);
232 j = 0;
233 PRINTK("nicstar%d: freeing %d iovec buffers.\n", i,
234 card->iovpool.count);
235 while ((iovb = skb_dequeue(&card->iovpool.queue)) != NULL) {
236 dev_kfree_skb_any(iovb);
237 j++;
238 }
239 PRINTK("nicstar%d: %d iovec buffers freed.\n", i, j);
240 while ((lb = skb_dequeue(&card->lbpool.queue)) != NULL)
241 dev_kfree_skb_any(lb);
242 while ((sb = skb_dequeue(&card->sbpool.queue)) != NULL)
243 dev_kfree_skb_any(sb);
244 free_scq(card, card->scq0, NULL);
245 for (j = 0; j < NS_FRSCD_NUM; j++) {
246 if (card->scd2vc[j] != NULL)
247 free_scq(card, card->scd2vc[j]->scq, card->scd2vc[j]->tx_vcc);
248 }
249 idr_destroy(&card->idr);
250 dma_free_coherent(&card->pcidev->dev, NS_RSQSIZE + NS_RSQ_ALIGNMENT,
251 card->rsq.org, card->rsq.dma);
252 dma_free_coherent(&card->pcidev->dev, NS_TSQSIZE + NS_TSQ_ALIGNMENT,
253 card->tsq.org, card->tsq.dma);
254 free_irq(card->pcidev->irq, card);
255 iounmap(card->membase);
256 kfree(card);
257 }
258
259 static const struct pci_device_id nicstar_pci_tbl[] = {
260 { PCI_VDEVICE(IDT, PCI_DEVICE_ID_IDT_IDT77201), 0 },
261 {0,} /* terminate list */
262 };
263
264 MODULE_DEVICE_TABLE(pci, nicstar_pci_tbl);
265
266 static struct pci_driver nicstar_driver = {
267 .name = "nicstar",
268 .id_table = nicstar_pci_tbl,
269 .probe = nicstar_init_one,
270 .remove = nicstar_remove_one,
271 };
272
273 static int __init nicstar_init(void)
274 {
275 unsigned error = 0; /* Initialized to remove compile warning */
276
277 XPRINTK("nicstar: nicstar_init() called.\n");
278
279 error = pci_register_driver(&nicstar_driver);
280
281 TXPRINTK("nicstar: TX debug enabled.\n");
282 RXPRINTK("nicstar: RX debug enabled.\n");
283 PRINTK("nicstar: General debug enabled.\n");
284 #ifdef PHY_LOOPBACK
285 printk("nicstar: using PHY loopback.\n");
286 #endif /* PHY_LOOPBACK */
287 XPRINTK("nicstar: nicstar_init() returned.\n");
288
289 if (!error) {
290 timer_setup(&ns_timer, ns_poll, 0);
291 ns_timer.expires = jiffies + NS_POLL_PERIOD;
292 add_timer(&ns_timer);
293 }
294
295 return error;
296 }
297
298 static void __exit nicstar_cleanup(void)
299 {
300 XPRINTK("nicstar: nicstar_cleanup() called.\n");
301
302 del_timer(&ns_timer);
303
304 pci_unregister_driver(&nicstar_driver);
305
306 XPRINTK("nicstar: nicstar_cleanup() returned.\n");
307 }
308
309 static u32 ns_read_sram(ns_dev * card, u32 sram_address)
310 {
311 unsigned long flags;
312 u32 data;
313 sram_address <<= 2;
314 sram_address &= 0x0007FFFC; /* address must be dword aligned */
315 sram_address |= 0x50000000; /* SRAM read command */
316 spin_lock_irqsave(&card->res_lock, flags);
317 while (CMD_BUSY(card)) ;
318 writel(sram_address, card->membase + CMD);
319 while (CMD_BUSY(card)) ;
320 data = readl(card->membase + DR0);
321 spin_unlock_irqrestore(&card->res_lock, flags);
322 return data;
323 }
324
325 static void ns_write_sram(ns_dev * card, u32 sram_address, u32 * value,
326 int count)
327 {
328 unsigned long flags;
329 int i, c;
330 count--; /* count range now is 0..3 instead of 1..4 */
331 c = count;
332 c <<= 2; /* to use increments of 4 */
333 spin_lock_irqsave(&card->res_lock, flags);
334 while (CMD_BUSY(card)) ;
335 for (i = 0; i <= c; i += 4)
336 writel(*(value++), card->membase + i);
337 /* Note: DR# registers are the first 4 dwords in nicstar's memspace,
338 so card->membase + DR0 == card->membase */
339 sram_address <<= 2;
340 sram_address &= 0x0007FFFC;
341 sram_address |= (0x40000000 | count);
342 writel(sram_address, card->membase + CMD);
343 spin_unlock_irqrestore(&card->res_lock, flags);
344 }
345
346 static int ns_init_card(int i, struct pci_dev *pcidev)
347 {
348 int j;
349 struct ns_dev *card = NULL;
350 unsigned char pci_latency;
351 unsigned error;
352 u32 data;
353 u32 u32d[4];
354 u32 ns_cfg_rctsize;
355 int bcount;
356 unsigned long membase;
357
358 error = 0;
359
360 if (pci_enable_device(pcidev)) {
361 printk("nicstar%d: can't enable PCI device\n", i);
362 error = 2;
363 ns_init_card_error(card, error);
364 return error;
365 }
366 if (dma_set_mask_and_coherent(&pcidev->dev, DMA_BIT_MASK(32)) != 0) {
367 printk(KERN_WARNING
368 "nicstar%d: No suitable DMA available.\n", i);
369 error = 2;
370 ns_init_card_error(card, error);
371 return error;
372 }
373
374 card = kmalloc(sizeof(*card), GFP_KERNEL);
375 if (!card) {
376 printk
377 ("nicstar%d: can't allocate memory for device structure.\n",
378 i);
379 error = 2;
380 ns_init_card_error(card, error);
381 return error;
382 }
383 cards[i] = card;
384 spin_lock_init(&card->int_lock);
385 spin_lock_init(&card->res_lock);
386
387 pci_set_drvdata(pcidev, card);
388
389 card->index = i;
390 card->atmdev = NULL;
391 card->pcidev = pcidev;
392 membase = pci_resource_start(pcidev, 1);
393 card->membase = ioremap(membase, NS_IOREMAP_SIZE);
394 if (!card->membase) {
395 printk("nicstar%d: can't ioremap() membase.\n", i);
396 error = 3;
397 ns_init_card_error(card, error);
398 return error;
399 }
400 PRINTK("nicstar%d: membase at 0x%p.\n", i, card->membase);
401
402 pci_set_master(pcidev);
403
404 if (pci_read_config_byte(pcidev, PCI_LATENCY_TIMER, &pci_latency) != 0) {
405 printk("nicstar%d: can't read PCI latency timer.\n", i);
406 error = 6;
407 ns_init_card_error(card, error);
408 return error;
409 }
410 #ifdef NS_PCI_LATENCY
411 if (pci_latency < NS_PCI_LATENCY) {
412 PRINTK("nicstar%d: setting PCI latency timer to %d.\n", i,
413 NS_PCI_LATENCY);
414 for (j = 1; j < 4; j++) {
415 if (pci_write_config_byte
416 (pcidev, PCI_LATENCY_TIMER, NS_PCI_LATENCY) != 0)
417 break;
418 }
419 if (j == 4) {
420 printk
421 ("nicstar%d: can't set PCI latency timer to %d.\n",
422 i, NS_PCI_LATENCY);
423 error = 7;
424 ns_init_card_error(card, error);
425 return error;
426 }
427 }
428 #endif /* NS_PCI_LATENCY */
429
430 /* Clear timer overflow */
431 data = readl(card->membase + STAT);
432 if (data & NS_STAT_TMROF)
433 writel(NS_STAT_TMROF, card->membase + STAT);
434
435 /* Software reset */
436 writel(NS_CFG_SWRST, card->membase + CFG);
437 NS_DELAY;
438 writel(0x00000000, card->membase + CFG);
439
440 /* PHY reset */
441 writel(0x00000008, card->membase + GP);
442 NS_DELAY;
443 writel(0x00000001, card->membase + GP);
444 NS_DELAY;
445 while (CMD_BUSY(card)) ;
446 writel(NS_CMD_WRITE_UTILITY | 0x00000100, card->membase + CMD); /* Sync UTOPIA with SAR clock */
447 NS_DELAY;
448
449 /* Detect PHY type */
450 while (CMD_BUSY(card)) ;
451 writel(NS_CMD_READ_UTILITY | 0x00000200, card->membase + CMD);
452 while (CMD_BUSY(card)) ;
453 data = readl(card->membase + DR0);
454 switch (data) {
455 case 0x00000009:
456 printk("nicstar%d: PHY seems to be 25 Mbps.\n", i);
457 card->max_pcr = ATM_25_PCR;
458 while (CMD_BUSY(card)) ;
459 writel(0x00000008, card->membase + DR0);
460 writel(NS_CMD_WRITE_UTILITY | 0x00000200, card->membase + CMD);
461 /* Clear an eventual pending interrupt */
462 writel(NS_STAT_SFBQF, card->membase + STAT);
463 #ifdef PHY_LOOPBACK
464 while (CMD_BUSY(card)) ;
465 writel(0x00000022, card->membase + DR0);
466 writel(NS_CMD_WRITE_UTILITY | 0x00000202, card->membase + CMD);
467 #endif /* PHY_LOOPBACK */
468 break;
469 case 0x00000030:
470 case 0x00000031:
471 printk("nicstar%d: PHY seems to be 155 Mbps.\n", i);
472 card->max_pcr = ATM_OC3_PCR;
473 #ifdef PHY_LOOPBACK
474 while (CMD_BUSY(card)) ;
475 writel(0x00000002, card->membase + DR0);
476 writel(NS_CMD_WRITE_UTILITY | 0x00000205, card->membase + CMD);
477 #endif /* PHY_LOOPBACK */
478 break;
479 default:
480 printk("nicstar%d: unknown PHY type (0x%08X).\n", i, data);
481 error = 8;
482 ns_init_card_error(card, error);
483 return error;
484 }
485 writel(0x00000000, card->membase + GP);
486
487 /* Determine SRAM size */
488 data = 0x76543210;
489 ns_write_sram(card, 0x1C003, &data, 1);
490 data = 0x89ABCDEF;
491 ns_write_sram(card, 0x14003, &data, 1);
492 if (ns_read_sram(card, 0x14003) == 0x89ABCDEF &&
493 ns_read_sram(card, 0x1C003) == 0x76543210)
494 card->sram_size = 128;
495 else
496 card->sram_size = 32;
497 PRINTK("nicstar%d: %dK x 32bit SRAM size.\n", i, card->sram_size);
498
499 card->rct_size = NS_MAX_RCTSIZE;
500
501 #if (NS_MAX_RCTSIZE == 4096)
502 if (card->sram_size == 128)
503 printk
504 ("nicstar%d: limiting maximum VCI. See NS_MAX_RCTSIZE in nicstar.h\n",
505 i);
506 #elif (NS_MAX_RCTSIZE == 16384)
507 if (card->sram_size == 32) {
508 printk
509 ("nicstar%d: wasting memory. See NS_MAX_RCTSIZE in nicstar.h\n",
510 i);
511 card->rct_size = 4096;
512 }
513 #else
514 #error NS_MAX_RCTSIZE must be either 4096 or 16384 in nicstar.c
515 #endif
516
517 card->vpibits = NS_VPIBITS;
518 if (card->rct_size == 4096)
519 card->vcibits = 12 - NS_VPIBITS;
520 else /* card->rct_size == 16384 */
521 card->vcibits = 14 - NS_VPIBITS;
522
523 /* Initialize the nicstar eeprom/eprom stuff, for the MAC addr */
524 if (mac[i] == NULL)
525 nicstar_init_eprom(card->membase);
526
527 /* Set the VPI/VCI MSb mask to zero so we can receive OAM cells */
528 writel(0x00000000, card->membase + VPM);
529
530 /* Initialize TSQ */
531 card->tsq.org = dma_alloc_coherent(&card->pcidev->dev,
532 NS_TSQSIZE + NS_TSQ_ALIGNMENT,
533 &card->tsq.dma, GFP_KERNEL);
534 if (card->tsq.org == NULL) {
535 printk("nicstar%d: can't allocate TSQ.\n", i);
536 error = 10;
537 ns_init_card_error(card, error);
538 return error;
539 }
540 card->tsq.base = PTR_ALIGN(card->tsq.org, NS_TSQ_ALIGNMENT);
541 card->tsq.next = card->tsq.base;
542 card->tsq.last = card->tsq.base + (NS_TSQ_NUM_ENTRIES - 1);
543 for (j = 0; j < NS_TSQ_NUM_ENTRIES; j++)
544 ns_tsi_init(card->tsq.base + j);
545 writel(0x00000000, card->membase + TSQH);
546 writel(ALIGN(card->tsq.dma, NS_TSQ_ALIGNMENT), card->membase + TSQB);
547 PRINTK("nicstar%d: TSQ base at 0x%p.\n", i, card->tsq.base);
548
549 /* Initialize RSQ */
550 card->rsq.org = dma_alloc_coherent(&card->pcidev->dev,
551 NS_RSQSIZE + NS_RSQ_ALIGNMENT,
552 &card->rsq.dma, GFP_KERNEL);
553 if (card->rsq.org == NULL) {
554 printk("nicstar%d: can't allocate RSQ.\n", i);
555 error = 11;
556 ns_init_card_error(card, error);
557 return error;
558 }
559 card->rsq.base = PTR_ALIGN(card->rsq.org, NS_RSQ_ALIGNMENT);
560 card->rsq.next = card->rsq.base;
561 card->rsq.last = card->rsq.base + (NS_RSQ_NUM_ENTRIES - 1);
562 for (j = 0; j < NS_RSQ_NUM_ENTRIES; j++)
563 ns_rsqe_init(card->rsq.base + j);
564 writel(0x00000000, card->membase + RSQH);
565 writel(ALIGN(card->rsq.dma, NS_RSQ_ALIGNMENT), card->membase + RSQB);
566 PRINTK("nicstar%d: RSQ base at 0x%p.\n", i, card->rsq.base);
567
568 /* Initialize SCQ0, the only VBR SCQ used */
569 card->scq1 = NULL;
570 card->scq2 = NULL;
571 card->scq0 = get_scq(card, VBR_SCQSIZE, NS_VRSCD0);
572 if (card->scq0 == NULL) {
573 printk("nicstar%d: can't get SCQ0.\n", i);
574 error = 12;
575 ns_init_card_error(card, error);
576 return error;
577 }
578 u32d[0] = scq_virt_to_bus(card->scq0, card->scq0->base);
579 u32d[1] = (u32) 0x00000000;
580 u32d[2] = (u32) 0xffffffff;
581 u32d[3] = (u32) 0x00000000;
582 ns_write_sram(card, NS_VRSCD0, u32d, 4);
583 ns_write_sram(card, NS_VRSCD1, u32d, 4); /* These last two won't be used */
584 ns_write_sram(card, NS_VRSCD2, u32d, 4); /* but are initialized, just in case... */
585 card->scq0->scd = NS_VRSCD0;
586 PRINTK("nicstar%d: VBR-SCQ0 base at 0x%p.\n", i, card->scq0->base);
587
588 /* Initialize TSTs */
589 card->tst_addr = NS_TST0;
590 card->tst_free_entries = NS_TST_NUM_ENTRIES;
591 data = NS_TST_OPCODE_VARIABLE;
592 for (j = 0; j < NS_TST_NUM_ENTRIES; j++)
593 ns_write_sram(card, NS_TST0 + j, &data, 1);
594 data = ns_tste_make(NS_TST_OPCODE_END, NS_TST0);
595 ns_write_sram(card, NS_TST0 + NS_TST_NUM_ENTRIES, &data, 1);
596 for (j = 0; j < NS_TST_NUM_ENTRIES; j++)
597 ns_write_sram(card, NS_TST1 + j, &data, 1);
598 data = ns_tste_make(NS_TST_OPCODE_END, NS_TST1);
599 ns_write_sram(card, NS_TST1 + NS_TST_NUM_ENTRIES, &data, 1);
600 for (j = 0; j < NS_TST_NUM_ENTRIES; j++)
601 card->tste2vc[j] = NULL;
602 writel(NS_TST0 << 2, card->membase + TSTB);
603
604 /* Initialize RCT. AAL type is set on opening the VC. */
605 #ifdef RCQ_SUPPORT
606 u32d[0] = NS_RCTE_RAWCELLINTEN;
607 #else
608 u32d[0] = 0x00000000;
609 #endif /* RCQ_SUPPORT */
610 u32d[1] = 0x00000000;
611 u32d[2] = 0x00000000;
612 u32d[3] = 0xFFFFFFFF;
613 for (j = 0; j < card->rct_size; j++)
614 ns_write_sram(card, j * 4, u32d, 4);
615
616 memset(card->vcmap, 0, sizeof(card->vcmap));
617
618 for (j = 0; j < NS_FRSCD_NUM; j++)
619 card->scd2vc[j] = NULL;
620
621 /* Initialize buffer levels */
622 card->sbnr.min = MIN_SB;
623 card->sbnr.init = NUM_SB;
624 card->sbnr.max = MAX_SB;
625 card->lbnr.min = MIN_LB;
626 card->lbnr.init = NUM_LB;
627 card->lbnr.max = MAX_LB;
628 card->iovnr.min = MIN_IOVB;
629 card->iovnr.init = NUM_IOVB;
630 card->iovnr.max = MAX_IOVB;
631 card->hbnr.min = MIN_HB;
632 card->hbnr.init = NUM_HB;
633 card->hbnr.max = MAX_HB;
634
635 card->sm_handle = NULL;
636 card->sm_addr = 0x00000000;
637 card->lg_handle = NULL;
638 card->lg_addr = 0x00000000;
639
640 card->efbie = 1; /* To prevent push_rxbufs from enabling the interrupt */
641
642 idr_init(&card->idr);
643
644 /* Pre-allocate some huge buffers */
645 skb_queue_head_init(&card->hbpool.queue);
646 card->hbpool.count = 0;
647 for (j = 0; j < NUM_HB; j++) {
648 struct sk_buff *hb;
649 hb = __dev_alloc_skb(NS_HBUFSIZE, GFP_KERNEL);
650 if (hb == NULL) {
651 printk
652 ("nicstar%d: can't allocate %dth of %d huge buffers.\n",
653 i, j, NUM_HB);
654 error = 13;
655 ns_init_card_error(card, error);
656 return error;
657 }
658 NS_PRV_BUFTYPE(hb) = BUF_NONE;
659 skb_queue_tail(&card->hbpool.queue, hb);
660 card->hbpool.count++;
661 }
662
663 /* Allocate large buffers */
664 skb_queue_head_init(&card->lbpool.queue);
665 card->lbpool.count = 0; /* Not used */
666 for (j = 0; j < NUM_LB; j++) {
667 struct sk_buff *lb;
668 lb = __dev_alloc_skb(NS_LGSKBSIZE, GFP_KERNEL);
669 if (lb == NULL) {
670 printk
671 ("nicstar%d: can't allocate %dth of %d large buffers.\n",
672 i, j, NUM_LB);
673 error = 14;
674 ns_init_card_error(card, error);
675 return error;
676 }
677 NS_PRV_BUFTYPE(lb) = BUF_LG;
678 skb_queue_tail(&card->lbpool.queue, lb);
679 skb_reserve(lb, NS_SMBUFSIZE);
680 push_rxbufs(card, lb);
681 /* Due to the implementation of push_rxbufs() this is 1, not 0 */
682 if (j == 1) {
683 card->rcbuf = lb;
684 card->rawcell = (struct ns_rcqe *) lb->data;
685 card->rawch = NS_PRV_DMA(lb);
686 }
687 }
688 /* Test for strange behaviour which leads to crashes */
689 if ((bcount =
690 ns_stat_lfbqc_get(readl(card->membase + STAT))) < card->lbnr.min) {
691 printk
692 ("nicstar%d: Strange... Just allocated %d large buffers and lfbqc = %d.\n",
693 i, j, bcount);
694 error = 14;
695 ns_init_card_error(card, error);
696 return error;
697 }
698
699 /* Allocate small buffers */
700 skb_queue_head_init(&card->sbpool.queue);
701 card->sbpool.count = 0; /* Not used */
702 for (j = 0; j < NUM_SB; j++) {
703 struct sk_buff *sb;
704 sb = __dev_alloc_skb(NS_SMSKBSIZE, GFP_KERNEL);
705 if (sb == NULL) {
706 printk
707 ("nicstar%d: can't allocate %dth of %d small buffers.\n",
708 i, j, NUM_SB);
709 error = 15;
710 ns_init_card_error(card, error);
711 return error;
712 }
713 NS_PRV_BUFTYPE(sb) = BUF_SM;
714 skb_queue_tail(&card->sbpool.queue, sb);
715 skb_reserve(sb, NS_AAL0_HEADER);
716 push_rxbufs(card, sb);
717 }
718 /* Test for strange behaviour which leads to crashes */
719 if ((bcount =
720 ns_stat_sfbqc_get(readl(card->membase + STAT))) < card->sbnr.min) {
721 printk
722 ("nicstar%d: Strange... Just allocated %d small buffers and sfbqc = %d.\n",
723 i, j, bcount);
724 error = 15;
725 ns_init_card_error(card, error);
726 return error;
727 }
728
729 /* Allocate iovec buffers */
730 skb_queue_head_init(&card->iovpool.queue);
731 card->iovpool.count = 0;
732 for (j = 0; j < NUM_IOVB; j++) {
733 struct sk_buff *iovb;
734 iovb = alloc_skb(NS_IOVBUFSIZE, GFP_KERNEL);
735 if (iovb == NULL) {
736 printk
737 ("nicstar%d: can't allocate %dth of %d iovec buffers.\n",
738 i, j, NUM_IOVB);
739 error = 16;
740 ns_init_card_error(card, error);
741 return error;
742 }
743 NS_PRV_BUFTYPE(iovb) = BUF_NONE;
744 skb_queue_tail(&card->iovpool.queue, iovb);
745 card->iovpool.count++;
746 }
747
748 /* Configure NICStAR */
749 if (card->rct_size == 4096)
750 ns_cfg_rctsize = NS_CFG_RCTSIZE_4096_ENTRIES;
751 else /* (card->rct_size == 16384) */
752 ns_cfg_rctsize = NS_CFG_RCTSIZE_16384_ENTRIES;
753
754 card->efbie = 1;
755
756 card->intcnt = 0;
757 if (request_irq
758 (pcidev->irq, &ns_irq_handler, IRQF_SHARED, "nicstar", card) != 0) {
759 printk("nicstar%d: can't allocate IRQ %d.\n", i, pcidev->irq);
760 error = 9;
761 ns_init_card_error(card, error);
762 return error;
763 }
764
765 /* Register device */
766 card->atmdev = atm_dev_register("nicstar", &card->pcidev->dev, &atm_ops,
767 -1, NULL);
768 if (card->atmdev == NULL) {
769 printk("nicstar%d: can't register device.\n", i);
770 error = 17;
771 ns_init_card_error(card, error);
772 return error;
773 }
774
775 if (mac[i] == NULL || !mac_pton(mac[i], card->atmdev->esi)) {
776 nicstar_read_eprom(card->membase, NICSTAR_EPROM_MAC_ADDR_OFFSET,
777 card->atmdev->esi, 6);
778 if (ether_addr_equal(card->atmdev->esi, "\x00\x00\x00\x00\x00\x00")) {
779 nicstar_read_eprom(card->membase,
780 NICSTAR_EPROM_MAC_ADDR_OFFSET_ALT,
781 card->atmdev->esi, 6);
782 }
783 }
784
785 printk("nicstar%d: MAC address %pM\n", i, card->atmdev->esi);
786
787 card->atmdev->dev_data = card;
788 card->atmdev->ci_range.vpi_bits = card->vpibits;
789 card->atmdev->ci_range.vci_bits = card->vcibits;
790 card->atmdev->link_rate = card->max_pcr;
791 card->atmdev->phy = NULL;
792
793 #ifdef CONFIG_ATM_NICSTAR_USE_SUNI
794 if (card->max_pcr == ATM_OC3_PCR)
795 suni_init(card->atmdev);
796 #endif /* CONFIG_ATM_NICSTAR_USE_SUNI */
797
798 #ifdef CONFIG_ATM_NICSTAR_USE_IDT77105
799 if (card->max_pcr == ATM_25_PCR)
800 idt77105_init(card->atmdev);
801 #endif /* CONFIG_ATM_NICSTAR_USE_IDT77105 */
802
803 if (card->atmdev->phy && card->atmdev->phy->start)
804 card->atmdev->phy->start(card->atmdev);
805
806 writel(NS_CFG_RXPATH | NS_CFG_SMBUFSIZE | NS_CFG_LGBUFSIZE | NS_CFG_EFBIE | NS_CFG_RSQSIZE | NS_CFG_VPIBITS | ns_cfg_rctsize | NS_CFG_RXINT_NODELAY | NS_CFG_RAWIE | /* Only enabled if RCQ_SUPPORT */
807 NS_CFG_RSQAFIE | NS_CFG_TXEN | NS_CFG_TXIE | NS_CFG_TSQFIE_OPT | /* Only enabled if ENABLE_TSQFIE */
808 NS_CFG_PHYIE, card->membase + CFG);
809
810 num_cards++;
811
812 return error;
813 }
814
815 static void ns_init_card_error(ns_dev *card, int error)
816 {
817 if (error >= 17) {
818 writel(0x00000000, card->membase + CFG);
819 }
820 if (error >= 16) {
821 struct sk_buff *iovb;
822 while ((iovb = skb_dequeue(&card->iovpool.queue)) != NULL)
823 dev_kfree_skb_any(iovb);
824 }
825 if (error >= 15) {
826 struct sk_buff *sb;
827 while ((sb = skb_dequeue(&card->sbpool.queue)) != NULL)
828 dev_kfree_skb_any(sb);
829 free_scq(card, card->scq0, NULL);
830 }
831 if (error >= 14) {
832 struct sk_buff *lb;
833 while ((lb = skb_dequeue(&card->lbpool.queue)) != NULL)
834 dev_kfree_skb_any(lb);
835 }
836 if (error >= 13) {
837 struct sk_buff *hb;
838 while ((hb = skb_dequeue(&card->hbpool.queue)) != NULL)
839 dev_kfree_skb_any(hb);
840 }
841 if (error >= 12) {
842 kfree(card->rsq.org);
843 }
844 if (error >= 11) {
845 kfree(card->tsq.org);
846 }
847 if (error >= 10) {
848 free_irq(card->pcidev->irq, card);
849 }
850 if (error >= 4) {
851 iounmap(card->membase);
852 }
853 if (error >= 3) {
854 pci_disable_device(card->pcidev);
855 kfree(card);
856 }
857 }
858
859 static scq_info *get_scq(ns_dev *card, int size, u32 scd)
860 {
861 scq_info *scq;
862 int i;
863
864 if (size != VBR_SCQSIZE && size != CBR_SCQSIZE)
865 return NULL;
866
867 scq = kmalloc(sizeof(*scq), GFP_KERNEL);
868 if (!scq)
869 return NULL;
870 scq->org = dma_alloc_coherent(&card->pcidev->dev,
871 2 * size, &scq->dma, GFP_KERNEL);
872 if (!scq->org) {
873 kfree(scq);
874 return NULL;
875 }
876 scq->skb = kmalloc_array(size / NS_SCQE_SIZE,
877 sizeof(*scq->skb),
878 GFP_KERNEL);
879 if (!scq->skb) {
880 dma_free_coherent(&card->pcidev->dev,
881 2 * size, scq->org, scq->dma);
882 kfree(scq);
883 return NULL;
884 }
885 scq->num_entries = size / NS_SCQE_SIZE;
886 scq->base = PTR_ALIGN(scq->org, size);
887 scq->next = scq->base;
888 scq->last = scq->base + (scq->num_entries - 1);
889 scq->tail = scq->last;
890 scq->scd = scd;
891 scq->num_entries = size / NS_SCQE_SIZE;
892 scq->tbd_count = 0;
893 init_waitqueue_head(&scq->scqfull_waitq);
894 scq->full = 0;
895 spin_lock_init(&scq->lock);
896
897 for (i = 0; i < scq->num_entries; i++)
898 scq->skb[i] = NULL;
899
900 return scq;
901 }
902
903 /* For variable rate SCQ vcc must be NULL */
904 static void free_scq(ns_dev *card, scq_info *scq, struct atm_vcc *vcc)
905 {
906 int i;
907
908 if (scq->num_entries == VBR_SCQ_NUM_ENTRIES)
909 for (i = 0; i < scq->num_entries; i++) {
910 if (scq->skb[i] != NULL) {
911 vcc = ATM_SKB(scq->skb[i])->vcc;
912 if (vcc->pop != NULL)
913 vcc->pop(vcc, scq->skb[i]);
914 else
915 dev_kfree_skb_any(scq->skb[i]);
916 }
917 } else { /* vcc must be != NULL */
918
919 if (vcc == NULL) {
920 printk
921 ("nicstar: free_scq() called with vcc == NULL for fixed rate scq.");
922 for (i = 0; i < scq->num_entries; i++)
923 dev_kfree_skb_any(scq->skb[i]);
924 } else
925 for (i = 0; i < scq->num_entries; i++) {
926 if (scq->skb[i] != NULL) {
927 if (vcc->pop != NULL)
928 vcc->pop(vcc, scq->skb[i]);
929 else
930 dev_kfree_skb_any(scq->skb[i]);
931 }
932 }
933 }
934 kfree(scq->skb);
935 dma_free_coherent(&card->pcidev->dev,
936 2 * (scq->num_entries == VBR_SCQ_NUM_ENTRIES ?
937 VBR_SCQSIZE : CBR_SCQSIZE),
938 scq->org, scq->dma);
939 kfree(scq);
940 }
941
942 /* The handles passed must be pointers to the sk_buff containing the small
943 or large buffer(s) cast to u32. */
944 static void push_rxbufs(ns_dev * card, struct sk_buff *skb)
945 {
946 struct sk_buff *handle1, *handle2;
947 int id1, id2;
948 u32 addr1, addr2;
949 u32 stat;
950 unsigned long flags;
951
952 /* *BARF* */
953 handle2 = NULL;
954 addr2 = 0;
955 handle1 = skb;
956 addr1 = dma_map_single(&card->pcidev->dev,
957 skb->data,
958 (NS_PRV_BUFTYPE(skb) == BUF_SM
959 ? NS_SMSKBSIZE : NS_LGSKBSIZE),
960 DMA_TO_DEVICE);
961 NS_PRV_DMA(skb) = addr1; /* save so we can unmap later */
962
963 #ifdef GENERAL_DEBUG
964 if (!addr1)
965 printk("nicstar%d: push_rxbufs called with addr1 = 0.\n",
966 card->index);
967 #endif /* GENERAL_DEBUG */
968
969 stat = readl(card->membase + STAT);
970 card->sbfqc = ns_stat_sfbqc_get(stat);
971 card->lbfqc = ns_stat_lfbqc_get(stat);
972 if (NS_PRV_BUFTYPE(skb) == BUF_SM) {
973 if (!addr2) {
974 if (card->sm_addr) {
975 addr2 = card->sm_addr;
976 handle2 = card->sm_handle;
977 card->sm_addr = 0x00000000;
978 card->sm_handle = NULL;
979 } else { /* (!sm_addr) */
980
981 card->sm_addr = addr1;
982 card->sm_handle = handle1;
983 }
984 }
985 } else { /* buf_type == BUF_LG */
986
987 if (!addr2) {
988 if (card->lg_addr) {
989 addr2 = card->lg_addr;
990 handle2 = card->lg_handle;
991 card->lg_addr = 0x00000000;
992 card->lg_handle = NULL;
993 } else { /* (!lg_addr) */
994
995 card->lg_addr = addr1;
996 card->lg_handle = handle1;
997 }
998 }
999 }
1000
1001 if (addr2) {
1002 if (NS_PRV_BUFTYPE(skb) == BUF_SM) {
1003 if (card->sbfqc >= card->sbnr.max) {
1004 skb_unlink(handle1, &card->sbpool.queue);
1005 dev_kfree_skb_any(handle1);
1006 skb_unlink(handle2, &card->sbpool.queue);
1007 dev_kfree_skb_any(handle2);
1008 return;
1009 } else
1010 card->sbfqc += 2;
1011 } else { /* (buf_type == BUF_LG) */
1012
1013 if (card->lbfqc >= card->lbnr.max) {
1014 skb_unlink(handle1, &card->lbpool.queue);
1015 dev_kfree_skb_any(handle1);
1016 skb_unlink(handle2, &card->lbpool.queue);
1017 dev_kfree_skb_any(handle2);
1018 return;
1019 } else
1020 card->lbfqc += 2;
1021 }
1022
1023 id1 = idr_alloc(&card->idr, handle1, 0, 0, GFP_ATOMIC);
1024 if (id1 < 0)
1025 goto out;
1026
1027 id2 = idr_alloc(&card->idr, handle2, 0, 0, GFP_ATOMIC);
1028 if (id2 < 0)
1029 goto out;
1030
1031 spin_lock_irqsave(&card->res_lock, flags);
1032 while (CMD_BUSY(card)) ;
1033 writel(addr2, card->membase + DR3);
1034 writel(id2, card->membase + DR2);
1035 writel(addr1, card->membase + DR1);
1036 writel(id1, card->membase + DR0);
1037 writel(NS_CMD_WRITE_FREEBUFQ | NS_PRV_BUFTYPE(skb),
1038 card->membase + CMD);
1039 spin_unlock_irqrestore(&card->res_lock, flags);
1040
1041 XPRINTK("nicstar%d: Pushing %s buffers at 0x%x and 0x%x.\n",
1042 card->index,
1043 (NS_PRV_BUFTYPE(skb) == BUF_SM ? "small" : "large"),
1044 addr1, addr2);
1045 }
1046
1047 if (!card->efbie && card->sbfqc >= card->sbnr.min &&
1048 card->lbfqc >= card->lbnr.min) {
1049 card->efbie = 1;
1050 writel((readl(card->membase + CFG) | NS_CFG_EFBIE),
1051 card->membase + CFG);
1052 }
1053
1054 out:
1055 return;
1056 }
1057
1058 static irqreturn_t ns_irq_handler(int irq, void *dev_id)
1059 {
1060 u32 stat_r;
1061 ns_dev *card;
1062 struct atm_dev *dev;
1063 unsigned long flags;
1064
1065 card = (ns_dev *) dev_id;
1066 dev = card->atmdev;
1067 card->intcnt++;
1068
1069 PRINTK("nicstar%d: NICStAR generated an interrupt\n", card->index);
1070
1071 spin_lock_irqsave(&card->int_lock, flags);
1072
1073 stat_r = readl(card->membase + STAT);
1074
1075 /* Transmit Status Indicator has been written to T. S. Queue */
1076 if (stat_r & NS_STAT_TSIF) {
1077 TXPRINTK("nicstar%d: TSI interrupt\n", card->index);
1078 process_tsq(card);
1079 writel(NS_STAT_TSIF, card->membase + STAT);
1080 }
1081
1082 /* Incomplete CS-PDU has been transmitted */
1083 if (stat_r & NS_STAT_TXICP) {
1084 writel(NS_STAT_TXICP, card->membase + STAT);
1085 TXPRINTK("nicstar%d: Incomplete CS-PDU transmitted.\n",
1086 card->index);
1087 }
1088
1089 /* Transmit Status Queue 7/8 full */
1090 if (stat_r & NS_STAT_TSQF) {
1091 writel(NS_STAT_TSQF, card->membase + STAT);
1092 PRINTK("nicstar%d: TSQ full.\n", card->index);
1093 process_tsq(card);
1094 }
1095
1096 /* Timer overflow */
1097 if (stat_r & NS_STAT_TMROF) {
1098 writel(NS_STAT_TMROF, card->membase + STAT);
1099 PRINTK("nicstar%d: Timer overflow.\n", card->index);
1100 }
1101
1102 /* PHY device interrupt signal active */
1103 if (stat_r & NS_STAT_PHYI) {
1104 writel(NS_STAT_PHYI, card->membase + STAT);
1105 PRINTK("nicstar%d: PHY interrupt.\n", card->index);
1106 if (dev->phy && dev->phy->interrupt) {
1107 dev->phy->interrupt(dev);
1108 }
1109 }
1110
1111 /* Small Buffer Queue is full */
1112 if (stat_r & NS_STAT_SFBQF) {
1113 writel(NS_STAT_SFBQF, card->membase + STAT);
1114 printk("nicstar%d: Small free buffer queue is full.\n",
1115 card->index);
1116 }
1117
1118 /* Large Buffer Queue is full */
1119 if (stat_r & NS_STAT_LFBQF) {
1120 writel(NS_STAT_LFBQF, card->membase + STAT);
1121 printk("nicstar%d: Large free buffer queue is full.\n",
1122 card->index);
1123 }
1124
1125 /* Receive Status Queue is full */
1126 if (stat_r & NS_STAT_RSQF) {
1127 writel(NS_STAT_RSQF, card->membase + STAT);
1128 printk("nicstar%d: RSQ full.\n", card->index);
1129 process_rsq(card);
1130 }
1131
1132 /* Complete CS-PDU received */
1133 if (stat_r & NS_STAT_EOPDU) {
1134 RXPRINTK("nicstar%d: End of CS-PDU received.\n", card->index);
1135 process_rsq(card);
1136 writel(NS_STAT_EOPDU, card->membase + STAT);
1137 }
1138
1139 /* Raw cell received */
1140 if (stat_r & NS_STAT_RAWCF) {
1141 writel(NS_STAT_RAWCF, card->membase + STAT);
1142 #ifndef RCQ_SUPPORT
1143 printk("nicstar%d: Raw cell received and no support yet...\n",
1144 card->index);
1145 #endif /* RCQ_SUPPORT */
1146 /* NOTE: the following procedure may keep a raw cell pending until the
1147 next interrupt. As this preliminary support is only meant to
1148 avoid buffer leakage, this is not an issue. */
1149 while (readl(card->membase + RAWCT) != card->rawch) {
1150
1151 if (ns_rcqe_islast(card->rawcell)) {
1152 struct sk_buff *oldbuf;
1153
1154 oldbuf = card->rcbuf;
1155 card->rcbuf = idr_find(&card->idr,
1156 ns_rcqe_nextbufhandle(card->rawcell));
1157 card->rawch = NS_PRV_DMA(card->rcbuf);
1158 card->rawcell = (struct ns_rcqe *)
1159 card->rcbuf->data;
1160 recycle_rx_buf(card, oldbuf);
1161 } else {
1162 card->rawch += NS_RCQE_SIZE;
1163 card->rawcell++;
1164 }
1165 }
1166 }
1167
1168 /* Small buffer queue is empty */
1169 if (stat_r & NS_STAT_SFBQE) {
1170 int i;
1171 struct sk_buff *sb;
1172
1173 writel(NS_STAT_SFBQE, card->membase + STAT);
1174 printk("nicstar%d: Small free buffer queue empty.\n",
1175 card->index);
1176 for (i = 0; i < card->sbnr.min; i++) {
1177 sb = dev_alloc_skb(NS_SMSKBSIZE);
1178 if (sb == NULL) {
1179 writel(readl(card->membase + CFG) &
1180 ~NS_CFG_EFBIE, card->membase + CFG);
1181 card->efbie = 0;
1182 break;
1183 }
1184 NS_PRV_BUFTYPE(sb) = BUF_SM;
1185 skb_queue_tail(&card->sbpool.queue, sb);
1186 skb_reserve(sb, NS_AAL0_HEADER);
1187 push_rxbufs(card, sb);
1188 }
1189 card->sbfqc = i;
1190 process_rsq(card);
1191 }
1192
1193 /* Large buffer queue empty */
1194 if (stat_r & NS_STAT_LFBQE) {
1195 int i;
1196 struct sk_buff *lb;
1197
1198 writel(NS_STAT_LFBQE, card->membase + STAT);
1199 printk("nicstar%d: Large free buffer queue empty.\n",
1200 card->index);
1201 for (i = 0; i < card->lbnr.min; i++) {
1202 lb = dev_alloc_skb(NS_LGSKBSIZE);
1203 if (lb == NULL) {
1204 writel(readl(card->membase + CFG) &
1205 ~NS_CFG_EFBIE, card->membase + CFG);
1206 card->efbie = 0;
1207 break;
1208 }
1209 NS_PRV_BUFTYPE(lb) = BUF_LG;
1210 skb_queue_tail(&card->lbpool.queue, lb);
1211 skb_reserve(lb, NS_SMBUFSIZE);
1212 push_rxbufs(card, lb);
1213 }
1214 card->lbfqc = i;
1215 process_rsq(card);
1216 }
1217
1218 /* Receive Status Queue is 7/8 full */
1219 if (stat_r & NS_STAT_RSQAF) {
1220 writel(NS_STAT_RSQAF, card->membase + STAT);
1221 RXPRINTK("nicstar%d: RSQ almost full.\n", card->index);
1222 process_rsq(card);
1223 }
1224
1225 spin_unlock_irqrestore(&card->int_lock, flags);
1226 PRINTK("nicstar%d: end of interrupt service\n", card->index);
1227 return IRQ_HANDLED;
1228 }
1229
1230 static int ns_open(struct atm_vcc *vcc)
1231 {
1232 ns_dev *card;
1233 vc_map *vc;
1234 unsigned long tmpl, modl;
1235 int tcr, tcra; /* target cell rate, and absolute value */
1236 int n = 0; /* Number of entries in the TST. Initialized to remove
1237 the compiler warning. */
1238 u32 u32d[4];
1239 int frscdi = 0; /* Index of the SCD. Initialized to remove the compiler
1240 warning. How I wish compilers were clever enough to
1241 tell which variables can truly be used
1242 uninitialized... */
1243 int inuse; /* tx or rx vc already in use by another vcc */
1244 short vpi = vcc->vpi;
1245 int vci = vcc->vci;
1246
1247 card = (ns_dev *) vcc->dev->dev_data;
1248 PRINTK("nicstar%d: opening vpi.vci %d.%d \n", card->index, (int)vpi,
1249 vci);
1250 if (vcc->qos.aal != ATM_AAL5 && vcc->qos.aal != ATM_AAL0) {
1251 PRINTK("nicstar%d: unsupported AAL.\n", card->index);
1252 return -EINVAL;
1253 }
1254
1255 vc = &(card->vcmap[vpi << card->vcibits | vci]);
1256 vcc->dev_data = vc;
1257
1258 inuse = 0;
1259 if (vcc->qos.txtp.traffic_class != ATM_NONE && vc->tx)
1260 inuse = 1;
1261 if (vcc->qos.rxtp.traffic_class != ATM_NONE && vc->rx)
1262 inuse += 2;
1263 if (inuse) {
1264 printk("nicstar%d: %s vci already in use.\n", card->index,
1265 inuse == 1 ? "tx" : inuse == 2 ? "rx" : "tx and rx");
1266 return -EINVAL;
1267 }
1268
1269 set_bit(ATM_VF_ADDR, &vcc->flags);
1270
1271 /* NOTE: You are not allowed to modify an open connection's QOS. To change
1272 that, remove the ATM_VF_PARTIAL flag checking. There may be other changes
1273 needed to do that. */
1274 if (!test_bit(ATM_VF_PARTIAL, &vcc->flags)) {
1275 scq_info *scq;
1276
1277 set_bit(ATM_VF_PARTIAL, &vcc->flags);
1278 if (vcc->qos.txtp.traffic_class == ATM_CBR) {
1279 /* Check requested cell rate and availability of SCD */
1280 if (vcc->qos.txtp.max_pcr == 0 && vcc->qos.txtp.pcr == 0
1281 && vcc->qos.txtp.min_pcr == 0) {
1282 PRINTK
1283 ("nicstar%d: trying to open a CBR vc with cell rate = 0 \n",
1284 card->index);
1285 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1286 clear_bit(ATM_VF_ADDR, &vcc->flags);
1287 return -EINVAL;
1288 }
1289
1290 tcr = atm_pcr_goal(&(vcc->qos.txtp));
1291 tcra = tcr >= 0 ? tcr : -tcr;
1292
1293 PRINTK("nicstar%d: target cell rate = %d.\n",
1294 card->index, vcc->qos.txtp.max_pcr);
1295
1296 tmpl =
1297 (unsigned long)tcra *(unsigned long)
1298 NS_TST_NUM_ENTRIES;
1299 modl = tmpl % card->max_pcr;
1300
1301 n = (int)(tmpl / card->max_pcr);
1302 if (tcr > 0) {
1303 if (modl > 0)
1304 n++;
1305 } else if (tcr == 0) {
1306 if ((n =
1307 (card->tst_free_entries -
1308 NS_TST_RESERVED)) <= 0) {
1309 PRINTK
1310 ("nicstar%d: no CBR bandwidth free.\n",
1311 card->index);
1312 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1313 clear_bit(ATM_VF_ADDR, &vcc->flags);
1314 return -EINVAL;
1315 }
1316 }
1317
1318 if (n == 0) {
1319 printk
1320 ("nicstar%d: selected bandwidth < granularity.\n",
1321 card->index);
1322 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1323 clear_bit(ATM_VF_ADDR, &vcc->flags);
1324 return -EINVAL;
1325 }
1326
1327 if (n > (card->tst_free_entries - NS_TST_RESERVED)) {
1328 PRINTK
1329 ("nicstar%d: not enough free CBR bandwidth.\n",
1330 card->index);
1331 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1332 clear_bit(ATM_VF_ADDR, &vcc->flags);
1333 return -EINVAL;
1334 } else
1335 card->tst_free_entries -= n;
1336
1337 XPRINTK("nicstar%d: writing %d tst entries.\n",
1338 card->index, n);
1339 for (frscdi = 0; frscdi < NS_FRSCD_NUM; frscdi++) {
1340 if (card->scd2vc[frscdi] == NULL) {
1341 card->scd2vc[frscdi] = vc;
1342 break;
1343 }
1344 }
1345 if (frscdi == NS_FRSCD_NUM) {
1346 PRINTK
1347 ("nicstar%d: no SCD available for CBR channel.\n",
1348 card->index);
1349 card->tst_free_entries += n;
1350 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1351 clear_bit(ATM_VF_ADDR, &vcc->flags);
1352 return -EBUSY;
1353 }
1354
1355 vc->cbr_scd = NS_FRSCD + frscdi * NS_FRSCD_SIZE;
1356
1357 scq = get_scq(card, CBR_SCQSIZE, vc->cbr_scd);
1358 if (scq == NULL) {
1359 PRINTK("nicstar%d: can't get fixed rate SCQ.\n",
1360 card->index);
1361 card->scd2vc[frscdi] = NULL;
1362 card->tst_free_entries += n;
1363 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1364 clear_bit(ATM_VF_ADDR, &vcc->flags);
1365 return -ENOMEM;
1366 }
1367 vc->scq = scq;
1368 u32d[0] = scq_virt_to_bus(scq, scq->base);
1369 u32d[1] = (u32) 0x00000000;
1370 u32d[2] = (u32) 0xffffffff;
1371 u32d[3] = (u32) 0x00000000;
1372 ns_write_sram(card, vc->cbr_scd, u32d, 4);
1373
1374 fill_tst(card, n, vc);
1375 } else if (vcc->qos.txtp.traffic_class == ATM_UBR) {
1376 vc->cbr_scd = 0x00000000;
1377 vc->scq = card->scq0;
1378 }
1379
1380 if (vcc->qos.txtp.traffic_class != ATM_NONE) {
1381 vc->tx = 1;
1382 vc->tx_vcc = vcc;
1383 vc->tbd_count = 0;
1384 }
1385 if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
1386 u32 status;
1387
1388 vc->rx = 1;
1389 vc->rx_vcc = vcc;
1390 vc->rx_iov = NULL;
1391
1392 /* Open the connection in hardware */
1393 if (vcc->qos.aal == ATM_AAL5)
1394 status = NS_RCTE_AAL5 | NS_RCTE_CONNECTOPEN;
1395 else /* vcc->qos.aal == ATM_AAL0 */
1396 status = NS_RCTE_AAL0 | NS_RCTE_CONNECTOPEN;
1397 #ifdef RCQ_SUPPORT
1398 status |= NS_RCTE_RAWCELLINTEN;
1399 #endif /* RCQ_SUPPORT */
1400 ns_write_sram(card,
1401 NS_RCT +
1402 (vpi << card->vcibits | vci) *
1403 NS_RCT_ENTRY_SIZE, &status, 1);
1404 }
1405
1406 }
1407
1408 set_bit(ATM_VF_READY, &vcc->flags);
1409 return 0;
1410 }
1411
1412 static void ns_close(struct atm_vcc *vcc)
1413 {
1414 vc_map *vc;
1415 ns_dev *card;
1416 u32 data;
1417 int i;
1418
1419 vc = vcc->dev_data;
1420 card = vcc->dev->dev_data;
1421 PRINTK("nicstar%d: closing vpi.vci %d.%d \n", card->index,
1422 (int)vcc->vpi, vcc->vci);
1423
1424 clear_bit(ATM_VF_READY, &vcc->flags);
1425
1426 if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
1427 u32 addr;
1428 unsigned long flags;
1429
1430 addr =
1431 NS_RCT +
1432 (vcc->vpi << card->vcibits | vcc->vci) * NS_RCT_ENTRY_SIZE;
1433 spin_lock_irqsave(&card->res_lock, flags);
1434 while (CMD_BUSY(card)) ;
1435 writel(NS_CMD_CLOSE_CONNECTION | addr << 2,
1436 card->membase + CMD);
1437 spin_unlock_irqrestore(&card->res_lock, flags);
1438
1439 vc->rx = 0;
1440 if (vc->rx_iov != NULL) {
1441 struct sk_buff *iovb;
1442 u32 stat;
1443
1444 stat = readl(card->membase + STAT);
1445 card->sbfqc = ns_stat_sfbqc_get(stat);
1446 card->lbfqc = ns_stat_lfbqc_get(stat);
1447
1448 PRINTK
1449 ("nicstar%d: closing a VC with pending rx buffers.\n",
1450 card->index);
1451 iovb = vc->rx_iov;
1452 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
1453 NS_PRV_IOVCNT(iovb));
1454 NS_PRV_IOVCNT(iovb) = 0;
1455 spin_lock_irqsave(&card->int_lock, flags);
1456 recycle_iov_buf(card, iovb);
1457 spin_unlock_irqrestore(&card->int_lock, flags);
1458 vc->rx_iov = NULL;
1459 }
1460 }
1461
1462 if (vcc->qos.txtp.traffic_class != ATM_NONE) {
1463 vc->tx = 0;
1464 }
1465
1466 if (vcc->qos.txtp.traffic_class == ATM_CBR) {
1467 unsigned long flags;
1468 ns_scqe *scqep;
1469 scq_info *scq;
1470
1471 scq = vc->scq;
1472
1473 for (;;) {
1474 spin_lock_irqsave(&scq->lock, flags);
1475 scqep = scq->next;
1476 if (scqep == scq->base)
1477 scqep = scq->last;
1478 else
1479 scqep--;
1480 if (scqep == scq->tail) {
1481 spin_unlock_irqrestore(&scq->lock, flags);
1482 break;
1483 }
1484 /* If the last entry is not a TSR, place one in the SCQ in order to
1485 be able to completely drain it and then close. */
1486 if (!ns_scqe_is_tsr(scqep) && scq->tail != scq->next) {
1487 ns_scqe tsr;
1488 u32 scdi, scqi;
1489 u32 data;
1490 int index;
1491
1492 tsr.word_1 = ns_tsr_mkword_1(NS_TSR_INTENABLE);
1493 scdi = (vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE;
1494 scqi = scq->next - scq->base;
1495 tsr.word_2 = ns_tsr_mkword_2(scdi, scqi);
1496 tsr.word_3 = 0x00000000;
1497 tsr.word_4 = 0x00000000;
1498 *scq->next = tsr;
1499 index = (int)scqi;
1500 scq->skb[index] = NULL;
1501 if (scq->next == scq->last)
1502 scq->next = scq->base;
1503 else
1504 scq->next++;
1505 data = scq_virt_to_bus(scq, scq->next);
1506 ns_write_sram(card, scq->scd, &data, 1);
1507 }
1508 spin_unlock_irqrestore(&scq->lock, flags);
1509 schedule();
1510 }
1511
1512 /* Free all TST entries */
1513 data = NS_TST_OPCODE_VARIABLE;
1514 for (i = 0; i < NS_TST_NUM_ENTRIES; i++) {
1515 if (card->tste2vc[i] == vc) {
1516 ns_write_sram(card, card->tst_addr + i, &data,
1517 1);
1518 card->tste2vc[i] = NULL;
1519 card->tst_free_entries++;
1520 }
1521 }
1522
1523 card->scd2vc[(vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE] = NULL;
1524 free_scq(card, vc->scq, vcc);
1525 }
1526
1527 /* remove all references to vcc before deleting it */
1528 if (vcc->qos.txtp.traffic_class != ATM_NONE) {
1529 unsigned long flags;
1530 scq_info *scq = card->scq0;
1531
1532 spin_lock_irqsave(&scq->lock, flags);
1533
1534 for (i = 0; i < scq->num_entries; i++) {
1535 if (scq->skb[i] && ATM_SKB(scq->skb[i])->vcc == vcc) {
1536 ATM_SKB(scq->skb[i])->vcc = NULL;
1537 atm_return(vcc, scq->skb[i]->truesize);
1538 PRINTK
1539 ("nicstar: deleted pending vcc mapping\n");
1540 }
1541 }
1542
1543 spin_unlock_irqrestore(&scq->lock, flags);
1544 }
1545
1546 vcc->dev_data = NULL;
1547 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1548 clear_bit(ATM_VF_ADDR, &vcc->flags);
1549
1550 #ifdef RX_DEBUG
1551 {
1552 u32 stat, cfg;
1553 stat = readl(card->membase + STAT);
1554 cfg = readl(card->membase + CFG);
1555 printk("STAT = 0x%08X CFG = 0x%08X \n", stat, cfg);
1556 printk
1557 ("TSQ: base = 0x%p next = 0x%p last = 0x%p TSQT = 0x%08X \n",
1558 card->tsq.base, card->tsq.next,
1559 card->tsq.last, readl(card->membase + TSQT));
1560 printk
1561 ("RSQ: base = 0x%p next = 0x%p last = 0x%p RSQT = 0x%08X \n",
1562 card->rsq.base, card->rsq.next,
1563 card->rsq.last, readl(card->membase + RSQT));
1564 printk("Empty free buffer queue interrupt %s \n",
1565 card->efbie ? "enabled" : "disabled");
1566 printk("SBCNT = %d count = %d LBCNT = %d count = %d \n",
1567 ns_stat_sfbqc_get(stat), card->sbpool.count,
1568 ns_stat_lfbqc_get(stat), card->lbpool.count);
1569 printk("hbpool.count = %d iovpool.count = %d \n",
1570 card->hbpool.count, card->iovpool.count);
1571 }
1572 #endif /* RX_DEBUG */
1573 }
1574
1575 static void fill_tst(ns_dev * card, int n, vc_map * vc)
1576 {
1577 u32 new_tst;
1578 unsigned long cl;
1579 int e, r;
1580 u32 data;
1581
1582 /* It would be very complicated to keep the two TSTs synchronized while
1583 assuring that writes are only made to the inactive TST. So, for now I
1584 will use only one TST. If problems occur, I will change this again */
1585
1586 new_tst = card->tst_addr;
1587
1588 /* Fill procedure */
1589
1590 for (e = 0; e < NS_TST_NUM_ENTRIES; e++) {
1591 if (card->tste2vc[e] == NULL)
1592 break;
1593 }
1594 if (e == NS_TST_NUM_ENTRIES) {
1595 printk("nicstar%d: No free TST entries found. \n", card->index);
1596 return;
1597 }
1598
1599 r = n;
1600 cl = NS_TST_NUM_ENTRIES;
1601 data = ns_tste_make(NS_TST_OPCODE_FIXED, vc->cbr_scd);
1602
1603 while (r > 0) {
1604 if (cl >= NS_TST_NUM_ENTRIES && card->tste2vc[e] == NULL) {
1605 card->tste2vc[e] = vc;
1606 ns_write_sram(card, new_tst + e, &data, 1);
1607 cl -= NS_TST_NUM_ENTRIES;
1608 r--;
1609 }
1610
1611 if (++e == NS_TST_NUM_ENTRIES) {
1612 e = 0;
1613 }
1614 cl += n;
1615 }
1616
1617 /* End of fill procedure */
1618
1619 data = ns_tste_make(NS_TST_OPCODE_END, new_tst);
1620 ns_write_sram(card, new_tst + NS_TST_NUM_ENTRIES, &data, 1);
1621 ns_write_sram(card, card->tst_addr + NS_TST_NUM_ENTRIES, &data, 1);
1622 card->tst_addr = new_tst;
1623 }
1624
1625 static int _ns_send(struct atm_vcc *vcc, struct sk_buff *skb, bool may_sleep)
1626 {
1627 ns_dev *card;
1628 vc_map *vc;
1629 scq_info *scq;
1630 unsigned long buflen;
1631 ns_scqe scqe;
1632 u32 flags; /* TBD flags, not CPU flags */
1633
1634 card = vcc->dev->dev_data;
1635 TXPRINTK("nicstar%d: ns_send() called.\n", card->index);
1636 if ((vc = (vc_map *) vcc->dev_data) == NULL) {
1637 printk("nicstar%d: vcc->dev_data == NULL on ns_send().\n",
1638 card->index);
1639 atomic_inc(&vcc->stats->tx_err);
1640 dev_kfree_skb_any(skb);
1641 return -EINVAL;
1642 }
1643
1644 if (!vc->tx) {
1645 printk("nicstar%d: Trying to transmit on a non-tx VC.\n",
1646 card->index);
1647 atomic_inc(&vcc->stats->tx_err);
1648 dev_kfree_skb_any(skb);
1649 return -EINVAL;
1650 }
1651
1652 if (vcc->qos.aal != ATM_AAL5 && vcc->qos.aal != ATM_AAL0) {
1653 printk("nicstar%d: Only AAL0 and AAL5 are supported.\n",
1654 card->index);
1655 atomic_inc(&vcc->stats->tx_err);
1656 dev_kfree_skb_any(skb);
1657 return -EINVAL;
1658 }
1659
1660 if (skb_shinfo(skb)->nr_frags != 0) {
1661 printk("nicstar%d: No scatter-gather yet.\n", card->index);
1662 atomic_inc(&vcc->stats->tx_err);
1663 dev_kfree_skb_any(skb);
1664 return -EINVAL;
1665 }
1666
1667 ATM_SKB(skb)->vcc = vcc;
1668
1669 NS_PRV_DMA(skb) = dma_map_single(&card->pcidev->dev, skb->data,
1670 skb->len, DMA_TO_DEVICE);
1671
1672 if (vcc->qos.aal == ATM_AAL5) {
1673 buflen = (skb->len + 47 + 8) / 48 * 48; /* Multiple of 48 */
1674 flags = NS_TBD_AAL5;
1675 scqe.word_2 = cpu_to_le32(NS_PRV_DMA(skb));
1676 scqe.word_3 = cpu_to_le32(skb->len);
1677 scqe.word_4 =
1678 ns_tbd_mkword_4(0, (u32) vcc->vpi, (u32) vcc->vci, 0,
1679 ATM_SKB(skb)->
1680 atm_options & ATM_ATMOPT_CLP ? 1 : 0);
1681 flags |= NS_TBD_EOPDU;
1682 } else { /* (vcc->qos.aal == ATM_AAL0) */
1683
1684 buflen = ATM_CELL_PAYLOAD; /* i.e., 48 bytes */
1685 flags = NS_TBD_AAL0;
1686 scqe.word_2 = cpu_to_le32(NS_PRV_DMA(skb) + NS_AAL0_HEADER);
1687 scqe.word_3 = cpu_to_le32(0x00000000);
1688 if (*skb->data & 0x02) /* Payload type 1 - end of pdu */
1689 flags |= NS_TBD_EOPDU;
1690 scqe.word_4 =
1691 cpu_to_le32(*((u32 *) skb->data) & ~NS_TBD_VC_MASK);
1692 /* Force the VPI/VCI to be the same as in VCC struct */
1693 scqe.word_4 |=
1694 cpu_to_le32((((u32) vcc->
1695 vpi) << NS_TBD_VPI_SHIFT | ((u32) vcc->
1696 vci) <<
1697 NS_TBD_VCI_SHIFT) & NS_TBD_VC_MASK);
1698 }
1699
1700 if (vcc->qos.txtp.traffic_class == ATM_CBR) {
1701 scqe.word_1 = ns_tbd_mkword_1_novbr(flags, (u32) buflen);
1702 scq = ((vc_map *) vcc->dev_data)->scq;
1703 } else {
1704 scqe.word_1 =
1705 ns_tbd_mkword_1(flags, (u32) 1, (u32) 1, (u32) buflen);
1706 scq = card->scq0;
1707 }
1708
1709 if (push_scqe(card, vc, scq, &scqe, skb, may_sleep) != 0) {
1710 atomic_inc(&vcc->stats->tx_err);
1711 dma_unmap_single(&card->pcidev->dev, NS_PRV_DMA(skb), skb->len,
1712 DMA_TO_DEVICE);
1713 dev_kfree_skb_any(skb);
1714 return -EIO;
1715 }
1716 atomic_inc(&vcc->stats->tx);
1717
1718 return 0;
1719 }
1720
1721 static int ns_send(struct atm_vcc *vcc, struct sk_buff *skb)
1722 {
1723 return _ns_send(vcc, skb, true);
1724 }
1725
1726 static int ns_send_bh(struct atm_vcc *vcc, struct sk_buff *skb)
1727 {
1728 return _ns_send(vcc, skb, false);
1729 }
1730
1731 static int push_scqe(ns_dev * card, vc_map * vc, scq_info * scq, ns_scqe * tbd,
1732 struct sk_buff *skb, bool may_sleep)
1733 {
1734 unsigned long flags;
1735 ns_scqe tsr;
1736 u32 scdi, scqi;
1737 int scq_is_vbr;
1738 u32 data;
1739 int index;
1740
1741 spin_lock_irqsave(&scq->lock, flags);
1742 while (scq->tail == scq->next) {
1743 if (!may_sleep) {
1744 spin_unlock_irqrestore(&scq->lock, flags);
1745 printk("nicstar%d: Error pushing TBD.\n", card->index);
1746 return 1;
1747 }
1748
1749 scq->full = 1;
1750 wait_event_interruptible_lock_irq_timeout(scq->scqfull_waitq,
1751 scq->tail != scq->next,
1752 scq->lock,
1753 SCQFULL_TIMEOUT);
1754
1755 if (scq->full) {
1756 spin_unlock_irqrestore(&scq->lock, flags);
1757 printk("nicstar%d: Timeout pushing TBD.\n",
1758 card->index);
1759 return 1;
1760 }
1761 }
1762 *scq->next = *tbd;
1763 index = (int)(scq->next - scq->base);
1764 scq->skb[index] = skb;
1765 XPRINTK("nicstar%d: sending skb at 0x%p (pos %d).\n",
1766 card->index, skb, index);
1767 XPRINTK("nicstar%d: TBD written:\n0x%x\n0x%x\n0x%x\n0x%x\n at 0x%p.\n",
1768 card->index, le32_to_cpu(tbd->word_1), le32_to_cpu(tbd->word_2),
1769 le32_to_cpu(tbd->word_3), le32_to_cpu(tbd->word_4),
1770 scq->next);
1771 if (scq->next == scq->last)
1772 scq->next = scq->base;
1773 else
1774 scq->next++;
1775
1776 vc->tbd_count++;
1777 if (scq->num_entries == VBR_SCQ_NUM_ENTRIES) {
1778 scq->tbd_count++;
1779 scq_is_vbr = 1;
1780 } else
1781 scq_is_vbr = 0;
1782
1783 if (vc->tbd_count >= MAX_TBD_PER_VC
1784 || scq->tbd_count >= MAX_TBD_PER_SCQ) {
1785 int has_run = 0;
1786
1787 while (scq->tail == scq->next) {
1788 if (!may_sleep) {
1789 data = scq_virt_to_bus(scq, scq->next);
1790 ns_write_sram(card, scq->scd, &data, 1);
1791 spin_unlock_irqrestore(&scq->lock, flags);
1792 printk("nicstar%d: Error pushing TSR.\n",
1793 card->index);
1794 return 0;
1795 }
1796
1797 scq->full = 1;
1798 if (has_run++)
1799 break;
1800 wait_event_interruptible_lock_irq_timeout(scq->scqfull_waitq,
1801 scq->tail != scq->next,
1802 scq->lock,
1803 SCQFULL_TIMEOUT);
1804 }
1805
1806 if (!scq->full) {
1807 tsr.word_1 = ns_tsr_mkword_1(NS_TSR_INTENABLE);
1808 if (scq_is_vbr)
1809 scdi = NS_TSR_SCDISVBR;
1810 else
1811 scdi = (vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE;
1812 scqi = scq->next - scq->base;
1813 tsr.word_2 = ns_tsr_mkword_2(scdi, scqi);
1814 tsr.word_3 = 0x00000000;
1815 tsr.word_4 = 0x00000000;
1816
1817 *scq->next = tsr;
1818 index = (int)scqi;
1819 scq->skb[index] = NULL;
1820 XPRINTK
1821 ("nicstar%d: TSR written:\n0x%x\n0x%x\n0x%x\n0x%x\n at 0x%p.\n",
1822 card->index, le32_to_cpu(tsr.word_1),
1823 le32_to_cpu(tsr.word_2), le32_to_cpu(tsr.word_3),
1824 le32_to_cpu(tsr.word_4), scq->next);
1825 if (scq->next == scq->last)
1826 scq->next = scq->base;
1827 else
1828 scq->next++;
1829 vc->tbd_count = 0;
1830 scq->tbd_count = 0;
1831 } else
1832 PRINTK("nicstar%d: Timeout pushing TSR.\n",
1833 card->index);
1834 }
1835 data = scq_virt_to_bus(scq, scq->next);
1836 ns_write_sram(card, scq->scd, &data, 1);
1837
1838 spin_unlock_irqrestore(&scq->lock, flags);
1839
1840 return 0;
1841 }
1842
1843 static void process_tsq(ns_dev * card)
1844 {
1845 u32 scdi;
1846 scq_info *scq;
1847 ns_tsi *previous = NULL, *one_ahead, *two_ahead;
1848 int serviced_entries; /* flag indicating at least on entry was serviced */
1849
1850 serviced_entries = 0;
1851
1852 if (card->tsq.next == card->tsq.last)
1853 one_ahead = card->tsq.base;
1854 else
1855 one_ahead = card->tsq.next + 1;
1856
1857 if (one_ahead == card->tsq.last)
1858 two_ahead = card->tsq.base;
1859 else
1860 two_ahead = one_ahead + 1;
1861
1862 while (!ns_tsi_isempty(card->tsq.next) || !ns_tsi_isempty(one_ahead) ||
1863 !ns_tsi_isempty(two_ahead))
1864 /* At most two empty, as stated in the 77201 errata */
1865 {
1866 serviced_entries = 1;
1867
1868 /* Skip the one or two possible empty entries */
1869 while (ns_tsi_isempty(card->tsq.next)) {
1870 if (card->tsq.next == card->tsq.last)
1871 card->tsq.next = card->tsq.base;
1872 else
1873 card->tsq.next++;
1874 }
1875
1876 if (!ns_tsi_tmrof(card->tsq.next)) {
1877 scdi = ns_tsi_getscdindex(card->tsq.next);
1878 if (scdi == NS_TSI_SCDISVBR)
1879 scq = card->scq0;
1880 else {
1881 if (card->scd2vc[scdi] == NULL) {
1882 printk
1883 ("nicstar%d: could not find VC from SCD index.\n",
1884 card->index);
1885 ns_tsi_init(card->tsq.next);
1886 return;
1887 }
1888 scq = card->scd2vc[scdi]->scq;
1889 }
1890 drain_scq(card, scq, ns_tsi_getscqpos(card->tsq.next));
1891 scq->full = 0;
1892 wake_up_interruptible(&(scq->scqfull_waitq));
1893 }
1894
1895 ns_tsi_init(card->tsq.next);
1896 previous = card->tsq.next;
1897 if (card->tsq.next == card->tsq.last)
1898 card->tsq.next = card->tsq.base;
1899 else
1900 card->tsq.next++;
1901
1902 if (card->tsq.next == card->tsq.last)
1903 one_ahead = card->tsq.base;
1904 else
1905 one_ahead = card->tsq.next + 1;
1906
1907 if (one_ahead == card->tsq.last)
1908 two_ahead = card->tsq.base;
1909 else
1910 two_ahead = one_ahead + 1;
1911 }
1912
1913 if (serviced_entries)
1914 writel(PTR_DIFF(previous, card->tsq.base),
1915 card->membase + TSQH);
1916 }
1917
1918 static void drain_scq(ns_dev * card, scq_info * scq, int pos)
1919 {
1920 struct atm_vcc *vcc;
1921 struct sk_buff *skb;
1922 int i;
1923 unsigned long flags;
1924
1925 XPRINTK("nicstar%d: drain_scq() called, scq at 0x%p, pos %d.\n",
1926 card->index, scq, pos);
1927 if (pos >= scq->num_entries) {
1928 printk("nicstar%d: Bad index on drain_scq().\n", card->index);
1929 return;
1930 }
1931
1932 spin_lock_irqsave(&scq->lock, flags);
1933 i = (int)(scq->tail - scq->base);
1934 if (++i == scq->num_entries)
1935 i = 0;
1936 while (i != pos) {
1937 skb = scq->skb[i];
1938 XPRINTK("nicstar%d: freeing skb at 0x%p (index %d).\n",
1939 card->index, skb, i);
1940 if (skb != NULL) {
1941 dma_unmap_single(&card->pcidev->dev,
1942 NS_PRV_DMA(skb),
1943 skb->len,
1944 DMA_TO_DEVICE);
1945 vcc = ATM_SKB(skb)->vcc;
1946 if (vcc && vcc->pop != NULL) {
1947 vcc->pop(vcc, skb);
1948 } else {
1949 dev_kfree_skb_irq(skb);
1950 }
1951 scq->skb[i] = NULL;
1952 }
1953 if (++i == scq->num_entries)
1954 i = 0;
1955 }
1956 scq->tail = scq->base + pos;
1957 spin_unlock_irqrestore(&scq->lock, flags);
1958 }
1959
1960 static void process_rsq(ns_dev * card)
1961 {
1962 ns_rsqe *previous;
1963
1964 if (!ns_rsqe_valid(card->rsq.next))
1965 return;
1966 do {
1967 dequeue_rx(card, card->rsq.next);
1968 ns_rsqe_init(card->rsq.next);
1969 previous = card->rsq.next;
1970 if (card->rsq.next == card->rsq.last)
1971 card->rsq.next = card->rsq.base;
1972 else
1973 card->rsq.next++;
1974 } while (ns_rsqe_valid(card->rsq.next));
1975 writel(PTR_DIFF(previous, card->rsq.base), card->membase + RSQH);
1976 }
1977
1978 static void dequeue_rx(ns_dev * card, ns_rsqe * rsqe)
1979 {
1980 u32 vpi, vci;
1981 vc_map *vc;
1982 struct sk_buff *iovb;
1983 struct iovec *iov;
1984 struct atm_vcc *vcc;
1985 struct sk_buff *skb;
1986 unsigned short aal5_len;
1987 int len;
1988 u32 stat;
1989 u32 id;
1990
1991 stat = readl(card->membase + STAT);
1992 card->sbfqc = ns_stat_sfbqc_get(stat);
1993 card->lbfqc = ns_stat_lfbqc_get(stat);
1994
1995 id = le32_to_cpu(rsqe->buffer_handle);
1996 skb = idr_remove(&card->idr, id);
1997 if (!skb) {
1998 RXPRINTK(KERN_ERR
1999 "nicstar%d: skb not found!\n", card->index);
2000 return;
2001 }
2002 dma_sync_single_for_cpu(&card->pcidev->dev,
2003 NS_PRV_DMA(skb),
2004 (NS_PRV_BUFTYPE(skb) == BUF_SM
2005 ? NS_SMSKBSIZE : NS_LGSKBSIZE),
2006 DMA_FROM_DEVICE);
2007 dma_unmap_single(&card->pcidev->dev,
2008 NS_PRV_DMA(skb),
2009 (NS_PRV_BUFTYPE(skb) == BUF_SM
2010 ? NS_SMSKBSIZE : NS_LGSKBSIZE),
2011 DMA_FROM_DEVICE);
2012 vpi = ns_rsqe_vpi(rsqe);
2013 vci = ns_rsqe_vci(rsqe);
2014 if (vpi >= 1UL << card->vpibits || vci >= 1UL << card->vcibits) {
2015 printk("nicstar%d: SDU received for out-of-range vc %d.%d.\n",
2016 card->index, vpi, vci);
2017 recycle_rx_buf(card, skb);
2018 return;
2019 }
2020
2021 vc = &(card->vcmap[vpi << card->vcibits | vci]);
2022 if (!vc->rx) {
2023 RXPRINTK("nicstar%d: SDU received on non-rx vc %d.%d.\n",
2024 card->index, vpi, vci);
2025 recycle_rx_buf(card, skb);
2026 return;
2027 }
2028
2029 vcc = vc->rx_vcc;
2030
2031 if (vcc->qos.aal == ATM_AAL0) {
2032 struct sk_buff *sb;
2033 unsigned char *cell;
2034 int i;
2035
2036 cell = skb->data;
2037 for (i = ns_rsqe_cellcount(rsqe); i; i--) {
2038 sb = dev_alloc_skb(NS_SMSKBSIZE);
2039 if (!sb) {
2040 printk
2041 ("nicstar%d: Can't allocate buffers for aal0.\n",
2042 card->index);
2043 atomic_add(i, &vcc->stats->rx_drop);
2044 break;
2045 }
2046 if (!atm_charge(vcc, sb->truesize)) {
2047 RXPRINTK
2048 ("nicstar%d: atm_charge() dropped aal0 packets.\n",
2049 card->index);
2050 atomic_add(i - 1, &vcc->stats->rx_drop); /* already increased by 1 */
2051 dev_kfree_skb_any(sb);
2052 break;
2053 }
2054 /* Rebuild the header */
2055 *((u32 *) sb->data) = le32_to_cpu(rsqe->word_1) << 4 |
2056 (ns_rsqe_clp(rsqe) ? 0x00000001 : 0x00000000);
2057 if (i == 1 && ns_rsqe_eopdu(rsqe))
2058 *((u32 *) sb->data) |= 0x00000002;
2059 skb_put(sb, NS_AAL0_HEADER);
2060 memcpy(skb_tail_pointer(sb), cell, ATM_CELL_PAYLOAD);
2061 skb_put(sb, ATM_CELL_PAYLOAD);
2062 ATM_SKB(sb)->vcc = vcc;
2063 __net_timestamp(sb);
2064 vcc->push(vcc, sb);
2065 atomic_inc(&vcc->stats->rx);
2066 cell += ATM_CELL_PAYLOAD;
2067 }
2068
2069 recycle_rx_buf(card, skb);
2070 return;
2071 }
2072
2073 /* To reach this point, the AAL layer can only be AAL5 */
2074
2075 if ((iovb = vc->rx_iov) == NULL) {
2076 iovb = skb_dequeue(&(card->iovpool.queue));
2077 if (iovb == NULL) { /* No buffers in the queue */
2078 iovb = alloc_skb(NS_IOVBUFSIZE, GFP_ATOMIC);
2079 if (iovb == NULL) {
2080 printk("nicstar%d: Out of iovec buffers.\n",
2081 card->index);
2082 atomic_inc(&vcc->stats->rx_drop);
2083 recycle_rx_buf(card, skb);
2084 return;
2085 }
2086 NS_PRV_BUFTYPE(iovb) = BUF_NONE;
2087 } else if (--card->iovpool.count < card->iovnr.min) {
2088 struct sk_buff *new_iovb;
2089 if ((new_iovb =
2090 alloc_skb(NS_IOVBUFSIZE, GFP_ATOMIC)) != NULL) {
2091 NS_PRV_BUFTYPE(iovb) = BUF_NONE;
2092 skb_queue_tail(&card->iovpool.queue, new_iovb);
2093 card->iovpool.count++;
2094 }
2095 }
2096 vc->rx_iov = iovb;
2097 NS_PRV_IOVCNT(iovb) = 0;
2098 iovb->len = 0;
2099 iovb->data = iovb->head;
2100 skb_reset_tail_pointer(iovb);
2101 /* IMPORTANT: a pointer to the sk_buff containing the small or large
2102 buffer is stored as iovec base, NOT a pointer to the
2103 small or large buffer itself. */
2104 } else if (NS_PRV_IOVCNT(iovb) >= NS_MAX_IOVECS) {
2105 printk("nicstar%d: received too big AAL5 SDU.\n", card->index);
2106 atomic_inc(&vcc->stats->rx_err);
2107 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
2108 NS_MAX_IOVECS);
2109 NS_PRV_IOVCNT(iovb) = 0;
2110 iovb->len = 0;
2111 iovb->data = iovb->head;
2112 skb_reset_tail_pointer(iovb);
2113 }
2114 iov = &((struct iovec *)iovb->data)[NS_PRV_IOVCNT(iovb)++];
2115 iov->iov_base = (void *)skb;
2116 iov->iov_len = ns_rsqe_cellcount(rsqe) * 48;
2117 iovb->len += iov->iov_len;
2118
2119 #ifdef EXTRA_DEBUG
2120 if (NS_PRV_IOVCNT(iovb) == 1) {
2121 if (NS_PRV_BUFTYPE(skb) != BUF_SM) {
2122 printk
2123 ("nicstar%d: Expected a small buffer, and this is not one.\n",
2124 card->index);
2125 which_list(card, skb);
2126 atomic_inc(&vcc->stats->rx_err);
2127 recycle_rx_buf(card, skb);
2128 vc->rx_iov = NULL;
2129 recycle_iov_buf(card, iovb);
2130 return;
2131 }
2132 } else { /* NS_PRV_IOVCNT(iovb) >= 2 */
2133
2134 if (NS_PRV_BUFTYPE(skb) != BUF_LG) {
2135 printk
2136 ("nicstar%d: Expected a large buffer, and this is not one.\n",
2137 card->index);
2138 which_list(card, skb);
2139 atomic_inc(&vcc->stats->rx_err);
2140 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
2141 NS_PRV_IOVCNT(iovb));
2142 vc->rx_iov = NULL;
2143 recycle_iov_buf(card, iovb);
2144 return;
2145 }
2146 }
2147 #endif /* EXTRA_DEBUG */
2148
2149 if (ns_rsqe_eopdu(rsqe)) {
2150 /* This works correctly regardless of the endianness of the host */
2151 unsigned char *L1L2 = (unsigned char *)
2152 (skb->data + iov->iov_len - 6);
2153 aal5_len = L1L2[0] << 8 | L1L2[1];
2154 len = (aal5_len == 0x0000) ? 0x10000 : aal5_len;
2155 if (ns_rsqe_crcerr(rsqe) ||
2156 len + 8 > iovb->len || len + (47 + 8) < iovb->len) {
2157 printk("nicstar%d: AAL5 CRC error", card->index);
2158 if (len + 8 > iovb->len || len + (47 + 8) < iovb->len)
2159 printk(" - PDU size mismatch.\n");
2160 else
2161 printk(".\n");
2162 atomic_inc(&vcc->stats->rx_err);
2163 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
2164 NS_PRV_IOVCNT(iovb));
2165 vc->rx_iov = NULL;
2166 recycle_iov_buf(card, iovb);
2167 return;
2168 }
2169
2170 /* By this point we (hopefully) have a complete SDU without errors. */
2171
2172 if (NS_PRV_IOVCNT(iovb) == 1) { /* Just a small buffer */
2173 /* skb points to a small buffer */
2174 if (!atm_charge(vcc, skb->truesize)) {
2175 push_rxbufs(card, skb);
2176 atomic_inc(&vcc->stats->rx_drop);
2177 } else {
2178 skb_put(skb, len);
2179 dequeue_sm_buf(card, skb);
2180 ATM_SKB(skb)->vcc = vcc;
2181 __net_timestamp(skb);
2182 vcc->push(vcc, skb);
2183 atomic_inc(&vcc->stats->rx);
2184 }
2185 } else if (NS_PRV_IOVCNT(iovb) == 2) { /* One small plus one large buffer */
2186 struct sk_buff *sb;
2187
2188 sb = (struct sk_buff *)(iov - 1)->iov_base;
2189 /* skb points to a large buffer */
2190
2191 if (len <= NS_SMBUFSIZE) {
2192 if (!atm_charge(vcc, sb->truesize)) {
2193 push_rxbufs(card, sb);
2194 atomic_inc(&vcc->stats->rx_drop);
2195 } else {
2196 skb_put(sb, len);
2197 dequeue_sm_buf(card, sb);
2198 ATM_SKB(sb)->vcc = vcc;
2199 __net_timestamp(sb);
2200 vcc->push(vcc, sb);
2201 atomic_inc(&vcc->stats->rx);
2202 }
2203
2204 push_rxbufs(card, skb);
2205
2206 } else { /* len > NS_SMBUFSIZE, the usual case */
2207
2208 if (!atm_charge(vcc, skb->truesize)) {
2209 push_rxbufs(card, skb);
2210 atomic_inc(&vcc->stats->rx_drop);
2211 } else {
2212 dequeue_lg_buf(card, skb);
2213 skb_push(skb, NS_SMBUFSIZE);
2214 skb_copy_from_linear_data(sb, skb->data,
2215 NS_SMBUFSIZE);
2216 skb_put(skb, len - NS_SMBUFSIZE);
2217 ATM_SKB(skb)->vcc = vcc;
2218 __net_timestamp(skb);
2219 vcc->push(vcc, skb);
2220 atomic_inc(&vcc->stats->rx);
2221 }
2222
2223 push_rxbufs(card, sb);
2224
2225 }
2226
2227 } else { /* Must push a huge buffer */
2228
2229 struct sk_buff *hb, *sb, *lb;
2230 int remaining, tocopy;
2231 int j;
2232
2233 hb = skb_dequeue(&(card->hbpool.queue));
2234 if (hb == NULL) { /* No buffers in the queue */
2235
2236 hb = dev_alloc_skb(NS_HBUFSIZE);
2237 if (hb == NULL) {
2238 printk
2239 ("nicstar%d: Out of huge buffers.\n",
2240 card->index);
2241 atomic_inc(&vcc->stats->rx_drop);
2242 recycle_iovec_rx_bufs(card,
2243 (struct iovec *)
2244 iovb->data,
2245 NS_PRV_IOVCNT(iovb));
2246 vc->rx_iov = NULL;
2247 recycle_iov_buf(card, iovb);
2248 return;
2249 } else if (card->hbpool.count < card->hbnr.min) {
2250 struct sk_buff *new_hb;
2251 if ((new_hb =
2252 dev_alloc_skb(NS_HBUFSIZE)) !=
2253 NULL) {
2254 skb_queue_tail(&card->hbpool.
2255 queue, new_hb);
2256 card->hbpool.count++;
2257 }
2258 }
2259 NS_PRV_BUFTYPE(hb) = BUF_NONE;
2260 } else if (--card->hbpool.count < card->hbnr.min) {
2261 struct sk_buff *new_hb;
2262 if ((new_hb =
2263 dev_alloc_skb(NS_HBUFSIZE)) != NULL) {
2264 NS_PRV_BUFTYPE(new_hb) = BUF_NONE;
2265 skb_queue_tail(&card->hbpool.queue,
2266 new_hb);
2267 card->hbpool.count++;
2268 }
2269 if (card->hbpool.count < card->hbnr.min) {
2270 if ((new_hb =
2271 dev_alloc_skb(NS_HBUFSIZE)) !=
2272 NULL) {
2273 NS_PRV_BUFTYPE(new_hb) =
2274 BUF_NONE;
2275 skb_queue_tail(&card->hbpool.
2276 queue, new_hb);
2277 card->hbpool.count++;
2278 }
2279 }
2280 }
2281
2282 iov = (struct iovec *)iovb->data;
2283
2284 if (!atm_charge(vcc, hb->truesize)) {
2285 recycle_iovec_rx_bufs(card, iov,
2286 NS_PRV_IOVCNT(iovb));
2287 if (card->hbpool.count < card->hbnr.max) {
2288 skb_queue_tail(&card->hbpool.queue, hb);
2289 card->hbpool.count++;
2290 } else
2291 dev_kfree_skb_any(hb);
2292 atomic_inc(&vcc->stats->rx_drop);
2293 } else {
2294 /* Copy the small buffer to the huge buffer */
2295 sb = (struct sk_buff *)iov->iov_base;
2296 skb_copy_from_linear_data(sb, hb->data,
2297 iov->iov_len);
2298 skb_put(hb, iov->iov_len);
2299 remaining = len - iov->iov_len;
2300 iov++;
2301 /* Free the small buffer */
2302 push_rxbufs(card, sb);
2303
2304 /* Copy all large buffers to the huge buffer and free them */
2305 for (j = 1; j < NS_PRV_IOVCNT(iovb); j++) {
2306 lb = (struct sk_buff *)iov->iov_base;
2307 tocopy =
2308 min_t(int, remaining, iov->iov_len);
2309 skb_copy_from_linear_data(lb,
2310 skb_tail_pointer
2311 (hb), tocopy);
2312 skb_put(hb, tocopy);
2313 iov++;
2314 remaining -= tocopy;
2315 push_rxbufs(card, lb);
2316 }
2317 #ifdef EXTRA_DEBUG
2318 if (remaining != 0 || hb->len != len)
2319 printk
2320 ("nicstar%d: Huge buffer len mismatch.\n",
2321 card->index);
2322 #endif /* EXTRA_DEBUG */
2323 ATM_SKB(hb)->vcc = vcc;
2324 __net_timestamp(hb);
2325 vcc->push(vcc, hb);
2326 atomic_inc(&vcc->stats->rx);
2327 }
2328 }
2329
2330 vc->rx_iov = NULL;
2331 recycle_iov_buf(card, iovb);
2332 }
2333
2334 }
2335
2336 static void recycle_rx_buf(ns_dev * card, struct sk_buff *skb)
2337 {
2338 if (unlikely(NS_PRV_BUFTYPE(skb) == BUF_NONE)) {
2339 printk("nicstar%d: What kind of rx buffer is this?\n",
2340 card->index);
2341 dev_kfree_skb_any(skb);
2342 } else
2343 push_rxbufs(card, skb);
2344 }
2345
2346 static void recycle_iovec_rx_bufs(ns_dev * card, struct iovec *iov, int count)
2347 {
2348 while (count-- > 0)
2349 recycle_rx_buf(card, (struct sk_buff *)(iov++)->iov_base);
2350 }
2351
2352 static void recycle_iov_buf(ns_dev * card, struct sk_buff *iovb)
2353 {
2354 if (card->iovpool.count < card->iovnr.max) {
2355 skb_queue_tail(&card->iovpool.queue, iovb);
2356 card->iovpool.count++;
2357 } else
2358 dev_kfree_skb_any(iovb);
2359 }
2360
2361 static void dequeue_sm_buf(ns_dev * card, struct sk_buff *sb)
2362 {
2363 skb_unlink(sb, &card->sbpool.queue);
2364 if (card->sbfqc < card->sbnr.init) {
2365 struct sk_buff *new_sb;
2366 if ((new_sb = dev_alloc_skb(NS_SMSKBSIZE)) != NULL) {
2367 NS_PRV_BUFTYPE(new_sb) = BUF_SM;
2368 skb_queue_tail(&card->sbpool.queue, new_sb);
2369 skb_reserve(new_sb, NS_AAL0_HEADER);
2370 push_rxbufs(card, new_sb);
2371 }
2372 }
2373 if (card->sbfqc < card->sbnr.init)
2374 {
2375 struct sk_buff *new_sb;
2376 if ((new_sb = dev_alloc_skb(NS_SMSKBSIZE)) != NULL) {
2377 NS_PRV_BUFTYPE(new_sb) = BUF_SM;
2378 skb_queue_tail(&card->sbpool.queue, new_sb);
2379 skb_reserve(new_sb, NS_AAL0_HEADER);
2380 push_rxbufs(card, new_sb);
2381 }
2382 }
2383 }
2384
2385 static void dequeue_lg_buf(ns_dev * card, struct sk_buff *lb)
2386 {
2387 skb_unlink(lb, &card->lbpool.queue);
2388 if (card->lbfqc < card->lbnr.init) {
2389 struct sk_buff *new_lb;
2390 if ((new_lb = dev_alloc_skb(NS_LGSKBSIZE)) != NULL) {
2391 NS_PRV_BUFTYPE(new_lb) = BUF_LG;
2392 skb_queue_tail(&card->lbpool.queue, new_lb);
2393 skb_reserve(new_lb, NS_SMBUFSIZE);
2394 push_rxbufs(card, new_lb);
2395 }
2396 }
2397 if (card->lbfqc < card->lbnr.init)
2398 {
2399 struct sk_buff *new_lb;
2400 if ((new_lb = dev_alloc_skb(NS_LGSKBSIZE)) != NULL) {
2401 NS_PRV_BUFTYPE(new_lb) = BUF_LG;
2402 skb_queue_tail(&card->lbpool.queue, new_lb);
2403 skb_reserve(new_lb, NS_SMBUFSIZE);
2404 push_rxbufs(card, new_lb);
2405 }
2406 }
2407 }
2408
2409 static int ns_proc_read(struct atm_dev *dev, loff_t * pos, char *page)
2410 {
2411 u32 stat;
2412 ns_dev *card;
2413 int left;
2414
2415 left = (int)*pos;
2416 card = (ns_dev *) dev->dev_data;
2417 stat = readl(card->membase + STAT);
2418 if (!left--)
2419 return sprintf(page, "Pool count min init max \n");
2420 if (!left--)
2421 return sprintf(page, "Small %5d %5d %5d %5d \n",
2422 ns_stat_sfbqc_get(stat), card->sbnr.min,
2423 card->sbnr.init, card->sbnr.max);
2424 if (!left--)
2425 return sprintf(page, "Large %5d %5d %5d %5d \n",
2426 ns_stat_lfbqc_get(stat), card->lbnr.min,
2427 card->lbnr.init, card->lbnr.max);
2428 if (!left--)
2429 return sprintf(page, "Huge %5d %5d %5d %5d \n",
2430 card->hbpool.count, card->hbnr.min,
2431 card->hbnr.init, card->hbnr.max);
2432 if (!left--)
2433 return sprintf(page, "Iovec %5d %5d %5d %5d \n",
2434 card->iovpool.count, card->iovnr.min,
2435 card->iovnr.init, card->iovnr.max);
2436 if (!left--) {
2437 int retval;
2438 retval =
2439 sprintf(page, "Interrupt counter: %u \n", card->intcnt);
2440 card->intcnt = 0;
2441 return retval;
2442 }
2443 #if 0
2444 /* Dump 25.6 Mbps PHY registers */
2445 /* Now there's a 25.6 Mbps PHY driver this code isn't needed. I left it
2446 here just in case it's needed for debugging. */
2447 if (card->max_pcr == ATM_25_PCR && !left--) {
2448 u32 phy_regs[4];
2449 u32 i;
2450
2451 for (i = 0; i < 4; i++) {
2452 while (CMD_BUSY(card)) ;
2453 writel(NS_CMD_READ_UTILITY | 0x00000200 | i,
2454 card->membase + CMD);
2455 while (CMD_BUSY(card)) ;
2456 phy_regs[i] = readl(card->membase + DR0) & 0x000000FF;
2457 }
2458
2459 return sprintf(page, "PHY regs: 0x%02X 0x%02X 0x%02X 0x%02X \n",
2460 phy_regs[0], phy_regs[1], phy_regs[2],
2461 phy_regs[3]);
2462 }
2463 #endif /* 0 - Dump 25.6 Mbps PHY registers */
2464 #if 0
2465 /* Dump TST */
2466 if (left-- < NS_TST_NUM_ENTRIES) {
2467 if (card->tste2vc[left + 1] == NULL)
2468 return sprintf(page, "%5d - VBR/UBR \n", left + 1);
2469 else
2470 return sprintf(page, "%5d - %d %d \n", left + 1,
2471 card->tste2vc[left + 1]->tx_vcc->vpi,
2472 card->tste2vc[left + 1]->tx_vcc->vci);
2473 }
2474 #endif /* 0 */
2475 return 0;
2476 }
2477
2478 static int ns_ioctl(struct atm_dev *dev, unsigned int cmd, void __user * arg)
2479 {
2480 ns_dev *card;
2481 pool_levels pl;
2482 long btype;
2483 unsigned long flags;
2484
2485 card = dev->dev_data;
2486 switch (cmd) {
2487 case NS_GETPSTAT:
2488 if (get_user
2489 (pl.buftype, &((pool_levels __user *) arg)->buftype))
2490 return -EFAULT;
2491 switch (pl.buftype) {
2492 case NS_BUFTYPE_SMALL:
2493 pl.count =
2494 ns_stat_sfbqc_get(readl(card->membase + STAT));
2495 pl.level.min = card->sbnr.min;
2496 pl.level.init = card->sbnr.init;
2497 pl.level.max = card->sbnr.max;
2498 break;
2499
2500 case NS_BUFTYPE_LARGE:
2501 pl.count =
2502 ns_stat_lfbqc_get(readl(card->membase + STAT));
2503 pl.level.min = card->lbnr.min;
2504 pl.level.init = card->lbnr.init;
2505 pl.level.max = card->lbnr.max;
2506 break;
2507
2508 case NS_BUFTYPE_HUGE:
2509 pl.count = card->hbpool.count;
2510 pl.level.min = card->hbnr.min;
2511 pl.level.init = card->hbnr.init;
2512 pl.level.max = card->hbnr.max;
2513 break;
2514
2515 case NS_BUFTYPE_IOVEC:
2516 pl.count = card->iovpool.count;
2517 pl.level.min = card->iovnr.min;
2518 pl.level.init = card->iovnr.init;
2519 pl.level.max = card->iovnr.max;
2520 break;
2521
2522 default:
2523 return -ENOIOCTLCMD;
2524
2525 }
2526 if (!copy_to_user((pool_levels __user *) arg, &pl, sizeof(pl)))
2527 return (sizeof(pl));
2528 else
2529 return -EFAULT;
2530
2531 case NS_SETBUFLEV:
2532 if (!capable(CAP_NET_ADMIN))
2533 return -EPERM;
2534 if (copy_from_user(&pl, (pool_levels __user *) arg, sizeof(pl)))
2535 return -EFAULT;
2536 if (pl.level.min >= pl.level.init
2537 || pl.level.init >= pl.level.max)
2538 return -EINVAL;
2539 if (pl.level.min == 0)
2540 return -EINVAL;
2541 switch (pl.buftype) {
2542 case NS_BUFTYPE_SMALL:
2543 if (pl.level.max > TOP_SB)
2544 return -EINVAL;
2545 card->sbnr.min = pl.level.min;
2546 card->sbnr.init = pl.level.init;
2547 card->sbnr.max = pl.level.max;
2548 break;
2549
2550 case NS_BUFTYPE_LARGE:
2551 if (pl.level.max > TOP_LB)
2552 return -EINVAL;
2553 card->lbnr.min = pl.level.min;
2554 card->lbnr.init = pl.level.init;
2555 card->lbnr.max = pl.level.max;
2556 break;
2557
2558 case NS_BUFTYPE_HUGE:
2559 if (pl.level.max > TOP_HB)
2560 return -EINVAL;
2561 card->hbnr.min = pl.level.min;
2562 card->hbnr.init = pl.level.init;
2563 card->hbnr.max = pl.level.max;
2564 break;
2565
2566 case NS_BUFTYPE_IOVEC:
2567 if (pl.level.max > TOP_IOVB)
2568 return -EINVAL;
2569 card->iovnr.min = pl.level.min;
2570 card->iovnr.init = pl.level.init;
2571 card->iovnr.max = pl.level.max;
2572 break;
2573
2574 default:
2575 return -EINVAL;
2576
2577 }
2578 return 0;
2579
2580 case NS_ADJBUFLEV:
2581 if (!capable(CAP_NET_ADMIN))
2582 return -EPERM;
2583 btype = (long)arg; /* a long is the same size as a pointer or bigger */
2584 switch (btype) {
2585 case NS_BUFTYPE_SMALL:
2586 while (card->sbfqc < card->sbnr.init) {
2587 struct sk_buff *sb;
2588
2589 sb = __dev_alloc_skb(NS_SMSKBSIZE, GFP_KERNEL);
2590 if (sb == NULL)
2591 return -ENOMEM;
2592 NS_PRV_BUFTYPE(sb) = BUF_SM;
2593 skb_queue_tail(&card->sbpool.queue, sb);
2594 skb_reserve(sb, NS_AAL0_HEADER);
2595 push_rxbufs(card, sb);
2596 }
2597 break;
2598
2599 case NS_BUFTYPE_LARGE:
2600 while (card->lbfqc < card->lbnr.init) {
2601 struct sk_buff *lb;
2602
2603 lb = __dev_alloc_skb(NS_LGSKBSIZE, GFP_KERNEL);
2604 if (lb == NULL)
2605 return -ENOMEM;
2606 NS_PRV_BUFTYPE(lb) = BUF_LG;
2607 skb_queue_tail(&card->lbpool.queue, lb);
2608 skb_reserve(lb, NS_SMBUFSIZE);
2609 push_rxbufs(card, lb);
2610 }
2611 break;
2612
2613 case NS_BUFTYPE_HUGE:
2614 while (card->hbpool.count > card->hbnr.init) {
2615 struct sk_buff *hb;
2616
2617 spin_lock_irqsave(&card->int_lock, flags);
2618 hb = skb_dequeue(&card->hbpool.queue);
2619 card->hbpool.count--;
2620 spin_unlock_irqrestore(&card->int_lock, flags);
2621 if (hb == NULL)
2622 printk
2623 ("nicstar%d: huge buffer count inconsistent.\n",
2624 card->index);
2625 else
2626 dev_kfree_skb_any(hb);
2627
2628 }
2629 while (card->hbpool.count < card->hbnr.init) {
2630 struct sk_buff *hb;
2631
2632 hb = __dev_alloc_skb(NS_HBUFSIZE, GFP_KERNEL);
2633 if (hb == NULL)
2634 return -ENOMEM;
2635 NS_PRV_BUFTYPE(hb) = BUF_NONE;
2636 spin_lock_irqsave(&card->int_lock, flags);
2637 skb_queue_tail(&card->hbpool.queue, hb);
2638 card->hbpool.count++;
2639 spin_unlock_irqrestore(&card->int_lock, flags);
2640 }
2641 break;
2642
2643 case NS_BUFTYPE_IOVEC:
2644 while (card->iovpool.count > card->iovnr.init) {
2645 struct sk_buff *iovb;
2646
2647 spin_lock_irqsave(&card->int_lock, flags);
2648 iovb = skb_dequeue(&card->iovpool.queue);
2649 card->iovpool.count--;
2650 spin_unlock_irqrestore(&card->int_lock, flags);
2651 if (iovb == NULL)
2652 printk
2653 ("nicstar%d: iovec buffer count inconsistent.\n",
2654 card->index);
2655 else
2656 dev_kfree_skb_any(iovb);
2657
2658 }
2659 while (card->iovpool.count < card->iovnr.init) {
2660 struct sk_buff *iovb;
2661
2662 iovb = alloc_skb(NS_IOVBUFSIZE, GFP_KERNEL);
2663 if (iovb == NULL)
2664 return -ENOMEM;
2665 NS_PRV_BUFTYPE(iovb) = BUF_NONE;
2666 spin_lock_irqsave(&card->int_lock, flags);
2667 skb_queue_tail(&card->iovpool.queue, iovb);
2668 card->iovpool.count++;
2669 spin_unlock_irqrestore(&card->int_lock, flags);
2670 }
2671 break;
2672
2673 default:
2674 return -EINVAL;
2675
2676 }
2677 return 0;
2678
2679 default:
2680 if (dev->phy && dev->phy->ioctl) {
2681 return dev->phy->ioctl(dev, cmd, arg);
2682 } else {
2683 printk("nicstar%d: %s == NULL \n", card->index,
2684 dev->phy ? "dev->phy->ioctl" : "dev->phy");
2685 return -ENOIOCTLCMD;
2686 }
2687 }
2688 }
2689
2690 #ifdef EXTRA_DEBUG
2691 static void which_list(ns_dev * card, struct sk_buff *skb)
2692 {
2693 printk("skb buf_type: 0x%08x\n", NS_PRV_BUFTYPE(skb));
2694 }
2695 #endif /* EXTRA_DEBUG */
2696
2697 static void ns_poll(struct timer_list *unused)
2698 {
2699 int i;
2700 ns_dev *card;
2701 unsigned long flags;
2702 u32 stat_r, stat_w;
2703
2704 PRINTK("nicstar: Entering ns_poll().\n");
2705 for (i = 0; i < num_cards; i++) {
2706 card = cards[i];
2707 if (!spin_trylock_irqsave(&card->int_lock, flags)) {
2708 /* Probably it isn't worth spinning */
2709 continue;
2710 }
2711
2712 stat_w = 0;
2713 stat_r = readl(card->membase + STAT);
2714 if (stat_r & NS_STAT_TSIF)
2715 stat_w |= NS_STAT_TSIF;
2716 if (stat_r & NS_STAT_EOPDU)
2717 stat_w |= NS_STAT_EOPDU;
2718
2719 process_tsq(card);
2720 process_rsq(card);
2721
2722 writel(stat_w, card->membase + STAT);
2723 spin_unlock_irqrestore(&card->int_lock, flags);
2724 }
2725 mod_timer(&ns_timer, jiffies + NS_POLL_PERIOD);
2726 PRINTK("nicstar: Leaving ns_poll().\n");
2727 }
2728
2729 static void ns_phy_put(struct atm_dev *dev, unsigned char value,
2730 unsigned long addr)
2731 {
2732 ns_dev *card;
2733 unsigned long flags;
2734
2735 card = dev->dev_data;
2736 spin_lock_irqsave(&card->res_lock, flags);
2737 while (CMD_BUSY(card)) ;
2738 writel((u32) value, card->membase + DR0);
2739 writel(NS_CMD_WRITE_UTILITY | 0x00000200 | (addr & 0x000000FF),
2740 card->membase + CMD);
2741 spin_unlock_irqrestore(&card->res_lock, flags);
2742 }
2743
2744 static unsigned char ns_phy_get(struct atm_dev *dev, unsigned long addr)
2745 {
2746 ns_dev *card;
2747 unsigned long flags;
2748 u32 data;
2749
2750 card = dev->dev_data;
2751 spin_lock_irqsave(&card->res_lock, flags);
2752 while (CMD_BUSY(card)) ;
2753 writel(NS_CMD_READ_UTILITY | 0x00000200 | (addr & 0x000000FF),
2754 card->membase + CMD);
2755 while (CMD_BUSY(card)) ;
2756 data = readl(card->membase + DR0) & 0x000000FF;
2757 spin_unlock_irqrestore(&card->res_lock, flags);
2758 return (unsigned char)data;
2759 }
2760
2761 module_init(nicstar_init);
2762 module_exit(nicstar_cleanup);
Linux with added FPC-III support