2 * RNG driver for VIA RNGs
4 * Copyright 2005 (c) MontaVista Software, Inc.
6 * with the majority of the code coming from:
8 * Hardware driver for the Intel/AMD/VIA Random Number Generators (RNG)
9 * (c) Copyright 2003 Red Hat Inc <jgarzik@redhat.com>
13 * Hardware driver for the AMD 768 Random Number Generator (RNG)
14 * (c) Copyright 2001 Red Hat Inc
18 * Hardware driver for Intel i810 Random Number Generator (RNG)
19 * Copyright 2000,2001 Jeff Garzik <jgarzik@pobox.com>
20 * Copyright 2000,2001 Philipp Rumpf <prumpf@mandrakesoft.com>
22 * This file is licensed under the terms of the GNU General Public
23 * License version 2. This program is licensed "as is" without any
24 * warranty of any kind, whether express or implied.
27 #include <crypto/padlock.h>
28 #include <linux/module.h>
29 #include <linux/kernel.h>
30 #include <linux/hw_random.h>
31 #include <linux/delay.h>
32 #include <asm/cpu_device_id.h>
35 #include <asm/cpufeature.h>
36 #include <asm/fpu/api.h>
42 VIA_STRFILT_CNT_SHIFT
= 16,
43 VIA_STRFILT_FAIL
= (1 << 15),
44 VIA_STRFILT_ENABLE
= (1 << 14),
45 VIA_RAWBITS_ENABLE
= (1 << 13),
46 VIA_RNG_ENABLE
= (1 << 6),
47 VIA_NOISESRC1
= (1 << 8),
48 VIA_NOISESRC2
= (1 << 9),
49 VIA_XSTORE_CNT_MASK
= 0x0F,
51 VIA_RNG_CHUNK_8
= 0x00, /* 64 rand bits, 64 stored bits */
52 VIA_RNG_CHUNK_4
= 0x01, /* 32 rand bits, 32 stored bits */
53 VIA_RNG_CHUNK_4_MASK
= 0xFFFFFFFF,
54 VIA_RNG_CHUNK_2
= 0x02, /* 16 rand bits, 32 stored bits */
55 VIA_RNG_CHUNK_2_MASK
= 0xFFFF,
56 VIA_RNG_CHUNK_1
= 0x03, /* 8 rand bits, 32 stored bits */
57 VIA_RNG_CHUNK_1_MASK
= 0xFF,
61 * Investigate using the 'rep' prefix to obtain 32 bits of random data
62 * in one insn. The upside is potentially better performance. The
63 * downside is that the instruction becomes no longer atomic. Due to
64 * this, just like familiar issues with /dev/random itself, the worst
65 * case of a 'rep xstore' could potentially pause a cpu for an
66 * unreasonably long time. In practice, this condition would likely
67 * only occur when the hardware is failing. (or so we hope :))
69 * Another possible performance boost may come from simply buffering
70 * until we have 4 bytes, thus returning a u32 at a time,
71 * instead of the current u8-at-a-time.
73 * Padlock instructions can generate a spurious DNA fault, but the
74 * kernel doesn't use CR0.TS, so this doesn't matter.
77 static inline u32
xstore(u32
*addr
, u32 edx_in
)
81 asm(".byte 0x0F,0xA7,0xC0 /* xstore %%edi (addr=%0) */"
82 : "=m" (*addr
), "=a" (eax_out
), "+d" (edx_in
), "+D" (addr
));
87 static int via_rng_data_present(struct hwrng
*rng
, int wait
)
89 char buf
[16 + PADLOCK_ALIGNMENT
- STACK_ALIGN
] __attribute__
90 ((aligned(STACK_ALIGN
)));
91 u32
*via_rng_datum
= (u32
*)PTR_ALIGN(&buf
[0], PADLOCK_ALIGNMENT
);
95 /* We choose the recommended 1-byte-per-instruction RNG rate,
96 * for greater randomness at the expense of speed. Larger
97 * values 2, 4, or 8 bytes-per-instruction yield greater
98 * speed at lesser randomness.
100 * If you change this to another VIA_CHUNK_n, you must also
101 * change the ->n_bytes values in rng_vendor_ops[] tables.
102 * VIA_CHUNK_8 requires further code changes.
104 * A copy of MSR_VIA_RNG is placed in eax_out when xstore
108 for (i
= 0; i
< 20; i
++) {
109 *via_rng_datum
= 0; /* paranoia, not really necessary */
110 bytes_out
= xstore(via_rng_datum
, VIA_RNG_CHUNK_1
);
111 bytes_out
&= VIA_XSTORE_CNT_MASK
;
112 if (bytes_out
|| !wait
)
116 rng
->priv
= *via_rng_datum
;
117 return bytes_out
? 1 : 0;
120 static int via_rng_data_read(struct hwrng
*rng
, u32
*data
)
122 u32 via_rng_datum
= (u32
)rng
->priv
;
124 *data
= via_rng_datum
;
129 static int via_rng_init(struct hwrng
*rng
)
131 struct cpuinfo_x86
*c
= &cpu_data(0);
134 /* VIA Nano CPUs don't have the MSR_VIA_RNG anymore. The RNG
135 * is always enabled if CPUID rng_en is set. There is no
136 * RNG configuration like it used to be the case in this
138 if (((c
->x86
== 6) && (c
->x86_model
>= 0x0f)) || (c
->x86
> 6)){
139 if (!boot_cpu_has(X86_FEATURE_XSTORE_EN
)) {
140 pr_err(PFX
"can't enable hardware RNG "
141 "if XSTORE is not enabled\n");
147 /* Control the RNG via MSR. Tread lightly and pay very close
148 * close attention to values written, as the reserved fields
149 * are documented to be "undefined and unpredictable"; but it
150 * does not say to write them as zero, so I make a guess that
151 * we restore the values we find in the register.
153 rdmsr(MSR_VIA_RNG
, lo
, hi
);
156 lo
&= ~(0x7f << VIA_STRFILT_CNT_SHIFT
);
157 lo
&= ~VIA_XSTORE_CNT_MASK
;
158 lo
&= ~(VIA_STRFILT_ENABLE
| VIA_STRFILT_FAIL
| VIA_RAWBITS_ENABLE
);
159 lo
|= VIA_RNG_ENABLE
;
162 /* Enable secondary noise source on CPUs where it is present. */
164 /* Nehemiah stepping 8 and higher */
165 if ((c
->x86_model
== 9) && (c
->x86_stepping
> 7))
169 if (c
->x86_model
>= 10)
173 wrmsr(MSR_VIA_RNG
, lo
, hi
);
175 /* perhaps-unnecessary sanity check; remove after testing if
177 rdmsr(MSR_VIA_RNG
, lo
, hi
);
178 if ((lo
& VIA_RNG_ENABLE
) == 0) {
179 pr_err(PFX
"cannot enable VIA C3 RNG, aborting\n");
187 static struct hwrng via_rng
= {
189 .init
= via_rng_init
,
190 .data_present
= via_rng_data_present
,
191 .data_read
= via_rng_data_read
,
195 static int __init
mod_init(void)
199 if (!boot_cpu_has(X86_FEATURE_XSTORE
))
202 pr_info("VIA RNG detected\n");
203 err
= hwrng_register(&via_rng
);
205 pr_err(PFX
"RNG registering failed (%d)\n",
212 module_init(mod_init
);
214 static void __exit
mod_exit(void)
216 hwrng_unregister(&via_rng
);
218 module_exit(mod_exit
);
220 static struct x86_cpu_id __maybe_unused via_rng_cpu_id
[] = {
221 X86_MATCH_FEATURE(X86_FEATURE_XSTORE
, NULL
),
224 MODULE_DEVICE_TABLE(x86cpu
, via_rng_cpu_id
);
226 MODULE_DESCRIPTION("H/W RNG driver for VIA CPU with PadLock");
227 MODULE_LICENSE("GPL");