drivers/clk/imx/clk.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __MACH_IMX_CLK_H
   3 #define __MACH_IMX_CLK_H
   4
   5 #include <linux/bits.h>
   6 #include <linux/spinlock.h>
   7 #include <linux/clk-provider.h>
   8
   9 extern spinlock_t imx_ccm_lock;
  10
  11 void imx_check_clocks(struct clk *clks[], unsigned int count);
  12 void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count);
  13 #ifndef MODULE
  14 void imx_register_uart_clocks(struct clk ** const clks[]);
  15 #else
  16 static inline void imx_register_uart_clocks(struct clk ** const clks[])
  17 {
  18 }
  19 #endif
  20 void imx_mmdc_mask_handshake(void __iomem *ccm_base, unsigned int chn);
  21 void imx_unregister_clocks(struct clk *clks[], unsigned int count);
  22 void imx_unregister_hw_clocks(struct clk_hw *hws[], unsigned int count);
  23
  24 extern void imx_cscmr1_fixup(u32 *val);
  25
  26 enum imx_pllv1_type {
  27         IMX_PLLV1_IMX1,
  28         IMX_PLLV1_IMX21,
  29         IMX_PLLV1_IMX25,
  30         IMX_PLLV1_IMX27,
  31         IMX_PLLV1_IMX31,
  32         IMX_PLLV1_IMX35,
  33 };
  34
  35 enum imx_sscg_pll_type {
  36         SCCG_PLL1,
  37         SCCG_PLL2,
  38 };
  39
  40 enum imx_pll14xx_type {
  41         PLL_1416X,
  42         PLL_1443X,
  43 };
  44
  45 /* NOTE: Rate table should be kept sorted in descending order. */
  46 struct imx_pll14xx_rate_table {
  47         unsigned int rate;
  48         unsigned int pdiv;
  49         unsigned int mdiv;
  50         unsigned int sdiv;
  51         unsigned int kdiv;
  52 };
  53
  54 struct imx_pll14xx_clk {
  55         enum imx_pll14xx_type type;
  56         const struct imx_pll14xx_rate_table *rate_table;
  57         int rate_count;
  58         int flags;
  59 };
  60
  61 extern struct imx_pll14xx_clk imx_1416x_pll;
  62 extern struct imx_pll14xx_clk imx_1443x_pll;
  63 extern struct imx_pll14xx_clk imx_1443x_dram_pll;
  64
  65 #define imx_clk_cpu(name, parent_name, div, mux, pll, step) \
  66         to_clk(imx_clk_hw_cpu(name, parent_name, div, mux, pll, step))
  67
  68 #define clk_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \
  69                                 cgr_val, cgr_mask, clk_gate_flags, lock, share_count) \
  70         to_clk(clk_hw_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \
  71                                 cgr_val, cgr_mask, clk_gate_flags, lock, share_count))
  72
  73 #define imx_clk_pllv3(type, name, parent_name, base, div_mask) \
  74         to_clk(imx_clk_hw_pllv3(type, name, parent_name, base, div_mask))
  75
  76 #define imx_clk_pfd(name, parent_name, reg, idx) \
  77         to_clk(imx_clk_hw_pfd(name, parent_name, reg, idx))
  78
  79 #define imx_clk_gate_exclusive(name, parent, reg, shift, exclusive_mask) \
  80         to_clk(imx_clk_hw_gate_exclusive(name, parent, reg, shift, exclusive_mask))
  81
  82 #define imx_clk_fixed(name, rate) \
  83         to_clk(imx_clk_hw_fixed(name, rate))
  84
  85 #define imx_clk_fixed_factor(name, parent, mult, div) \
  86         to_clk(imx_clk_hw_fixed_factor(name, parent, mult, div))
  87
  88 #define imx_clk_divider(name, parent, reg, shift, width) \
  89         to_clk(imx_clk_hw_divider(name, parent, reg, shift, width))
  90
  91 #define imx_clk_divider2(name, parent, reg, shift, width) \
  92         to_clk(imx_clk_hw_divider2(name, parent, reg, shift, width))
  93
  94 #define imx_clk_divider_flags(name, parent, reg, shift, width, flags) \
  95         to_clk(imx_clk_hw_divider_flags(name, parent, reg, shift, width, flags))
  96
  97 #define imx_clk_gate(name, parent, reg, shift) \
  98         to_clk(imx_clk_hw_gate(name, parent, reg, shift))
  99
 100 #define imx_clk_gate_dis(name, parent, reg, shift) \
 101         to_clk(imx_clk_hw_gate_dis(name, parent, reg, shift))
 102
 103 #define imx_clk_gate2(name, parent, reg, shift) \
 104         to_clk(imx_clk_hw_gate2(name, parent, reg, shift))
 105
 106 #define imx_clk_gate2_flags(name, parent, reg, shift, flags) \
 107         to_clk(imx_clk_hw_gate2_flags(name, parent, reg, shift, flags))
 108
 109 #define imx_clk_gate2_shared2(name, parent, reg, shift, share_count) \
 110         to_clk(imx_clk_hw_gate2_shared2(name, parent, reg, shift, share_count))
 111
 112 #define imx_clk_gate3(name, parent, reg, shift) \
 113         to_clk(imx_clk_hw_gate3(name, parent, reg, shift))
 114
 115 #define imx_clk_gate4(name, parent, reg, shift) \
 116         to_clk(imx_clk_hw_gate4(name, parent, reg, shift))
 117
 118 #define imx_clk_mux(name, reg, shift, width, parents, num_parents) \
 119         to_clk(imx_clk_hw_mux(name, reg, shift, width, parents, num_parents))
 120
 121 #define imx_clk_pllv1(type, name, parent, base) \
 122         to_clk(imx_clk_hw_pllv1(type, name, parent, base))
 123
 124 #define imx_clk_pllv2(name, parent, base) \
 125         to_clk(imx_clk_hw_pllv2(name, parent, base))
 126
 127 #define imx_clk_frac_pll(name, parent_name, base) \
 128         to_clk(imx_clk_hw_frac_pll(name, parent_name, base))
 129
 130 #define imx_clk_sscg_pll(name, parent_names, num_parents, parent,\
 131                                 bypass1, bypass2, base, flags) \
 132         to_clk(imx_clk_hw_sscg_pll(name, parent_names, num_parents, parent,\
 133                                 bypass1, bypass2, base, flags))
 134
 135 struct clk *imx_clk_pll14xx(const char *name, const char *parent_name,
 136                  void __iomem *base, const struct imx_pll14xx_clk *pll_clk);
 137
 138 #define imx_clk_pll14xx(name, parent_name, base, pll_clk) \
 139         to_clk(imx_clk_hw_pll14xx(name, parent_name, base, pll_clk))
 140
 141 struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name,
 142                                 const char *parent_name, void __iomem *base,
 143                                 const struct imx_pll14xx_clk *pll_clk);
 144
 145 struct clk_hw *imx_clk_hw_pllv1(enum imx_pllv1_type type, const char *name,
 146                 const char *parent, void __iomem *base);
 147
 148 struct clk_hw *imx_clk_hw_pllv2(const char *name, const char *parent,
 149                 void __iomem *base);
 150
 151 struct clk_hw *imx_clk_hw_frac_pll(const char *name, const char *parent_name,
 152                              void __iomem *base);
 153
 154 struct clk_hw *imx_clk_hw_sscg_pll(const char *name,
 155                                 const char * const *parent_names,
 156                                 u8 num_parents,
 157                                 u8 parent, u8 bypass1, u8 bypass2,
 158                                 void __iomem *base,
 159                                 unsigned long flags);
 160
 161 enum imx_pllv3_type {
 162         IMX_PLLV3_GENERIC,
 163         IMX_PLLV3_SYS,
 164         IMX_PLLV3_USB,
 165         IMX_PLLV3_USB_VF610,
 166         IMX_PLLV3_AV,
 167         IMX_PLLV3_ENET,
 168         IMX_PLLV3_ENET_IMX7,
 169         IMX_PLLV3_SYS_VF610,
 170         IMX_PLLV3_DDR_IMX7,
 171         IMX_PLLV3_AV_IMX7,
 172 };
 173
 174 struct clk_hw *imx_clk_hw_pllv3(enum imx_pllv3_type type, const char *name,
 175                 const char *parent_name, void __iomem *base, u32 div_mask);
 176
 177 #define PLL_1416X_RATE(_rate, _m, _p, _s)               \
 178         {                                               \
 179                 .rate   =       (_rate),                \
 180                 .mdiv   =       (_m),                   \
 181                 .pdiv   =       (_p),                   \
 182                 .sdiv   =       (_s),                   \
 183         }
 184
 185 #define PLL_1443X_RATE(_rate, _m, _p, _s, _k)           \
 186         {                                               \
 187                 .rate   =       (_rate),                \
 188                 .mdiv   =       (_m),                   \
 189                 .pdiv   =       (_p),                   \
 190                 .sdiv   =       (_s),                   \
 191                 .kdiv   =       (_k),                   \
 192         }
 193
 194 struct clk_hw *imx_clk_hw_pllv4(const char *name, const char *parent_name,
 195                              void __iomem *base);
 196
 197 struct clk_hw *clk_hw_register_gate2(struct device *dev, const char *name,
 198                 const char *parent_name, unsigned long flags,
 199                 void __iomem *reg, u8 bit_idx, u8 cgr_val, u8 cgr_mask,
 200                 u8 clk_gate_flags, spinlock_t *lock,
 201                 unsigned int *share_count);
 202
 203 struct clk * imx_obtain_fixed_clock(
 204                         const char *name, unsigned long rate);
 205
 206 struct clk_hw *imx_obtain_fixed_clock_hw(
 207                         const char *name, unsigned long rate);
 208
 209 struct clk_hw *imx_obtain_fixed_clk_hw(struct device_node *np,
 210                                        const char *name);
 211
 212 struct clk_hw *imx_clk_hw_gate_exclusive(const char *name, const char *parent,
 213          void __iomem *reg, u8 shift, u32 exclusive_mask);
 214
 215 struct clk_hw *imx_clk_hw_pfd(const char *name, const char *parent_name,
 216                 void __iomem *reg, u8 idx);
 217
 218 struct clk_hw *imx_clk_hw_pfdv2(const char *name, const char *parent_name,
 219                              void __iomem *reg, u8 idx);
 220
 221 struct clk_hw *imx_clk_hw_busy_divider(const char *name, const char *parent_name,
 222                                  void __iomem *reg, u8 shift, u8 width,
 223                                  void __iomem *busy_reg, u8 busy_shift);
 224
 225 struct clk_hw *imx_clk_hw_busy_mux(const char *name, void __iomem *reg, u8 shift,
 226                              u8 width, void __iomem *busy_reg, u8 busy_shift,
 227                              const char * const *parent_names, int num_parents);
 228
 229 struct clk_hw *imx7ulp_clk_hw_composite(const char *name,
 230                                      const char * const *parent_names,
 231                                      int num_parents, bool mux_present,
 232                                      bool rate_present, bool gate_present,
 233                                      void __iomem *reg);
 234
 235 struct clk_hw *imx_clk_hw_fixup_divider(const char *name, const char *parent,
 236                                   void __iomem *reg, u8 shift, u8 width,
 237                                   void (*fixup)(u32 *val));
 238
 239 struct clk_hw *imx_clk_hw_fixup_mux(const char *name, void __iomem *reg,
 240                               u8 shift, u8 width, const char * const *parents,
 241                               int num_parents, void (*fixup)(u32 *val));
 242
 243 static inline struct clk *to_clk(struct clk_hw *hw)
 244 {
 245         if (IS_ERR_OR_NULL(hw))
 246                 return ERR_CAST(hw);
 247         return hw->clk;
 248 }
 249
 250 static inline struct clk_hw *imx_clk_hw_pll14xx(const char *name, const char *parent_name,
 251                                   void __iomem *base,
 252                                   const struct imx_pll14xx_clk *pll_clk)
 253 {
 254         return imx_dev_clk_hw_pll14xx(NULL, name, parent_name, base, pll_clk);
 255 }
 256
 257 static inline struct clk_hw *imx_clk_hw_fixed(const char *name, int rate)
 258 {
 259         return clk_hw_register_fixed_rate(NULL, name, NULL, 0, rate);
 260 }
 261
 262 static inline struct clk_hw *imx_clk_hw_mux_ldb(const char *name, void __iomem *reg,
 263                         u8 shift, u8 width, const char * const *parents,
 264                         int num_parents)
 265 {
 266         return clk_hw_register_mux(NULL, name, parents, num_parents,
 267                         CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, reg,
 268                         shift, width, CLK_MUX_READ_ONLY, &imx_ccm_lock);
 269 }
 270
 271 static inline struct clk_hw *imx_clk_hw_fixed_factor(const char *name,
 272                 const char *parent, unsigned int mult, unsigned int div)
 273 {
 274         return clk_hw_register_fixed_factor(NULL, name, parent,
 275                         CLK_SET_RATE_PARENT, mult, div);
 276 }
 277
 278 static inline struct clk_hw *imx_clk_hw_divider(const char *name,
 279                                                 const char *parent,
 280                                                 void __iomem *reg, u8 shift,
 281                                                 u8 width)
 282 {
 283         return clk_hw_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
 284                                        reg, shift, width, 0, &imx_ccm_lock);
 285 }
 286
 287 static inline struct clk_hw *imx_clk_hw_divider_flags(const char *name,
 288                                                    const char *parent,
 289                                                    void __iomem *reg, u8 shift,
 290                                                    u8 width, unsigned long flags)
 291 {
 292         return clk_hw_register_divider(NULL, name, parent, flags,
 293                                        reg, shift, width, 0, &imx_ccm_lock);
 294 }
 295
 296 static inline struct clk_hw *imx_clk_hw_divider2(const char *name, const char *parent,
 297                 void __iomem *reg, u8 shift, u8 width)
 298 {
 299         return clk_hw_register_divider(NULL, name, parent,
 300                         CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
 301                         reg, shift, width, 0, &imx_ccm_lock);
 302 }
 303
 304 static inline struct clk *imx_clk_divider2_flags(const char *name,
 305                 const char *parent, void __iomem *reg, u8 shift, u8 width,
 306                 unsigned long flags)
 307 {
 308         return clk_register_divider(NULL, name, parent,
 309                         flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
 310                         reg, shift, width, 0, &imx_ccm_lock);
 311 }
 312
 313 static inline struct clk_hw *imx_clk_hw_gate_flags(const char *name, const char *parent,
 314                 void __iomem *reg, u8 shift, unsigned long flags)
 315 {
 316         return clk_hw_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
 317                         shift, 0, &imx_ccm_lock);
 318 }
 319
 320 static inline struct clk_hw *imx_clk_hw_gate(const char *name, const char *parent,
 321                                              void __iomem *reg, u8 shift)
 322 {
 323         return clk_hw_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
 324                                     shift, 0, &imx_ccm_lock);
 325 }
 326
 327 static inline struct clk_hw *imx_dev_clk_hw_gate(struct device *dev, const char *name,
 328                                                 const char *parent, void __iomem *reg, u8 shift)
 329 {
 330         return clk_hw_register_gate(dev, name, parent, CLK_SET_RATE_PARENT, reg,
 331                                     shift, 0, &imx_ccm_lock);
 332 }
 333
 334 static inline struct clk_hw *imx_clk_hw_gate_dis(const char *name, const char *parent,
 335                 void __iomem *reg, u8 shift)
 336 {
 337         return clk_hw_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
 338                         shift, CLK_GATE_SET_TO_DISABLE, &imx_ccm_lock);
 339 }
 340
 341 static inline struct clk_hw *imx_clk_hw_gate_dis_flags(const char *name, const char *parent,
 342                 void __iomem *reg, u8 shift, unsigned long flags)
 343 {
 344         return clk_hw_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
 345                         shift, CLK_GATE_SET_TO_DISABLE, &imx_ccm_lock);
 346 }
 347
 348 static inline struct clk_hw *imx_clk_hw_gate2(const char *name, const char *parent,
 349                 void __iomem *reg, u8 shift)
 350 {
 351         return clk_hw_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
 352                         shift, 0x3, 0x3, 0, &imx_ccm_lock, NULL);
 353 }
 354
 355 static inline struct clk_hw *imx_clk_hw_gate2_flags(const char *name, const char *parent,
 356                 void __iomem *reg, u8 shift, unsigned long flags)
 357 {
 358         return clk_hw_register_gate2(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
 359                         shift, 0x3, 0x3, 0, &imx_ccm_lock, NULL);
 360 }
 361
 362 static inline struct clk_hw *imx_clk_hw_gate2_shared(const char *name,
 363                 const char *parent, void __iomem *reg, u8 shift,
 364                 unsigned int *share_count)
 365 {
 366         return clk_hw_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
 367                         shift, 0x3, 0x3, 0, &imx_ccm_lock, share_count);
 368 }
 369
 370 static inline struct clk_hw *imx_clk_hw_gate2_shared2(const char *name,
 371                 const char *parent, void __iomem *reg, u8 shift,
 372                 unsigned int *share_count)
 373 {
 374         return clk_hw_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT |
 375                                   CLK_OPS_PARENT_ENABLE, reg, shift, 0x3, 0x3, 0,
 376                                   &imx_ccm_lock, share_count);
 377 }
 378
 379 static inline struct clk_hw *imx_dev_clk_hw_gate_shared(struct device *dev,
 380                                 const char *name, const char *parent,
 381                                 void __iomem *reg, u8 shift,
 382                                 unsigned int *share_count)
 383 {
 384         return clk_hw_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT |
 385                                         CLK_OPS_PARENT_ENABLE, reg, shift, 0x1,
 386                                         0x1, 0, &imx_ccm_lock, share_count);
 387 }
 388
 389 static inline struct clk *imx_clk_gate2_cgr(const char *name,
 390                 const char *parent, void __iomem *reg, u8 shift, u8 cgr_val)
 391 {
 392         return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
 393                         shift, cgr_val, 0x3, 0, &imx_ccm_lock, NULL);
 394 }
 395
 396 static inline struct clk_hw *imx_clk_hw_gate3(const char *name, const char *parent,
 397                 void __iomem *reg, u8 shift)
 398 {
 399         return clk_hw_register_gate(NULL, name, parent,
 400                         CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
 401                         reg, shift, 0, &imx_ccm_lock);
 402 }
 403
 404 static inline struct clk_hw *imx_clk_hw_gate3_flags(const char *name,
 405                 const char *parent, void __iomem *reg, u8 shift,
 406                 unsigned long flags)
 407 {
 408         return clk_hw_register_gate(NULL, name, parent,
 409                         flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
 410                         reg, shift, 0, &imx_ccm_lock);
 411 }
 412
 413 #define imx_clk_gate3_flags(name, parent, reg, shift, flags) \
 414         to_clk(imx_clk_hw_gate3_flags(name, parent, reg, shift, flags))
 415
 416 static inline struct clk_hw *imx_clk_hw_gate4(const char *name, const char *parent,
 417                 void __iomem *reg, u8 shift)
 418 {
 419         return clk_hw_register_gate2(NULL, name, parent,
 420                         CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
 421                         reg, shift, 0x3, 0x3, 0, &imx_ccm_lock, NULL);
 422 }
 423
 424 static inline struct clk_hw *imx_clk_hw_gate4_flags(const char *name,
 425                 const char *parent, void __iomem *reg, u8 shift,
 426                 unsigned long flags)
 427 {
 428         return clk_hw_register_gate2(NULL, name, parent,
 429                         flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
 430                         reg, shift, 0x3, 0x3, 0, &imx_ccm_lock, NULL);
 431 }
 432
 433 #define imx_clk_gate4_flags(name, parent, reg, shift, flags) \
 434         to_clk(imx_clk_hw_gate4_flags(name, parent, reg, shift, flags))
 435
 436 static inline struct clk_hw *imx_clk_hw_mux(const char *name, void __iomem *reg,
 437                         u8 shift, u8 width, const char * const *parents,
 438                         int num_parents)
 439 {
 440         return clk_hw_register_mux(NULL, name, parents, num_parents,
 441                         CLK_SET_RATE_NO_REPARENT, reg, shift,
 442                         width, 0, &imx_ccm_lock);
 443 }
 444
 445 static inline struct clk_hw *imx_dev_clk_hw_mux(struct device *dev,
 446                         const char *name, void __iomem *reg, u8 shift,
 447                         u8 width, const char * const *parents, int num_parents)
 448 {
 449         return clk_hw_register_mux(dev, name, parents, num_parents,
 450                         CLK_SET_RATE_NO_REPARENT | CLK_SET_PARENT_GATE,
 451                         reg, shift, width, 0, &imx_ccm_lock);
 452 }
 453
 454 static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg,
 455                         u8 shift, u8 width, const char * const *parents,
 456                         int num_parents)
 457 {
 458         return clk_register_mux(NULL, name, parents, num_parents,
 459                         CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE,
 460                         reg, shift, width, 0, &imx_ccm_lock);
 461 }
 462
 463 static inline struct clk_hw *imx_clk_hw_mux2(const char *name, void __iomem *reg,
 464                                              u8 shift, u8 width,
 465                                              const char * const *parents,
 466                                              int num_parents)
 467 {
 468         return clk_hw_register_mux(NULL, name, parents, num_parents,
 469                                    CLK_SET_RATE_NO_REPARENT |
 470                                    CLK_OPS_PARENT_ENABLE,
 471                                    reg, shift, width, 0, &imx_ccm_lock);
 472 }
 473
 474 static inline struct clk *imx_clk_mux_flags(const char *name,
 475                         void __iomem *reg, u8 shift, u8 width,
 476                         const char * const *parents, int num_parents,
 477                         unsigned long flags)
 478 {
 479         return clk_register_mux(NULL, name, parents, num_parents,
 480                         flags | CLK_SET_RATE_NO_REPARENT, reg, shift, width, 0,
 481                         &imx_ccm_lock);
 482 }
 483
 484 static inline struct clk_hw *imx_clk_hw_mux2_flags(const char *name,
 485                 void __iomem *reg, u8 shift, u8 width,
 486                 const char * const *parents,
 487                 int num_parents, unsigned long flags)
 488 {
 489         return clk_hw_register_mux(NULL, name, parents, num_parents,
 490                         flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE,
 491                         reg, shift, width, 0, &imx_ccm_lock);
 492 }
 493
 494 static inline struct clk *imx_clk_mux2_flags(const char *name,
 495                 void __iomem *reg, u8 shift, u8 width,
 496                 const char * const *parents,
 497                 int num_parents, unsigned long flags)
 498 {
 499         return clk_register_mux(NULL, name, parents, num_parents,
 500                         flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE,
 501                         reg, shift, width, 0, &imx_ccm_lock);
 502 }
 503
 504 static inline struct clk_hw *imx_clk_hw_mux_flags(const char *name,
 505                                                   void __iomem *reg, u8 shift,
 506                                                   u8 width,
 507                                                   const char * const *parents,
 508                                                   int num_parents,
 509                                                   unsigned long flags)
 510 {
 511         return clk_hw_register_mux(NULL, name, parents, num_parents,
 512                                    flags | CLK_SET_RATE_NO_REPARENT,
 513                                    reg, shift, width, 0, &imx_ccm_lock);
 514 }
 515
 516 static inline struct clk_hw *imx_dev_clk_hw_mux_flags(struct device *dev,
 517                                                   const char *name,
 518                                                   void __iomem *reg, u8 shift,
 519                                                   u8 width,
 520                                                   const char * const *parents,
 521                                                   int num_parents,
 522                                                   unsigned long flags)
 523 {
 524         return clk_hw_register_mux(dev, name, parents, num_parents,
 525                                    flags | CLK_SET_RATE_NO_REPARENT,
 526                                    reg, shift, width, 0, &imx_ccm_lock);
 527 }
 528
 529 struct clk_hw *imx_clk_hw_cpu(const char *name, const char *parent_name,
 530                 struct clk *div, struct clk *mux, struct clk *pll,
 531                 struct clk *step);
 532
 533 #define IMX_COMPOSITE_CORE      BIT(0)
 534 #define IMX_COMPOSITE_BUS       BIT(1)
 535
 536 struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
 537                                             const char * const *parent_names,
 538                                             int num_parents,
 539                                             void __iomem *reg,
 540                                             u32 composite_flags,
 541                                             unsigned long flags);
 542
 543 #define imx8m_clk_hw_composite_bus(name, parent_names, reg)     \
 544         imx8m_clk_hw_composite_flags(name, parent_names, \
 545                         ARRAY_SIZE(parent_names), reg, \
 546                         IMX_COMPOSITE_BUS, \
 547                         CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
 548
 549 #define imx8m_clk_hw_composite_bus_critical(name, parent_names, reg)    \
 550         imx8m_clk_hw_composite_flags(name, parent_names, ARRAY_SIZE(parent_names), reg, \
 551                         IMX_COMPOSITE_BUS, \
 552                         CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE | CLK_IS_CRITICAL)
 553
 554 #define imx8m_clk_hw_composite_core(name, parent_names, reg)    \
 555         imx8m_clk_hw_composite_flags(name, parent_names, \
 556                         ARRAY_SIZE(parent_names), reg, \
 557                         IMX_COMPOSITE_CORE, \
 558                         CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
 559
 560 #define imx8m_clk_composite_flags(name, parent_names, num_parents, reg, \
 561                                   flags) \
 562         to_clk(imx8m_clk_hw_composite_flags(name, parent_names, \
 563                                 num_parents, reg, 0, flags))
 564
 565 #define __imx8m_clk_hw_composite(name, parent_names, reg, flags) \
 566         imx8m_clk_hw_composite_flags(name, parent_names, \
 567                 ARRAY_SIZE(parent_names), reg, 0, \
 568                 flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
 569
 570 #define __imx8m_clk_composite(name, parent_names, reg, flags) \
 571         to_clk(__imx8m_clk_hw_composite(name, parent_names, reg, flags))
 572
 573 #define imx8m_clk_hw_composite(name, parent_names, reg) \
 574         __imx8m_clk_hw_composite(name, parent_names, reg, 0)
 575
 576 #define imx8m_clk_composite(name, parent_names, reg) \
 577         __imx8m_clk_composite(name, parent_names, reg, 0)
 578
 579 #define imx8m_clk_hw_composite_critical(name, parent_names, reg) \
 580         __imx8m_clk_hw_composite(name, parent_names, reg, CLK_IS_CRITICAL)
 581
 582 #define imx8m_clk_composite_critical(name, parent_names, reg) \
 583         __imx8m_clk_composite(name, parent_names, reg, CLK_IS_CRITICAL)
 584
 585 struct clk_hw *imx_clk_hw_divider_gate(const char *name, const char *parent_name,
 586                 unsigned long flags, void __iomem *reg, u8 shift, u8 width,
 587                 u8 clk_divider_flags, const struct clk_div_table *table,
 588                 spinlock_t *lock);
 589 #endif