1 // SPDX-License-Identifier: GPL-2.0
3 // Copyright (c) 2018 MediaTek Inc.
4 // Author: Weiyi Lu <weiyi.lu@mediatek.com>
6 #include <linux/clk-provider.h>
7 #include <linux/platform_device.h>
12 #include <dt-bindings/clock/mt8183-clk.h>
14 static const struct mtk_gate_regs ipu_core0_cg_regs
= {
20 #define GATE_IPU_CORE0(_id, _name, _parent, _shift) \
21 GATE_MTK(_id, _name, _parent, &ipu_core0_cg_regs, _shift, \
22 &mtk_clk_gate_ops_setclr)
24 static const struct mtk_gate ipu_core0_clks
[] = {
25 GATE_IPU_CORE0(CLK_IPU_CORE0_JTAG
, "ipu_core0_jtag", "dsp_sel", 0),
26 GATE_IPU_CORE0(CLK_IPU_CORE0_AXI
, "ipu_core0_axi", "dsp_sel", 1),
27 GATE_IPU_CORE0(CLK_IPU_CORE0_IPU
, "ipu_core0_ipu", "dsp_sel", 2),
30 static int clk_mt8183_ipu_core0_probe(struct platform_device
*pdev
)
32 struct clk_onecell_data
*clk_data
;
33 struct device_node
*node
= pdev
->dev
.of_node
;
35 clk_data
= mtk_alloc_clk_data(CLK_IPU_CORE0_NR_CLK
);
37 mtk_clk_register_gates(node
, ipu_core0_clks
, ARRAY_SIZE(ipu_core0_clks
),
40 return of_clk_add_provider(node
, of_clk_src_onecell_get
, clk_data
);
43 static const struct of_device_id of_match_clk_mt8183_ipu_core0
[] = {
44 { .compatible
= "mediatek,mt8183-ipu_core0", },
48 static struct platform_driver clk_mt8183_ipu_core0_drv
= {
49 .probe
= clk_mt8183_ipu_core0_probe
,
51 .name
= "clk-mt8183-ipu_core0",
52 .of_match_table
= of_match_clk_mt8183_ipu_core0
,
56 builtin_platform_driver(clk_mt8183_ipu_core0_drv
);