drivers/clk/renesas/renesas-cpg-mssr.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Renesas Clock Pulse Generator / Module Standby and Software Reset
   4  *
   5  * Copyright (C) 2015 Glider bvba
   6  */
   7
   8 #ifndef __CLK_RENESAS_CPG_MSSR_H__
   9 #define __CLK_RENESAS_CPG_MSSR_H__
  10
  11     /*
  12      * Definitions of CPG Core Clocks
  13      *
  14      * These include:
  15      *   - Clock outputs exported to DT
  16      *   - External input clocks
  17      *   - Internal CPG clocks
  18      */
  19
  20 struct cpg_core_clk {
  21         /* Common */
  22         const char *name;
  23         unsigned int id;
  24         unsigned int type;
  25         /* Depending on type */
  26         unsigned int parent;    /* Core Clocks only */
  27         unsigned int div;
  28         unsigned int mult;
  29         unsigned int offset;
  30 };
  31
  32 enum clk_types {
  33         /* Generic */
  34         CLK_TYPE_IN,            /* External Clock Input */
  35         CLK_TYPE_FF,            /* Fixed Factor Clock */
  36         CLK_TYPE_DIV6P1,        /* DIV6 Clock with 1 parent clock */
  37         CLK_TYPE_DIV6_RO,       /* DIV6 Clock read only with extra divisor */
  38         CLK_TYPE_FR,            /* Fixed Rate Clock */
  39
  40         /* Custom definitions start here */
  41         CLK_TYPE_CUSTOM,
  42 };
  43
  44 #define DEF_TYPE(_name, _id, _type...)  \
  45         { .name = _name, .id = _id, .type = _type }
  46 #define DEF_BASE(_name, _id, _type, _parent...) \
  47         DEF_TYPE(_name, _id, _type, .parent = _parent)
  48
  49 #define DEF_INPUT(_name, _id) \
  50         DEF_TYPE(_name, _id, CLK_TYPE_IN)
  51 #define DEF_FIXED(_name, _id, _parent, _div, _mult)     \
  52         DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
  53 #define DEF_DIV6P1(_name, _id, _parent, _offset)        \
  54         DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
  55 #define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \
  56         DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1)
  57 #define DEF_RATE(_name, _id, _rate)     \
  58         DEF_TYPE(_name, _id, CLK_TYPE_FR, .mult = _rate)
  59
  60     /*
  61      * Definitions of Module Clocks
  62      */
  63
  64 struct mssr_mod_clk {
  65         const char *name;
  66         unsigned int id;
  67         unsigned int parent;    /* Add MOD_CLK_BASE for Module Clocks */
  68 };
  69
  70 /* Convert from sparse base-100 to packed index space */
  71 #define MOD_CLK_PACK(x) ((x) - ((x) / 100) * (100 - 32))
  72
  73 #define MOD_CLK_ID(x)   (MOD_CLK_BASE + MOD_CLK_PACK(x))
  74
  75 #define DEF_MOD(_name, _mod, _parent...)        \
  76         { .name = _name, .id = MOD_CLK_ID(_mod), .parent = _parent }
  77
  78 /* Convert from sparse base-10 to packed index space */
  79 #define MOD_CLK_PACK_10(x)      ((x / 10) * 32 + (x % 10))
  80
  81 #define MOD_CLK_ID_10(x)        (MOD_CLK_BASE + MOD_CLK_PACK_10(x))
  82
  83 #define DEF_MOD_STB(_name, _mod, _parent...)    \
  84         { .name = _name, .id = MOD_CLK_ID_10(_mod), .parent = _parent }
  85
  86 struct device_node;
  87
  88 enum clk_reg_layout {
  89         CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3 = 0,
  90         CLK_REG_LAYOUT_RZ_A,
  91         CLK_REG_LAYOUT_RCAR_V3U,
  92 };
  93
  94     /**
  95      * SoC-specific CPG/MSSR Description
  96      *
  97      * @early_core_clks: Array of Early Core Clock definitions
  98      * @num_early_core_clks: Number of entries in early_core_clks[]
  99      * @early_mod_clks: Array of Early Module Clock definitions
 100      * @num_early_mod_clks: Number of entries in early_mod_clks[]
 101      *
 102      * @core_clks: Array of Core Clock definitions
 103      * @num_core_clks: Number of entries in core_clks[]
 104      * @last_dt_core_clk: ID of the last Core Clock exported to DT
 105      * @num_total_core_clks: Total number of Core Clocks (exported + internal)
 106      *
 107      * @mod_clks: Array of Module Clock definitions
 108      * @num_mod_clks: Number of entries in mod_clks[]
 109      * @num_hw_mod_clks: Number of Module Clocks supported by the hardware
 110      *
 111      * @crit_mod_clks: Array with Module Clock IDs of critical clocks that
 112      *                 should not be disabled without a knowledgeable driver
 113      * @num_crit_mod_clks: Number of entries in crit_mod_clks[]
 114      * @reg_layout: CPG/MSSR register layout from enum clk_reg_layout
 115      *
 116      * @core_pm_clks: Array with IDs of Core Clocks that are suitable for Power
 117      *                Management, in addition to Module Clocks
 118      * @num_core_pm_clks: Number of entries in core_pm_clks[]
 119      *
 120      * @init: Optional callback to perform SoC-specific initialization
 121      * @cpg_clk_register: Optional callback to handle special Core Clock types
 122      */
 123
 124 struct cpg_mssr_info {
 125         /* Early Clocks */
 126         const struct cpg_core_clk *early_core_clks;
 127         unsigned int num_early_core_clks;
 128         const struct mssr_mod_clk *early_mod_clks;
 129         unsigned int num_early_mod_clks;
 130
 131         /* Core Clocks */
 132         const struct cpg_core_clk *core_clks;
 133         unsigned int num_core_clks;
 134         unsigned int last_dt_core_clk;
 135         unsigned int num_total_core_clks;
 136         enum clk_reg_layout reg_layout;
 137
 138         /* Module Clocks */
 139         const struct mssr_mod_clk *mod_clks;
 140         unsigned int num_mod_clks;
 141         unsigned int num_hw_mod_clks;
 142
 143         /* Critical Module Clocks that should not be disabled */
 144         const unsigned int *crit_mod_clks;
 145         unsigned int num_crit_mod_clks;
 146
 147         /* Core Clocks suitable for PM, in addition to the Module Clocks */
 148         const unsigned int *core_pm_clks;
 149         unsigned int num_core_pm_clks;
 150
 151         /* Callbacks */
 152         int (*init)(struct device *dev);
 153         struct clk *(*cpg_clk_register)(struct device *dev,
 154                                         const struct cpg_core_clk *core,
 155                                         const struct cpg_mssr_info *info,
 156                                         struct clk **clks, void __iomem *base,
 157                                         struct raw_notifier_head *notifiers);
 158 };
 159
 160 extern const struct cpg_mssr_info r7s9210_cpg_mssr_info;
 161 extern const struct cpg_mssr_info r8a7742_cpg_mssr_info;
 162 extern const struct cpg_mssr_info r8a7743_cpg_mssr_info;
 163 extern const struct cpg_mssr_info r8a7745_cpg_mssr_info;
 164 extern const struct cpg_mssr_info r8a77470_cpg_mssr_info;
 165 extern const struct cpg_mssr_info r8a774a1_cpg_mssr_info;
 166 extern const struct cpg_mssr_info r8a774b1_cpg_mssr_info;
 167 extern const struct cpg_mssr_info r8a774c0_cpg_mssr_info;
 168 extern const struct cpg_mssr_info r8a774e1_cpg_mssr_info;
 169 extern const struct cpg_mssr_info r8a7790_cpg_mssr_info;
 170 extern const struct cpg_mssr_info r8a7791_cpg_mssr_info;
 171 extern const struct cpg_mssr_info r8a7792_cpg_mssr_info;
 172 extern const struct cpg_mssr_info r8a7794_cpg_mssr_info;
 173 extern const struct cpg_mssr_info r8a7795_cpg_mssr_info;
 174 extern const struct cpg_mssr_info r8a7796_cpg_mssr_info;
 175 extern const struct cpg_mssr_info r8a77965_cpg_mssr_info;
 176 extern const struct cpg_mssr_info r8a77970_cpg_mssr_info;
 177 extern const struct cpg_mssr_info r8a77980_cpg_mssr_info;
 178 extern const struct cpg_mssr_info r8a77990_cpg_mssr_info;
 179 extern const struct cpg_mssr_info r8a77995_cpg_mssr_info;
 180 extern const struct cpg_mssr_info r8a779a0_cpg_mssr_info;
 181
 182 void __init cpg_mssr_early_init(struct device_node *np,
 183                                 const struct cpg_mssr_info *info);
 184
 185     /*
 186      * Helpers for fixing up clock tables depending on SoC revision
 187      */
 188
 189 struct mssr_mod_reparent {
 190         unsigned int clk, parent;
 191 };
 192
 193
 194 extern void cpg_core_nullify_range(struct cpg_core_clk *core_clks,
 195                                    unsigned int num_core_clks,
 196                                    unsigned int first_clk,
 197                                    unsigned int last_clk);
 198 extern void mssr_mod_nullify(struct mssr_mod_clk *mod_clks,
 199                              unsigned int num_mod_clks,
 200                              const unsigned int *clks, unsigned int n);
 201 extern void mssr_mod_reparent(struct mssr_mod_clk *mod_clks,
 202                               unsigned int num_mod_clks,
 203                               const struct mssr_mod_reparent *clks,
 204                               unsigned int n);
 205 #endif