drivers/clk/sunxi-ng/ccu-sun8i-a83t.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * Copyright 2016 Chen-Yu Tsai
   4  *
   5  * Chen-Yu Tsai <wens@csie.org>
   6  */
   7
   8 #ifndef _CCU_SUN8I_A83T_H_
   9 #define _CCU_SUN8I_A83T_H_
  10
  11 #include <dt-bindings/clock/sun8i-a83t-ccu.h>
  12 #include <dt-bindings/reset/sun8i-a83t-ccu.h>
  13
  14 #define CLK_PLL_C0CPUX          0
  15 #define CLK_PLL_C1CPUX          1
  16 #define CLK_PLL_AUDIO           2
  17 #define CLK_PLL_VIDEO0          3
  18 #define CLK_PLL_VE              4
  19 #define CLK_PLL_DDR             5
  20
  21 /* pll-periph is exported to the PRCM block */
  22
  23 #define CLK_PLL_GPU             7
  24 #define CLK_PLL_HSIC            8
  25
  26 /* pll-de is exported for the display engine */
  27
  28 #define CLK_PLL_VIDEO1          10
  29
  30 /* The CPUX clocks are exported */
  31
  32 #define CLK_AXI0                13
  33 #define CLK_AXI1                14
  34 #define CLK_AHB1                15
  35 #define CLK_AHB2                16
  36 #define CLK_APB1                17
  37 #define CLK_APB2                18
  38
  39 /* bus gates exported */
  40
  41 #define CLK_CCI400              58
  42
  43 /* module and usb clocks exported */
  44
  45 #define CLK_DRAM                82
  46
  47 /* dram gates and more module clocks exported */
  48
  49 #define CLK_MBUS                95
  50
  51 /* more module clocks exported */
  52
  53 #define CLK_NUMBER              (CLK_GPU_HYD + 1)
  54
  55 #endif /* _CCU_SUN8I_A83T_H_ */