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Merge tag 'block-5.11-2021-01-10' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / clk / ti / adpll.c
blobbb2f2836dab22cf82b1c067d2f0951900756574a
1 /*
2 * This program is free software; you can redistribute it and/or
3 * modify it under the terms of the GNU General Public License as
4 * published by the Free Software Foundation version 2.
5 *
6 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
7 * kind, whether express or implied; without even the implied warranty
8 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 */
11
12 #include <linux/clk.h>
13 #include <linux/clkdev.h>
14 #include <linux/clk-provider.h>
15 #include <linux/delay.h>
16 #include <linux/err.h>
17 #include <linux/io.h>
18 #include <linux/math64.h>
19 #include <linux/module.h>
20 #include <linux/of_device.h>
21 #include <linux/string.h>
22
23 #define ADPLL_PLLSS_MMR_LOCK_OFFSET 0x00 /* Managed by MPPULL */
24 #define ADPLL_PLLSS_MMR_LOCK_ENABLED 0x1f125B64
25 #define ADPLL_PLLSS_MMR_UNLOCK_MAGIC 0x1eda4c3d
26
27 #define ADPLL_PWRCTRL_OFFSET 0x00
28 #define ADPLL_PWRCTRL_PONIN 5
29 #define ADPLL_PWRCTRL_PGOODIN 4
30 #define ADPLL_PWRCTRL_RET 3
31 #define ADPLL_PWRCTRL_ISORET 2
32 #define ADPLL_PWRCTRL_ISOSCAN 1
33 #define ADPLL_PWRCTRL_OFFMODE 0
34
35 #define ADPLL_CLKCTRL_OFFSET 0x04
36 #define ADPLL_CLKCTRL_CLKDCOLDOEN 29
37 #define ADPLL_CLKCTRL_IDLE 23
38 #define ADPLL_CLKCTRL_CLKOUTEN 20
39 #define ADPLL_CLKINPHIFSEL_ADPLL_S 19 /* REVISIT: which bit? */
40 #define ADPLL_CLKCTRL_CLKOUTLDOEN_ADPLL_LJ 19
41 #define ADPLL_CLKCTRL_ULOWCLKEN 18
42 #define ADPLL_CLKCTRL_CLKDCOLDOPWDNZ 17
43 #define ADPLL_CLKCTRL_M2PWDNZ 16
44 #define ADPLL_CLKCTRL_M3PWDNZ_ADPLL_S 15
45 #define ADPLL_CLKCTRL_LOWCURRSTDBY_ADPLL_S 13
46 #define ADPLL_CLKCTRL_LPMODE_ADPLL_S 12
47 #define ADPLL_CLKCTRL_REGM4XEN_ADPLL_S 10
48 #define ADPLL_CLKCTRL_SELFREQDCO_ADPLL_LJ 10
49 #define ADPLL_CLKCTRL_TINITZ 0
50
51 #define ADPLL_TENABLE_OFFSET 0x08
52 #define ADPLL_TENABLEDIV_OFFSET 0x8c
53
54 #define ADPLL_M2NDIV_OFFSET 0x10
55 #define ADPLL_M2NDIV_M2 16
56 #define ADPLL_M2NDIV_M2_ADPLL_S_WIDTH 5
57 #define ADPLL_M2NDIV_M2_ADPLL_LJ_WIDTH 7
58
59 #define ADPLL_MN2DIV_OFFSET 0x14
60 #define ADPLL_MN2DIV_N2 16
61
62 #define ADPLL_FRACDIV_OFFSET 0x18
63 #define ADPLL_FRACDIV_REGSD 24
64 #define ADPLL_FRACDIV_FRACTIONALM 0
65 #define ADPLL_FRACDIV_FRACTIONALM_MASK 0x3ffff
66
67 #define ADPLL_BWCTRL_OFFSET 0x1c
68 #define ADPLL_BWCTRL_BWCONTROL 1
69 #define ADPLL_BWCTRL_BW_INCR_DECRZ 0
70
71 #define ADPLL_RESERVED_OFFSET 0x20
72
73 #define ADPLL_STATUS_OFFSET 0x24
74 #define ADPLL_STATUS_PONOUT 31
75 #define ADPLL_STATUS_PGOODOUT 30
76 #define ADPLL_STATUS_LDOPWDN 29
77 #define ADPLL_STATUS_RECAL_BSTATUS3 28
78 #define ADPLL_STATUS_RECAL_OPPIN 27
79 #define ADPLL_STATUS_PHASELOCK 10
80 #define ADPLL_STATUS_FREQLOCK 9
81 #define ADPLL_STATUS_BYPASSACK 8
82 #define ADPLL_STATUS_LOSSREF 6
83 #define ADPLL_STATUS_CLKOUTENACK 5
84 #define ADPLL_STATUS_LOCK2 4
85 #define ADPLL_STATUS_M2CHANGEACK 3
86 #define ADPLL_STATUS_HIGHJITTER 1
87 #define ADPLL_STATUS_BYPASS 0
88 #define ADPLL_STATUS_PREPARED_MASK (BIT(ADPLL_STATUS_PHASELOCK) | \
89 BIT(ADPLL_STATUS_FREQLOCK))
90
91 #define ADPLL_M3DIV_OFFSET 0x28 /* Only on MPUPLL */
92 #define ADPLL_M3DIV_M3 0
93 #define ADPLL_M3DIV_M3_WIDTH 5
94 #define ADPLL_M3DIV_M3_MASK 0x1f
95
96 #define ADPLL_RAMPCTRL_OFFSET 0x2c /* Only on MPUPLL */
97 #define ADPLL_RAMPCTRL_CLKRAMPLEVEL 19
98 #define ADPLL_RAMPCTRL_CLKRAMPRATE 16
99 #define ADPLL_RAMPCTRL_RELOCK_RAMP_EN 0
100
101 #define MAX_ADPLL_INPUTS 3
102 #define MAX_ADPLL_OUTPUTS 4
103 #define ADPLL_MAX_RETRIES 5
104
105 #define to_dco(_hw) container_of(_hw, struct ti_adpll_dco_data, hw)
106 #define to_adpll(_hw) container_of(_hw, struct ti_adpll_data, dco)
107 #define to_clkout(_hw) container_of(_hw, struct ti_adpll_clkout_data, hw)
108
109 enum ti_adpll_clocks {
110 TI_ADPLL_DCO,
111 TI_ADPLL_DCO_GATE,
112 TI_ADPLL_N2,
113 TI_ADPLL_M2,
114 TI_ADPLL_M2_GATE,
115 TI_ADPLL_BYPASS,
116 TI_ADPLL_HIF,
117 TI_ADPLL_DIV2,
118 TI_ADPLL_CLKOUT,
119 TI_ADPLL_CLKOUT2,
120 TI_ADPLL_M3,
121 };
122
123 #define TI_ADPLL_NR_CLOCKS (TI_ADPLL_M3 + 1)
124
125 enum ti_adpll_inputs {
126 TI_ADPLL_CLKINP,
127 TI_ADPLL_CLKINPULOW,
128 TI_ADPLL_CLKINPHIF,
129 };
130
131 enum ti_adpll_s_outputs {
132 TI_ADPLL_S_DCOCLKLDO,
133 TI_ADPLL_S_CLKOUT,
134 TI_ADPLL_S_CLKOUTX2,
135 TI_ADPLL_S_CLKOUTHIF,
136 };
137
138 enum ti_adpll_lj_outputs {
139 TI_ADPLL_LJ_CLKDCOLDO,
140 TI_ADPLL_LJ_CLKOUT,
141 TI_ADPLL_LJ_CLKOUTLDO,
142 };
143
144 struct ti_adpll_platform_data {
145 const bool is_type_s;
146 const int nr_max_inputs;
147 const int nr_max_outputs;
148 const int output_index;
149 };
150
151 struct ti_adpll_clock {
152 struct clk *clk;
153 struct clk_lookup *cl;
154 void (*unregister)(struct clk *clk);
155 };
156
157 struct ti_adpll_dco_data {
158 struct clk_hw hw;
159 };
160
161 struct ti_adpll_clkout_data {
162 struct ti_adpll_data *adpll;
163 struct clk_gate gate;
164 struct clk_hw hw;
165 };
166
167 struct ti_adpll_data {
168 struct device *dev;
169 const struct ti_adpll_platform_data *c;
170 struct device_node *np;
171 unsigned long pa;
172 void __iomem *iobase;
173 void __iomem *regs;
174 spinlock_t lock; /* For ADPLL shared register access */
175 const char *parent_names[MAX_ADPLL_INPUTS];
176 struct clk *parent_clocks[MAX_ADPLL_INPUTS];
177 struct ti_adpll_clock *clocks;
178 struct clk_onecell_data outputs;
179 struct ti_adpll_dco_data dco;
180 };
181
182 static const char *ti_adpll_clk_get_name(struct ti_adpll_data *d,
183 int output_index,
184 const char *postfix)
185 {
186 const char *name;
187 int err;
188
189 if (output_index >= 0) {
190 err = of_property_read_string_index(d->np,
191 "clock-output-names",
192 output_index,
193 &name);
194 if (err)
195 return NULL;
196 } else {
197 name = devm_kasprintf(d->dev, GFP_KERNEL, "%08lx.adpll.%s",
198 d->pa, postfix);
199 }
200
201 return name;
202 }
203
204 #define ADPLL_MAX_CON_ID 16 /* See MAX_CON_ID */
205
206 static int ti_adpll_setup_clock(struct ti_adpll_data *d, struct clk *clock,
207 int index, int output_index, const char *name,
208 void (*unregister)(struct clk *clk))
209 {
210 struct clk_lookup *cl;
211 const char *postfix = NULL;
212 char con_id[ADPLL_MAX_CON_ID];
213
214 d->clocks[index].clk = clock;
215 d->clocks[index].unregister = unregister;
216
217 /* Separate con_id in format "pll040dcoclkldo" to fit MAX_CON_ID */
218 postfix = strrchr(name, '.');
219 if (postfix && strlen(postfix) > 1) {
220 if (strlen(postfix) > ADPLL_MAX_CON_ID)
221 dev_warn(d->dev, "clock %s con_id lookup may fail\n",
222 name);
223 snprintf(con_id, 16, "pll%03lx%s", d->pa & 0xfff, postfix + 1);
224 cl = clkdev_create(clock, con_id, NULL);
225 if (!cl)
226 return -ENOMEM;
227 d->clocks[index].cl = cl;
228 } else {
229 dev_warn(d->dev, "no con_id for clock %s\n", name);
230 }
231
232 if (output_index < 0)
233 return 0;
234
235 d->outputs.clks[output_index] = clock;
236 d->outputs.clk_num++;
237
238 return 0;
239 }
240
241 static int ti_adpll_init_divider(struct ti_adpll_data *d,
242 enum ti_adpll_clocks index,
243 int output_index, char *name,
244 struct clk *parent_clock,
245 void __iomem *reg,
246 u8 shift, u8 width,
247 u8 clk_divider_flags)
248 {
249 const char *child_name;
250 const char *parent_name;
251 struct clk *clock;
252
253 child_name = ti_adpll_clk_get_name(d, output_index, name);
254 if (!child_name)
255 return -EINVAL;
256
257 parent_name = __clk_get_name(parent_clock);
258 clock = clk_register_divider(d->dev, child_name, parent_name, 0,
259 reg, shift, width, clk_divider_flags,
260 &d->lock);
261 if (IS_ERR(clock)) {
262 dev_err(d->dev, "failed to register divider %s: %li\n",
263 name, PTR_ERR(clock));
264 return PTR_ERR(clock);
265 }
266
267 return ti_adpll_setup_clock(d, clock, index, output_index, child_name,
268 clk_unregister_divider);
269 }
270
271 static int ti_adpll_init_mux(struct ti_adpll_data *d,
272 enum ti_adpll_clocks index,
273 char *name, struct clk *clk0,
274 struct clk *clk1,
275 void __iomem *reg,
276 u8 shift)
277 {
278 const char *child_name;
279 const char *parents[2];
280 struct clk *clock;
281
282 child_name = ti_adpll_clk_get_name(d, -ENODEV, name);
283 if (!child_name)
284 return -ENOMEM;
285 parents[0] = __clk_get_name(clk0);
286 parents[1] = __clk_get_name(clk1);
287 clock = clk_register_mux(d->dev, child_name, parents, 2, 0,
288 reg, shift, 1, 0, &d->lock);
289 if (IS_ERR(clock)) {
290 dev_err(d->dev, "failed to register mux %s: %li\n",
291 name, PTR_ERR(clock));
292 return PTR_ERR(clock);
293 }
294
295 return ti_adpll_setup_clock(d, clock, index, -ENODEV, child_name,
296 clk_unregister_mux);
297 }
298
299 static int ti_adpll_init_gate(struct ti_adpll_data *d,
300 enum ti_adpll_clocks index,
301 int output_index, char *name,
302 struct clk *parent_clock,
303 void __iomem *reg,
304 u8 bit_idx,
305 u8 clk_gate_flags)
306 {
307 const char *child_name;
308 const char *parent_name;
309 struct clk *clock;
310
311 child_name = ti_adpll_clk_get_name(d, output_index, name);
312 if (!child_name)
313 return -EINVAL;
314
315 parent_name = __clk_get_name(parent_clock);
316 clock = clk_register_gate(d->dev, child_name, parent_name, 0,
317 reg, bit_idx, clk_gate_flags,
318 &d->lock);
319 if (IS_ERR(clock)) {
320 dev_err(d->dev, "failed to register gate %s: %li\n",
321 name, PTR_ERR(clock));
322 return PTR_ERR(clock);
323 }
324
325 return ti_adpll_setup_clock(d, clock, index, output_index, child_name,
326 clk_unregister_gate);
327 }
328
329 static int ti_adpll_init_fixed_factor(struct ti_adpll_data *d,
330 enum ti_adpll_clocks index,
331 char *name,
332 struct clk *parent_clock,
333 unsigned int mult,
334 unsigned int div)
335 {
336 const char *child_name;
337 const char *parent_name;
338 struct clk *clock;
339
340 child_name = ti_adpll_clk_get_name(d, -ENODEV, name);
341 if (!child_name)
342 return -ENOMEM;
343
344 parent_name = __clk_get_name(parent_clock);
345 clock = clk_register_fixed_factor(d->dev, child_name, parent_name,
346 0, mult, div);
347 if (IS_ERR(clock))
348 return PTR_ERR(clock);
349
350 return ti_adpll_setup_clock(d, clock, index, -ENODEV, child_name,
351 clk_unregister);
352 }
353
354 static void ti_adpll_set_idle_bypass(struct ti_adpll_data *d)
355 {
356 unsigned long flags;
357 u32 v;
358
359 spin_lock_irqsave(&d->lock, flags);
360 v = readl_relaxed(d->regs + ADPLL_CLKCTRL_OFFSET);
361 v |= BIT(ADPLL_CLKCTRL_IDLE);
362 writel_relaxed(v, d->regs + ADPLL_CLKCTRL_OFFSET);
363 spin_unlock_irqrestore(&d->lock, flags);
364 }
365
366 static void ti_adpll_clear_idle_bypass(struct ti_adpll_data *d)
367 {
368 unsigned long flags;
369 u32 v;
370
371 spin_lock_irqsave(&d->lock, flags);
372 v = readl_relaxed(d->regs + ADPLL_CLKCTRL_OFFSET);
373 v &= ~BIT(ADPLL_CLKCTRL_IDLE);
374 writel_relaxed(v, d->regs + ADPLL_CLKCTRL_OFFSET);
375 spin_unlock_irqrestore(&d->lock, flags);
376 }
377
378 static bool ti_adpll_clock_is_bypass(struct ti_adpll_data *d)
379 {
380 u32 v;
381
382 v = readl_relaxed(d->regs + ADPLL_STATUS_OFFSET);
383
384 return v & BIT(ADPLL_STATUS_BYPASS);
385 }
386
387 /*
388 * Locked and bypass are not actually mutually exclusive: if you only care
389 * about the DCO clock and not CLKOUT you can clear M2PWDNZ before enabling
390 * the PLL, resulting in status (FREQLOCK | PHASELOCK | BYPASS) after lock.
391 */
392 static bool ti_adpll_is_locked(struct ti_adpll_data *d)
393 {
394 u32 v = readl_relaxed(d->regs + ADPLL_STATUS_OFFSET);
395
396 return (v & ADPLL_STATUS_PREPARED_MASK) == ADPLL_STATUS_PREPARED_MASK;
397 }
398
399 static int ti_adpll_wait_lock(struct ti_adpll_data *d)
400 {
401 int retries = ADPLL_MAX_RETRIES;
402
403 do {
404 if (ti_adpll_is_locked(d))
405 return 0;
406 usleep_range(200, 300);
407 } while (retries--);
408
409 dev_err(d->dev, "pll failed to lock\n");
410 return -ETIMEDOUT;
411 }
412
413 static int ti_adpll_prepare(struct clk_hw *hw)
414 {
415 struct ti_adpll_dco_data *dco = to_dco(hw);
416 struct ti_adpll_data *d = to_adpll(dco);
417
418 ti_adpll_clear_idle_bypass(d);
419 ti_adpll_wait_lock(d);
420
421 return 0;
422 }
423
424 static void ti_adpll_unprepare(struct clk_hw *hw)
425 {
426 struct ti_adpll_dco_data *dco = to_dco(hw);
427 struct ti_adpll_data *d = to_adpll(dco);
428
429 ti_adpll_set_idle_bypass(d);
430 }
431
432 static int ti_adpll_is_prepared(struct clk_hw *hw)
433 {
434 struct ti_adpll_dco_data *dco = to_dco(hw);
435 struct ti_adpll_data *d = to_adpll(dco);
436
437 return ti_adpll_is_locked(d);
438 }
439
440 /*
441 * Note that the DCO clock is never subject to bypass: if the PLL is off,
442 * dcoclk is low.
443 */
444 static unsigned long ti_adpll_recalc_rate(struct clk_hw *hw,
445 unsigned long parent_rate)
446 {
447 struct ti_adpll_dco_data *dco = to_dco(hw);
448 struct ti_adpll_data *d = to_adpll(dco);
449 u32 frac_m, divider, v;
450 u64 rate;
451 unsigned long flags;
452
453 if (ti_adpll_clock_is_bypass(d))
454 return 0;
455
456 spin_lock_irqsave(&d->lock, flags);
457 frac_m = readl_relaxed(d->regs + ADPLL_FRACDIV_OFFSET);
458 frac_m &= ADPLL_FRACDIV_FRACTIONALM_MASK;
459 rate = (u64)readw_relaxed(d->regs + ADPLL_MN2DIV_OFFSET) << 18;
460 rate += frac_m;
461 rate *= parent_rate;
462 divider = (readw_relaxed(d->regs + ADPLL_M2NDIV_OFFSET) + 1) << 18;
463 spin_unlock_irqrestore(&d->lock, flags);
464
465 do_div(rate, divider);
466
467 if (d->c->is_type_s) {
468 v = readl_relaxed(d->regs + ADPLL_CLKCTRL_OFFSET);
469 if (v & BIT(ADPLL_CLKCTRL_REGM4XEN_ADPLL_S))
470 rate *= 4;
471 rate *= 2;
472 }
473
474 return rate;
475 }
476
477 /* PLL parent is always clkinp, bypass only affects the children */
478 static u8 ti_adpll_get_parent(struct clk_hw *hw)
479 {
480 return 0;
481 }
482
483 static const struct clk_ops ti_adpll_ops = {
484 .prepare = ti_adpll_prepare,
485 .unprepare = ti_adpll_unprepare,
486 .is_prepared = ti_adpll_is_prepared,
487 .recalc_rate = ti_adpll_recalc_rate,
488 .get_parent = ti_adpll_get_parent,
489 };
490
491 static int ti_adpll_init_dco(struct ti_adpll_data *d)
492 {
493 struct clk_init_data init;
494 struct clk *clock;
495 const char *postfix;
496 int width, err;
497
498 d->outputs.clks = devm_kcalloc(d->dev,
499 MAX_ADPLL_OUTPUTS,
500 sizeof(struct clk *),
501 GFP_KERNEL);
502 if (!d->outputs.clks)
503 return -ENOMEM;
504
505 if (d->c->output_index < 0)
506 postfix = "dco";
507 else
508 postfix = NULL;
509
510 init.name = ti_adpll_clk_get_name(d, d->c->output_index, postfix);
511 if (!init.name)
512 return -EINVAL;
513
514 init.parent_names = d->parent_names;
515 init.num_parents = d->c->nr_max_inputs;
516 init.ops = &ti_adpll_ops;
517 init.flags = CLK_GET_RATE_NOCACHE;
518 d->dco.hw.init = &init;
519
520 if (d->c->is_type_s)
521 width = 5;
522 else
523 width = 4;
524
525 /* Internal input clock divider N2 */
526 err = ti_adpll_init_divider(d, TI_ADPLL_N2, -ENODEV, "n2",
527 d->parent_clocks[TI_ADPLL_CLKINP],
528 d->regs + ADPLL_MN2DIV_OFFSET,
529 ADPLL_MN2DIV_N2, width, 0);
530 if (err)
531 return err;
532
533 clock = devm_clk_register(d->dev, &d->dco.hw);
534 if (IS_ERR(clock))
535 return PTR_ERR(clock);
536
537 return ti_adpll_setup_clock(d, clock, TI_ADPLL_DCO, d->c->output_index,
538 init.name, NULL);
539 }
540
541 static int ti_adpll_clkout_enable(struct clk_hw *hw)
542 {
543 struct ti_adpll_clkout_data *co = to_clkout(hw);
544 struct clk_hw *gate_hw = &co->gate.hw;
545
546 __clk_hw_set_clk(gate_hw, hw);
547
548 return clk_gate_ops.enable(gate_hw);
549 }
550
551 static void ti_adpll_clkout_disable(struct clk_hw *hw)
552 {
553 struct ti_adpll_clkout_data *co = to_clkout(hw);
554 struct clk_hw *gate_hw = &co->gate.hw;
555
556 __clk_hw_set_clk(gate_hw, hw);
557 clk_gate_ops.disable(gate_hw);
558 }
559
560 static int ti_adpll_clkout_is_enabled(struct clk_hw *hw)
561 {
562 struct ti_adpll_clkout_data *co = to_clkout(hw);
563 struct clk_hw *gate_hw = &co->gate.hw;
564
565 __clk_hw_set_clk(gate_hw, hw);
566
567 return clk_gate_ops.is_enabled(gate_hw);
568 }
569
570 /* Setting PLL bypass puts clkout and clkoutx2 into bypass */
571 static u8 ti_adpll_clkout_get_parent(struct clk_hw *hw)
572 {
573 struct ti_adpll_clkout_data *co = to_clkout(hw);
574 struct ti_adpll_data *d = co->adpll;
575
576 return ti_adpll_clock_is_bypass(d);
577 }
578
579 static int ti_adpll_init_clkout(struct ti_adpll_data *d,
580 enum ti_adpll_clocks index,
581 int output_index, int gate_bit,
582 char *name, struct clk *clk0,
583 struct clk *clk1)
584 {
585 struct ti_adpll_clkout_data *co;
586 struct clk_init_data init;
587 struct clk_ops *ops;
588 const char *parent_names[2];
589 const char *child_name;
590 struct clk *clock;
591 int err;
592
593 co = devm_kzalloc(d->dev, sizeof(*co), GFP_KERNEL);
594 if (!co)
595 return -ENOMEM;
596 co->adpll = d;
597
598 err = of_property_read_string_index(d->np,
599 "clock-output-names",
600 output_index,
601 &child_name);
602 if (err)
603 return err;
604
605 ops = devm_kzalloc(d->dev, sizeof(*ops), GFP_KERNEL);
606 if (!ops)
607 return -ENOMEM;
608
609 init.name = child_name;
610 init.ops = ops;
611 init.flags = 0;
612 co->hw.init = &init;
613 parent_names[0] = __clk_get_name(clk0);
614 parent_names[1] = __clk_get_name(clk1);
615 init.parent_names = parent_names;
616 init.num_parents = 2;
617
618 ops->get_parent = ti_adpll_clkout_get_parent;
619 ops->determine_rate = __clk_mux_determine_rate;
620 if (gate_bit) {
621 co->gate.lock = &d->lock;
622 co->gate.reg = d->regs + ADPLL_CLKCTRL_OFFSET;
623 co->gate.bit_idx = gate_bit;
624 ops->enable = ti_adpll_clkout_enable;
625 ops->disable = ti_adpll_clkout_disable;
626 ops->is_enabled = ti_adpll_clkout_is_enabled;
627 }
628
629 clock = devm_clk_register(d->dev, &co->hw);
630 if (IS_ERR(clock)) {
631 dev_err(d->dev, "failed to register output %s: %li\n",
632 name, PTR_ERR(clock));
633 return PTR_ERR(clock);
634 }
635
636 return ti_adpll_setup_clock(d, clock, index, output_index, child_name,
637 NULL);
638 }
639
640 static int ti_adpll_init_children_adpll_s(struct ti_adpll_data *d)
641 {
642 int err;
643
644 if (!d->c->is_type_s)
645 return 0;
646
647 /* Internal mux, sources from divider N2 or clkinpulow */
648 err = ti_adpll_init_mux(d, TI_ADPLL_BYPASS, "bypass",
649 d->clocks[TI_ADPLL_N2].clk,
650 d->parent_clocks[TI_ADPLL_CLKINPULOW],
651 d->regs + ADPLL_CLKCTRL_OFFSET,
652 ADPLL_CLKCTRL_ULOWCLKEN);
653 if (err)
654 return err;
655
656 /* Internal divider M2, sources DCO */
657 err = ti_adpll_init_divider(d, TI_ADPLL_M2, -ENODEV, "m2",
658 d->clocks[TI_ADPLL_DCO].clk,
659 d->regs + ADPLL_M2NDIV_OFFSET,
660 ADPLL_M2NDIV_M2,
661 ADPLL_M2NDIV_M2_ADPLL_S_WIDTH,
662 CLK_DIVIDER_ONE_BASED);
663 if (err)
664 return err;
665
666 /* Internal fixed divider, after M2 before clkout */
667 err = ti_adpll_init_fixed_factor(d, TI_ADPLL_DIV2, "div2",
668 d->clocks[TI_ADPLL_M2].clk,
669 1, 2);
670 if (err)
671 return err;
672
673 /* Output clkout with a mux and gate, sources from div2 or bypass */
674 err = ti_adpll_init_clkout(d, TI_ADPLL_CLKOUT, TI_ADPLL_S_CLKOUT,
675 ADPLL_CLKCTRL_CLKOUTEN, "clkout",
676 d->clocks[TI_ADPLL_DIV2].clk,
677 d->clocks[TI_ADPLL_BYPASS].clk);
678 if (err)
679 return err;
680
681 /* Output clkoutx2 with a mux and gate, sources from M2 or bypass */
682 err = ti_adpll_init_clkout(d, TI_ADPLL_CLKOUT2, TI_ADPLL_S_CLKOUTX2, 0,
683 "clkout2", d->clocks[TI_ADPLL_M2].clk,
684 d->clocks[TI_ADPLL_BYPASS].clk);
685 if (err)
686 return err;
687
688 /* Internal mux, sources from DCO and clkinphif */
689 if (d->parent_clocks[TI_ADPLL_CLKINPHIF]) {
690 err = ti_adpll_init_mux(d, TI_ADPLL_HIF, "hif",
691 d->clocks[TI_ADPLL_DCO].clk,
692 d->parent_clocks[TI_ADPLL_CLKINPHIF],
693 d->regs + ADPLL_CLKCTRL_OFFSET,
694 ADPLL_CLKINPHIFSEL_ADPLL_S);
695 if (err)
696 return err;
697 }
698
699 /* Output clkouthif with a divider M3, sources from hif */
700 err = ti_adpll_init_divider(d, TI_ADPLL_M3, TI_ADPLL_S_CLKOUTHIF, "m3",
701 d->clocks[TI_ADPLL_HIF].clk,
702 d->regs + ADPLL_M3DIV_OFFSET,
703 ADPLL_M3DIV_M3,
704 ADPLL_M3DIV_M3_WIDTH,
705 CLK_DIVIDER_ONE_BASED);
706 if (err)
707 return err;
708
709 /* Output clock dcoclkldo is the DCO */
710
711 return 0;
712 }
713
714 static int ti_adpll_init_children_adpll_lj(struct ti_adpll_data *d)
715 {
716 int err;
717
718 if (d->c->is_type_s)
719 return 0;
720
721 /* Output clkdcoldo, gated output of DCO */
722 err = ti_adpll_init_gate(d, TI_ADPLL_DCO_GATE, TI_ADPLL_LJ_CLKDCOLDO,
723 "clkdcoldo", d->clocks[TI_ADPLL_DCO].clk,
724 d->regs + ADPLL_CLKCTRL_OFFSET,
725 ADPLL_CLKCTRL_CLKDCOLDOEN, 0);
726 if (err)
727 return err;
728
729 /* Internal divider M2, sources from DCO */
730 err = ti_adpll_init_divider(d, TI_ADPLL_M2, -ENODEV,
731 "m2", d->clocks[TI_ADPLL_DCO].clk,
732 d->regs + ADPLL_M2NDIV_OFFSET,
733 ADPLL_M2NDIV_M2,
734 ADPLL_M2NDIV_M2_ADPLL_LJ_WIDTH,
735 CLK_DIVIDER_ONE_BASED);
736 if (err)
737 return err;
738
739 /* Output clkoutldo, gated output of M2 */
740 err = ti_adpll_init_gate(d, TI_ADPLL_M2_GATE, TI_ADPLL_LJ_CLKOUTLDO,
741 "clkoutldo", d->clocks[TI_ADPLL_M2].clk,
742 d->regs + ADPLL_CLKCTRL_OFFSET,
743 ADPLL_CLKCTRL_CLKOUTLDOEN_ADPLL_LJ,
744 0);
745 if (err)
746 return err;
747
748 /* Internal mux, sources from divider N2 or clkinpulow */
749 err = ti_adpll_init_mux(d, TI_ADPLL_BYPASS, "bypass",
750 d->clocks[TI_ADPLL_N2].clk,
751 d->parent_clocks[TI_ADPLL_CLKINPULOW],
752 d->regs + ADPLL_CLKCTRL_OFFSET,
753 ADPLL_CLKCTRL_ULOWCLKEN);
754 if (err)
755 return err;
756
757 /* Output clkout, sources M2 or bypass */
758 err = ti_adpll_init_clkout(d, TI_ADPLL_CLKOUT, TI_ADPLL_S_CLKOUT,
759 ADPLL_CLKCTRL_CLKOUTEN, "clkout",
760 d->clocks[TI_ADPLL_M2].clk,
761 d->clocks[TI_ADPLL_BYPASS].clk);
762 if (err)
763 return err;
764
765 return 0;
766 }
767
768 static void ti_adpll_free_resources(struct ti_adpll_data *d)
769 {
770 int i;
771
772 for (i = TI_ADPLL_M3; i >= 0; i--) {
773 struct ti_adpll_clock *ac = &d->clocks[i];
774
775 if (!ac || IS_ERR_OR_NULL(ac->clk))
776 continue;
777 if (ac->cl)
778 clkdev_drop(ac->cl);
779 if (ac->unregister)
780 ac->unregister(ac->clk);
781 }
782 }
783
784 /* MPU PLL manages the lock register for all PLLs */
785 static void ti_adpll_unlock_all(void __iomem *reg)
786 {
787 u32 v;
788
789 v = readl_relaxed(reg);
790 if (v == ADPLL_PLLSS_MMR_LOCK_ENABLED)
791 writel_relaxed(ADPLL_PLLSS_MMR_UNLOCK_MAGIC, reg);
792 }
793
794 static int ti_adpll_init_registers(struct ti_adpll_data *d)
795 {
796 int register_offset = 0;
797
798 if (d->c->is_type_s) {
799 register_offset = 8;
800 ti_adpll_unlock_all(d->iobase + ADPLL_PLLSS_MMR_LOCK_OFFSET);
801 }
802
803 d->regs = d->iobase + register_offset + ADPLL_PWRCTRL_OFFSET;
804
805 return 0;
806 }
807
808 static int ti_adpll_init_inputs(struct ti_adpll_data *d)
809 {
810 const char *error = "need at least %i inputs";
811 struct clk *clock;
812 int nr_inputs;
813
814 nr_inputs = of_clk_get_parent_count(d->np);
815 if (nr_inputs < d->c->nr_max_inputs) {
816 dev_err(d->dev, error, nr_inputs);
817 return -EINVAL;
818 }
819 of_clk_parent_fill(d->np, d->parent_names, nr_inputs);
820
821 clock = devm_clk_get(d->dev, d->parent_names[0]);
822 if (IS_ERR(clock)) {
823 dev_err(d->dev, "could not get clkinp\n");
824 return PTR_ERR(clock);
825 }
826 d->parent_clocks[TI_ADPLL_CLKINP] = clock;
827
828 clock = devm_clk_get(d->dev, d->parent_names[1]);
829 if (IS_ERR(clock)) {
830 dev_err(d->dev, "could not get clkinpulow clock\n");
831 return PTR_ERR(clock);
832 }
833 d->parent_clocks[TI_ADPLL_CLKINPULOW] = clock;
834
835 if (d->c->is_type_s) {
836 clock = devm_clk_get(d->dev, d->parent_names[2]);
837 if (IS_ERR(clock)) {
838 dev_err(d->dev, "could not get clkinphif clock\n");
839 return PTR_ERR(clock);
840 }
841 d->parent_clocks[TI_ADPLL_CLKINPHIF] = clock;
842 }
843
844 return 0;
845 }
846
847 static const struct ti_adpll_platform_data ti_adpll_type_s = {
848 .is_type_s = true,
849 .nr_max_inputs = MAX_ADPLL_INPUTS,
850 .nr_max_outputs = MAX_ADPLL_OUTPUTS,
851 .output_index = TI_ADPLL_S_DCOCLKLDO,
852 };
853
854 static const struct ti_adpll_platform_data ti_adpll_type_lj = {
855 .is_type_s = false,
856 .nr_max_inputs = MAX_ADPLL_INPUTS - 1,
857 .nr_max_outputs = MAX_ADPLL_OUTPUTS - 1,
858 .output_index = -EINVAL,
859 };
860
861 static const struct of_device_id ti_adpll_match[] = {
862 { .compatible = "ti,dm814-adpll-s-clock", &ti_adpll_type_s },
863 { .compatible = "ti,dm814-adpll-lj-clock", &ti_adpll_type_lj },
864 {},
865 };
866 MODULE_DEVICE_TABLE(of, ti_adpll_match);
867
868 static int ti_adpll_probe(struct platform_device *pdev)
869 {
870 struct device_node *node = pdev->dev.of_node;
871 struct device *dev = &pdev->dev;
872 const struct of_device_id *match;
873 const struct ti_adpll_platform_data *pdata;
874 struct ti_adpll_data *d;
875 struct resource *res;
876 int err;
877
878 match = of_match_device(ti_adpll_match, dev);
879 if (match)
880 pdata = match->data;
881 else
882 return -ENODEV;
883
884 d = devm_kzalloc(dev, sizeof(*d), GFP_KERNEL);
885 if (!d)
886 return -ENOMEM;
887 d->dev = dev;
888 d->np = node;
889 d->c = pdata;
890 dev_set_drvdata(d->dev, d);
891 spin_lock_init(&d->lock);
892
893 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
894 if (!res)
895 return -ENODEV;
896 d->pa = res->start;
897
898 d->iobase = devm_ioremap_resource(dev, res);
899 if (IS_ERR(d->iobase)) {
900 dev_err(dev, "could not get IO base: %li\n",
901 PTR_ERR(d->iobase));
902 return PTR_ERR(d->iobase);
903 }
904
905 err = ti_adpll_init_registers(d);
906 if (err)
907 return err;
908
909 err = ti_adpll_init_inputs(d);
910 if (err)
911 return err;
912
913 d->clocks = devm_kcalloc(d->dev,
914 TI_ADPLL_NR_CLOCKS,
915 sizeof(struct ti_adpll_clock),
916 GFP_KERNEL);
917 if (!d->clocks)
918 return -ENOMEM;
919
920 err = ti_adpll_init_dco(d);
921 if (err) {
922 dev_err(dev, "could not register dco: %i\n", err);
923 goto free;
924 }
925
926 err = ti_adpll_init_children_adpll_s(d);
927 if (err)
928 goto free;
929 err = ti_adpll_init_children_adpll_lj(d);
930 if (err)
931 goto free;
932
933 err = of_clk_add_provider(d->np, of_clk_src_onecell_get, &d->outputs);
934 if (err)
935 goto free;
936
937 return 0;
938
939 free:
940 WARN_ON(1);
941 ti_adpll_free_resources(d);
942
943 return err;
944 }
945
946 static int ti_adpll_remove(struct platform_device *pdev)
947 {
948 struct ti_adpll_data *d = dev_get_drvdata(&pdev->dev);
949
950 ti_adpll_free_resources(d);
951
952 return 0;
953 }
954
955 static struct platform_driver ti_adpll_driver = {
956 .driver = {
957 .name = "ti-adpll",
958 .of_match_table = ti_adpll_match,
959 },
960 .probe = ti_adpll_probe,
961 .remove = ti_adpll_remove,
962 };
963
964 static int __init ti_adpll_init(void)
965 {
966 return platform_driver_register(&ti_adpll_driver);
967 }
968 core_initcall(ti_adpll_init);
969
970 static void __exit ti_adpll_exit(void)
971 {
972 platform_driver_unregister(&ti_adpll_driver);
973 }
974 module_exit(ti_adpll_exit);
975
976 MODULE_DESCRIPTION("Clock driver for dm814x ADPLL");
977 MODULE_ALIAS("platform:dm814-adpll-clock");
978 MODULE_AUTHOR("Tony LIndgren <tony@atomide.com>");
979 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support