drivers/clk/ti/clk-43xx.c

   1 /*
   2  * AM43XX Clock init
   3  *
   4  * Copyright (C) 2013 Texas Instruments, Inc
   5  *     Tero Kristo (t-kristo@ti.com)
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation version 2.
  10  *
  11  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12  * kind, whether express or implied; without even the implied warranty
  13  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/kernel.h>
  18 #include <linux/list.h>
  19 #include <linux/clk.h>
  20 #include <linux/clk-provider.h>
  21 #include <linux/clk/ti.h>
  22 #include <dt-bindings/clock/am4.h>
  23
  24 #include "clock.h"
  25
  26 static const struct omap_clkctrl_reg_data am4_l3s_tsc_clkctrl_regs[] __initconst = {
  27         { AM4_L3S_TSC_ADC_TSC_CLKCTRL, NULL, CLKF_SW_SUP, "adc_tsc_fck" },
  28         { 0 },
  29 };
  30
  31 static const char * const am4_synctimer_32kclk_parents[] __initconst = {
  32         "mux_synctimer32k_ck",
  33         NULL,
  34 };
  35
  36 static const struct omap_clkctrl_bit_data am4_counter_32k_bit_data[] __initconst = {
  37         { 8, TI_CLK_GATE, am4_synctimer_32kclk_parents, NULL },
  38         { 0 },
  39 };
  40
  41 static const struct omap_clkctrl_reg_data am4_l4_wkup_aon_clkctrl_regs[] __initconst = {
  42         { AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sys_clkin_ck" },
  43         { AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL, am4_counter_32k_bit_data, CLKF_SW_SUP, "l4-wkup-aon-clkctrl:0008:8" },
  44         { 0 },
  45 };
  46
  47 static const char * const am4_gpio0_dbclk_parents[] __initconst = {
  48         "gpio0_dbclk_mux_ck",
  49         NULL,
  50 };
  51
  52 static const struct omap_clkctrl_bit_data am4_gpio1_bit_data[] __initconst = {
  53         { 8, TI_CLK_GATE, am4_gpio0_dbclk_parents, NULL },
  54         { 0 },
  55 };
  56
  57 static const struct omap_clkctrl_reg_data am4_l4_wkup_clkctrl_regs[] __initconst = {
  58         { AM4_L4_WKUP_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck" },
  59         { AM4_L4_WKUP_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck" },
  60         { AM4_L4_WKUP_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "wdt1_fck" },
  61         { AM4_L4_WKUP_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
  62         { AM4_L4_WKUP_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
  63         { AM4_L4_WKUP_SMARTREFLEX0_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex0_fck" },
  64         { AM4_L4_WKUP_SMARTREFLEX1_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex1_fck" },
  65         { AM4_L4_WKUP_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck" },
  66         { AM4_L4_WKUP_GPIO1_CLKCTRL, am4_gpio1_bit_data, CLKF_SW_SUP, "sys_clkin_ck" },
  67         { 0 },
  68 };
  69
  70 static const struct omap_clkctrl_reg_data am4_mpu_clkctrl_regs[] __initconst = {
  71         { AM4_MPU_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_mpu_m2_ck" },
  72         { 0 },
  73 };
  74
  75 static const struct omap_clkctrl_reg_data am4_gfx_l3_clkctrl_regs[] __initconst = {
  76         { AM4_GFX_L3_GFX_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "gfx_fck_div_ck" },
  77         { 0 },
  78 };
  79
  80 static const struct omap_clkctrl_reg_data am4_l4_rtc_clkctrl_regs[] __initconst = {
  81         { AM4_L4_RTC_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clkdiv32k_ick" },
  82         { 0 },
  83 };
  84
  85 static const struct omap_clkctrl_reg_data am4_l3_clkctrl_regs[] __initconst = {
  86         { AM4_L3_L3_MAIN_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
  87         { AM4_L3_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck" },
  88         { AM4_L3_DES_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
  89         { AM4_L3_L3_INSTR_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
  90         { AM4_L3_OCMCRAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
  91         { AM4_L3_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
  92         { AM4_L3_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
  93         { AM4_L3_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
  94         { AM4_L3_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
  95         { AM4_L3_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
  96         { AM4_L3_L4_HS_CLKCTRL, NULL, CLKF_SW_SUP, "l4hs_gclk" },
  97         { 0 },
  98 };
  99
 100 static const char * const am4_usb_otg_ss0_refclk960m_parents[] __initconst = {
 101         "dpll_per_clkdcoldo",
 102         NULL,
 103 };
 104
 105 static const struct omap_clkctrl_bit_data am4_usb_otg_ss0_bit_data[] __initconst = {
 106         { 8, TI_CLK_GATE, am4_usb_otg_ss0_refclk960m_parents, NULL },
 107         { 0 },
 108 };
 109
 110 static const struct omap_clkctrl_bit_data am4_usb_otg_ss1_bit_data[] __initconst = {
 111         { 8, TI_CLK_GATE, am4_usb_otg_ss0_refclk960m_parents, NULL },
 112         { 0 },
 113 };
 114
 115 static const struct omap_clkctrl_reg_data am4_l3s_clkctrl_regs[] __initconst = {
 116         { AM4_L3S_VPFE0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
 117         { AM4_L3S_VPFE1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
 118         { AM4_L3S_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk" },
 119         { AM4_L3S_MCASP0_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp0_fck" },
 120         { AM4_L3S_MCASP1_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp1_fck" },
 121         { AM4_L3S_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
 122         { AM4_L3S_QSPI_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk" },
 123         { AM4_L3S_USB_OTG_SS0_CLKCTRL, am4_usb_otg_ss0_bit_data, CLKF_SW_SUP, "l3s_gclk" },
 124         { AM4_L3S_USB_OTG_SS1_CLKCTRL, am4_usb_otg_ss1_bit_data, CLKF_SW_SUP, "l3s_gclk" },
 125         { 0 },
 126 };
 127
 128 static const struct omap_clkctrl_reg_data am4_pruss_ocp_clkctrl_regs[] __initconst = {
 129         { AM4_PRUSS_OCP_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "pruss_ocp_gclk" },
 130         { 0 },
 131 };
 132
 133 static const char * const am4_gpio1_dbclk_parents[] __initconst = {
 134         "clkdiv32k_ick",
 135         NULL,
 136 };
 137
 138 static const struct omap_clkctrl_bit_data am4_gpio2_bit_data[] __initconst = {
 139         { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
 140         { 0 },
 141 };
 142
 143 static const struct omap_clkctrl_bit_data am4_gpio3_bit_data[] __initconst = {
 144         { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
 145         { 0 },
 146 };
 147
 148 static const struct omap_clkctrl_bit_data am4_gpio4_bit_data[] __initconst = {
 149         { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
 150         { 0 },
 151 };
 152
 153 static const struct omap_clkctrl_bit_data am4_gpio5_bit_data[] __initconst = {
 154         { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
 155         { 0 },
 156 };
 157
 158 static const struct omap_clkctrl_bit_data am4_gpio6_bit_data[] __initconst = {
 159         { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
 160         { 0 },
 161 };
 162
 163 static const struct omap_clkctrl_reg_data am4_l4ls_clkctrl_regs[] __initconst = {
 164         { AM4_L4LS_L4_LS_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
 165         { AM4_L4LS_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" },
 166         { AM4_L4LS_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" },
 167         { AM4_L4LS_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
 168         { AM4_L4LS_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
 169         { AM4_L4LS_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
 170         { AM4_L4LS_EPWMSS3_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
 171         { AM4_L4LS_EPWMSS4_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
 172         { AM4_L4LS_EPWMSS5_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
 173         { AM4_L4LS_ELM_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
 174         { AM4_L4LS_GPIO2_CLKCTRL, am4_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
 175         { AM4_L4LS_GPIO3_CLKCTRL, am4_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
 176         { AM4_L4LS_GPIO4_CLKCTRL, am4_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
 177         { AM4_L4LS_GPIO5_CLKCTRL, am4_gpio5_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
 178         { AM4_L4LS_GPIO6_CLKCTRL, am4_gpio6_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
 179         { AM4_L4LS_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_clk" },
 180         { AM4_L4LS_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
 181         { AM4_L4LS_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
 182         { AM4_L4LS_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
 183         { AM4_L4LS_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
 184         { AM4_L4LS_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
 185         { AM4_L4LS_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" },
 186         { AM4_L4LS_SPI0_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
 187         { AM4_L4LS_SPI1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
 188         { AM4_L4LS_SPI2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
 189         { AM4_L4LS_SPI3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
 190         { AM4_L4LS_SPI4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
 191         { AM4_L4LS_SPINLOCK_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
 192         { AM4_L4LS_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" },
 193         { AM4_L4LS_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" },
 194         { AM4_L4LS_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" },
 195         { AM4_L4LS_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" },
 196         { AM4_L4LS_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" },
 197         { AM4_L4LS_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" },
 198         { AM4_L4LS_TIMER8_CLKCTRL, NULL, CLKF_SW_SUP, "timer8_fck" },
 199         { AM4_L4LS_TIMER9_CLKCTRL, NULL, CLKF_SW_SUP, "timer9_fck" },
 200         { AM4_L4LS_TIMER10_CLKCTRL, NULL, CLKF_SW_SUP, "timer10_fck" },
 201         { AM4_L4LS_TIMER11_CLKCTRL, NULL, CLKF_SW_SUP, "timer11_fck" },
 202         { AM4_L4LS_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
 203         { AM4_L4LS_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
 204         { AM4_L4LS_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
 205         { AM4_L4LS_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
 206         { AM4_L4LS_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
 207         { AM4_L4LS_OCP2SCP0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
 208         { AM4_L4LS_OCP2SCP1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
 209         { 0 },
 210 };
 211
 212 static const struct omap_clkctrl_reg_data am4_emif_clkctrl_regs[] __initconst = {
 213         { AM4_EMIF_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_ck" },
 214         { 0 },
 215 };
 216
 217 static const struct omap_clkctrl_reg_data am4_dss_clkctrl_regs[] __initconst = {
 218         { AM4_DSS_DSS_CORE_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SET_RATE_PARENT, "disp_clk" },
 219         { 0 },
 220 };
 221
 222 static const struct omap_clkctrl_reg_data am4_cpsw_125mhz_clkctrl_regs[] __initconst = {
 223         { AM4_CPSW_125MHZ_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk" },
 224         { 0 },
 225 };
 226
 227 const struct omap_clkctrl_data am4_clkctrl_data[] __initconst = {
 228         { 0x44df2920, am4_l3s_tsc_clkctrl_regs },
 229         { 0x44df2a28, am4_l4_wkup_aon_clkctrl_regs },
 230         { 0x44df2a20, am4_l4_wkup_clkctrl_regs },
 231         { 0x44df8320, am4_mpu_clkctrl_regs },
 232         { 0x44df8420, am4_gfx_l3_clkctrl_regs },
 233         { 0x44df8520, am4_l4_rtc_clkctrl_regs },
 234         { 0x44df8820, am4_l3_clkctrl_regs },
 235         { 0x44df8868, am4_l3s_clkctrl_regs },
 236         { 0x44df8b20, am4_pruss_ocp_clkctrl_regs },
 237         { 0x44df8c20, am4_l4ls_clkctrl_regs },
 238         { 0x44df8f20, am4_emif_clkctrl_regs },
 239         { 0x44df9220, am4_dss_clkctrl_regs },
 240         { 0x44df9320, am4_cpsw_125mhz_clkctrl_regs },
 241         { 0 },
 242 };
 243
 244 const struct omap_clkctrl_data am438x_clkctrl_data[] __initconst = {
 245         { 0x44df2920, am4_l3s_tsc_clkctrl_regs },
 246         { 0x44df2a28, am4_l4_wkup_aon_clkctrl_regs },
 247         { 0x44df2a20, am4_l4_wkup_clkctrl_regs },
 248         { 0x44df8320, am4_mpu_clkctrl_regs },
 249         { 0x44df8420, am4_gfx_l3_clkctrl_regs },
 250         { 0x44df8820, am4_l3_clkctrl_regs },
 251         { 0x44df8868, am4_l3s_clkctrl_regs },
 252         { 0x44df8b20, am4_pruss_ocp_clkctrl_regs },
 253         { 0x44df8c20, am4_l4ls_clkctrl_regs },
 254         { 0x44df8f20, am4_emif_clkctrl_regs },
 255         { 0x44df9220, am4_dss_clkctrl_regs },
 256         { 0x44df9320, am4_cpsw_125mhz_clkctrl_regs },
 257         { 0 },
 258 };
 259
 260 static struct ti_dt_clk am43xx_clks[] = {
 261         DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"),
 262         DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
 263         DT_CLK(NULL, "gpio0_dbclk", "l4-wkup-clkctrl:0148:8"),
 264         DT_CLK(NULL, "gpio1_dbclk", "l4ls-clkctrl:0058:8"),
 265         DT_CLK(NULL, "gpio2_dbclk", "l4ls-clkctrl:0060:8"),
 266         DT_CLK(NULL, "gpio3_dbclk", "l4ls-clkctrl:0068:8"),
 267         DT_CLK(NULL, "gpio4_dbclk", "l4ls-clkctrl:0070:8"),
 268         DT_CLK(NULL, "gpio5_dbclk", "l4ls-clkctrl:0078:8"),
 269         DT_CLK(NULL, "synctimer_32kclk", "l4-wkup-aon-clkctrl:0008:8"),
 270         DT_CLK(NULL, "usb_otg_ss0_refclk960m", "l3s-clkctrl:01f8:8"),
 271         DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l3s-clkctrl:0200:8"),
 272         { .node_name = NULL },
 273 };
 274
 275 static const char *enable_init_clks[] = {
 276         /* AM4_L3_L3_MAIN_CLKCTRL, needed during suspend */
 277         "l3-clkctrl:0000:0",
 278 };
 279
 280 int __init am43xx_dt_clk_init(void)
 281 {
 282         struct clk *clk1, *clk2;
 283
 284         if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
 285                 ti_dt_clocks_register(am43xx_compat_clks);
 286         else
 287                 ti_dt_clocks_register(am43xx_clks);
 288
 289         omap2_clk_disable_autoidle_all();
 290
 291         omap2_clk_enable_init_clocks(enable_init_clks,
 292                                      ARRAY_SIZE(enable_init_clks));
 293
 294         ti_clk_add_aliases();
 295
 296         /*
 297          * cpsw_cpts_rft_clk  has got the choice of 3 clocksources
 298          * dpll_core_m4_ck, dpll_core_m5_ck and dpll_disp_m2_ck.
 299          * By default dpll_core_m4_ck is selected, witn this as clock
 300          * source the CPTS doesnot work properly. It gives clockcheck errors
 301          * while running PTP.
 302          * clockcheck: clock jumped backward or running slower than expected!
 303          * By selecting dpll_core_m5_ck as the clocksource fixes this issue.
 304          * In AM335x dpll_core_m5_ck is the default clocksource.
 305          */
 306         clk1 = clk_get_sys(NULL, "cpsw_cpts_rft_clk");
 307         clk2 = clk_get_sys(NULL, "dpll_core_m5_ck");
 308         clk_set_parent(clk1, clk2);
 309
 310         return 0;
 311 }