drivers/clk/ti/fapll.c

   1 /*
   2  * This program is free software; you can redistribute it and/or
   3  * modify it under the terms of the GNU General Public License as
   4  * published by the Free Software Foundation version 2.
   5  *
   6  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
   7  * kind, whether express or implied; without even the implied warranty
   8  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
   9  * GNU General Public License for more details.
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/clk-provider.h>
  14 #include <linux/delay.h>
  15 #include <linux/err.h>
  16 #include <linux/io.h>
  17 #include <linux/math64.h>
  18 #include <linux/of.h>
  19 #include <linux/of_address.h>
  20 #include <linux/clk/ti.h>
  21
  22 /* FAPLL Control Register PLL_CTRL */
  23 #define FAPLL_MAIN_MULT_N_SHIFT 16
  24 #define FAPLL_MAIN_DIV_P_SHIFT  8
  25 #define FAPLL_MAIN_LOCK         BIT(7)
  26 #define FAPLL_MAIN_PLLEN        BIT(3)
  27 #define FAPLL_MAIN_BP           BIT(2)
  28 #define FAPLL_MAIN_LOC_CTL      BIT(0)
  29
  30 #define FAPLL_MAIN_MAX_MULT_N   0xffff
  31 #define FAPLL_MAIN_MAX_DIV_P    0xff
  32 #define FAPLL_MAIN_CLEAR_MASK   \
  33         ((FAPLL_MAIN_MAX_MULT_N << FAPLL_MAIN_MULT_N_SHIFT) | \
  34          (FAPLL_MAIN_DIV_P_SHIFT << FAPLL_MAIN_DIV_P_SHIFT) | \
  35          FAPLL_MAIN_LOC_CTL)
  36
  37 /* FAPLL powerdown register PWD */
  38 #define FAPLL_PWD_OFFSET        4
  39
  40 #define MAX_FAPLL_OUTPUTS       7
  41 #define FAPLL_MAX_RETRIES       1000
  42
  43 #define to_fapll(_hw)           container_of(_hw, struct fapll_data, hw)
  44 #define to_synth(_hw)           container_of(_hw, struct fapll_synth, hw)
  45
  46 /* The bypass bit is inverted on the ddr_pll.. */
  47 #define fapll_is_ddr_pll(va)    (((u32)(va) & 0xffff) == 0x0440)
  48
  49 /*
  50  * The audio_pll_clk1 input is hard wired to the 27MHz bypass clock,
  51  * and the audio_pll_clk1 synthesizer is hardwared to 32KiHz output.
  52  */
  53 #define is_ddr_pll_clk1(va)     (((u32)(va) & 0xffff) == 0x044c)
  54 #define is_audio_pll_clk1(va)   (((u32)(va) & 0xffff) == 0x04a8)
  55
  56 /* Synthesizer divider register */
  57 #define SYNTH_LDMDIV1           BIT(8)
  58
  59 /* Synthesizer frequency register */
  60 #define SYNTH_LDFREQ            BIT(31)
  61
  62 #define SYNTH_PHASE_K           8
  63 #define SYNTH_MAX_INT_DIV       0xf
  64 #define SYNTH_MAX_DIV_M         0xff
  65
  66 struct fapll_data {
  67         struct clk_hw hw;
  68         void __iomem *base;
  69         const char *name;
  70         struct clk *clk_ref;
  71         struct clk *clk_bypass;
  72         struct clk_onecell_data outputs;
  73         bool bypass_bit_inverted;
  74 };
  75
  76 struct fapll_synth {
  77         struct clk_hw hw;
  78         struct fapll_data *fd;
  79         int index;
  80         void __iomem *freq;
  81         void __iomem *div;
  82         const char *name;
  83         struct clk *clk_pll;
  84 };
  85
  86 static bool ti_fapll_clock_is_bypass(struct fapll_data *fd)
  87 {
  88         u32 v = readl_relaxed(fd->base);
  89
  90         if (fd->bypass_bit_inverted)
  91                 return !(v & FAPLL_MAIN_BP);
  92         else
  93                 return !!(v & FAPLL_MAIN_BP);
  94 }
  95
  96 static void ti_fapll_set_bypass(struct fapll_data *fd)
  97 {
  98         u32 v = readl_relaxed(fd->base);
  99
 100         if (fd->bypass_bit_inverted)
 101                 v &= ~FAPLL_MAIN_BP;
 102         else
 103                 v |= FAPLL_MAIN_BP;
 104         writel_relaxed(v, fd->base);
 105 }
 106
 107 static void ti_fapll_clear_bypass(struct fapll_data *fd)
 108 {
 109         u32 v = readl_relaxed(fd->base);
 110
 111         if (fd->bypass_bit_inverted)
 112                 v |= FAPLL_MAIN_BP;
 113         else
 114                 v &= ~FAPLL_MAIN_BP;
 115         writel_relaxed(v, fd->base);
 116 }
 117
 118 static int ti_fapll_wait_lock(struct fapll_data *fd)
 119 {
 120         int retries = FAPLL_MAX_RETRIES;
 121         u32 v;
 122
 123         while ((v = readl_relaxed(fd->base))) {
 124                 if (v & FAPLL_MAIN_LOCK)
 125                         return 0;
 126
 127                 if (retries-- <= 0)
 128                         break;
 129
 130                 udelay(1);
 131         }
 132
 133         pr_err("%s failed to lock\n", fd->name);
 134
 135         return -ETIMEDOUT;
 136 }
 137
 138 static int ti_fapll_enable(struct clk_hw *hw)
 139 {
 140         struct fapll_data *fd = to_fapll(hw);
 141         u32 v = readl_relaxed(fd->base);
 142
 143         v |= FAPLL_MAIN_PLLEN;
 144         writel_relaxed(v, fd->base);
 145         ti_fapll_wait_lock(fd);
 146
 147         return 0;
 148 }
 149
 150 static void ti_fapll_disable(struct clk_hw *hw)
 151 {
 152         struct fapll_data *fd = to_fapll(hw);
 153         u32 v = readl_relaxed(fd->base);
 154
 155         v &= ~FAPLL_MAIN_PLLEN;
 156         writel_relaxed(v, fd->base);
 157 }
 158
 159 static int ti_fapll_is_enabled(struct clk_hw *hw)
 160 {
 161         struct fapll_data *fd = to_fapll(hw);
 162         u32 v = readl_relaxed(fd->base);
 163
 164         return v & FAPLL_MAIN_PLLEN;
 165 }
 166
 167 static unsigned long ti_fapll_recalc_rate(struct clk_hw *hw,
 168                                           unsigned long parent_rate)
 169 {
 170         struct fapll_data *fd = to_fapll(hw);
 171         u32 fapll_n, fapll_p, v;
 172         u64 rate;
 173
 174         if (ti_fapll_clock_is_bypass(fd))
 175                 return parent_rate;
 176
 177         rate = parent_rate;
 178
 179         /* PLL pre-divider is P and multiplier is N */
 180         v = readl_relaxed(fd->base);
 181         fapll_p = (v >> 8) & 0xff;
 182         if (fapll_p)
 183                 do_div(rate, fapll_p);
 184         fapll_n = v >> 16;
 185         if (fapll_n)
 186                 rate *= fapll_n;
 187
 188         return rate;
 189 }
 190
 191 static u8 ti_fapll_get_parent(struct clk_hw *hw)
 192 {
 193         struct fapll_data *fd = to_fapll(hw);
 194
 195         if (ti_fapll_clock_is_bypass(fd))
 196                 return 1;
 197
 198         return 0;
 199 }
 200
 201 static int ti_fapll_set_div_mult(unsigned long rate,
 202                                  unsigned long parent_rate,
 203                                  u32 *pre_div_p, u32 *mult_n)
 204 {
 205         /*
 206          * So far no luck getting decent clock with PLL divider,
 207          * PLL does not seem to lock and the signal does not look
 208          * right. It seems the divider can only be used together
 209          * with the multiplier?
 210          */
 211         if (rate < parent_rate) {
 212                 pr_warn("FAPLL main divider rates unsupported\n");
 213                 return -EINVAL;
 214         }
 215
 216         *mult_n = rate / parent_rate;
 217         if (*mult_n > FAPLL_MAIN_MAX_MULT_N)
 218                 return -EINVAL;
 219         *pre_div_p = 1;
 220
 221         return 0;
 222 }
 223
 224 static long ti_fapll_round_rate(struct clk_hw *hw, unsigned long rate,
 225                                 unsigned long *parent_rate)
 226 {
 227         u32 pre_div_p, mult_n;
 228         int error;
 229
 230         if (!rate)
 231                 return -EINVAL;
 232
 233         error = ti_fapll_set_div_mult(rate, *parent_rate,
 234                                       &pre_div_p, &mult_n);
 235         if (error)
 236                 return error;
 237
 238         rate = *parent_rate / pre_div_p;
 239         rate *= mult_n;
 240
 241         return rate;
 242 }
 243
 244 static int ti_fapll_set_rate(struct clk_hw *hw, unsigned long rate,
 245                              unsigned long parent_rate)
 246 {
 247         struct fapll_data *fd = to_fapll(hw);
 248         u32 pre_div_p, mult_n, v;
 249         int error;
 250
 251         if (!rate)
 252                 return -EINVAL;
 253
 254         error = ti_fapll_set_div_mult(rate, parent_rate,
 255                                       &pre_div_p, &mult_n);
 256         if (error)
 257                 return error;
 258
 259         ti_fapll_set_bypass(fd);
 260         v = readl_relaxed(fd->base);
 261         v &= ~FAPLL_MAIN_CLEAR_MASK;
 262         v |= pre_div_p << FAPLL_MAIN_DIV_P_SHIFT;
 263         v |= mult_n << FAPLL_MAIN_MULT_N_SHIFT;
 264         writel_relaxed(v, fd->base);
 265         if (ti_fapll_is_enabled(hw))
 266                 ti_fapll_wait_lock(fd);
 267         ti_fapll_clear_bypass(fd);
 268
 269         return 0;
 270 }
 271
 272 static const struct clk_ops ti_fapll_ops = {
 273         .enable = ti_fapll_enable,
 274         .disable = ti_fapll_disable,
 275         .is_enabled = ti_fapll_is_enabled,
 276         .recalc_rate = ti_fapll_recalc_rate,
 277         .get_parent = ti_fapll_get_parent,
 278         .round_rate = ti_fapll_round_rate,
 279         .set_rate = ti_fapll_set_rate,
 280 };
 281
 282 static int ti_fapll_synth_enable(struct clk_hw *hw)
 283 {
 284         struct fapll_synth *synth = to_synth(hw);
 285         u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET);
 286
 287         v &= ~(1 << synth->index);
 288         writel_relaxed(v, synth->fd->base + FAPLL_PWD_OFFSET);
 289
 290         return 0;
 291 }
 292
 293 static void ti_fapll_synth_disable(struct clk_hw *hw)
 294 {
 295         struct fapll_synth *synth = to_synth(hw);
 296         u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET);
 297
 298         v |= 1 << synth->index;
 299         writel_relaxed(v, synth->fd->base + FAPLL_PWD_OFFSET);
 300 }
 301
 302 static int ti_fapll_synth_is_enabled(struct clk_hw *hw)
 303 {
 304         struct fapll_synth *synth = to_synth(hw);
 305         u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET);
 306
 307         return !(v & (1 << synth->index));
 308 }
 309
 310 /*
 311  * See dm816x TRM chapter 1.10.3 Flying Adder PLL fore more info
 312  */
 313 static unsigned long ti_fapll_synth_recalc_rate(struct clk_hw *hw,
 314                                                 unsigned long parent_rate)
 315 {
 316         struct fapll_synth *synth = to_synth(hw);
 317         u32 synth_div_m;
 318         u64 rate;
 319
 320         /* The audio_pll_clk1 is hardwired to produce 32.768KiHz clock */
 321         if (!synth->div)
 322                 return 32768;
 323
 324         /*
 325          * PLL in bypass sets the synths in bypass mode too. The PLL rate
 326          * can be also be set to 27MHz, so we can't use parent_rate to
 327          * check for bypass mode.
 328          */
 329         if (ti_fapll_clock_is_bypass(synth->fd))
 330                 return parent_rate;
 331
 332         rate = parent_rate;
 333
 334         /*
 335          * Synth frequency integer and fractional divider.
 336          * Note that the phase output K is 8, so the result needs
 337          * to be multiplied by SYNTH_PHASE_K.
 338          */
 339         if (synth->freq) {
 340                 u32 v, synth_int_div, synth_frac_div, synth_div_freq;
 341
 342                 v = readl_relaxed(synth->freq);
 343                 synth_int_div = (v >> 24) & 0xf;
 344                 synth_frac_div = v & 0xffffff;
 345                 synth_div_freq = (synth_int_div * 10000000) + synth_frac_div;
 346                 rate *= 10000000;
 347                 do_div(rate, synth_div_freq);
 348                 rate *= SYNTH_PHASE_K;
 349         }
 350
 351         /* Synth post-divider M */
 352         synth_div_m = readl_relaxed(synth->div) & SYNTH_MAX_DIV_M;
 353
 354         return DIV_ROUND_UP_ULL(rate, synth_div_m);
 355 }
 356
 357 static unsigned long ti_fapll_synth_get_frac_rate(struct clk_hw *hw,
 358                                                   unsigned long parent_rate)
 359 {
 360         struct fapll_synth *synth = to_synth(hw);
 361         unsigned long current_rate, frac_rate;
 362         u32 post_div_m;
 363
 364         current_rate = ti_fapll_synth_recalc_rate(hw, parent_rate);
 365         post_div_m = readl_relaxed(synth->div) & SYNTH_MAX_DIV_M;
 366         frac_rate = current_rate * post_div_m;
 367
 368         return frac_rate;
 369 }
 370
 371 static u32 ti_fapll_synth_set_frac_rate(struct fapll_synth *synth,
 372                                         unsigned long rate,
 373                                         unsigned long parent_rate)
 374 {
 375         u32 post_div_m, synth_int_div = 0, synth_frac_div = 0, v;
 376
 377         post_div_m = DIV_ROUND_UP_ULL((u64)parent_rate * SYNTH_PHASE_K, rate);
 378         post_div_m = post_div_m / SYNTH_MAX_INT_DIV;
 379         if (post_div_m > SYNTH_MAX_DIV_M)
 380                 return -EINVAL;
 381         if (!post_div_m)
 382                 post_div_m = 1;
 383
 384         for (; post_div_m < SYNTH_MAX_DIV_M; post_div_m++) {
 385                 synth_int_div = DIV_ROUND_UP_ULL((u64)parent_rate *
 386                                                  SYNTH_PHASE_K *
 387                                                  10000000,
 388                                                  rate * post_div_m);
 389                 synth_frac_div = synth_int_div % 10000000;
 390                 synth_int_div /= 10000000;
 391
 392                 if (synth_int_div <= SYNTH_MAX_INT_DIV)
 393                         break;
 394         }
 395
 396         if (synth_int_div > SYNTH_MAX_INT_DIV)
 397                 return -EINVAL;
 398
 399         v = readl_relaxed(synth->freq);
 400         v &= ~0x1fffffff;
 401         v |= (synth_int_div & SYNTH_MAX_INT_DIV) << 24;
 402         v |= (synth_frac_div & 0xffffff);
 403         v |= SYNTH_LDFREQ;
 404         writel_relaxed(v, synth->freq);
 405
 406         return post_div_m;
 407 }
 408
 409 static long ti_fapll_synth_round_rate(struct clk_hw *hw, unsigned long rate,
 410                                       unsigned long *parent_rate)
 411 {
 412         struct fapll_synth *synth = to_synth(hw);
 413         struct fapll_data *fd = synth->fd;
 414         unsigned long r;
 415
 416         if (ti_fapll_clock_is_bypass(fd) || !synth->div || !rate)
 417                 return -EINVAL;
 418
 419         /* Only post divider m available with no fractional divider? */
 420         if (!synth->freq) {
 421                 unsigned long frac_rate;
 422                 u32 synth_post_div_m;
 423
 424                 frac_rate = ti_fapll_synth_get_frac_rate(hw, *parent_rate);
 425                 synth_post_div_m = DIV_ROUND_UP(frac_rate, rate);
 426                 r = DIV_ROUND_UP(frac_rate, synth_post_div_m);
 427                 goto out;
 428         }
 429
 430         r = *parent_rate * SYNTH_PHASE_K;
 431         if (rate > r)
 432                 goto out;
 433
 434         r = DIV_ROUND_UP_ULL(r, SYNTH_MAX_INT_DIV * SYNTH_MAX_DIV_M);
 435         if (rate < r)
 436                 goto out;
 437
 438         r = rate;
 439 out:
 440         return r;
 441 }
 442
 443 static int ti_fapll_synth_set_rate(struct clk_hw *hw, unsigned long rate,
 444                                    unsigned long parent_rate)
 445 {
 446         struct fapll_synth *synth = to_synth(hw);
 447         struct fapll_data *fd = synth->fd;
 448         unsigned long frac_rate, post_rate = 0;
 449         u32 post_div_m = 0, v;
 450
 451         if (ti_fapll_clock_is_bypass(fd) || !synth->div || !rate)
 452                 return -EINVAL;
 453
 454         /* Produce the rate with just post divider M? */
 455         frac_rate = ti_fapll_synth_get_frac_rate(hw, parent_rate);
 456         if (frac_rate < rate) {
 457                 if (!synth->freq)
 458                         return -EINVAL;
 459         } else {
 460                 post_div_m = DIV_ROUND_UP(frac_rate, rate);
 461                 if (post_div_m && (post_div_m <= SYNTH_MAX_DIV_M))
 462                         post_rate = DIV_ROUND_UP(frac_rate, post_div_m);
 463                 if (!synth->freq && !post_rate)
 464                         return -EINVAL;
 465         }
 466
 467         /* Need to recalculate the fractional divider? */
 468         if ((post_rate != rate) && synth->freq)
 469                 post_div_m = ti_fapll_synth_set_frac_rate(synth,
 470                                                           rate,
 471                                                           parent_rate);
 472
 473         v = readl_relaxed(synth->div);
 474         v &= ~SYNTH_MAX_DIV_M;
 475         v |= post_div_m;
 476         v |= SYNTH_LDMDIV1;
 477         writel_relaxed(v, synth->div);
 478
 479         return 0;
 480 }
 481
 482 static const struct clk_ops ti_fapll_synt_ops = {
 483         .enable = ti_fapll_synth_enable,
 484         .disable = ti_fapll_synth_disable,
 485         .is_enabled = ti_fapll_synth_is_enabled,
 486         .recalc_rate = ti_fapll_synth_recalc_rate,
 487         .round_rate = ti_fapll_synth_round_rate,
 488         .set_rate = ti_fapll_synth_set_rate,
 489 };
 490
 491 static struct clk * __init ti_fapll_synth_setup(struct fapll_data *fd,
 492                                                 void __iomem *freq,
 493                                                 void __iomem *div,
 494                                                 int index,
 495                                                 const char *name,
 496                                                 const char *parent,
 497                                                 struct clk *pll_clk)
 498 {
 499         struct clk_init_data *init;
 500         struct fapll_synth *synth;
 501         struct clk *clk = ERR_PTR(-ENOMEM);
 502
 503         init = kzalloc(sizeof(*init), GFP_KERNEL);
 504         if (!init)
 505                 return ERR_PTR(-ENOMEM);
 506
 507         init->ops = &ti_fapll_synt_ops;
 508         init->name = name;
 509         init->parent_names = &parent;
 510         init->num_parents = 1;
 511
 512         synth = kzalloc(sizeof(*synth), GFP_KERNEL);
 513         if (!synth)
 514                 goto free;
 515
 516         synth->fd = fd;
 517         synth->index = index;
 518         synth->freq = freq;
 519         synth->div = div;
 520         synth->name = name;
 521         synth->hw.init = init;
 522         synth->clk_pll = pll_clk;
 523
 524         clk = clk_register(NULL, &synth->hw);
 525         if (IS_ERR(clk)) {
 526                 pr_err("failed to register clock\n");
 527                 goto free;
 528         }
 529
 530         return clk;
 531
 532 free:
 533         kfree(synth);
 534         kfree(init);
 535
 536         return clk;
 537 }
 538
 539 static void __init ti_fapll_setup(struct device_node *node)
 540 {
 541         struct fapll_data *fd;
 542         struct clk_init_data *init = NULL;
 543         const char *parent_name[2];
 544         struct clk *pll_clk;
 545         int i;
 546
 547         fd = kzalloc(sizeof(*fd), GFP_KERNEL);
 548         if (!fd)
 549                 return;
 550
 551         fd->outputs.clks = kzalloc(sizeof(struct clk *) *
 552                                    MAX_FAPLL_OUTPUTS + 1,
 553                                    GFP_KERNEL);
 554         if (!fd->outputs.clks)
 555                 goto free;
 556
 557         init = kzalloc(sizeof(*init), GFP_KERNEL);
 558         if (!init)
 559                 goto free;
 560
 561         init->ops = &ti_fapll_ops;
 562         init->name = node->name;
 563
 564         init->num_parents = of_clk_get_parent_count(node);
 565         if (init->num_parents != 2) {
 566                 pr_err("%pOFn must have two parents\n", node);
 567                 goto free;
 568         }
 569
 570         of_clk_parent_fill(node, parent_name, 2);
 571         init->parent_names = parent_name;
 572
 573         fd->clk_ref = of_clk_get(node, 0);
 574         if (IS_ERR(fd->clk_ref)) {
 575                 pr_err("%pOFn could not get clk_ref\n", node);
 576                 goto free;
 577         }
 578
 579         fd->clk_bypass = of_clk_get(node, 1);
 580         if (IS_ERR(fd->clk_bypass)) {
 581                 pr_err("%pOFn could not get clk_bypass\n", node);
 582                 goto free;
 583         }
 584
 585         fd->base = of_iomap(node, 0);
 586         if (!fd->base) {
 587                 pr_err("%pOFn could not get IO base\n", node);
 588                 goto free;
 589         }
 590
 591         if (fapll_is_ddr_pll(fd->base))
 592                 fd->bypass_bit_inverted = true;
 593
 594         fd->name = node->name;
 595         fd->hw.init = init;
 596
 597         /* Register the parent PLL */
 598         pll_clk = clk_register(NULL, &fd->hw);
 599         if (IS_ERR(pll_clk))
 600                 goto unmap;
 601
 602         fd->outputs.clks[0] = pll_clk;
 603         fd->outputs.clk_num++;
 604
 605         /*
 606          * Set up the child synthesizers starting at index 1 as the
 607          * PLL output is at index 0. We need to check the clock-indices
 608          * for numbering in case there are holes in the synth mapping,
 609          * and then probe the synth register to see if it has a FREQ
 610          * register available.
 611          */
 612         for (i = 0; i < MAX_FAPLL_OUTPUTS; i++) {
 613                 const char *output_name;
 614                 void __iomem *freq, *div;
 615                 struct clk *synth_clk;
 616                 int output_instance;
 617                 u32 v;
 618
 619                 if (of_property_read_string_index(node, "clock-output-names",
 620                                                   i, &output_name))
 621                         continue;
 622
 623                 if (of_property_read_u32_index(node, "clock-indices", i,
 624                                                &output_instance))
 625                         output_instance = i;
 626
 627                 freq = fd->base + (output_instance * 8);
 628                 div = freq + 4;
 629
 630                 /* Check for hardwired audio_pll_clk1 */
 631                 if (is_audio_pll_clk1(freq)) {
 632                         freq = NULL;
 633                         div = NULL;
 634                 } else {
 635                         /* Does the synthesizer have a FREQ register? */
 636                         v = readl_relaxed(freq);
 637                         if (!v)
 638                                 freq = NULL;
 639                 }
 640                 synth_clk = ti_fapll_synth_setup(fd, freq, div, output_instance,
 641                                                  output_name, node->name,
 642                                                  pll_clk);
 643                 if (IS_ERR(synth_clk))
 644                         continue;
 645
 646                 fd->outputs.clks[output_instance] = synth_clk;
 647                 fd->outputs.clk_num++;
 648
 649                 clk_register_clkdev(synth_clk, output_name, NULL);
 650         }
 651
 652         /* Register the child synthesizers as the FAPLL outputs */
 653         of_clk_add_provider(node, of_clk_src_onecell_get, &fd->outputs);
 654         /* Add clock alias for the outputs */
 655
 656         kfree(init);
 657
 658         return;
 659
 660 unmap:
 661         iounmap(fd->base);
 662 free:
 663         if (fd->clk_bypass)
 664                 clk_put(fd->clk_bypass);
 665         if (fd->clk_ref)
 666                 clk_put(fd->clk_ref);
 667         kfree(fd->outputs.clks);
 668         kfree(fd);
 669         kfree(init);
 670 }
 671
 672 CLK_OF_DECLARE(ti_fapll_clock, "ti,dm816-fapll-clock", ti_fapll_setup);