1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Altera Corporation
4 * Copyright (c) 2011 Picochip Ltd., Jamie Iles
6 * Modified from mach-picoxcell/time.c
8 #include <linux/delay.h>
9 #include <linux/dw_apb_timer.h>
11 #include <linux/of_address.h>
12 #include <linux/of_irq.h>
13 #include <linux/clk.h>
14 #include <linux/reset.h>
15 #include <linux/sched_clock.h>
17 static int __init
timer_get_base_and_rate(struct device_node
*np
,
18 void __iomem
**base
, u32
*rate
)
20 struct clk
*timer_clk
;
22 struct reset_control
*rstc
;
25 *base
= of_iomap(np
, 0);
28 panic("Unable to map regs for %pOFn", np
);
31 * Reset the timer if the reset control is available, wiping
32 * out the state the firmware may have left it
34 rstc
= of_reset_control_get(np
, NULL
);
36 reset_control_assert(rstc
);
37 reset_control_deassert(rstc
);
41 * Not all implementations use a periphal clock, so don't panic
44 pclk
= of_clk_get_by_name(np
, "pclk");
46 if (clk_prepare_enable(pclk
))
47 pr_warn("pclk for %pOFn is present, but could not be activated\n",
50 if (!of_property_read_u32(np
, "clock-freq", rate
) &&
51 !of_property_read_u32(np
, "clock-frequency", rate
))
54 timer_clk
= of_clk_get_by_name(np
, "timer");
55 if (IS_ERR(timer_clk
))
56 return PTR_ERR(timer_clk
);
58 ret
= clk_prepare_enable(timer_clk
);
62 *rate
= clk_get_rate(timer_clk
);
69 static int __init
add_clockevent(struct device_node
*event_timer
)
72 struct dw_apb_clock_event_device
*ced
;
76 irq
= irq_of_parse_and_map(event_timer
, 0);
78 panic("No IRQ for clock event timer");
80 ret
= timer_get_base_and_rate(event_timer
, &iobase
, &rate
);
84 ced
= dw_apb_clockevent_init(-1, event_timer
->name
, 300, iobase
, irq
,
89 dw_apb_clockevent_register(ced
);
94 static void __iomem
*sched_io_base
;
95 static u32 sched_rate
;
97 static int __init
add_clocksource(struct device_node
*source_timer
)
100 struct dw_apb_clocksource
*cs
;
104 ret
= timer_get_base_and_rate(source_timer
, &iobase
, &rate
);
108 cs
= dw_apb_clocksource_init(300, source_timer
->name
, iobase
, rate
);
112 dw_apb_clocksource_start(cs
);
113 dw_apb_clocksource_register(cs
);
116 * Fallback to use the clocksource as sched_clock if no separate
117 * timer is found. sched_io_base then points to the current_value
118 * register of the clocksource timer.
120 sched_io_base
= iobase
+ 0x04;
126 static u64 notrace
read_sched_clock(void)
128 return ~readl_relaxed(sched_io_base
);
131 static const struct of_device_id sptimer_ids
[] __initconst
= {
132 { .compatible
= "picochip,pc3x2-rtc" },
136 static void __init
init_sched_clock(void)
138 struct device_node
*sched_timer
;
140 sched_timer
= of_find_matching_node(NULL
, sptimer_ids
);
142 timer_get_base_and_rate(sched_timer
, &sched_io_base
,
144 of_node_put(sched_timer
);
147 sched_clock_register(read_sched_clock
, 32, sched_rate
);
151 static unsigned long dw_apb_delay_timer_read(void)
153 return ~readl_relaxed(sched_io_base
);
156 static struct delay_timer dw_apb_delay_timer
= {
157 .read_current_timer
= dw_apb_delay_timer_read
,
161 static int num_called
;
162 static int __init
dw_apb_timer_init(struct device_node
*timer
)
166 switch (num_called
) {
168 pr_debug("%s: found clocksource timer\n", __func__
);
169 ret
= add_clocksource(timer
);
174 dw_apb_delay_timer
.freq
= sched_rate
;
175 register_current_timer_delay(&dw_apb_delay_timer
);
179 pr_debug("%s: found clockevent timer\n", __func__
);
180 ret
= add_clockevent(timer
);
190 TIMER_OF_DECLARE(pc3x2_timer
, "picochip,pc3x2-timer", dw_apb_timer_init
);
191 TIMER_OF_DECLARE(apb_timer_osc
, "snps,dw-apb-timer-osc", dw_apb_timer_init
);
192 TIMER_OF_DECLARE(apb_timer_sp
, "snps,dw-apb-timer-sp", dw_apb_timer_init
);
193 TIMER_OF_DECLARE(apb_timer
, "snps,dw-apb-timer", dw_apb_timer_init
);