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Merge tag 'block-5.11-2021-01-10' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / dma / ti / edma.c
blob35d81bd857f118200c575ccc2bf8143b3410a2e6
1 /*
2 * TI EDMA DMA engine driver
3 *
4 * Copyright 2012 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 #include <linux/dmaengine.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/bitmap.h>
19 #include <linux/err.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
22 #include <linux/list.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/slab.h>
26 #include <linux/spinlock.h>
27 #include <linux/of.h>
28 #include <linux/of_dma.h>
29 #include <linux/of_irq.h>
30 #include <linux/of_address.h>
31 #include <linux/of_device.h>
32 #include <linux/pm_runtime.h>
33
34 #include <linux/platform_data/edma.h>
35
36 #include "../dmaengine.h"
37 #include "../virt-dma.h"
38
39 /* Offsets matching "struct edmacc_param" */
40 #define PARM_OPT 0x00
41 #define PARM_SRC 0x04
42 #define PARM_A_B_CNT 0x08
43 #define PARM_DST 0x0c
44 #define PARM_SRC_DST_BIDX 0x10
45 #define PARM_LINK_BCNTRLD 0x14
46 #define PARM_SRC_DST_CIDX 0x18
47 #define PARM_CCNT 0x1c
48
49 #define PARM_SIZE 0x20
50
51 /* Offsets for EDMA CC global channel registers and their shadows */
52 #define SH_ER 0x00 /* 64 bits */
53 #define SH_ECR 0x08 /* 64 bits */
54 #define SH_ESR 0x10 /* 64 bits */
55 #define SH_CER 0x18 /* 64 bits */
56 #define SH_EER 0x20 /* 64 bits */
57 #define SH_EECR 0x28 /* 64 bits */
58 #define SH_EESR 0x30 /* 64 bits */
59 #define SH_SER 0x38 /* 64 bits */
60 #define SH_SECR 0x40 /* 64 bits */
61 #define SH_IER 0x50 /* 64 bits */
62 #define SH_IECR 0x58 /* 64 bits */
63 #define SH_IESR 0x60 /* 64 bits */
64 #define SH_IPR 0x68 /* 64 bits */
65 #define SH_ICR 0x70 /* 64 bits */
66 #define SH_IEVAL 0x78
67 #define SH_QER 0x80
68 #define SH_QEER 0x84
69 #define SH_QEECR 0x88
70 #define SH_QEESR 0x8c
71 #define SH_QSER 0x90
72 #define SH_QSECR 0x94
73 #define SH_SIZE 0x200
74
75 /* Offsets for EDMA CC global registers */
76 #define EDMA_REV 0x0000
77 #define EDMA_CCCFG 0x0004
78 #define EDMA_QCHMAP 0x0200 /* 8 registers */
79 #define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */
80 #define EDMA_QDMAQNUM 0x0260
81 #define EDMA_QUETCMAP 0x0280
82 #define EDMA_QUEPRI 0x0284
83 #define EDMA_EMR 0x0300 /* 64 bits */
84 #define EDMA_EMCR 0x0308 /* 64 bits */
85 #define EDMA_QEMR 0x0310
86 #define EDMA_QEMCR 0x0314
87 #define EDMA_CCERR 0x0318
88 #define EDMA_CCERRCLR 0x031c
89 #define EDMA_EEVAL 0x0320
90 #define EDMA_DRAE 0x0340 /* 4 x 64 bits*/
91 #define EDMA_QRAE 0x0380 /* 4 registers */
92 #define EDMA_QUEEVTENTRY 0x0400 /* 2 x 16 registers */
93 #define EDMA_QSTAT 0x0600 /* 2 registers */
94 #define EDMA_QWMTHRA 0x0620
95 #define EDMA_QWMTHRB 0x0624
96 #define EDMA_CCSTAT 0x0640
97
98 #define EDMA_M 0x1000 /* global channel registers */
99 #define EDMA_ECR 0x1008
100 #define EDMA_ECRH 0x100C
101 #define EDMA_SHADOW0 0x2000 /* 4 shadow regions */
102 #define EDMA_PARM 0x4000 /* PaRAM entries */
103
104 #define PARM_OFFSET(param_no) (EDMA_PARM + ((param_no) << 5))
105
106 #define EDMA_DCHMAP 0x0100 /* 64 registers */
107
108 /* CCCFG register */
109 #define GET_NUM_DMACH(x) (x & 0x7) /* bits 0-2 */
110 #define GET_NUM_QDMACH(x) ((x & 0x70) >> 4) /* bits 4-6 */
111 #define GET_NUM_PAENTRY(x) ((x & 0x7000) >> 12) /* bits 12-14 */
112 #define GET_NUM_EVQUE(x) ((x & 0x70000) >> 16) /* bits 16-18 */
113 #define GET_NUM_REGN(x) ((x & 0x300000) >> 20) /* bits 20-21 */
114 #define CHMAP_EXIST BIT(24)
115
116 /* CCSTAT register */
117 #define EDMA_CCSTAT_ACTV BIT(4)
118
119 /*
120 * Max of 20 segments per channel to conserve PaRAM slots
121 * Also note that MAX_NR_SG should be atleast the no.of periods
122 * that are required for ASoC, otherwise DMA prep calls will
123 * fail. Today davinci-pcm is the only user of this driver and
124 * requires atleast 17 slots, so we setup the default to 20.
125 */
126 #define MAX_NR_SG 20
127 #define EDMA_MAX_SLOTS MAX_NR_SG
128 #define EDMA_DESCRIPTORS 16
129
130 #define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */
131 #define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */
132 #define EDMA_CONT_PARAMS_ANY 1001
133 #define EDMA_CONT_PARAMS_FIXED_EXACT 1002
134 #define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003
135
136 /*
137 * 64bit array registers are split into two 32bit registers:
138 * reg0: channel/event 0-31
139 * reg1: channel/event 32-63
140 *
141 * bit 5 in the channel number tells the array index (0/1)
142 * bit 0-4 (0x1f) is the bit offset within the register
143 */
144 #define EDMA_REG_ARRAY_INDEX(channel) ((channel) >> 5)
145 #define EDMA_CHANNEL_BIT(channel) (BIT((channel) & 0x1f))
146
147 /* PaRAM slots are laid out like this */
148 struct edmacc_param {
149 u32 opt;
150 u32 src;
151 u32 a_b_cnt;
152 u32 dst;
153 u32 src_dst_bidx;
154 u32 link_bcntrld;
155 u32 src_dst_cidx;
156 u32 ccnt;
157 } __packed;
158
159 /* fields in edmacc_param.opt */
160 #define SAM BIT(0)
161 #define DAM BIT(1)
162 #define SYNCDIM BIT(2)
163 #define STATIC BIT(3)
164 #define EDMA_FWID (0x07 << 8)
165 #define TCCMODE BIT(11)
166 #define EDMA_TCC(t) ((t) << 12)
167 #define TCINTEN BIT(20)
168 #define ITCINTEN BIT(21)
169 #define TCCHEN BIT(22)
170 #define ITCCHEN BIT(23)
171
172 struct edma_pset {
173 u32 len;
174 dma_addr_t addr;
175 struct edmacc_param param;
176 };
177
178 struct edma_desc {
179 struct virt_dma_desc vdesc;
180 struct list_head node;
181 enum dma_transfer_direction direction;
182 int cyclic;
183 bool polled;
184 int absync;
185 int pset_nr;
186 struct edma_chan *echan;
187 int processed;
188
189 /*
190 * The following 4 elements are used for residue accounting.
191 *
192 * - processed_stat: the number of SG elements we have traversed
193 * so far to cover accounting. This is updated directly to processed
194 * during edma_callback and is always <= processed, because processed
195 * refers to the number of pending transfer (programmed to EDMA
196 * controller), where as processed_stat tracks number of transfers
197 * accounted for so far.
198 *
199 * - residue: The amount of bytes we have left to transfer for this desc
200 *
201 * - residue_stat: The residue in bytes of data we have covered
202 * so far for accounting. This is updated directly to residue
203 * during callbacks to keep it current.
204 *
205 * - sg_len: Tracks the length of the current intermediate transfer,
206 * this is required to update the residue during intermediate transfer
207 * completion callback.
208 */
209 int processed_stat;
210 u32 sg_len;
211 u32 residue;
212 u32 residue_stat;
213
214 struct edma_pset pset[];
215 };
216
217 struct edma_cc;
218
219 struct edma_tc {
220 struct device_node *node;
221 u16 id;
222 };
223
224 struct edma_chan {
225 struct virt_dma_chan vchan;
226 struct list_head node;
227 struct edma_desc *edesc;
228 struct edma_cc *ecc;
229 struct edma_tc *tc;
230 int ch_num;
231 bool alloced;
232 bool hw_triggered;
233 int slot[EDMA_MAX_SLOTS];
234 int missed;
235 struct dma_slave_config cfg;
236 };
237
238 struct edma_cc {
239 struct device *dev;
240 struct edma_soc_info *info;
241 void __iomem *base;
242 int id;
243 bool legacy_mode;
244
245 /* eDMA3 resource information */
246 unsigned num_channels;
247 unsigned num_qchannels;
248 unsigned num_region;
249 unsigned num_slots;
250 unsigned num_tc;
251 bool chmap_exist;
252 enum dma_event_q default_queue;
253
254 unsigned int ccint;
255 unsigned int ccerrint;
256
257 /*
258 * The slot_inuse bit for each PaRAM slot is clear unless the slot is
259 * in use by Linux or if it is allocated to be used by DSP.
260 */
261 unsigned long *slot_inuse;
262
263 /*
264 * For tracking reserved channels used by DSP.
265 * If the bit is cleared, the channel is allocated to be used by DSP
266 * and Linux must not touch it.
267 */
268 unsigned long *channels_mask;
269
270 struct dma_device dma_slave;
271 struct dma_device *dma_memcpy;
272 struct edma_chan *slave_chans;
273 struct edma_tc *tc_list;
274 int dummy_slot;
275 };
276
277 /* dummy param set used to (re)initialize parameter RAM slots */
278 static const struct edmacc_param dummy_paramset = {
279 .link_bcntrld = 0xffff,
280 .ccnt = 1,
281 };
282
283 #define EDMA_BINDING_LEGACY 0
284 #define EDMA_BINDING_TPCC 1
285 static const u32 edma_binding_type[] = {
286 [EDMA_BINDING_LEGACY] = EDMA_BINDING_LEGACY,
287 [EDMA_BINDING_TPCC] = EDMA_BINDING_TPCC,
288 };
289
290 static const struct of_device_id edma_of_ids[] = {
291 {
292 .compatible = "ti,edma3",
293 .data = &edma_binding_type[EDMA_BINDING_LEGACY],
294 },
295 {
296 .compatible = "ti,edma3-tpcc",
297 .data = &edma_binding_type[EDMA_BINDING_TPCC],
298 },
299 {}
300 };
301 MODULE_DEVICE_TABLE(of, edma_of_ids);
302
303 static const struct of_device_id edma_tptc_of_ids[] = {
304 { .compatible = "ti,edma3-tptc", },
305 {}
306 };
307 MODULE_DEVICE_TABLE(of, edma_tptc_of_ids);
308
309 static inline unsigned int edma_read(struct edma_cc *ecc, int offset)
310 {
311 return (unsigned int)__raw_readl(ecc->base + offset);
312 }
313
314 static inline void edma_write(struct edma_cc *ecc, int offset, int val)
315 {
316 __raw_writel(val, ecc->base + offset);
317 }
318
319 static inline void edma_modify(struct edma_cc *ecc, int offset, unsigned and,
320 unsigned or)
321 {
322 unsigned val = edma_read(ecc, offset);
323
324 val &= and;
325 val |= or;
326 edma_write(ecc, offset, val);
327 }
328
329 static inline void edma_and(struct edma_cc *ecc, int offset, unsigned and)
330 {
331 unsigned val = edma_read(ecc, offset);
332
333 val &= and;
334 edma_write(ecc, offset, val);
335 }
336
337 static inline void edma_or(struct edma_cc *ecc, int offset, unsigned or)
338 {
339 unsigned val = edma_read(ecc, offset);
340
341 val |= or;
342 edma_write(ecc, offset, val);
343 }
344
345 static inline unsigned int edma_read_array(struct edma_cc *ecc, int offset,
346 int i)
347 {
348 return edma_read(ecc, offset + (i << 2));
349 }
350
351 static inline void edma_write_array(struct edma_cc *ecc, int offset, int i,
352 unsigned val)
353 {
354 edma_write(ecc, offset + (i << 2), val);
355 }
356
357 static inline void edma_modify_array(struct edma_cc *ecc, int offset, int i,
358 unsigned and, unsigned or)
359 {
360 edma_modify(ecc, offset + (i << 2), and, or);
361 }
362
363 static inline void edma_or_array(struct edma_cc *ecc, int offset, int i,
364 unsigned or)
365 {
366 edma_or(ecc, offset + (i << 2), or);
367 }
368
369 static inline void edma_or_array2(struct edma_cc *ecc, int offset, int i, int j,
370 unsigned or)
371 {
372 edma_or(ecc, offset + ((i * 2 + j) << 2), or);
373 }
374
375 static inline void edma_write_array2(struct edma_cc *ecc, int offset, int i,
376 int j, unsigned val)
377 {
378 edma_write(ecc, offset + ((i * 2 + j) << 2), val);
379 }
380
381 static inline unsigned int edma_shadow0_read(struct edma_cc *ecc, int offset)
382 {
383 return edma_read(ecc, EDMA_SHADOW0 + offset);
384 }
385
386 static inline unsigned int edma_shadow0_read_array(struct edma_cc *ecc,
387 int offset, int i)
388 {
389 return edma_read(ecc, EDMA_SHADOW0 + offset + (i << 2));
390 }
391
392 static inline void edma_shadow0_write(struct edma_cc *ecc, int offset,
393 unsigned val)
394 {
395 edma_write(ecc, EDMA_SHADOW0 + offset, val);
396 }
397
398 static inline void edma_shadow0_write_array(struct edma_cc *ecc, int offset,
399 int i, unsigned val)
400 {
401 edma_write(ecc, EDMA_SHADOW0 + offset + (i << 2), val);
402 }
403
404 static inline unsigned int edma_param_read(struct edma_cc *ecc, int offset,
405 int param_no)
406 {
407 return edma_read(ecc, EDMA_PARM + offset + (param_no << 5));
408 }
409
410 static inline void edma_param_write(struct edma_cc *ecc, int offset,
411 int param_no, unsigned val)
412 {
413 edma_write(ecc, EDMA_PARM + offset + (param_no << 5), val);
414 }
415
416 static inline void edma_param_modify(struct edma_cc *ecc, int offset,
417 int param_no, unsigned and, unsigned or)
418 {
419 edma_modify(ecc, EDMA_PARM + offset + (param_no << 5), and, or);
420 }
421
422 static inline void edma_param_and(struct edma_cc *ecc, int offset, int param_no,
423 unsigned and)
424 {
425 edma_and(ecc, EDMA_PARM + offset + (param_no << 5), and);
426 }
427
428 static inline void edma_param_or(struct edma_cc *ecc, int offset, int param_no,
429 unsigned or)
430 {
431 edma_or(ecc, EDMA_PARM + offset + (param_no << 5), or);
432 }
433
434 static void edma_assign_priority_to_queue(struct edma_cc *ecc, int queue_no,
435 int priority)
436 {
437 int bit = queue_no * 4;
438
439 edma_modify(ecc, EDMA_QUEPRI, ~(0x7 << bit), ((priority & 0x7) << bit));
440 }
441
442 static void edma_set_chmap(struct edma_chan *echan, int slot)
443 {
444 struct edma_cc *ecc = echan->ecc;
445 int channel = EDMA_CHAN_SLOT(echan->ch_num);
446
447 if (ecc->chmap_exist) {
448 slot = EDMA_CHAN_SLOT(slot);
449 edma_write_array(ecc, EDMA_DCHMAP, channel, (slot << 5));
450 }
451 }
452
453 static void edma_setup_interrupt(struct edma_chan *echan, bool enable)
454 {
455 struct edma_cc *ecc = echan->ecc;
456 int channel = EDMA_CHAN_SLOT(echan->ch_num);
457 int idx = EDMA_REG_ARRAY_INDEX(channel);
458 int ch_bit = EDMA_CHANNEL_BIT(channel);
459
460 if (enable) {
461 edma_shadow0_write_array(ecc, SH_ICR, idx, ch_bit);
462 edma_shadow0_write_array(ecc, SH_IESR, idx, ch_bit);
463 } else {
464 edma_shadow0_write_array(ecc, SH_IECR, idx, ch_bit);
465 }
466 }
467
468 /*
469 * paRAM slot management functions
470 */
471 static void edma_write_slot(struct edma_cc *ecc, unsigned slot,
472 const struct edmacc_param *param)
473 {
474 slot = EDMA_CHAN_SLOT(slot);
475 if (slot >= ecc->num_slots)
476 return;
477 memcpy_toio(ecc->base + PARM_OFFSET(slot), param, PARM_SIZE);
478 }
479
480 static int edma_read_slot(struct edma_cc *ecc, unsigned slot,
481 struct edmacc_param *param)
482 {
483 slot = EDMA_CHAN_SLOT(slot);
484 if (slot >= ecc->num_slots)
485 return -EINVAL;
486 memcpy_fromio(param, ecc->base + PARM_OFFSET(slot), PARM_SIZE);
487
488 return 0;
489 }
490
491 /**
492 * edma_alloc_slot - allocate DMA parameter RAM
493 * @ecc: pointer to edma_cc struct
494 * @slot: specific slot to allocate; negative for "any unused slot"
495 *
496 * This allocates a parameter RAM slot, initializing it to hold a
497 * dummy transfer. Slots allocated using this routine have not been
498 * mapped to a hardware DMA channel, and will normally be used by
499 * linking to them from a slot associated with a DMA channel.
500 *
501 * Normal use is to pass EDMA_SLOT_ANY as the @slot, but specific
502 * slots may be allocated on behalf of DSP firmware.
503 *
504 * Returns the number of the slot, else negative errno.
505 */
506 static int edma_alloc_slot(struct edma_cc *ecc, int slot)
507 {
508 if (slot >= 0) {
509 slot = EDMA_CHAN_SLOT(slot);
510 /* Requesting entry paRAM slot for a HW triggered channel. */
511 if (ecc->chmap_exist && slot < ecc->num_channels)
512 slot = EDMA_SLOT_ANY;
513 }
514
515 if (slot < 0) {
516 if (ecc->chmap_exist)
517 slot = 0;
518 else
519 slot = ecc->num_channels;
520 for (;;) {
521 slot = find_next_zero_bit(ecc->slot_inuse,
522 ecc->num_slots,
523 slot);
524 if (slot == ecc->num_slots)
525 return -ENOMEM;
526 if (!test_and_set_bit(slot, ecc->slot_inuse))
527 break;
528 }
529 } else if (slot >= ecc->num_slots) {
530 return -EINVAL;
531 } else if (test_and_set_bit(slot, ecc->slot_inuse)) {
532 return -EBUSY;
533 }
534
535 edma_write_slot(ecc, slot, &dummy_paramset);
536
537 return EDMA_CTLR_CHAN(ecc->id, slot);
538 }
539
540 static void edma_free_slot(struct edma_cc *ecc, unsigned slot)
541 {
542 slot = EDMA_CHAN_SLOT(slot);
543 if (slot >= ecc->num_slots)
544 return;
545
546 edma_write_slot(ecc, slot, &dummy_paramset);
547 clear_bit(slot, ecc->slot_inuse);
548 }
549
550 /**
551 * edma_link - link one parameter RAM slot to another
552 * @ecc: pointer to edma_cc struct
553 * @from: parameter RAM slot originating the link
554 * @to: parameter RAM slot which is the link target
555 *
556 * The originating slot should not be part of any active DMA transfer.
557 */
558 static void edma_link(struct edma_cc *ecc, unsigned from, unsigned to)
559 {
560 if (unlikely(EDMA_CTLR(from) != EDMA_CTLR(to)))
561 dev_warn(ecc->dev, "Ignoring eDMA instance for linking\n");
562
563 from = EDMA_CHAN_SLOT(from);
564 to = EDMA_CHAN_SLOT(to);
565 if (from >= ecc->num_slots || to >= ecc->num_slots)
566 return;
567
568 edma_param_modify(ecc, PARM_LINK_BCNTRLD, from, 0xffff0000,
569 PARM_OFFSET(to));
570 }
571
572 /**
573 * edma_get_position - returns the current transfer point
574 * @ecc: pointer to edma_cc struct
575 * @slot: parameter RAM slot being examined
576 * @dst: true selects the dest position, false the source
577 *
578 * Returns the position of the current active slot
579 */
580 static dma_addr_t edma_get_position(struct edma_cc *ecc, unsigned slot,
581 bool dst)
582 {
583 u32 offs;
584
585 slot = EDMA_CHAN_SLOT(slot);
586 offs = PARM_OFFSET(slot);
587 offs += dst ? PARM_DST : PARM_SRC;
588
589 return edma_read(ecc, offs);
590 }
591
592 /*
593 * Channels with event associations will be triggered by their hardware
594 * events, and channels without such associations will be triggered by
595 * software. (At this writing there is no interface for using software
596 * triggers except with channels that don't support hardware triggers.)
597 */
598 static void edma_start(struct edma_chan *echan)
599 {
600 struct edma_cc *ecc = echan->ecc;
601 int channel = EDMA_CHAN_SLOT(echan->ch_num);
602 int idx = EDMA_REG_ARRAY_INDEX(channel);
603 int ch_bit = EDMA_CHANNEL_BIT(channel);
604
605 if (!echan->hw_triggered) {
606 /* EDMA channels without event association */
607 dev_dbg(ecc->dev, "ESR%d %08x\n", idx,
608 edma_shadow0_read_array(ecc, SH_ESR, idx));
609 edma_shadow0_write_array(ecc, SH_ESR, idx, ch_bit);
610 } else {
611 /* EDMA channel with event association */
612 dev_dbg(ecc->dev, "ER%d %08x\n", idx,
613 edma_shadow0_read_array(ecc, SH_ER, idx));
614 /* Clear any pending event or error */
615 edma_write_array(ecc, EDMA_ECR, idx, ch_bit);
616 edma_write_array(ecc, EDMA_EMCR, idx, ch_bit);
617 /* Clear any SER */
618 edma_shadow0_write_array(ecc, SH_SECR, idx, ch_bit);
619 edma_shadow0_write_array(ecc, SH_EESR, idx, ch_bit);
620 dev_dbg(ecc->dev, "EER%d %08x\n", idx,
621 edma_shadow0_read_array(ecc, SH_EER, idx));
622 }
623 }
624
625 static void edma_stop(struct edma_chan *echan)
626 {
627 struct edma_cc *ecc = echan->ecc;
628 int channel = EDMA_CHAN_SLOT(echan->ch_num);
629 int idx = EDMA_REG_ARRAY_INDEX(channel);
630 int ch_bit = EDMA_CHANNEL_BIT(channel);
631
632 edma_shadow0_write_array(ecc, SH_EECR, idx, ch_bit);
633 edma_shadow0_write_array(ecc, SH_ECR, idx, ch_bit);
634 edma_shadow0_write_array(ecc, SH_SECR, idx, ch_bit);
635 edma_write_array(ecc, EDMA_EMCR, idx, ch_bit);
636
637 /* clear possibly pending completion interrupt */
638 edma_shadow0_write_array(ecc, SH_ICR, idx, ch_bit);
639
640 dev_dbg(ecc->dev, "EER%d %08x\n", idx,
641 edma_shadow0_read_array(ecc, SH_EER, idx));
642
643 /* REVISIT: consider guarding against inappropriate event
644 * chaining by overwriting with dummy_paramset.
645 */
646 }
647
648 /*
649 * Temporarily disable EDMA hardware events on the specified channel,
650 * preventing them from triggering new transfers
651 */
652 static void edma_pause(struct edma_chan *echan)
653 {
654 int channel = EDMA_CHAN_SLOT(echan->ch_num);
655
656 edma_shadow0_write_array(echan->ecc, SH_EECR,
657 EDMA_REG_ARRAY_INDEX(channel),
658 EDMA_CHANNEL_BIT(channel));
659 }
660
661 /* Re-enable EDMA hardware events on the specified channel. */
662 static void edma_resume(struct edma_chan *echan)
663 {
664 int channel = EDMA_CHAN_SLOT(echan->ch_num);
665
666 edma_shadow0_write_array(echan->ecc, SH_EESR,
667 EDMA_REG_ARRAY_INDEX(channel),
668 EDMA_CHANNEL_BIT(channel));
669 }
670
671 static void edma_trigger_channel(struct edma_chan *echan)
672 {
673 struct edma_cc *ecc = echan->ecc;
674 int channel = EDMA_CHAN_SLOT(echan->ch_num);
675 int idx = EDMA_REG_ARRAY_INDEX(channel);
676 int ch_bit = EDMA_CHANNEL_BIT(channel);
677
678 edma_shadow0_write_array(ecc, SH_ESR, idx, ch_bit);
679
680 dev_dbg(ecc->dev, "ESR%d %08x\n", idx,
681 edma_shadow0_read_array(ecc, SH_ESR, idx));
682 }
683
684 static void edma_clean_channel(struct edma_chan *echan)
685 {
686 struct edma_cc *ecc = echan->ecc;
687 int channel = EDMA_CHAN_SLOT(echan->ch_num);
688 int idx = EDMA_REG_ARRAY_INDEX(channel);
689 int ch_bit = EDMA_CHANNEL_BIT(channel);
690
691 dev_dbg(ecc->dev, "EMR%d %08x\n", idx,
692 edma_read_array(ecc, EDMA_EMR, idx));
693 edma_shadow0_write_array(ecc, SH_ECR, idx, ch_bit);
694 /* Clear the corresponding EMR bits */
695 edma_write_array(ecc, EDMA_EMCR, idx, ch_bit);
696 /* Clear any SER */
697 edma_shadow0_write_array(ecc, SH_SECR, idx, ch_bit);
698 edma_write(ecc, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0));
699 }
700
701 /* Move channel to a specific event queue */
702 static void edma_assign_channel_eventq(struct edma_chan *echan,
703 enum dma_event_q eventq_no)
704 {
705 struct edma_cc *ecc = echan->ecc;
706 int channel = EDMA_CHAN_SLOT(echan->ch_num);
707 int bit = (channel & 0x7) * 4;
708
709 /* default to low priority queue */
710 if (eventq_no == EVENTQ_DEFAULT)
711 eventq_no = ecc->default_queue;
712 if (eventq_no >= ecc->num_tc)
713 return;
714
715 eventq_no &= 7;
716 edma_modify_array(ecc, EDMA_DMAQNUM, (channel >> 3), ~(0x7 << bit),
717 eventq_no << bit);
718 }
719
720 static int edma_alloc_channel(struct edma_chan *echan,
721 enum dma_event_q eventq_no)
722 {
723 struct edma_cc *ecc = echan->ecc;
724 int channel = EDMA_CHAN_SLOT(echan->ch_num);
725
726 if (!test_bit(echan->ch_num, ecc->channels_mask)) {
727 dev_err(ecc->dev, "Channel%d is reserved, can not be used!\n",
728 echan->ch_num);
729 return -EINVAL;
730 }
731
732 /* ensure access through shadow region 0 */
733 edma_or_array2(ecc, EDMA_DRAE, 0, EDMA_REG_ARRAY_INDEX(channel),
734 EDMA_CHANNEL_BIT(channel));
735
736 /* ensure no events are pending */
737 edma_stop(echan);
738
739 edma_setup_interrupt(echan, true);
740
741 edma_assign_channel_eventq(echan, eventq_no);
742
743 return 0;
744 }
745
746 static void edma_free_channel(struct edma_chan *echan)
747 {
748 /* ensure no events are pending */
749 edma_stop(echan);
750 /* REVISIT should probably take out of shadow region 0 */
751 edma_setup_interrupt(echan, false);
752 }
753
754 static inline struct edma_cc *to_edma_cc(struct dma_device *d)
755 {
756 return container_of(d, struct edma_cc, dma_slave);
757 }
758
759 static inline struct edma_chan *to_edma_chan(struct dma_chan *c)
760 {
761 return container_of(c, struct edma_chan, vchan.chan);
762 }
763
764 static inline struct edma_desc *to_edma_desc(struct dma_async_tx_descriptor *tx)
765 {
766 return container_of(tx, struct edma_desc, vdesc.tx);
767 }
768
769 static void edma_desc_free(struct virt_dma_desc *vdesc)
770 {
771 kfree(container_of(vdesc, struct edma_desc, vdesc));
772 }
773
774 /* Dispatch a queued descriptor to the controller (caller holds lock) */
775 static void edma_execute(struct edma_chan *echan)
776 {
777 struct edma_cc *ecc = echan->ecc;
778 struct virt_dma_desc *vdesc;
779 struct edma_desc *edesc;
780 struct device *dev = echan->vchan.chan.device->dev;
781 int i, j, left, nslots;
782
783 if (!echan->edesc) {
784 /* Setup is needed for the first transfer */
785 vdesc = vchan_next_desc(&echan->vchan);
786 if (!vdesc)
787 return;
788 list_del(&vdesc->node);
789 echan->edesc = to_edma_desc(&vdesc->tx);
790 }
791
792 edesc = echan->edesc;
793
794 /* Find out how many left */
795 left = edesc->pset_nr - edesc->processed;
796 nslots = min(MAX_NR_SG, left);
797 edesc->sg_len = 0;
798
799 /* Write descriptor PaRAM set(s) */
800 for (i = 0; i < nslots; i++) {
801 j = i + edesc->processed;
802 edma_write_slot(ecc, echan->slot[i], &edesc->pset[j].param);
803 edesc->sg_len += edesc->pset[j].len;
804 dev_vdbg(dev,
805 "\n pset[%d]:\n"
806 " chnum\t%d\n"
807 " slot\t%d\n"
808 " opt\t%08x\n"
809 " src\t%08x\n"
810 " dst\t%08x\n"
811 " abcnt\t%08x\n"
812 " ccnt\t%08x\n"
813 " bidx\t%08x\n"
814 " cidx\t%08x\n"
815 " lkrld\t%08x\n",
816 j, echan->ch_num, echan->slot[i],
817 edesc->pset[j].param.opt,
818 edesc->pset[j].param.src,
819 edesc->pset[j].param.dst,
820 edesc->pset[j].param.a_b_cnt,
821 edesc->pset[j].param.ccnt,
822 edesc->pset[j].param.src_dst_bidx,
823 edesc->pset[j].param.src_dst_cidx,
824 edesc->pset[j].param.link_bcntrld);
825 /* Link to the previous slot if not the last set */
826 if (i != (nslots - 1))
827 edma_link(ecc, echan->slot[i], echan->slot[i + 1]);
828 }
829
830 edesc->processed += nslots;
831
832 /*
833 * If this is either the last set in a set of SG-list transactions
834 * then setup a link to the dummy slot, this results in all future
835 * events being absorbed and that's OK because we're done
836 */
837 if (edesc->processed == edesc->pset_nr) {
838 if (edesc->cyclic)
839 edma_link(ecc, echan->slot[nslots - 1], echan->slot[1]);
840 else
841 edma_link(ecc, echan->slot[nslots - 1],
842 echan->ecc->dummy_slot);
843 }
844
845 if (echan->missed) {
846 /*
847 * This happens due to setup times between intermediate
848 * transfers in long SG lists which have to be broken up into
849 * transfers of MAX_NR_SG
850 */
851 dev_dbg(dev, "missed event on channel %d\n", echan->ch_num);
852 edma_clean_channel(echan);
853 edma_stop(echan);
854 edma_start(echan);
855 edma_trigger_channel(echan);
856 echan->missed = 0;
857 } else if (edesc->processed <= MAX_NR_SG) {
858 dev_dbg(dev, "first transfer starting on channel %d\n",
859 echan->ch_num);
860 edma_start(echan);
861 } else {
862 dev_dbg(dev, "chan: %d: completed %d elements, resuming\n",
863 echan->ch_num, edesc->processed);
864 edma_resume(echan);
865 }
866 }
867
868 static int edma_terminate_all(struct dma_chan *chan)
869 {
870 struct edma_chan *echan = to_edma_chan(chan);
871 unsigned long flags;
872 LIST_HEAD(head);
873
874 spin_lock_irqsave(&echan->vchan.lock, flags);
875
876 /*
877 * Stop DMA activity: we assume the callback will not be called
878 * after edma_dma() returns (even if it does, it will see
879 * echan->edesc is NULL and exit.)
880 */
881 if (echan->edesc) {
882 edma_stop(echan);
883 /* Move the cyclic channel back to default queue */
884 if (!echan->tc && echan->edesc->cyclic)
885 edma_assign_channel_eventq(echan, EVENTQ_DEFAULT);
886
887 vchan_terminate_vdesc(&echan->edesc->vdesc);
888 echan->edesc = NULL;
889 }
890
891 vchan_get_all_descriptors(&echan->vchan, &head);
892 spin_unlock_irqrestore(&echan->vchan.lock, flags);
893 vchan_dma_desc_free_list(&echan->vchan, &head);
894
895 return 0;
896 }
897
898 static void edma_synchronize(struct dma_chan *chan)
899 {
900 struct edma_chan *echan = to_edma_chan(chan);
901
902 vchan_synchronize(&echan->vchan);
903 }
904
905 static int edma_slave_config(struct dma_chan *chan,
906 struct dma_slave_config *cfg)
907 {
908 struct edma_chan *echan = to_edma_chan(chan);
909
910 if (cfg->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES ||
911 cfg->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES)
912 return -EINVAL;
913
914 if (cfg->src_maxburst > chan->device->max_burst ||
915 cfg->dst_maxburst > chan->device->max_burst)
916 return -EINVAL;
917
918 memcpy(&echan->cfg, cfg, sizeof(echan->cfg));
919
920 return 0;
921 }
922
923 static int edma_dma_pause(struct dma_chan *chan)
924 {
925 struct edma_chan *echan = to_edma_chan(chan);
926
927 if (!echan->edesc)
928 return -EINVAL;
929
930 edma_pause(echan);
931 return 0;
932 }
933
934 static int edma_dma_resume(struct dma_chan *chan)
935 {
936 struct edma_chan *echan = to_edma_chan(chan);
937
938 edma_resume(echan);
939 return 0;
940 }
941
942 /*
943 * A PaRAM set configuration abstraction used by other modes
944 * @chan: Channel who's PaRAM set we're configuring
945 * @pset: PaRAM set to initialize and setup.
946 * @src_addr: Source address of the DMA
947 * @dst_addr: Destination address of the DMA
948 * @burst: In units of dev_width, how much to send
949 * @dev_width: How much is the dev_width
950 * @dma_length: Total length of the DMA transfer
951 * @direction: Direction of the transfer
952 */
953 static int edma_config_pset(struct dma_chan *chan, struct edma_pset *epset,
954 dma_addr_t src_addr, dma_addr_t dst_addr, u32 burst,
955 unsigned int acnt, unsigned int dma_length,
956 enum dma_transfer_direction direction)
957 {
958 struct edma_chan *echan = to_edma_chan(chan);
959 struct device *dev = chan->device->dev;
960 struct edmacc_param *param = &epset->param;
961 int bcnt, ccnt, cidx;
962 int src_bidx, dst_bidx, src_cidx, dst_cidx;
963 int absync;
964
965 /* src/dst_maxburst == 0 is the same case as src/dst_maxburst == 1 */
966 if (!burst)
967 burst = 1;
968 /*
969 * If the maxburst is equal to the fifo width, use
970 * A-synced transfers. This allows for large contiguous
971 * buffer transfers using only one PaRAM set.
972 */
973 if (burst == 1) {
974 /*
975 * For the A-sync case, bcnt and ccnt are the remainder
976 * and quotient respectively of the division of:
977 * (dma_length / acnt) by (SZ_64K -1). This is so
978 * that in case bcnt over flows, we have ccnt to use.
979 * Note: In A-sync tranfer only, bcntrld is used, but it
980 * only applies for sg_dma_len(sg) >= SZ_64K.
981 * In this case, the best way adopted is- bccnt for the
982 * first frame will be the remainder below. Then for
983 * every successive frame, bcnt will be SZ_64K-1. This
984 * is assured as bcntrld = 0xffff in end of function.
985 */
986 absync = false;
987 ccnt = dma_length / acnt / (SZ_64K - 1);
988 bcnt = dma_length / acnt - ccnt * (SZ_64K - 1);
989 /*
990 * If bcnt is non-zero, we have a remainder and hence an
991 * extra frame to transfer, so increment ccnt.
992 */
993 if (bcnt)
994 ccnt++;
995 else
996 bcnt = SZ_64K - 1;
997 cidx = acnt;
998 } else {
999 /*
1000 * If maxburst is greater than the fifo address_width,
1001 * use AB-synced transfers where A count is the fifo
1002 * address_width and B count is the maxburst. In this
1003 * case, we are limited to transfers of C count frames
1004 * of (address_width * maxburst) where C count is limited
1005 * to SZ_64K-1. This places an upper bound on the length
1006 * of an SG segment that can be handled.
1007 */
1008 absync = true;
1009 bcnt = burst;
1010 ccnt = dma_length / (acnt * bcnt);
1011 if (ccnt > (SZ_64K - 1)) {
1012 dev_err(dev, "Exceeded max SG segment size\n");
1013 return -EINVAL;
1014 }
1015 cidx = acnt * bcnt;
1016 }
1017
1018 epset->len = dma_length;
1019
1020 if (direction == DMA_MEM_TO_DEV) {
1021 src_bidx = acnt;
1022 src_cidx = cidx;
1023 dst_bidx = 0;
1024 dst_cidx = 0;
1025 epset->addr = src_addr;
1026 } else if (direction == DMA_DEV_TO_MEM) {
1027 src_bidx = 0;
1028 src_cidx = 0;
1029 dst_bidx = acnt;
1030 dst_cidx = cidx;
1031 epset->addr = dst_addr;
1032 } else if (direction == DMA_MEM_TO_MEM) {
1033 src_bidx = acnt;
1034 src_cidx = cidx;
1035 dst_bidx = acnt;
1036 dst_cidx = cidx;
1037 epset->addr = src_addr;
1038 } else {
1039 dev_err(dev, "%s: direction not implemented yet\n", __func__);
1040 return -EINVAL;
1041 }
1042
1043 param->opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num));
1044 /* Configure A or AB synchronized transfers */
1045 if (absync)
1046 param->opt |= SYNCDIM;
1047
1048 param->src = src_addr;
1049 param->dst = dst_addr;
1050
1051 param->src_dst_bidx = (dst_bidx << 16) | src_bidx;
1052 param->src_dst_cidx = (dst_cidx << 16) | src_cidx;
1053
1054 param->a_b_cnt = bcnt << 16 | acnt;
1055 param->ccnt = ccnt;
1056 /*
1057 * Only time when (bcntrld) auto reload is required is for
1058 * A-sync case, and in this case, a requirement of reload value
1059 * of SZ_64K-1 only is assured. 'link' is initially set to NULL
1060 * and then later will be populated by edma_execute.
1061 */
1062 param->link_bcntrld = 0xffffffff;
1063 return absync;
1064 }
1065
1066 static struct dma_async_tx_descriptor *edma_prep_slave_sg(
1067 struct dma_chan *chan, struct scatterlist *sgl,
1068 unsigned int sg_len, enum dma_transfer_direction direction,
1069 unsigned long tx_flags, void *context)
1070 {
1071 struct edma_chan *echan = to_edma_chan(chan);
1072 struct device *dev = chan->device->dev;
1073 struct edma_desc *edesc;
1074 dma_addr_t src_addr = 0, dst_addr = 0;
1075 enum dma_slave_buswidth dev_width;
1076 u32 burst;
1077 struct scatterlist *sg;
1078 int i, nslots, ret;
1079
1080 if (unlikely(!echan || !sgl || !sg_len))
1081 return NULL;
1082
1083 if (direction == DMA_DEV_TO_MEM) {
1084 src_addr = echan->cfg.src_addr;
1085 dev_width = echan->cfg.src_addr_width;
1086 burst = echan->cfg.src_maxburst;
1087 } else if (direction == DMA_MEM_TO_DEV) {
1088 dst_addr = echan->cfg.dst_addr;
1089 dev_width = echan->cfg.dst_addr_width;
1090 burst = echan->cfg.dst_maxburst;
1091 } else {
1092 dev_err(dev, "%s: bad direction: %d\n", __func__, direction);
1093 return NULL;
1094 }
1095
1096 if (dev_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) {
1097 dev_err(dev, "%s: Undefined slave buswidth\n", __func__);
1098 return NULL;
1099 }
1100
1101 edesc = kzalloc(struct_size(edesc, pset, sg_len), GFP_ATOMIC);
1102 if (!edesc)
1103 return NULL;
1104
1105 edesc->pset_nr = sg_len;
1106 edesc->residue = 0;
1107 edesc->direction = direction;
1108 edesc->echan = echan;
1109
1110 /* Allocate a PaRAM slot, if needed */
1111 nslots = min_t(unsigned, MAX_NR_SG, sg_len);
1112
1113 for (i = 0; i < nslots; i++) {
1114 if (echan->slot[i] < 0) {
1115 echan->slot[i] =
1116 edma_alloc_slot(echan->ecc, EDMA_SLOT_ANY);
1117 if (echan->slot[i] < 0) {
1118 kfree(edesc);
1119 dev_err(dev, "%s: Failed to allocate slot\n",
1120 __func__);
1121 return NULL;
1122 }
1123 }
1124 }
1125
1126 /* Configure PaRAM sets for each SG */
1127 for_each_sg(sgl, sg, sg_len, i) {
1128 /* Get address for each SG */
1129 if (direction == DMA_DEV_TO_MEM)
1130 dst_addr = sg_dma_address(sg);
1131 else
1132 src_addr = sg_dma_address(sg);
1133
1134 ret = edma_config_pset(chan, &edesc->pset[i], src_addr,
1135 dst_addr, burst, dev_width,
1136 sg_dma_len(sg), direction);
1137 if (ret < 0) {
1138 kfree(edesc);
1139 return NULL;
1140 }
1141
1142 edesc->absync = ret;
1143 edesc->residue += sg_dma_len(sg);
1144
1145 if (i == sg_len - 1)
1146 /* Enable completion interrupt */
1147 edesc->pset[i].param.opt |= TCINTEN;
1148 else if (!((i+1) % MAX_NR_SG))
1149 /*
1150 * Enable early completion interrupt for the
1151 * intermediateset. In this case the driver will be
1152 * notified when the paRAM set is submitted to TC. This
1153 * will allow more time to set up the next set of slots.
1154 */
1155 edesc->pset[i].param.opt |= (TCINTEN | TCCMODE);
1156 }
1157 edesc->residue_stat = edesc->residue;
1158
1159 return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
1160 }
1161
1162 static struct dma_async_tx_descriptor *edma_prep_dma_memcpy(
1163 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
1164 size_t len, unsigned long tx_flags)
1165 {
1166 int ret, nslots;
1167 struct edma_desc *edesc;
1168 struct device *dev = chan->device->dev;
1169 struct edma_chan *echan = to_edma_chan(chan);
1170 unsigned int width, pset_len, array_size;
1171
1172 if (unlikely(!echan || !len))
1173 return NULL;
1174
1175 /* Align the array size (acnt block) with the transfer properties */
1176 switch (__ffs((src | dest | len))) {
1177 case 0:
1178 array_size = SZ_32K - 1;
1179 break;
1180 case 1:
1181 array_size = SZ_32K - 2;
1182 break;
1183 default:
1184 array_size = SZ_32K - 4;
1185 break;
1186 }
1187
1188 if (len < SZ_64K) {
1189 /*
1190 * Transfer size less than 64K can be handled with one paRAM
1191 * slot and with one burst.
1192 * ACNT = length
1193 */
1194 width = len;
1195 pset_len = len;
1196 nslots = 1;
1197 } else {
1198 /*
1199 * Transfer size bigger than 64K will be handled with maximum of
1200 * two paRAM slots.
1201 * slot1: (full_length / 32767) times 32767 bytes bursts.
1202 * ACNT = 32767, length1: (full_length / 32767) * 32767
1203 * slot2: the remaining amount of data after slot1.
1204 * ACNT = full_length - length1, length2 = ACNT
1205 *
1206 * When the full_length is multibple of 32767 one slot can be
1207 * used to complete the transfer.
1208 */
1209 width = array_size;
1210 pset_len = rounddown(len, width);
1211 /* One slot is enough for lengths multiple of (SZ_32K -1) */
1212 if (unlikely(pset_len == len))
1213 nslots = 1;
1214 else
1215 nslots = 2;
1216 }
1217
1218 edesc = kzalloc(struct_size(edesc, pset, nslots), GFP_ATOMIC);
1219 if (!edesc)
1220 return NULL;
1221
1222 edesc->pset_nr = nslots;
1223 edesc->residue = edesc->residue_stat = len;
1224 edesc->direction = DMA_MEM_TO_MEM;
1225 edesc->echan = echan;
1226
1227 ret = edma_config_pset(chan, &edesc->pset[0], src, dest, 1,
1228 width, pset_len, DMA_MEM_TO_MEM);
1229 if (ret < 0) {
1230 kfree(edesc);
1231 return NULL;
1232 }
1233
1234 edesc->absync = ret;
1235
1236 edesc->pset[0].param.opt |= ITCCHEN;
1237 if (nslots == 1) {
1238 /* Enable transfer complete interrupt if requested */
1239 if (tx_flags & DMA_PREP_INTERRUPT)
1240 edesc->pset[0].param.opt |= TCINTEN;
1241 } else {
1242 /* Enable transfer complete chaining for the first slot */
1243 edesc->pset[0].param.opt |= TCCHEN;
1244
1245 if (echan->slot[1] < 0) {
1246 echan->slot[1] = edma_alloc_slot(echan->ecc,
1247 EDMA_SLOT_ANY);
1248 if (echan->slot[1] < 0) {
1249 kfree(edesc);
1250 dev_err(dev, "%s: Failed to allocate slot\n",
1251 __func__);
1252 return NULL;
1253 }
1254 }
1255 dest += pset_len;
1256 src += pset_len;
1257 pset_len = width = len % array_size;
1258
1259 ret = edma_config_pset(chan, &edesc->pset[1], src, dest, 1,
1260 width, pset_len, DMA_MEM_TO_MEM);
1261 if (ret < 0) {
1262 kfree(edesc);
1263 return NULL;
1264 }
1265
1266 edesc->pset[1].param.opt |= ITCCHEN;
1267 /* Enable transfer complete interrupt if requested */
1268 if (tx_flags & DMA_PREP_INTERRUPT)
1269 edesc->pset[1].param.opt |= TCINTEN;
1270 }
1271
1272 if (!(tx_flags & DMA_PREP_INTERRUPT))
1273 edesc->polled = true;
1274
1275 return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
1276 }
1277
1278 static struct dma_async_tx_descriptor *
1279 edma_prep_dma_interleaved(struct dma_chan *chan,
1280 struct dma_interleaved_template *xt,
1281 unsigned long tx_flags)
1282 {
1283 struct device *dev = chan->device->dev;
1284 struct edma_chan *echan = to_edma_chan(chan);
1285 struct edmacc_param *param;
1286 struct edma_desc *edesc;
1287 size_t src_icg, dst_icg;
1288 int src_bidx, dst_bidx;
1289
1290 /* Slave mode is not supported */
1291 if (is_slave_direction(xt->dir))
1292 return NULL;
1293
1294 if (xt->frame_size != 1 || xt->numf == 0)
1295 return NULL;
1296
1297 if (xt->sgl[0].size > SZ_64K || xt->numf > SZ_64K)
1298 return NULL;
1299
1300 src_icg = dmaengine_get_src_icg(xt, &xt->sgl[0]);
1301 if (src_icg) {
1302 src_bidx = src_icg + xt->sgl[0].size;
1303 } else if (xt->src_inc) {
1304 src_bidx = xt->sgl[0].size;
1305 } else {
1306 dev_err(dev, "%s: SRC constant addressing is not supported\n",
1307 __func__);
1308 return NULL;
1309 }
1310
1311 dst_icg = dmaengine_get_dst_icg(xt, &xt->sgl[0]);
1312 if (dst_icg) {
1313 dst_bidx = dst_icg + xt->sgl[0].size;
1314 } else if (xt->dst_inc) {
1315 dst_bidx = xt->sgl[0].size;
1316 } else {
1317 dev_err(dev, "%s: DST constant addressing is not supported\n",
1318 __func__);
1319 return NULL;
1320 }
1321
1322 if (src_bidx > SZ_64K || dst_bidx > SZ_64K)
1323 return NULL;
1324
1325 edesc = kzalloc(struct_size(edesc, pset, 1), GFP_ATOMIC);
1326 if (!edesc)
1327 return NULL;
1328
1329 edesc->direction = DMA_MEM_TO_MEM;
1330 edesc->echan = echan;
1331 edesc->pset_nr = 1;
1332
1333 param = &edesc->pset[0].param;
1334
1335 param->src = xt->src_start;
1336 param->dst = xt->dst_start;
1337 param->a_b_cnt = xt->numf << 16 | xt->sgl[0].size;
1338 param->ccnt = 1;
1339 param->src_dst_bidx = (dst_bidx << 16) | src_bidx;
1340 param->src_dst_cidx = 0;
1341
1342 param->opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num));
1343 param->opt |= ITCCHEN;
1344 /* Enable transfer complete interrupt if requested */
1345 if (tx_flags & DMA_PREP_INTERRUPT)
1346 param->opt |= TCINTEN;
1347 else
1348 edesc->polled = true;
1349
1350 return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
1351 }
1352
1353 static struct dma_async_tx_descriptor *edma_prep_dma_cyclic(
1354 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
1355 size_t period_len, enum dma_transfer_direction direction,
1356 unsigned long tx_flags)
1357 {
1358 struct edma_chan *echan = to_edma_chan(chan);
1359 struct device *dev = chan->device->dev;
1360 struct edma_desc *edesc;
1361 dma_addr_t src_addr, dst_addr;
1362 enum dma_slave_buswidth dev_width;
1363 bool use_intermediate = false;
1364 u32 burst;
1365 int i, ret, nslots;
1366
1367 if (unlikely(!echan || !buf_len || !period_len))
1368 return NULL;
1369
1370 if (direction == DMA_DEV_TO_MEM) {
1371 src_addr = echan->cfg.src_addr;
1372 dst_addr = buf_addr;
1373 dev_width = echan->cfg.src_addr_width;
1374 burst = echan->cfg.src_maxburst;
1375 } else if (direction == DMA_MEM_TO_DEV) {
1376 src_addr = buf_addr;
1377 dst_addr = echan->cfg.dst_addr;
1378 dev_width = echan->cfg.dst_addr_width;
1379 burst = echan->cfg.dst_maxburst;
1380 } else {
1381 dev_err(dev, "%s: bad direction: %d\n", __func__, direction);
1382 return NULL;
1383 }
1384
1385 if (dev_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) {
1386 dev_err(dev, "%s: Undefined slave buswidth\n", __func__);
1387 return NULL;
1388 }
1389
1390 if (unlikely(buf_len % period_len)) {
1391 dev_err(dev, "Period should be multiple of Buffer length\n");
1392 return NULL;
1393 }
1394
1395 nslots = (buf_len / period_len) + 1;
1396
1397 /*
1398 * Cyclic DMA users such as audio cannot tolerate delays introduced
1399 * by cases where the number of periods is more than the maximum
1400 * number of SGs the EDMA driver can handle at a time. For DMA types
1401 * such as Slave SGs, such delays are tolerable and synchronized,
1402 * but the synchronization is difficult to achieve with Cyclic and
1403 * cannot be guaranteed, so we error out early.
1404 */
1405 if (nslots > MAX_NR_SG) {
1406 /*
1407 * If the burst and period sizes are the same, we can put
1408 * the full buffer into a single period and activate
1409 * intermediate interrupts. This will produce interrupts
1410 * after each burst, which is also after each desired period.
1411 */
1412 if (burst == period_len) {
1413 period_len = buf_len;
1414 nslots = 2;
1415 use_intermediate = true;
1416 } else {
1417 return NULL;
1418 }
1419 }
1420
1421 edesc = kzalloc(struct_size(edesc, pset, nslots), GFP_ATOMIC);
1422 if (!edesc)
1423 return NULL;
1424
1425 edesc->cyclic = 1;
1426 edesc->pset_nr = nslots;
1427 edesc->residue = edesc->residue_stat = buf_len;
1428 edesc->direction = direction;
1429 edesc->echan = echan;
1430
1431 dev_dbg(dev, "%s: channel=%d nslots=%d period_len=%zu buf_len=%zu\n",
1432 __func__, echan->ch_num, nslots, period_len, buf_len);
1433
1434 for (i = 0; i < nslots; i++) {
1435 /* Allocate a PaRAM slot, if needed */
1436 if (echan->slot[i] < 0) {
1437 echan->slot[i] =
1438 edma_alloc_slot(echan->ecc, EDMA_SLOT_ANY);
1439 if (echan->slot[i] < 0) {
1440 kfree(edesc);
1441 dev_err(dev, "%s: Failed to allocate slot\n",
1442 __func__);
1443 return NULL;
1444 }
1445 }
1446
1447 if (i == nslots - 1) {
1448 memcpy(&edesc->pset[i], &edesc->pset[0],
1449 sizeof(edesc->pset[0]));
1450 break;
1451 }
1452
1453 ret = edma_config_pset(chan, &edesc->pset[i], src_addr,
1454 dst_addr, burst, dev_width, period_len,
1455 direction);
1456 if (ret < 0) {
1457 kfree(edesc);
1458 return NULL;
1459 }
1460
1461 if (direction == DMA_DEV_TO_MEM)
1462 dst_addr += period_len;
1463 else
1464 src_addr += period_len;
1465
1466 dev_vdbg(dev, "%s: Configure period %d of buf:\n", __func__, i);
1467 dev_vdbg(dev,
1468 "\n pset[%d]:\n"
1469 " chnum\t%d\n"
1470 " slot\t%d\n"
1471 " opt\t%08x\n"
1472 " src\t%08x\n"
1473 " dst\t%08x\n"
1474 " abcnt\t%08x\n"
1475 " ccnt\t%08x\n"
1476 " bidx\t%08x\n"
1477 " cidx\t%08x\n"
1478 " lkrld\t%08x\n",
1479 i, echan->ch_num, echan->slot[i],
1480 edesc->pset[i].param.opt,
1481 edesc->pset[i].param.src,
1482 edesc->pset[i].param.dst,
1483 edesc->pset[i].param.a_b_cnt,
1484 edesc->pset[i].param.ccnt,
1485 edesc->pset[i].param.src_dst_bidx,
1486 edesc->pset[i].param.src_dst_cidx,
1487 edesc->pset[i].param.link_bcntrld);
1488
1489 edesc->absync = ret;
1490
1491 /*
1492 * Enable period interrupt only if it is requested
1493 */
1494 if (tx_flags & DMA_PREP_INTERRUPT) {
1495 edesc->pset[i].param.opt |= TCINTEN;
1496
1497 /* Also enable intermediate interrupts if necessary */
1498 if (use_intermediate)
1499 edesc->pset[i].param.opt |= ITCINTEN;
1500 }
1501 }
1502
1503 /* Place the cyclic channel to highest priority queue */
1504 if (!echan->tc)
1505 edma_assign_channel_eventq(echan, EVENTQ_0);
1506
1507 return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
1508 }
1509
1510 static void edma_completion_handler(struct edma_chan *echan)
1511 {
1512 struct device *dev = echan->vchan.chan.device->dev;
1513 struct edma_desc *edesc;
1514
1515 spin_lock(&echan->vchan.lock);
1516 edesc = echan->edesc;
1517 if (edesc) {
1518 if (edesc->cyclic) {
1519 vchan_cyclic_callback(&edesc->vdesc);
1520 spin_unlock(&echan->vchan.lock);
1521 return;
1522 } else if (edesc->processed == edesc->pset_nr) {
1523 edesc->residue = 0;
1524 edma_stop(echan);
1525 vchan_cookie_complete(&edesc->vdesc);
1526 echan->edesc = NULL;
1527
1528 dev_dbg(dev, "Transfer completed on channel %d\n",
1529 echan->ch_num);
1530 } else {
1531 dev_dbg(dev, "Sub transfer completed on channel %d\n",
1532 echan->ch_num);
1533
1534 edma_pause(echan);
1535
1536 /* Update statistics for tx_status */
1537 edesc->residue -= edesc->sg_len;
1538 edesc->residue_stat = edesc->residue;
1539 edesc->processed_stat = edesc->processed;
1540 }
1541 edma_execute(echan);
1542 }
1543
1544 spin_unlock(&echan->vchan.lock);
1545 }
1546
1547 /* eDMA interrupt handler */
1548 static irqreturn_t dma_irq_handler(int irq, void *data)
1549 {
1550 struct edma_cc *ecc = data;
1551 int ctlr;
1552 u32 sh_ier;
1553 u32 sh_ipr;
1554 u32 bank;
1555
1556 ctlr = ecc->id;
1557 if (ctlr < 0)
1558 return IRQ_NONE;
1559
1560 dev_vdbg(ecc->dev, "dma_irq_handler\n");
1561
1562 sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 0);
1563 if (!sh_ipr) {
1564 sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 1);
1565 if (!sh_ipr)
1566 return IRQ_NONE;
1567 sh_ier = edma_shadow0_read_array(ecc, SH_IER, 1);
1568 bank = 1;
1569 } else {
1570 sh_ier = edma_shadow0_read_array(ecc, SH_IER, 0);
1571 bank = 0;
1572 }
1573
1574 do {
1575 u32 slot;
1576 u32 channel;
1577
1578 slot = __ffs(sh_ipr);
1579 sh_ipr &= ~(BIT(slot));
1580
1581 if (sh_ier & BIT(slot)) {
1582 channel = (bank << 5) | slot;
1583 /* Clear the corresponding IPR bits */
1584 edma_shadow0_write_array(ecc, SH_ICR, bank, BIT(slot));
1585 edma_completion_handler(&ecc->slave_chans[channel]);
1586 }
1587 } while (sh_ipr);
1588
1589 edma_shadow0_write(ecc, SH_IEVAL, 1);
1590 return IRQ_HANDLED;
1591 }
1592
1593 static void edma_error_handler(struct edma_chan *echan)
1594 {
1595 struct edma_cc *ecc = echan->ecc;
1596 struct device *dev = echan->vchan.chan.device->dev;
1597 struct edmacc_param p;
1598 int err;
1599
1600 if (!echan->edesc)
1601 return;
1602
1603 spin_lock(&echan->vchan.lock);
1604
1605 err = edma_read_slot(ecc, echan->slot[0], &p);
1606
1607 /*
1608 * Issue later based on missed flag which will be sure
1609 * to happen as:
1610 * (1) we finished transmitting an intermediate slot and
1611 * edma_execute is coming up.
1612 * (2) or we finished current transfer and issue will
1613 * call edma_execute.
1614 *
1615 * Important note: issuing can be dangerous here and
1616 * lead to some nasty recursion when we are in a NULL
1617 * slot. So we avoid doing so and set the missed flag.
1618 */
1619 if (err || (p.a_b_cnt == 0 && p.ccnt == 0)) {
1620 dev_dbg(dev, "Error on null slot, setting miss\n");
1621 echan->missed = 1;
1622 } else {
1623 /*
1624 * The slot is already programmed but the event got
1625 * missed, so its safe to issue it here.
1626 */
1627 dev_dbg(dev, "Missed event, TRIGGERING\n");
1628 edma_clean_channel(echan);
1629 edma_stop(echan);
1630 edma_start(echan);
1631 edma_trigger_channel(echan);
1632 }
1633 spin_unlock(&echan->vchan.lock);
1634 }
1635
1636 static inline bool edma_error_pending(struct edma_cc *ecc)
1637 {
1638 if (edma_read_array(ecc, EDMA_EMR, 0) ||
1639 edma_read_array(ecc, EDMA_EMR, 1) ||
1640 edma_read(ecc, EDMA_QEMR) || edma_read(ecc, EDMA_CCERR))
1641 return true;
1642
1643 return false;
1644 }
1645
1646 /* eDMA error interrupt handler */
1647 static irqreturn_t dma_ccerr_handler(int irq, void *data)
1648 {
1649 struct edma_cc *ecc = data;
1650 int i, j;
1651 int ctlr;
1652 unsigned int cnt = 0;
1653 unsigned int val;
1654
1655 ctlr = ecc->id;
1656 if (ctlr < 0)
1657 return IRQ_NONE;
1658
1659 dev_vdbg(ecc->dev, "dma_ccerr_handler\n");
1660
1661 if (!edma_error_pending(ecc)) {
1662 /*
1663 * The registers indicate no pending error event but the irq
1664 * handler has been called.
1665 * Ask eDMA to re-evaluate the error registers.
1666 */
1667 dev_err(ecc->dev, "%s: Error interrupt without error event!\n",
1668 __func__);
1669 edma_write(ecc, EDMA_EEVAL, 1);
1670 return IRQ_NONE;
1671 }
1672
1673 while (1) {
1674 /* Event missed register(s) */
1675 for (j = 0; j < 2; j++) {
1676 unsigned long emr;
1677
1678 val = edma_read_array(ecc, EDMA_EMR, j);
1679 if (!val)
1680 continue;
1681
1682 dev_dbg(ecc->dev, "EMR%d 0x%08x\n", j, val);
1683 emr = val;
1684 for (i = find_next_bit(&emr, 32, 0); i < 32;
1685 i = find_next_bit(&emr, 32, i + 1)) {
1686 int k = (j << 5) + i;
1687
1688 /* Clear the corresponding EMR bits */
1689 edma_write_array(ecc, EDMA_EMCR, j, BIT(i));
1690 /* Clear any SER */
1691 edma_shadow0_write_array(ecc, SH_SECR, j,
1692 BIT(i));
1693 edma_error_handler(&ecc->slave_chans[k]);
1694 }
1695 }
1696
1697 val = edma_read(ecc, EDMA_QEMR);
1698 if (val) {
1699 dev_dbg(ecc->dev, "QEMR 0x%02x\n", val);
1700 /* Not reported, just clear the interrupt reason. */
1701 edma_write(ecc, EDMA_QEMCR, val);
1702 edma_shadow0_write(ecc, SH_QSECR, val);
1703 }
1704
1705 val = edma_read(ecc, EDMA_CCERR);
1706 if (val) {
1707 dev_warn(ecc->dev, "CCERR 0x%08x\n", val);
1708 /* Not reported, just clear the interrupt reason. */
1709 edma_write(ecc, EDMA_CCERRCLR, val);
1710 }
1711
1712 if (!edma_error_pending(ecc))
1713 break;
1714 cnt++;
1715 if (cnt > 10)
1716 break;
1717 }
1718 edma_write(ecc, EDMA_EEVAL, 1);
1719 return IRQ_HANDLED;
1720 }
1721
1722 /* Alloc channel resources */
1723 static int edma_alloc_chan_resources(struct dma_chan *chan)
1724 {
1725 struct edma_chan *echan = to_edma_chan(chan);
1726 struct edma_cc *ecc = echan->ecc;
1727 struct device *dev = ecc->dev;
1728 enum dma_event_q eventq_no = EVENTQ_DEFAULT;
1729 int ret;
1730
1731 if (echan->tc) {
1732 eventq_no = echan->tc->id;
1733 } else if (ecc->tc_list) {
1734 /* memcpy channel */
1735 echan->tc = &ecc->tc_list[ecc->info->default_queue];
1736 eventq_no = echan->tc->id;
1737 }
1738
1739 ret = edma_alloc_channel(echan, eventq_no);
1740 if (ret)
1741 return ret;
1742
1743 echan->slot[0] = edma_alloc_slot(ecc, echan->ch_num);
1744 if (echan->slot[0] < 0) {
1745 dev_err(dev, "Entry slot allocation failed for channel %u\n",
1746 EDMA_CHAN_SLOT(echan->ch_num));
1747 ret = echan->slot[0];
1748 goto err_slot;
1749 }
1750
1751 /* Set up channel -> slot mapping for the entry slot */
1752 edma_set_chmap(echan, echan->slot[0]);
1753 echan->alloced = true;
1754
1755 dev_dbg(dev, "Got eDMA channel %d for virt channel %d (%s trigger)\n",
1756 EDMA_CHAN_SLOT(echan->ch_num), chan->chan_id,
1757 echan->hw_triggered ? "HW" : "SW");
1758
1759 return 0;
1760
1761 err_slot:
1762 edma_free_channel(echan);
1763 return ret;
1764 }
1765
1766 /* Free channel resources */
1767 static void edma_free_chan_resources(struct dma_chan *chan)
1768 {
1769 struct edma_chan *echan = to_edma_chan(chan);
1770 struct device *dev = echan->ecc->dev;
1771 int i;
1772
1773 /* Terminate transfers */
1774 edma_stop(echan);
1775
1776 vchan_free_chan_resources(&echan->vchan);
1777
1778 /* Free EDMA PaRAM slots */
1779 for (i = 0; i < EDMA_MAX_SLOTS; i++) {
1780 if (echan->slot[i] >= 0) {
1781 edma_free_slot(echan->ecc, echan->slot[i]);
1782 echan->slot[i] = -1;
1783 }
1784 }
1785
1786 /* Set entry slot to the dummy slot */
1787 edma_set_chmap(echan, echan->ecc->dummy_slot);
1788
1789 /* Free EDMA channel */
1790 if (echan->alloced) {
1791 edma_free_channel(echan);
1792 echan->alloced = false;
1793 }
1794
1795 echan->tc = NULL;
1796 echan->hw_triggered = false;
1797
1798 dev_dbg(dev, "Free eDMA channel %d for virt channel %d\n",
1799 EDMA_CHAN_SLOT(echan->ch_num), chan->chan_id);
1800 }
1801
1802 /* Send pending descriptor to hardware */
1803 static void edma_issue_pending(struct dma_chan *chan)
1804 {
1805 struct edma_chan *echan = to_edma_chan(chan);
1806 unsigned long flags;
1807
1808 spin_lock_irqsave(&echan->vchan.lock, flags);
1809 if (vchan_issue_pending(&echan->vchan) && !echan->edesc)
1810 edma_execute(echan);
1811 spin_unlock_irqrestore(&echan->vchan.lock, flags);
1812 }
1813
1814 /*
1815 * This limit exists to avoid a possible infinite loop when waiting for proof
1816 * that a particular transfer is completed. This limit can be hit if there
1817 * are large bursts to/from slow devices or the CPU is never able to catch
1818 * the DMA hardware idle. On an AM335x transfering 48 bytes from the UART
1819 * RX-FIFO, as many as 55 loops have been seen.
1820 */
1821 #define EDMA_MAX_TR_WAIT_LOOPS 1000
1822
1823 static u32 edma_residue(struct edma_desc *edesc)
1824 {
1825 bool dst = edesc->direction == DMA_DEV_TO_MEM;
1826 int loop_count = EDMA_MAX_TR_WAIT_LOOPS;
1827 struct edma_chan *echan = edesc->echan;
1828 struct edma_pset *pset = edesc->pset;
1829 dma_addr_t done, pos, pos_old;
1830 int channel = EDMA_CHAN_SLOT(echan->ch_num);
1831 int idx = EDMA_REG_ARRAY_INDEX(channel);
1832 int ch_bit = EDMA_CHANNEL_BIT(channel);
1833 int event_reg;
1834 int i;
1835
1836 /*
1837 * We always read the dst/src position from the first RamPar
1838 * pset. That's the one which is active now.
1839 */
1840 pos = edma_get_position(echan->ecc, echan->slot[0], dst);
1841
1842 /*
1843 * "pos" may represent a transfer request that is still being
1844 * processed by the EDMACC or EDMATC. We will busy wait until
1845 * any one of the situations occurs:
1846 * 1. while and event is pending for the channel
1847 * 2. a position updated
1848 * 3. we hit the loop limit
1849 */
1850 if (is_slave_direction(edesc->direction))
1851 event_reg = SH_ER;
1852 else
1853 event_reg = SH_ESR;
1854
1855 pos_old = pos;
1856 while (edma_shadow0_read_array(echan->ecc, event_reg, idx) & ch_bit) {
1857 pos = edma_get_position(echan->ecc, echan->slot[0], dst);
1858 if (pos != pos_old)
1859 break;
1860
1861 if (!--loop_count) {
1862 dev_dbg_ratelimited(echan->vchan.chan.device->dev,
1863 "%s: timeout waiting for PaRAM update\n",
1864 __func__);
1865 break;
1866 }
1867
1868 cpu_relax();
1869 }
1870
1871 /*
1872 * Cyclic is simple. Just subtract pset[0].addr from pos.
1873 *
1874 * We never update edesc->residue in the cyclic case, so we
1875 * can tell the remaining room to the end of the circular
1876 * buffer.
1877 */
1878 if (edesc->cyclic) {
1879 done = pos - pset->addr;
1880 edesc->residue_stat = edesc->residue - done;
1881 return edesc->residue_stat;
1882 }
1883
1884 /*
1885 * If the position is 0, then EDMA loaded the closing dummy slot, the
1886 * transfer is completed
1887 */
1888 if (!pos)
1889 return 0;
1890 /*
1891 * For SG operation we catch up with the last processed
1892 * status.
1893 */
1894 pset += edesc->processed_stat;
1895
1896 for (i = edesc->processed_stat; i < edesc->processed; i++, pset++) {
1897 /*
1898 * If we are inside this pset address range, we know
1899 * this is the active one. Get the current delta and
1900 * stop walking the psets.
1901 */
1902 if (pos >= pset->addr && pos < pset->addr + pset->len)
1903 return edesc->residue_stat - (pos - pset->addr);
1904
1905 /* Otherwise mark it done and update residue_stat. */
1906 edesc->processed_stat++;
1907 edesc->residue_stat -= pset->len;
1908 }
1909 return edesc->residue_stat;
1910 }
1911
1912 /* Check request completion status */
1913 static enum dma_status edma_tx_status(struct dma_chan *chan,
1914 dma_cookie_t cookie,
1915 struct dma_tx_state *txstate)
1916 {
1917 struct edma_chan *echan = to_edma_chan(chan);
1918 struct dma_tx_state txstate_tmp;
1919 enum dma_status ret;
1920 unsigned long flags;
1921
1922 ret = dma_cookie_status(chan, cookie, txstate);
1923
1924 if (ret == DMA_COMPLETE)
1925 return ret;
1926
1927 /* Provide a dummy dma_tx_state for completion checking */
1928 if (!txstate)
1929 txstate = &txstate_tmp;
1930
1931 spin_lock_irqsave(&echan->vchan.lock, flags);
1932 if (echan->edesc && echan->edesc->vdesc.tx.cookie == cookie) {
1933 txstate->residue = edma_residue(echan->edesc);
1934 } else {
1935 struct virt_dma_desc *vdesc = vchan_find_desc(&echan->vchan,
1936 cookie);
1937
1938 if (vdesc)
1939 txstate->residue = to_edma_desc(&vdesc->tx)->residue;
1940 else
1941 txstate->residue = 0;
1942 }
1943
1944 /*
1945 * Mark the cookie completed if the residue is 0 for non cyclic
1946 * transfers
1947 */
1948 if (ret != DMA_COMPLETE && !txstate->residue &&
1949 echan->edesc && echan->edesc->polled &&
1950 echan->edesc->vdesc.tx.cookie == cookie) {
1951 edma_stop(echan);
1952 vchan_cookie_complete(&echan->edesc->vdesc);
1953 echan->edesc = NULL;
1954 edma_execute(echan);
1955 ret = DMA_COMPLETE;
1956 }
1957
1958 spin_unlock_irqrestore(&echan->vchan.lock, flags);
1959
1960 return ret;
1961 }
1962
1963 static bool edma_is_memcpy_channel(int ch_num, s32 *memcpy_channels)
1964 {
1965 if (!memcpy_channels)
1966 return false;
1967 while (*memcpy_channels != -1) {
1968 if (*memcpy_channels == ch_num)
1969 return true;
1970 memcpy_channels++;
1971 }
1972 return false;
1973 }
1974
1975 #define EDMA_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
1976 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
1977 BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) | \
1978 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
1979
1980 static void edma_dma_init(struct edma_cc *ecc, bool legacy_mode)
1981 {
1982 struct dma_device *s_ddev = &ecc->dma_slave;
1983 struct dma_device *m_ddev = NULL;
1984 s32 *memcpy_channels = ecc->info->memcpy_channels;
1985 int i, j;
1986
1987 dma_cap_zero(s_ddev->cap_mask);
1988 dma_cap_set(DMA_SLAVE, s_ddev->cap_mask);
1989 dma_cap_set(DMA_CYCLIC, s_ddev->cap_mask);
1990 if (ecc->legacy_mode && !memcpy_channels) {
1991 dev_warn(ecc->dev,
1992 "Legacy memcpy is enabled, things might not work\n");
1993
1994 dma_cap_set(DMA_MEMCPY, s_ddev->cap_mask);
1995 dma_cap_set(DMA_INTERLEAVE, s_ddev->cap_mask);
1996 s_ddev->device_prep_dma_memcpy = edma_prep_dma_memcpy;
1997 s_ddev->device_prep_interleaved_dma = edma_prep_dma_interleaved;
1998 s_ddev->directions = BIT(DMA_MEM_TO_MEM);
1999 }
2000
2001 s_ddev->device_prep_slave_sg = edma_prep_slave_sg;
2002 s_ddev->device_prep_dma_cyclic = edma_prep_dma_cyclic;
2003 s_ddev->device_alloc_chan_resources = edma_alloc_chan_resources;
2004 s_ddev->device_free_chan_resources = edma_free_chan_resources;
2005 s_ddev->device_issue_pending = edma_issue_pending;
2006 s_ddev->device_tx_status = edma_tx_status;
2007 s_ddev->device_config = edma_slave_config;
2008 s_ddev->device_pause = edma_dma_pause;
2009 s_ddev->device_resume = edma_dma_resume;
2010 s_ddev->device_terminate_all = edma_terminate_all;
2011 s_ddev->device_synchronize = edma_synchronize;
2012
2013 s_ddev->src_addr_widths = EDMA_DMA_BUSWIDTHS;
2014 s_ddev->dst_addr_widths = EDMA_DMA_BUSWIDTHS;
2015 s_ddev->directions |= (BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV));
2016 s_ddev->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
2017 s_ddev->max_burst = SZ_32K - 1; /* CIDX: 16bit signed */
2018
2019 s_ddev->dev = ecc->dev;
2020 INIT_LIST_HEAD(&s_ddev->channels);
2021
2022 if (memcpy_channels) {
2023 m_ddev = devm_kzalloc(ecc->dev, sizeof(*m_ddev), GFP_KERNEL);
2024 if (!m_ddev) {
2025 dev_warn(ecc->dev, "memcpy is disabled due to OoM\n");
2026 memcpy_channels = NULL;
2027 goto ch_setup;
2028 }
2029 ecc->dma_memcpy = m_ddev;
2030
2031 dma_cap_zero(m_ddev->cap_mask);
2032 dma_cap_set(DMA_MEMCPY, m_ddev->cap_mask);
2033 dma_cap_set(DMA_INTERLEAVE, m_ddev->cap_mask);
2034
2035 m_ddev->device_prep_dma_memcpy = edma_prep_dma_memcpy;
2036 m_ddev->device_prep_interleaved_dma = edma_prep_dma_interleaved;
2037 m_ddev->device_alloc_chan_resources = edma_alloc_chan_resources;
2038 m_ddev->device_free_chan_resources = edma_free_chan_resources;
2039 m_ddev->device_issue_pending = edma_issue_pending;
2040 m_ddev->device_tx_status = edma_tx_status;
2041 m_ddev->device_config = edma_slave_config;
2042 m_ddev->device_pause = edma_dma_pause;
2043 m_ddev->device_resume = edma_dma_resume;
2044 m_ddev->device_terminate_all = edma_terminate_all;
2045 m_ddev->device_synchronize = edma_synchronize;
2046
2047 m_ddev->src_addr_widths = EDMA_DMA_BUSWIDTHS;
2048 m_ddev->dst_addr_widths = EDMA_DMA_BUSWIDTHS;
2049 m_ddev->directions = BIT(DMA_MEM_TO_MEM);
2050 m_ddev->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
2051
2052 m_ddev->dev = ecc->dev;
2053 INIT_LIST_HEAD(&m_ddev->channels);
2054 } else if (!ecc->legacy_mode) {
2055 dev_info(ecc->dev, "memcpy is disabled\n");
2056 }
2057
2058 ch_setup:
2059 for (i = 0; i < ecc->num_channels; i++) {
2060 struct edma_chan *echan = &ecc->slave_chans[i];
2061 echan->ch_num = EDMA_CTLR_CHAN(ecc->id, i);
2062 echan->ecc = ecc;
2063 echan->vchan.desc_free = edma_desc_free;
2064
2065 if (m_ddev && edma_is_memcpy_channel(i, memcpy_channels))
2066 vchan_init(&echan->vchan, m_ddev);
2067 else
2068 vchan_init(&echan->vchan, s_ddev);
2069
2070 INIT_LIST_HEAD(&echan->node);
2071 for (j = 0; j < EDMA_MAX_SLOTS; j++)
2072 echan->slot[j] = -1;
2073 }
2074 }
2075
2076 static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata,
2077 struct edma_cc *ecc)
2078 {
2079 int i;
2080 u32 value, cccfg;
2081 s8 (*queue_priority_map)[2];
2082
2083 /* Decode the eDMA3 configuration from CCCFG register */
2084 cccfg = edma_read(ecc, EDMA_CCCFG);
2085
2086 value = GET_NUM_REGN(cccfg);
2087 ecc->num_region = BIT(value);
2088
2089 value = GET_NUM_DMACH(cccfg);
2090 ecc->num_channels = BIT(value + 1);
2091
2092 value = GET_NUM_QDMACH(cccfg);
2093 ecc->num_qchannels = value * 2;
2094
2095 value = GET_NUM_PAENTRY(cccfg);
2096 ecc->num_slots = BIT(value + 4);
2097
2098 value = GET_NUM_EVQUE(cccfg);
2099 ecc->num_tc = value + 1;
2100
2101 ecc->chmap_exist = (cccfg & CHMAP_EXIST) ? true : false;
2102
2103 dev_dbg(dev, "eDMA3 CC HW configuration (cccfg: 0x%08x):\n", cccfg);
2104 dev_dbg(dev, "num_region: %u\n", ecc->num_region);
2105 dev_dbg(dev, "num_channels: %u\n", ecc->num_channels);
2106 dev_dbg(dev, "num_qchannels: %u\n", ecc->num_qchannels);
2107 dev_dbg(dev, "num_slots: %u\n", ecc->num_slots);
2108 dev_dbg(dev, "num_tc: %u\n", ecc->num_tc);
2109 dev_dbg(dev, "chmap_exist: %s\n", ecc->chmap_exist ? "yes" : "no");
2110
2111 /* Nothing need to be done if queue priority is provided */
2112 if (pdata->queue_priority_mapping)
2113 return 0;
2114
2115 /*
2116 * Configure TC/queue priority as follows:
2117 * Q0 - priority 0
2118 * Q1 - priority 1
2119 * Q2 - priority 2
2120 * ...
2121 * The meaning of priority numbers: 0 highest priority, 7 lowest
2122 * priority. So Q0 is the highest priority queue and the last queue has
2123 * the lowest priority.
2124 */
2125 queue_priority_map = devm_kcalloc(dev, ecc->num_tc + 1, sizeof(s8),
2126 GFP_KERNEL);
2127 if (!queue_priority_map)
2128 return -ENOMEM;
2129
2130 for (i = 0; i < ecc->num_tc; i++) {
2131 queue_priority_map[i][0] = i;
2132 queue_priority_map[i][1] = i;
2133 }
2134 queue_priority_map[i][0] = -1;
2135 queue_priority_map[i][1] = -1;
2136
2137 pdata->queue_priority_mapping = queue_priority_map;
2138 /* Default queue has the lowest priority */
2139 pdata->default_queue = i - 1;
2140
2141 return 0;
2142 }
2143
2144 #if IS_ENABLED(CONFIG_OF)
2145 static int edma_xbar_event_map(struct device *dev, struct edma_soc_info *pdata,
2146 size_t sz)
2147 {
2148 const char pname[] = "ti,edma-xbar-event-map";
2149 struct resource res;
2150 void __iomem *xbar;
2151 s16 (*xbar_chans)[2];
2152 size_t nelm = sz / sizeof(s16);
2153 u32 shift, offset, mux;
2154 int ret, i;
2155
2156 xbar_chans = devm_kcalloc(dev, nelm + 2, sizeof(s16), GFP_KERNEL);
2157 if (!xbar_chans)
2158 return -ENOMEM;
2159
2160 ret = of_address_to_resource(dev->of_node, 1, &res);
2161 if (ret)
2162 return -ENOMEM;
2163
2164 xbar = devm_ioremap(dev, res.start, resource_size(&res));
2165 if (!xbar)
2166 return -ENOMEM;
2167
2168 ret = of_property_read_u16_array(dev->of_node, pname, (u16 *)xbar_chans,
2169 nelm);
2170 if (ret)
2171 return -EIO;
2172
2173 /* Invalidate last entry for the other user of this mess */
2174 nelm >>= 1;
2175 xbar_chans[nelm][0] = -1;
2176 xbar_chans[nelm][1] = -1;
2177
2178 for (i = 0; i < nelm; i++) {
2179 shift = (xbar_chans[i][1] & 0x03) << 3;
2180 offset = xbar_chans[i][1] & 0xfffffffc;
2181 mux = readl(xbar + offset);
2182 mux &= ~(0xff << shift);
2183 mux |= xbar_chans[i][0] << shift;
2184 writel(mux, (xbar + offset));
2185 }
2186
2187 pdata->xbar_chans = (const s16 (*)[2]) xbar_chans;
2188 return 0;
2189 }
2190
2191 static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev,
2192 bool legacy_mode)
2193 {
2194 struct edma_soc_info *info;
2195 struct property *prop;
2196 int sz, ret;
2197
2198 info = devm_kzalloc(dev, sizeof(struct edma_soc_info), GFP_KERNEL);
2199 if (!info)
2200 return ERR_PTR(-ENOMEM);
2201
2202 if (legacy_mode) {
2203 prop = of_find_property(dev->of_node, "ti,edma-xbar-event-map",
2204 &sz);
2205 if (prop) {
2206 ret = edma_xbar_event_map(dev, info, sz);
2207 if (ret)
2208 return ERR_PTR(ret);
2209 }
2210 return info;
2211 }
2212
2213 /* Get the list of channels allocated to be used for memcpy */
2214 prop = of_find_property(dev->of_node, "ti,edma-memcpy-channels", &sz);
2215 if (prop) {
2216 const char pname[] = "ti,edma-memcpy-channels";
2217 size_t nelm = sz / sizeof(s32);
2218 s32 *memcpy_ch;
2219
2220 memcpy_ch = devm_kcalloc(dev, nelm + 1, sizeof(s32),
2221 GFP_KERNEL);
2222 if (!memcpy_ch)
2223 return ERR_PTR(-ENOMEM);
2224
2225 ret = of_property_read_u32_array(dev->of_node, pname,
2226 (u32 *)memcpy_ch, nelm);
2227 if (ret)
2228 return ERR_PTR(ret);
2229
2230 memcpy_ch[nelm] = -1;
2231 info->memcpy_channels = memcpy_ch;
2232 }
2233
2234 prop = of_find_property(dev->of_node, "ti,edma-reserved-slot-ranges",
2235 &sz);
2236 if (prop) {
2237 const char pname[] = "ti,edma-reserved-slot-ranges";
2238 u32 (*tmp)[2];
2239 s16 (*rsv_slots)[2];
2240 size_t nelm = sz / sizeof(*tmp);
2241 struct edma_rsv_info *rsv_info;
2242 int i;
2243
2244 if (!nelm)
2245 return info;
2246
2247 tmp = kcalloc(nelm, sizeof(*tmp), GFP_KERNEL);
2248 if (!tmp)
2249 return ERR_PTR(-ENOMEM);
2250
2251 rsv_info = devm_kzalloc(dev, sizeof(*rsv_info), GFP_KERNEL);
2252 if (!rsv_info) {
2253 kfree(tmp);
2254 return ERR_PTR(-ENOMEM);
2255 }
2256
2257 rsv_slots = devm_kcalloc(dev, nelm + 1, sizeof(*rsv_slots),
2258 GFP_KERNEL);
2259 if (!rsv_slots) {
2260 kfree(tmp);
2261 return ERR_PTR(-ENOMEM);
2262 }
2263
2264 ret = of_property_read_u32_array(dev->of_node, pname,
2265 (u32 *)tmp, nelm * 2);
2266 if (ret) {
2267 kfree(tmp);
2268 return ERR_PTR(ret);
2269 }
2270
2271 for (i = 0; i < nelm; i++) {
2272 rsv_slots[i][0] = tmp[i][0];
2273 rsv_slots[i][1] = tmp[i][1];
2274 }
2275 rsv_slots[nelm][0] = -1;
2276 rsv_slots[nelm][1] = -1;
2277
2278 info->rsv = rsv_info;
2279 info->rsv->rsv_slots = (const s16 (*)[2])rsv_slots;
2280
2281 kfree(tmp);
2282 }
2283
2284 return info;
2285 }
2286
2287 static struct dma_chan *of_edma_xlate(struct of_phandle_args *dma_spec,
2288 struct of_dma *ofdma)
2289 {
2290 struct edma_cc *ecc = ofdma->of_dma_data;
2291 struct dma_chan *chan = NULL;
2292 struct edma_chan *echan;
2293 int i;
2294
2295 if (!ecc || dma_spec->args_count < 1)
2296 return NULL;
2297
2298 for (i = 0; i < ecc->num_channels; i++) {
2299 echan = &ecc->slave_chans[i];
2300 if (echan->ch_num == dma_spec->args[0]) {
2301 chan = &echan->vchan.chan;
2302 break;
2303 }
2304 }
2305
2306 if (!chan)
2307 return NULL;
2308
2309 if (echan->ecc->legacy_mode && dma_spec->args_count == 1)
2310 goto out;
2311
2312 if (!echan->ecc->legacy_mode && dma_spec->args_count == 2 &&
2313 dma_spec->args[1] < echan->ecc->num_tc) {
2314 echan->tc = &echan->ecc->tc_list[dma_spec->args[1]];
2315 goto out;
2316 }
2317
2318 return NULL;
2319 out:
2320 /* The channel is going to be used as HW synchronized */
2321 echan->hw_triggered = true;
2322 return dma_get_slave_channel(chan);
2323 }
2324 #else
2325 static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev,
2326 bool legacy_mode)
2327 {
2328 return ERR_PTR(-EINVAL);
2329 }
2330
2331 static struct dma_chan *of_edma_xlate(struct of_phandle_args *dma_spec,
2332 struct of_dma *ofdma)
2333 {
2334 return NULL;
2335 }
2336 #endif
2337
2338 static bool edma_filter_fn(struct dma_chan *chan, void *param);
2339
2340 static int edma_probe(struct platform_device *pdev)
2341 {
2342 struct edma_soc_info *info = pdev->dev.platform_data;
2343 s8 (*queue_priority_mapping)[2];
2344 const s16 (*reserved)[2];
2345 int i, irq;
2346 char *irq_name;
2347 struct resource *mem;
2348 struct device_node *node = pdev->dev.of_node;
2349 struct device *dev = &pdev->dev;
2350 struct edma_cc *ecc;
2351 bool legacy_mode = true;
2352 int ret;
2353
2354 if (node) {
2355 const struct of_device_id *match;
2356
2357 match = of_match_node(edma_of_ids, node);
2358 if (match && (*(u32 *)match->data) == EDMA_BINDING_TPCC)
2359 legacy_mode = false;
2360
2361 info = edma_setup_info_from_dt(dev, legacy_mode);
2362 if (IS_ERR(info)) {
2363 dev_err(dev, "failed to get DT data\n");
2364 return PTR_ERR(info);
2365 }
2366 }
2367
2368 if (!info)
2369 return -ENODEV;
2370
2371 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
2372 if (ret)
2373 return ret;
2374
2375 ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL);
2376 if (!ecc)
2377 return -ENOMEM;
2378
2379 ecc->dev = dev;
2380 ecc->id = pdev->id;
2381 ecc->legacy_mode = legacy_mode;
2382 /* When booting with DT the pdev->id is -1 */
2383 if (ecc->id < 0)
2384 ecc->id = 0;
2385
2386 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "edma3_cc");
2387 if (!mem) {
2388 dev_dbg(dev, "mem resource not found, using index 0\n");
2389 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2390 if (!mem) {
2391 dev_err(dev, "no mem resource?\n");
2392 return -ENODEV;
2393 }
2394 }
2395 ecc->base = devm_ioremap_resource(dev, mem);
2396 if (IS_ERR(ecc->base))
2397 return PTR_ERR(ecc->base);
2398
2399 platform_set_drvdata(pdev, ecc);
2400
2401 pm_runtime_enable(dev);
2402 ret = pm_runtime_get_sync(dev);
2403 if (ret < 0) {
2404 dev_err(dev, "pm_runtime_get_sync() failed\n");
2405 pm_runtime_disable(dev);
2406 return ret;
2407 }
2408
2409 /* Get eDMA3 configuration from IP */
2410 ret = edma_setup_from_hw(dev, info, ecc);
2411 if (ret)
2412 goto err_disable_pm;
2413
2414 /* Allocate memory based on the information we got from the IP */
2415 ecc->slave_chans = devm_kcalloc(dev, ecc->num_channels,
2416 sizeof(*ecc->slave_chans), GFP_KERNEL);
2417
2418 ecc->slot_inuse = devm_kcalloc(dev, BITS_TO_LONGS(ecc->num_slots),
2419 sizeof(unsigned long), GFP_KERNEL);
2420
2421 ecc->channels_mask = devm_kcalloc(dev,
2422 BITS_TO_LONGS(ecc->num_channels),
2423 sizeof(unsigned long), GFP_KERNEL);
2424 if (!ecc->slave_chans || !ecc->slot_inuse || !ecc->channels_mask) {
2425 ret = -ENOMEM;
2426 goto err_disable_pm;
2427 }
2428
2429 /* Mark all channels available initially */
2430 bitmap_fill(ecc->channels_mask, ecc->num_channels);
2431
2432 ecc->default_queue = info->default_queue;
2433
2434 if (info->rsv) {
2435 /* Set the reserved slots in inuse list */
2436 reserved = info->rsv->rsv_slots;
2437 if (reserved) {
2438 for (i = 0; reserved[i][0] != -1; i++)
2439 bitmap_set(ecc->slot_inuse, reserved[i][0],
2440 reserved[i][1]);
2441 }
2442
2443 /* Clear channels not usable for Linux */
2444 reserved = info->rsv->rsv_chans;
2445 if (reserved) {
2446 for (i = 0; reserved[i][0] != -1; i++)
2447 bitmap_clear(ecc->channels_mask, reserved[i][0],
2448 reserved[i][1]);
2449 }
2450 }
2451
2452 for (i = 0; i < ecc->num_slots; i++) {
2453 /* Reset only unused - not reserved - paRAM slots */
2454 if (!test_bit(i, ecc->slot_inuse))
2455 edma_write_slot(ecc, i, &dummy_paramset);
2456 }
2457
2458 irq = platform_get_irq_byname(pdev, "edma3_ccint");
2459 if (irq < 0 && node)
2460 irq = irq_of_parse_and_map(node, 0);
2461
2462 if (irq >= 0) {
2463 irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_ccint",
2464 dev_name(dev));
2465 ret = devm_request_irq(dev, irq, dma_irq_handler, 0, irq_name,
2466 ecc);
2467 if (ret) {
2468 dev_err(dev, "CCINT (%d) failed --> %d\n", irq, ret);
2469 goto err_disable_pm;
2470 }
2471 ecc->ccint = irq;
2472 }
2473
2474 irq = platform_get_irq_byname(pdev, "edma3_ccerrint");
2475 if (irq < 0 && node)
2476 irq = irq_of_parse_and_map(node, 2);
2477
2478 if (irq >= 0) {
2479 irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_ccerrint",
2480 dev_name(dev));
2481 ret = devm_request_irq(dev, irq, dma_ccerr_handler, 0, irq_name,
2482 ecc);
2483 if (ret) {
2484 dev_err(dev, "CCERRINT (%d) failed --> %d\n", irq, ret);
2485 goto err_disable_pm;
2486 }
2487 ecc->ccerrint = irq;
2488 }
2489
2490 ecc->dummy_slot = edma_alloc_slot(ecc, EDMA_SLOT_ANY);
2491 if (ecc->dummy_slot < 0) {
2492 dev_err(dev, "Can't allocate PaRAM dummy slot\n");
2493 ret = ecc->dummy_slot;
2494 goto err_disable_pm;
2495 }
2496
2497 queue_priority_mapping = info->queue_priority_mapping;
2498
2499 if (!ecc->legacy_mode) {
2500 int lowest_priority = 0;
2501 unsigned int array_max;
2502 struct of_phandle_args tc_args;
2503
2504 ecc->tc_list = devm_kcalloc(dev, ecc->num_tc,
2505 sizeof(*ecc->tc_list), GFP_KERNEL);
2506 if (!ecc->tc_list) {
2507 ret = -ENOMEM;
2508 goto err_reg1;
2509 }
2510
2511 for (i = 0;; i++) {
2512 ret = of_parse_phandle_with_fixed_args(node, "ti,tptcs",
2513 1, i, &tc_args);
2514 if (ret || i == ecc->num_tc)
2515 break;
2516
2517 ecc->tc_list[i].node = tc_args.np;
2518 ecc->tc_list[i].id = i;
2519 queue_priority_mapping[i][1] = tc_args.args[0];
2520 if (queue_priority_mapping[i][1] > lowest_priority) {
2521 lowest_priority = queue_priority_mapping[i][1];
2522 info->default_queue = i;
2523 }
2524 }
2525
2526 /* See if we have optional dma-channel-mask array */
2527 array_max = DIV_ROUND_UP(ecc->num_channels, BITS_PER_TYPE(u32));
2528 ret = of_property_read_variable_u32_array(node,
2529 "dma-channel-mask",
2530 (u32 *)ecc->channels_mask,
2531 1, array_max);
2532 if (ret > 0 && ret != array_max)
2533 dev_warn(dev, "dma-channel-mask is not complete.\n");
2534 else if (ret == -EOVERFLOW || ret == -ENODATA)
2535 dev_warn(dev,
2536 "dma-channel-mask is out of range or empty\n");
2537 }
2538
2539 /* Event queue priority mapping */
2540 for (i = 0; queue_priority_mapping[i][0] != -1; i++)
2541 edma_assign_priority_to_queue(ecc, queue_priority_mapping[i][0],
2542 queue_priority_mapping[i][1]);
2543
2544 edma_write_array2(ecc, EDMA_DRAE, 0, 0, 0x0);
2545 edma_write_array2(ecc, EDMA_DRAE, 0, 1, 0x0);
2546 edma_write_array(ecc, EDMA_QRAE, 0, 0x0);
2547
2548 ecc->info = info;
2549
2550 /* Init the dma device and channels */
2551 edma_dma_init(ecc, legacy_mode);
2552
2553 for (i = 0; i < ecc->num_channels; i++) {
2554 /* Do not touch reserved channels */
2555 if (!test_bit(i, ecc->channels_mask))
2556 continue;
2557
2558 /* Assign all channels to the default queue */
2559 edma_assign_channel_eventq(&ecc->slave_chans[i],
2560 info->default_queue);
2561 /* Set entry slot to the dummy slot */
2562 edma_set_chmap(&ecc->slave_chans[i], ecc->dummy_slot);
2563 }
2564
2565 ecc->dma_slave.filter.map = info->slave_map;
2566 ecc->dma_slave.filter.mapcnt = info->slavecnt;
2567 ecc->dma_slave.filter.fn = edma_filter_fn;
2568
2569 ret = dma_async_device_register(&ecc->dma_slave);
2570 if (ret) {
2571 dev_err(dev, "slave ddev registration failed (%d)\n", ret);
2572 goto err_reg1;
2573 }
2574
2575 if (ecc->dma_memcpy) {
2576 ret = dma_async_device_register(ecc->dma_memcpy);
2577 if (ret) {
2578 dev_err(dev, "memcpy ddev registration failed (%d)\n",
2579 ret);
2580 dma_async_device_unregister(&ecc->dma_slave);
2581 goto err_reg1;
2582 }
2583 }
2584
2585 if (node)
2586 of_dma_controller_register(node, of_edma_xlate, ecc);
2587
2588 dev_info(dev, "TI EDMA DMA engine driver\n");
2589
2590 return 0;
2591
2592 err_reg1:
2593 edma_free_slot(ecc, ecc->dummy_slot);
2594 err_disable_pm:
2595 pm_runtime_put_sync(dev);
2596 pm_runtime_disable(dev);
2597 return ret;
2598 }
2599
2600 static void edma_cleanupp_vchan(struct dma_device *dmadev)
2601 {
2602 struct edma_chan *echan, *_echan;
2603
2604 list_for_each_entry_safe(echan, _echan,
2605 &dmadev->channels, vchan.chan.device_node) {
2606 list_del(&echan->vchan.chan.device_node);
2607 tasklet_kill(&echan->vchan.task);
2608 }
2609 }
2610
2611 static int edma_remove(struct platform_device *pdev)
2612 {
2613 struct device *dev = &pdev->dev;
2614 struct edma_cc *ecc = dev_get_drvdata(dev);
2615
2616 devm_free_irq(dev, ecc->ccint, ecc);
2617 devm_free_irq(dev, ecc->ccerrint, ecc);
2618
2619 edma_cleanupp_vchan(&ecc->dma_slave);
2620
2621 if (dev->of_node)
2622 of_dma_controller_free(dev->of_node);
2623 dma_async_device_unregister(&ecc->dma_slave);
2624 if (ecc->dma_memcpy)
2625 dma_async_device_unregister(ecc->dma_memcpy);
2626 edma_free_slot(ecc, ecc->dummy_slot);
2627 pm_runtime_put_sync(dev);
2628 pm_runtime_disable(dev);
2629
2630 return 0;
2631 }
2632
2633 #ifdef CONFIG_PM_SLEEP
2634 static int edma_pm_suspend(struct device *dev)
2635 {
2636 struct edma_cc *ecc = dev_get_drvdata(dev);
2637 struct edma_chan *echan = ecc->slave_chans;
2638 int i;
2639
2640 for (i = 0; i < ecc->num_channels; i++) {
2641 if (echan[i].alloced)
2642 edma_setup_interrupt(&echan[i], false);
2643 }
2644
2645 return 0;
2646 }
2647
2648 static int edma_pm_resume(struct device *dev)
2649 {
2650 struct edma_cc *ecc = dev_get_drvdata(dev);
2651 struct edma_chan *echan = ecc->slave_chans;
2652 int i;
2653 s8 (*queue_priority_mapping)[2];
2654
2655 /* re initialize dummy slot to dummy param set */
2656 edma_write_slot(ecc, ecc->dummy_slot, &dummy_paramset);
2657
2658 queue_priority_mapping = ecc->info->queue_priority_mapping;
2659
2660 /* Event queue priority mapping */
2661 for (i = 0; queue_priority_mapping[i][0] != -1; i++)
2662 edma_assign_priority_to_queue(ecc, queue_priority_mapping[i][0],
2663 queue_priority_mapping[i][1]);
2664
2665 for (i = 0; i < ecc->num_channels; i++) {
2666 if (echan[i].alloced) {
2667 /* ensure access through shadow region 0 */
2668 edma_or_array2(ecc, EDMA_DRAE, 0,
2669 EDMA_REG_ARRAY_INDEX(i),
2670 EDMA_CHANNEL_BIT(i));
2671
2672 edma_setup_interrupt(&echan[i], true);
2673
2674 /* Set up channel -> slot mapping for the entry slot */
2675 edma_set_chmap(&echan[i], echan[i].slot[0]);
2676 }
2677 }
2678
2679 return 0;
2680 }
2681 #endif
2682
2683 static const struct dev_pm_ops edma_pm_ops = {
2684 SET_LATE_SYSTEM_SLEEP_PM_OPS(edma_pm_suspend, edma_pm_resume)
2685 };
2686
2687 static struct platform_driver edma_driver = {
2688 .probe = edma_probe,
2689 .remove = edma_remove,
2690 .driver = {
2691 .name = "edma",
2692 .pm = &edma_pm_ops,
2693 .of_match_table = edma_of_ids,
2694 },
2695 };
2696
2697 static int edma_tptc_probe(struct platform_device *pdev)
2698 {
2699 pm_runtime_enable(&pdev->dev);
2700 return pm_runtime_get_sync(&pdev->dev);
2701 }
2702
2703 static struct platform_driver edma_tptc_driver = {
2704 .probe = edma_tptc_probe,
2705 .driver = {
2706 .name = "edma3-tptc",
2707 .of_match_table = edma_tptc_of_ids,
2708 },
2709 };
2710
2711 static bool edma_filter_fn(struct dma_chan *chan, void *param)
2712 {
2713 bool match = false;
2714
2715 if (chan->device->dev->driver == &edma_driver.driver) {
2716 struct edma_chan *echan = to_edma_chan(chan);
2717 unsigned ch_req = *(unsigned *)param;
2718 if (ch_req == echan->ch_num) {
2719 /* The channel is going to be used as HW synchronized */
2720 echan->hw_triggered = true;
2721 match = true;
2722 }
2723 }
2724 return match;
2725 }
2726
2727 static int edma_init(void)
2728 {
2729 int ret;
2730
2731 ret = platform_driver_register(&edma_tptc_driver);
2732 if (ret)
2733 return ret;
2734
2735 return platform_driver_register(&edma_driver);
2736 }
2737 subsys_initcall(edma_init);
2738
2739 static void __exit edma_exit(void)
2740 {
2741 platform_driver_unregister(&edma_driver);
2742 platform_driver_unregister(&edma_tptc_driver);
2743 }
2744 module_exit(edma_exit);
2745
2746 MODULE_AUTHOR("Matt Porter <matt.porter@linaro.org>");
2747 MODULE_DESCRIPTION("TI EDMA DMA engine driver");
2748 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support