1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * amd8111_edac.h, EDAC defs for AMD8111 hypertransport chip
5 * Copyright (c) 2008 Wind River Systems, Inc.
7 * Authors: Cao Qingtao <qingtao.cao@windriver.com>
8 * Benjamin Walsh <benjamin.walsh@windriver.com>
9 * Hu Yongqi <yongqi.hu@windriver.com>
12 #ifndef _AMD8111_EDAC_H_
13 #define _AMD8111_EDAC_H_
15 /************************************************************
16 * PCI Bridge Status and Command Register, DevA:0x04
17 ************************************************************/
18 #define REG_PCI_STSCMD 0x04
19 enum pci_stscmd_bits
{
20 PCI_STSCMD_SSE
= BIT(30),
21 PCI_STSCMD_RMA
= BIT(29),
22 PCI_STSCMD_RTA
= BIT(28),
23 PCI_STSCMD_SERREN
= BIT(8),
24 PCI_STSCMD_CLEAR_MASK
= (PCI_STSCMD_SSE
|
29 /************************************************************
30 * PCI Bridge Memory Base-Limit Register, DevA:0x1c
31 ************************************************************/
32 #define REG_MEM_LIM 0x1c
34 MEM_LIMIT_DPE
= BIT(31),
35 MEM_LIMIT_RSE
= BIT(30),
36 MEM_LIMIT_RMA
= BIT(29),
37 MEM_LIMIT_RTA
= BIT(28),
38 MEM_LIMIT_STA
= BIT(27),
39 MEM_LIMIT_MDPE
= BIT(24),
40 MEM_LIMIT_CLEAR_MASK
= (MEM_LIMIT_DPE
|
48 /************************************************************
49 * HyperTransport Link Control Register, DevA:0xc4
50 ************************************************************/
51 #define REG_HT_LINK 0xc4
53 HT_LINK_LKFAIL
= BIT(4),
54 HT_LINK_CRCFEN
= BIT(1),
55 HT_LINK_CLEAR_MASK
= (HT_LINK_LKFAIL
)
58 /************************************************************
59 * PCI Bridge Interrupt and Bridge Control, DevA:0x3c
60 ************************************************************/
61 #define REG_PCI_INTBRG_CTRL 0x3c
62 enum pci_intbrg_ctrl_bits
{
63 PCI_INTBRG_CTRL_DTSERREN
= BIT(27),
64 PCI_INTBRG_CTRL_DTSTAT
= BIT(26),
65 PCI_INTBRG_CTRL_MARSP
= BIT(21),
66 PCI_INTBRG_CTRL_SERREN
= BIT(17),
67 PCI_INTBRG_CTRL_PEREN
= BIT(16),
68 PCI_INTBRG_CTRL_CLEAR_MASK
= (PCI_INTBRG_CTRL_DTSTAT
),
69 PCI_INTBRG_CTRL_POLL_MASK
= (PCI_INTBRG_CTRL_DTSERREN
|
70 PCI_INTBRG_CTRL_MARSP
|
71 PCI_INTBRG_CTRL_SERREN
)
74 /************************************************************
75 * I/O Control 1 Register, DevB:0x40
76 ************************************************************/
77 #define REG_IO_CTRL_1 0x40
79 IO_CTRL_1_NMIONERR
= BIT(7),
80 IO_CTRL_1_LPC_ERR
= BIT(6),
81 IO_CTRL_1_PW2LPC
= BIT(1),
82 IO_CTRL_1_CLEAR_MASK
= (IO_CTRL_1_LPC_ERR
| IO_CTRL_1_PW2LPC
)
85 /************************************************************
86 * Legacy I/O Space Registers
87 ************************************************************/
88 #define REG_AT_COMPAT 0x61
90 AT_COMPAT_SERR
= BIT(7),
91 AT_COMPAT_IOCHK
= BIT(6),
92 AT_COMPAT_CLRIOCHK
= BIT(3),
93 AT_COMPAT_CLRSERR
= BIT(2),
96 struct amd8111_dev_info
{
97 u16 err_dev
; /* PCI Device ID */
99 int edac_idx
; /* device index */
101 struct edac_device_ctl_info
*edac_dev
;
102 void (*init
)(struct amd8111_dev_info
*dev_info
);
103 void (*exit
)(struct amd8111_dev_info
*dev_info
);
104 void (*check
)(struct edac_device_ctl_info
*edac_dev
);
107 struct amd8111_pci_info
{
108 u16 err_dev
; /* PCI Device ID */
110 int edac_idx
; /* pci index */
111 const char *ctl_name
;
112 struct edac_pci_ctl_info
*edac_dev
;
113 void (*init
)(struct amd8111_pci_info
*dev_info
);
114 void (*exit
)(struct amd8111_pci_info
*dev_info
);
115 void (*check
)(struct edac_pci_ctl_info
*edac_dev
);
118 #endif /* _AMD8111_EDAC_H_ */