drivers/gpio/gpio-altera.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright (C) 2013 Altera Corporation
   4  * Based on gpio-mpc8xxx.c
   5  */
   6
   7 #include <linux/io.h>
   8 #include <linux/module.h>
   9 #include <linux/gpio/driver.h>
  10 #include <linux/of_gpio.h> /* For of_mm_gpio_chip */
  11 #include <linux/platform_device.h>
  12
  13 #define ALTERA_GPIO_MAX_NGPIO           32
  14 #define ALTERA_GPIO_DATA                0x0
  15 #define ALTERA_GPIO_DIR                 0x4
  16 #define ALTERA_GPIO_IRQ_MASK            0x8
  17 #define ALTERA_GPIO_EDGE_CAP            0xc
  18
  19 /**
  20 * struct altera_gpio_chip
  21 * @mmchip               : memory mapped chip structure.
  22 * @gpio_lock            : synchronization lock so that new irq/set/get requests
  23 *                         will be blocked until the current one completes.
  24 * @interrupt_trigger    : specifies the hardware configured IRQ trigger type
  25 *                         (rising, falling, both, high)
  26 * @mapped_irq           : kernel mapped irq number.
  27 * @irq_chip             : IRQ chip configuration
  28 */
  29 struct altera_gpio_chip {
  30         struct of_mm_gpio_chip mmchip;
  31         raw_spinlock_t gpio_lock;
  32         int interrupt_trigger;
  33         int mapped_irq;
  34         struct irq_chip irq_chip;
  35 };
  36
  37 static void altera_gpio_irq_unmask(struct irq_data *d)
  38 {
  39         struct altera_gpio_chip *altera_gc;
  40         struct of_mm_gpio_chip *mm_gc;
  41         unsigned long flags;
  42         u32 intmask;
  43
  44         altera_gc = gpiochip_get_data(irq_data_get_irq_chip_data(d));
  45         mm_gc = &altera_gc->mmchip;
  46
  47         raw_spin_lock_irqsave(&altera_gc->gpio_lock, flags);
  48         intmask = readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
  49         /* Set ALTERA_GPIO_IRQ_MASK bit to unmask */
  50         intmask |= BIT(irqd_to_hwirq(d));
  51         writel(intmask, mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
  52         raw_spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
  53 }
  54
  55 static void altera_gpio_irq_mask(struct irq_data *d)
  56 {
  57         struct altera_gpio_chip *altera_gc;
  58         struct of_mm_gpio_chip *mm_gc;
  59         unsigned long flags;
  60         u32 intmask;
  61
  62         altera_gc = gpiochip_get_data(irq_data_get_irq_chip_data(d));
  63         mm_gc = &altera_gc->mmchip;
  64
  65         raw_spin_lock_irqsave(&altera_gc->gpio_lock, flags);
  66         intmask = readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
  67         /* Clear ALTERA_GPIO_IRQ_MASK bit to mask */
  68         intmask &= ~BIT(irqd_to_hwirq(d));
  69         writel(intmask, mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
  70         raw_spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
  71 }
  72
  73 /*
  74  * This controller's IRQ type is synthesized in hardware, so this function
  75  * just checks if the requested set_type matches the synthesized IRQ type
  76  */
  77 static int altera_gpio_irq_set_type(struct irq_data *d,
  78                                    unsigned int type)
  79 {
  80         struct altera_gpio_chip *altera_gc;
  81
  82         altera_gc = gpiochip_get_data(irq_data_get_irq_chip_data(d));
  83
  84         if (type == IRQ_TYPE_NONE) {
  85                 irq_set_handler_locked(d, handle_bad_irq);
  86                 return 0;
  87         }
  88         if (type == altera_gc->interrupt_trigger) {
  89                 if (type == IRQ_TYPE_LEVEL_HIGH)
  90                         irq_set_handler_locked(d, handle_level_irq);
  91                 else
  92                         irq_set_handler_locked(d, handle_simple_irq);
  93                 return 0;
  94         }
  95         irq_set_handler_locked(d, handle_bad_irq);
  96         return -EINVAL;
  97 }
  98
  99 static unsigned int altera_gpio_irq_startup(struct irq_data *d)
 100 {
 101         altera_gpio_irq_unmask(d);
 102
 103         return 0;
 104 }
 105
 106 static int altera_gpio_get(struct gpio_chip *gc, unsigned offset)
 107 {
 108         struct of_mm_gpio_chip *mm_gc;
 109
 110         mm_gc = to_of_mm_gpio_chip(gc);
 111
 112         return !!(readl(mm_gc->regs + ALTERA_GPIO_DATA) & BIT(offset));
 113 }
 114
 115 static void altera_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
 116 {
 117         struct of_mm_gpio_chip *mm_gc;
 118         struct altera_gpio_chip *chip;
 119         unsigned long flags;
 120         unsigned int data_reg;
 121
 122         mm_gc = to_of_mm_gpio_chip(gc);
 123         chip = gpiochip_get_data(gc);
 124
 125         raw_spin_lock_irqsave(&chip->gpio_lock, flags);
 126         data_reg = readl(mm_gc->regs + ALTERA_GPIO_DATA);
 127         if (value)
 128                 data_reg |= BIT(offset);
 129         else
 130                 data_reg &= ~BIT(offset);
 131         writel(data_reg, mm_gc->regs + ALTERA_GPIO_DATA);
 132         raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);
 133 }
 134
 135 static int altera_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
 136 {
 137         struct of_mm_gpio_chip *mm_gc;
 138         struct altera_gpio_chip *chip;
 139         unsigned long flags;
 140         unsigned int gpio_ddr;
 141
 142         mm_gc = to_of_mm_gpio_chip(gc);
 143         chip = gpiochip_get_data(gc);
 144
 145         raw_spin_lock_irqsave(&chip->gpio_lock, flags);
 146         /* Set pin as input, assumes software controlled IP */
 147         gpio_ddr = readl(mm_gc->regs + ALTERA_GPIO_DIR);
 148         gpio_ddr &= ~BIT(offset);
 149         writel(gpio_ddr, mm_gc->regs + ALTERA_GPIO_DIR);
 150         raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);
 151
 152         return 0;
 153 }
 154
 155 static int altera_gpio_direction_output(struct gpio_chip *gc,
 156                 unsigned offset, int value)
 157 {
 158         struct of_mm_gpio_chip *mm_gc;
 159         struct altera_gpio_chip *chip;
 160         unsigned long flags;
 161         unsigned int data_reg, gpio_ddr;
 162
 163         mm_gc = to_of_mm_gpio_chip(gc);
 164         chip = gpiochip_get_data(gc);
 165
 166         raw_spin_lock_irqsave(&chip->gpio_lock, flags);
 167         /* Sets the GPIO value */
 168         data_reg = readl(mm_gc->regs + ALTERA_GPIO_DATA);
 169         if (value)
 170                 data_reg |= BIT(offset);
 171         else
 172                 data_reg &= ~BIT(offset);
 173         writel(data_reg, mm_gc->regs + ALTERA_GPIO_DATA);
 174
 175         /* Set pin as output, assumes software controlled IP */
 176         gpio_ddr = readl(mm_gc->regs + ALTERA_GPIO_DIR);
 177         gpio_ddr |= BIT(offset);
 178         writel(gpio_ddr, mm_gc->regs + ALTERA_GPIO_DIR);
 179         raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);
 180
 181         return 0;
 182 }
 183
 184 static void altera_gpio_irq_edge_handler(struct irq_desc *desc)
 185 {
 186         struct altera_gpio_chip *altera_gc;
 187         struct irq_chip *chip;
 188         struct of_mm_gpio_chip *mm_gc;
 189         struct irq_domain *irqdomain;
 190         unsigned long status;
 191         int i;
 192
 193         altera_gc = gpiochip_get_data(irq_desc_get_handler_data(desc));
 194         chip = irq_desc_get_chip(desc);
 195         mm_gc = &altera_gc->mmchip;
 196         irqdomain = altera_gc->mmchip.gc.irq.domain;
 197
 198         chained_irq_enter(chip, desc);
 199
 200         while ((status =
 201               (readl(mm_gc->regs + ALTERA_GPIO_EDGE_CAP) &
 202               readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK)))) {
 203                 writel(status, mm_gc->regs + ALTERA_GPIO_EDGE_CAP);
 204                 for_each_set_bit(i, &status, mm_gc->gc.ngpio) {
 205                         generic_handle_irq(irq_find_mapping(irqdomain, i));
 206                 }
 207         }
 208
 209         chained_irq_exit(chip, desc);
 210 }
 211
 212 static void altera_gpio_irq_leveL_high_handler(struct irq_desc *desc)
 213 {
 214         struct altera_gpio_chip *altera_gc;
 215         struct irq_chip *chip;
 216         struct of_mm_gpio_chip *mm_gc;
 217         struct irq_domain *irqdomain;
 218         unsigned long status;
 219         int i;
 220
 221         altera_gc = gpiochip_get_data(irq_desc_get_handler_data(desc));
 222         chip = irq_desc_get_chip(desc);
 223         mm_gc = &altera_gc->mmchip;
 224         irqdomain = altera_gc->mmchip.gc.irq.domain;
 225
 226         chained_irq_enter(chip, desc);
 227
 228         status = readl(mm_gc->regs + ALTERA_GPIO_DATA);
 229         status &= readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
 230
 231         for_each_set_bit(i, &status, mm_gc->gc.ngpio) {
 232                 generic_handle_irq(irq_find_mapping(irqdomain, i));
 233         }
 234         chained_irq_exit(chip, desc);
 235 }
 236
 237 static int altera_gpio_probe(struct platform_device *pdev)
 238 {
 239         struct device_node *node = pdev->dev.of_node;
 240         int reg, ret;
 241         struct altera_gpio_chip *altera_gc;
 242         struct gpio_irq_chip *girq;
 243
 244         altera_gc = devm_kzalloc(&pdev->dev, sizeof(*altera_gc), GFP_KERNEL);
 245         if (!altera_gc)
 246                 return -ENOMEM;
 247
 248         raw_spin_lock_init(&altera_gc->gpio_lock);
 249
 250         if (of_property_read_u32(node, "altr,ngpio", &reg))
 251                 /* By default assume maximum ngpio */
 252                 altera_gc->mmchip.gc.ngpio = ALTERA_GPIO_MAX_NGPIO;
 253         else
 254                 altera_gc->mmchip.gc.ngpio = reg;
 255
 256         if (altera_gc->mmchip.gc.ngpio > ALTERA_GPIO_MAX_NGPIO) {
 257                 dev_warn(&pdev->dev,
 258                         "ngpio is greater than %d, defaulting to %d\n",
 259                         ALTERA_GPIO_MAX_NGPIO, ALTERA_GPIO_MAX_NGPIO);
 260                 altera_gc->mmchip.gc.ngpio = ALTERA_GPIO_MAX_NGPIO;
 261         }
 262
 263         altera_gc->mmchip.gc.direction_input    = altera_gpio_direction_input;
 264         altera_gc->mmchip.gc.direction_output   = altera_gpio_direction_output;
 265         altera_gc->mmchip.gc.get                = altera_gpio_get;
 266         altera_gc->mmchip.gc.set                = altera_gpio_set;
 267         altera_gc->mmchip.gc.owner              = THIS_MODULE;
 268         altera_gc->mmchip.gc.parent             = &pdev->dev;
 269
 270         altera_gc->mapped_irq = platform_get_irq_optional(pdev, 0);
 271
 272         if (altera_gc->mapped_irq < 0)
 273                 goto skip_irq;
 274
 275         if (of_property_read_u32(node, "altr,interrupt-type", &reg)) {
 276                 dev_err(&pdev->dev,
 277                         "altr,interrupt-type value not set in device tree\n");
 278                 return -EINVAL;
 279         }
 280         altera_gc->interrupt_trigger = reg;
 281
 282         altera_gc->irq_chip.name = "altera-gpio";
 283         altera_gc->irq_chip.irq_mask     = altera_gpio_irq_mask;
 284         altera_gc->irq_chip.irq_unmask   = altera_gpio_irq_unmask;
 285         altera_gc->irq_chip.irq_set_type = altera_gpio_irq_set_type;
 286         altera_gc->irq_chip.irq_startup  = altera_gpio_irq_startup;
 287         altera_gc->irq_chip.irq_shutdown = altera_gpio_irq_mask;
 288
 289         girq = &altera_gc->mmchip.gc.irq;
 290         girq->chip = &altera_gc->irq_chip;
 291         if (altera_gc->interrupt_trigger == IRQ_TYPE_LEVEL_HIGH)
 292                 girq->parent_handler = altera_gpio_irq_leveL_high_handler;
 293         else
 294                 girq->parent_handler = altera_gpio_irq_edge_handler;
 295         girq->num_parents = 1;
 296         girq->parents = devm_kcalloc(&pdev->dev, 1, sizeof(*girq->parents),
 297                                      GFP_KERNEL);
 298         if (!girq->parents)
 299                 return -ENOMEM;
 300         girq->default_type = IRQ_TYPE_NONE;
 301         girq->handler = handle_bad_irq;
 302         girq->parents[0] = altera_gc->mapped_irq;
 303
 304 skip_irq:
 305         ret = of_mm_gpiochip_add_data(node, &altera_gc->mmchip, altera_gc);
 306         if (ret) {
 307                 dev_err(&pdev->dev, "Failed adding memory mapped gpiochip\n");
 308                 return ret;
 309         }
 310
 311         platform_set_drvdata(pdev, altera_gc);
 312
 313         return 0;
 314 }
 315
 316 static int altera_gpio_remove(struct platform_device *pdev)
 317 {
 318         struct altera_gpio_chip *altera_gc = platform_get_drvdata(pdev);
 319
 320         of_mm_gpiochip_remove(&altera_gc->mmchip);
 321
 322         return 0;
 323 }
 324
 325 static const struct of_device_id altera_gpio_of_match[] = {
 326         { .compatible = "altr,pio-1.0", },
 327         {},
 328 };
 329 MODULE_DEVICE_TABLE(of, altera_gpio_of_match);
 330
 331 static struct platform_driver altera_gpio_driver = {
 332         .driver = {
 333                 .name   = "altera_gpio",
 334                 .of_match_table = of_match_ptr(altera_gpio_of_match),
 335         },
 336         .probe          = altera_gpio_probe,
 337         .remove         = altera_gpio_remove,
 338 };
 339
 340 static int __init altera_gpio_init(void)
 341 {
 342         return platform_driver_register(&altera_gpio_driver);
 343 }
 344 subsys_initcall(altera_gpio_init);
 345
 346 static void __exit altera_gpio_exit(void)
 347 {
 348         platform_driver_unregister(&altera_gpio_driver);
 349 }
 350 module_exit(altera_gpio_exit);
 351
 352 MODULE_AUTHOR("Tien Hock Loh <thloh@altera.com>");
 353 MODULE_DESCRIPTION("Altera GPIO driver");
 354 MODULE_LICENSE("GPL");