drivers/gpio/gpio-merrifield.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Intel Merrifield SoC GPIO driver
   4  *
   5  * Copyright (c) 2016 Intel Corporation.
   6  * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
   7  */
   8
   9 #include <linux/acpi.h>
  10 #include <linux/bitops.h>
  11 #include <linux/gpio/driver.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/io.h>
  14 #include <linux/module.h>
  15 #include <linux/pci.h>
  16 #include <linux/pinctrl/consumer.h>
  17
  18 #define GCCR            0x000   /* controller configuration */
  19 #define GPLR            0x004   /* pin level r/o */
  20 #define GPDR            0x01c   /* pin direction */
  21 #define GPSR            0x034   /* pin set w/o */
  22 #define GPCR            0x04c   /* pin clear w/o */
  23 #define GRER            0x064   /* rising edge detect */
  24 #define GFER            0x07c   /* falling edge detect */
  25 #define GFBR            0x094   /* glitch filter bypass */
  26 #define GIMR            0x0ac   /* interrupt mask */
  27 #define GISR            0x0c4   /* interrupt source */
  28 #define GITR            0x300   /* input type */
  29 #define GLPR            0x318   /* level input polarity */
  30 #define GWMR            0x400   /* wake mask */
  31 #define GWSR            0x418   /* wake source */
  32 #define GSIR            0xc00   /* secure input */
  33
  34 /* Intel Merrifield has 192 GPIO pins */
  35 #define MRFLD_NGPIO     192
  36
  37 struct mrfld_gpio_pinrange {
  38         unsigned int gpio_base;
  39         unsigned int pin_base;
  40         unsigned int npins;
  41 };
  42
  43 #define GPIO_PINRANGE(gstart, gend, pstart)             \
  44         {                                               \
  45                 .gpio_base = (gstart),                  \
  46                 .pin_base = (pstart),                   \
  47                 .npins = (gend) - (gstart) + 1,         \
  48         }
  49
  50 struct mrfld_gpio {
  51         struct gpio_chip        chip;
  52         void __iomem            *reg_base;
  53         raw_spinlock_t          lock;
  54         struct device           *dev;
  55 };
  56
  57 static const struct mrfld_gpio_pinrange mrfld_gpio_ranges[] = {
  58         GPIO_PINRANGE(0, 11, 146),
  59         GPIO_PINRANGE(12, 13, 144),
  60         GPIO_PINRANGE(14, 15, 35),
  61         GPIO_PINRANGE(16, 16, 164),
  62         GPIO_PINRANGE(17, 18, 105),
  63         GPIO_PINRANGE(19, 22, 101),
  64         GPIO_PINRANGE(23, 30, 107),
  65         GPIO_PINRANGE(32, 43, 67),
  66         GPIO_PINRANGE(44, 63, 195),
  67         GPIO_PINRANGE(64, 67, 140),
  68         GPIO_PINRANGE(68, 69, 165),
  69         GPIO_PINRANGE(70, 71, 65),
  70         GPIO_PINRANGE(72, 76, 228),
  71         GPIO_PINRANGE(77, 86, 37),
  72         GPIO_PINRANGE(87, 87, 48),
  73         GPIO_PINRANGE(88, 88, 47),
  74         GPIO_PINRANGE(89, 96, 49),
  75         GPIO_PINRANGE(97, 97, 34),
  76         GPIO_PINRANGE(102, 119, 83),
  77         GPIO_PINRANGE(120, 123, 79),
  78         GPIO_PINRANGE(124, 135, 115),
  79         GPIO_PINRANGE(137, 142, 158),
  80         GPIO_PINRANGE(154, 163, 24),
  81         GPIO_PINRANGE(164, 176, 215),
  82         GPIO_PINRANGE(177, 189, 127),
  83         GPIO_PINRANGE(190, 191, 178),
  84 };
  85
  86 static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned int offset,
  87                               unsigned int reg_type_offset)
  88 {
  89         struct mrfld_gpio *priv = gpiochip_get_data(chip);
  90         u8 reg = offset / 32;
  91
  92         return priv->reg_base + reg_type_offset + reg * 4;
  93 }
  94
  95 static int mrfld_gpio_get(struct gpio_chip *chip, unsigned int offset)
  96 {
  97         void __iomem *gplr = gpio_reg(chip, offset, GPLR);
  98
  99         return !!(readl(gplr) & BIT(offset % 32));
 100 }
 101
 102 static void mrfld_gpio_set(struct gpio_chip *chip, unsigned int offset,
 103                            int value)
 104 {
 105         struct mrfld_gpio *priv = gpiochip_get_data(chip);
 106         void __iomem *gpsr, *gpcr;
 107         unsigned long flags;
 108
 109         raw_spin_lock_irqsave(&priv->lock, flags);
 110
 111         if (value) {
 112                 gpsr = gpio_reg(chip, offset, GPSR);
 113                 writel(BIT(offset % 32), gpsr);
 114         } else {
 115                 gpcr = gpio_reg(chip, offset, GPCR);
 116                 writel(BIT(offset % 32), gpcr);
 117         }
 118
 119         raw_spin_unlock_irqrestore(&priv->lock, flags);
 120 }
 121
 122 static int mrfld_gpio_direction_input(struct gpio_chip *chip,
 123                                       unsigned int offset)
 124 {
 125         struct mrfld_gpio *priv = gpiochip_get_data(chip);
 126         void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
 127         unsigned long flags;
 128         u32 value;
 129
 130         raw_spin_lock_irqsave(&priv->lock, flags);
 131
 132         value = readl(gpdr);
 133         value &= ~BIT(offset % 32);
 134         writel(value, gpdr);
 135
 136         raw_spin_unlock_irqrestore(&priv->lock, flags);
 137
 138         return 0;
 139 }
 140
 141 static int mrfld_gpio_direction_output(struct gpio_chip *chip,
 142                                        unsigned int offset, int value)
 143 {
 144         struct mrfld_gpio *priv = gpiochip_get_data(chip);
 145         void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
 146         unsigned long flags;
 147
 148         mrfld_gpio_set(chip, offset, value);
 149
 150         raw_spin_lock_irqsave(&priv->lock, flags);
 151
 152         value = readl(gpdr);
 153         value |= BIT(offset % 32);
 154         writel(value, gpdr);
 155
 156         raw_spin_unlock_irqrestore(&priv->lock, flags);
 157
 158         return 0;
 159 }
 160
 161 static int mrfld_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
 162 {
 163         void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
 164
 165         if (readl(gpdr) & BIT(offset % 32))
 166                 return GPIO_LINE_DIRECTION_OUT;
 167
 168         return GPIO_LINE_DIRECTION_IN;
 169 }
 170
 171 static int mrfld_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset,
 172                                    unsigned int debounce)
 173 {
 174         struct mrfld_gpio *priv = gpiochip_get_data(chip);
 175         void __iomem *gfbr = gpio_reg(chip, offset, GFBR);
 176         unsigned long flags;
 177         u32 value;
 178
 179         raw_spin_lock_irqsave(&priv->lock, flags);
 180
 181         if (debounce)
 182                 value = readl(gfbr) & ~BIT(offset % 32);
 183         else
 184                 value = readl(gfbr) | BIT(offset % 32);
 185         writel(value, gfbr);
 186
 187         raw_spin_unlock_irqrestore(&priv->lock, flags);
 188
 189         return 0;
 190 }
 191
 192 static int mrfld_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
 193                                  unsigned long config)
 194 {
 195         u32 debounce;
 196
 197         if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
 198                 return -ENOTSUPP;
 199
 200         debounce = pinconf_to_config_argument(config);
 201         return mrfld_gpio_set_debounce(chip, offset, debounce);
 202 }
 203
 204 static void mrfld_irq_ack(struct irq_data *d)
 205 {
 206         struct mrfld_gpio *priv = irq_data_get_irq_chip_data(d);
 207         u32 gpio = irqd_to_hwirq(d);
 208         void __iomem *gisr = gpio_reg(&priv->chip, gpio, GISR);
 209         unsigned long flags;
 210
 211         raw_spin_lock_irqsave(&priv->lock, flags);
 212
 213         writel(BIT(gpio % 32), gisr);
 214
 215         raw_spin_unlock_irqrestore(&priv->lock, flags);
 216 }
 217
 218 static void mrfld_irq_unmask_mask(struct irq_data *d, bool unmask)
 219 {
 220         struct mrfld_gpio *priv = irq_data_get_irq_chip_data(d);
 221         u32 gpio = irqd_to_hwirq(d);
 222         void __iomem *gimr = gpio_reg(&priv->chip, gpio, GIMR);
 223         unsigned long flags;
 224         u32 value;
 225
 226         raw_spin_lock_irqsave(&priv->lock, flags);
 227
 228         if (unmask)
 229                 value = readl(gimr) | BIT(gpio % 32);
 230         else
 231                 value = readl(gimr) & ~BIT(gpio % 32);
 232         writel(value, gimr);
 233
 234         raw_spin_unlock_irqrestore(&priv->lock, flags);
 235 }
 236
 237 static void mrfld_irq_mask(struct irq_data *d)
 238 {
 239         mrfld_irq_unmask_mask(d, false);
 240 }
 241
 242 static void mrfld_irq_unmask(struct irq_data *d)
 243 {
 244         mrfld_irq_unmask_mask(d, true);
 245 }
 246
 247 static int mrfld_irq_set_type(struct irq_data *d, unsigned int type)
 248 {
 249         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 250         struct mrfld_gpio *priv = gpiochip_get_data(gc);
 251         u32 gpio = irqd_to_hwirq(d);
 252         void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER);
 253         void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER);
 254         void __iomem *gitr = gpio_reg(&priv->chip, gpio, GITR);
 255         void __iomem *glpr = gpio_reg(&priv->chip, gpio, GLPR);
 256         unsigned long flags;
 257         u32 value;
 258
 259         raw_spin_lock_irqsave(&priv->lock, flags);
 260
 261         if (type & IRQ_TYPE_EDGE_RISING)
 262                 value = readl(grer) | BIT(gpio % 32);
 263         else
 264                 value = readl(grer) & ~BIT(gpio % 32);
 265         writel(value, grer);
 266
 267         if (type & IRQ_TYPE_EDGE_FALLING)
 268                 value = readl(gfer) | BIT(gpio % 32);
 269         else
 270                 value = readl(gfer) & ~BIT(gpio % 32);
 271         writel(value, gfer);
 272
 273         /*
 274          * To prevent glitches from triggering an unintended level interrupt,
 275          * configure GLPR register first and then configure GITR.
 276          */
 277         if (type & IRQ_TYPE_LEVEL_LOW)
 278                 value = readl(glpr) | BIT(gpio % 32);
 279         else
 280                 value = readl(glpr) & ~BIT(gpio % 32);
 281         writel(value, glpr);
 282
 283         if (type & IRQ_TYPE_LEVEL_MASK) {
 284                 value = readl(gitr) | BIT(gpio % 32);
 285                 writel(value, gitr);
 286
 287                 irq_set_handler_locked(d, handle_level_irq);
 288         } else if (type & IRQ_TYPE_EDGE_BOTH) {
 289                 value = readl(gitr) & ~BIT(gpio % 32);
 290                 writel(value, gitr);
 291
 292                 irq_set_handler_locked(d, handle_edge_irq);
 293         }
 294
 295         raw_spin_unlock_irqrestore(&priv->lock, flags);
 296
 297         return 0;
 298 }
 299
 300 static int mrfld_irq_set_wake(struct irq_data *d, unsigned int on)
 301 {
 302         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 303         struct mrfld_gpio *priv = gpiochip_get_data(gc);
 304         u32 gpio = irqd_to_hwirq(d);
 305         void __iomem *gwmr = gpio_reg(&priv->chip, gpio, GWMR);
 306         void __iomem *gwsr = gpio_reg(&priv->chip, gpio, GWSR);
 307         unsigned long flags;
 308         u32 value;
 309
 310         raw_spin_lock_irqsave(&priv->lock, flags);
 311
 312         /* Clear the existing wake status */
 313         writel(BIT(gpio % 32), gwsr);
 314
 315         if (on)
 316                 value = readl(gwmr) | BIT(gpio % 32);
 317         else
 318                 value = readl(gwmr) & ~BIT(gpio % 32);
 319         writel(value, gwmr);
 320
 321         raw_spin_unlock_irqrestore(&priv->lock, flags);
 322
 323         dev_dbg(priv->dev, "%sable wake for gpio %u\n", on ? "en" : "dis", gpio);
 324         return 0;
 325 }
 326
 327 static struct irq_chip mrfld_irqchip = {
 328         .name           = "gpio-merrifield",
 329         .irq_ack        = mrfld_irq_ack,
 330         .irq_mask       = mrfld_irq_mask,
 331         .irq_unmask     = mrfld_irq_unmask,
 332         .irq_set_type   = mrfld_irq_set_type,
 333         .irq_set_wake   = mrfld_irq_set_wake,
 334 };
 335
 336 static void mrfld_irq_handler(struct irq_desc *desc)
 337 {
 338         struct gpio_chip *gc = irq_desc_get_handler_data(desc);
 339         struct mrfld_gpio *priv = gpiochip_get_data(gc);
 340         struct irq_chip *irqchip = irq_desc_get_chip(desc);
 341         unsigned long base, gpio;
 342
 343         chained_irq_enter(irqchip, desc);
 344
 345         /* Check GPIO controller to check which pin triggered the interrupt */
 346         for (base = 0; base < priv->chip.ngpio; base += 32) {
 347                 void __iomem *gisr = gpio_reg(&priv->chip, base, GISR);
 348                 void __iomem *gimr = gpio_reg(&priv->chip, base, GIMR);
 349                 unsigned long pending, enabled;
 350
 351                 pending = readl(gisr);
 352                 enabled = readl(gimr);
 353
 354                 /* Only interrupts that are enabled */
 355                 pending &= enabled;
 356
 357                 for_each_set_bit(gpio, &pending, 32) {
 358                         unsigned int irq;
 359
 360                         irq = irq_find_mapping(gc->irq.domain, base + gpio);
 361                         generic_handle_irq(irq);
 362                 }
 363         }
 364
 365         chained_irq_exit(irqchip, desc);
 366 }
 367
 368 static int mrfld_irq_init_hw(struct gpio_chip *chip)
 369 {
 370         struct mrfld_gpio *priv = gpiochip_get_data(chip);
 371         void __iomem *reg;
 372         unsigned int base;
 373
 374         for (base = 0; base < priv->chip.ngpio; base += 32) {
 375                 /* Clear the rising-edge detect register */
 376                 reg = gpio_reg(&priv->chip, base, GRER);
 377                 writel(0, reg);
 378                 /* Clear the falling-edge detect register */
 379                 reg = gpio_reg(&priv->chip, base, GFER);
 380                 writel(0, reg);
 381         }
 382
 383         return 0;
 384 }
 385
 386 static const char *mrfld_gpio_get_pinctrl_dev_name(struct mrfld_gpio *priv)
 387 {
 388         struct acpi_device *adev;
 389         const char *name;
 390
 391         adev = acpi_dev_get_first_match_dev("INTC1002", NULL, -1);
 392         if (adev) {
 393                 name = devm_kstrdup(priv->dev, acpi_dev_name(adev), GFP_KERNEL);
 394                 acpi_dev_put(adev);
 395         } else {
 396                 name = "pinctrl-merrifield";
 397         }
 398
 399         return name;
 400 }
 401
 402 static int mrfld_gpio_add_pin_ranges(struct gpio_chip *chip)
 403 {
 404         struct mrfld_gpio *priv = gpiochip_get_data(chip);
 405         const struct mrfld_gpio_pinrange *range;
 406         const char *pinctrl_dev_name;
 407         unsigned int i;
 408         int retval;
 409
 410         pinctrl_dev_name = mrfld_gpio_get_pinctrl_dev_name(priv);
 411         for (i = 0; i < ARRAY_SIZE(mrfld_gpio_ranges); i++) {
 412                 range = &mrfld_gpio_ranges[i];
 413                 retval = gpiochip_add_pin_range(&priv->chip, pinctrl_dev_name,
 414                                                 range->gpio_base,
 415                                                 range->pin_base,
 416                                                 range->npins);
 417                 if (retval) {
 418                         dev_err(priv->dev, "failed to add GPIO pin range\n");
 419                         return retval;
 420                 }
 421         }
 422
 423         return 0;
 424 }
 425
 426 static int mrfld_gpio_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 427 {
 428         struct gpio_irq_chip *girq;
 429         struct mrfld_gpio *priv;
 430         u32 gpio_base, irq_base;
 431         void __iomem *base;
 432         int retval;
 433
 434         retval = pcim_enable_device(pdev);
 435         if (retval)
 436                 return retval;
 437
 438         retval = pcim_iomap_regions(pdev, BIT(1) | BIT(0), pci_name(pdev));
 439         if (retval) {
 440                 dev_err(&pdev->dev, "I/O memory mapping error\n");
 441                 return retval;
 442         }
 443
 444         base = pcim_iomap_table(pdev)[1];
 445
 446         irq_base = readl(base + 0 * sizeof(u32));
 447         gpio_base = readl(base + 1 * sizeof(u32));
 448
 449         /* Release the IO mapping, since we already get the info from BAR1 */
 450         pcim_iounmap_regions(pdev, BIT(1));
 451
 452         priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
 453         if (!priv)
 454                 return -ENOMEM;
 455
 456         priv->dev = &pdev->dev;
 457         priv->reg_base = pcim_iomap_table(pdev)[0];
 458
 459         priv->chip.label = dev_name(&pdev->dev);
 460         priv->chip.parent = &pdev->dev;
 461         priv->chip.request = gpiochip_generic_request;
 462         priv->chip.free = gpiochip_generic_free;
 463         priv->chip.direction_input = mrfld_gpio_direction_input;
 464         priv->chip.direction_output = mrfld_gpio_direction_output;
 465         priv->chip.get = mrfld_gpio_get;
 466         priv->chip.set = mrfld_gpio_set;
 467         priv->chip.get_direction = mrfld_gpio_get_direction;
 468         priv->chip.set_config = mrfld_gpio_set_config;
 469         priv->chip.base = gpio_base;
 470         priv->chip.ngpio = MRFLD_NGPIO;
 471         priv->chip.can_sleep = false;
 472         priv->chip.add_pin_ranges = mrfld_gpio_add_pin_ranges;
 473
 474         raw_spin_lock_init(&priv->lock);
 475
 476         retval = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
 477         if (retval < 0)
 478                 return retval;
 479
 480         girq = &priv->chip.irq;
 481         girq->chip = &mrfld_irqchip;
 482         girq->init_hw = mrfld_irq_init_hw;
 483         girq->parent_handler = mrfld_irq_handler;
 484         girq->num_parents = 1;
 485         girq->parents = devm_kcalloc(&pdev->dev, girq->num_parents,
 486                                      sizeof(*girq->parents), GFP_KERNEL);
 487         if (!girq->parents)
 488                 return -ENOMEM;
 489         girq->parents[0] = pci_irq_vector(pdev, 0);
 490         girq->first = irq_base;
 491         girq->default_type = IRQ_TYPE_NONE;
 492         girq->handler = handle_bad_irq;
 493
 494         retval = devm_gpiochip_add_data(&pdev->dev, &priv->chip, priv);
 495         if (retval) {
 496                 dev_err(&pdev->dev, "gpiochip_add error %d\n", retval);
 497                 return retval;
 498         }
 499
 500         pci_set_drvdata(pdev, priv);
 501         return 0;
 502 }
 503
 504 static const struct pci_device_id mrfld_gpio_ids[] = {
 505         { PCI_VDEVICE(INTEL, 0x1199) },
 506         { }
 507 };
 508 MODULE_DEVICE_TABLE(pci, mrfld_gpio_ids);
 509
 510 static struct pci_driver mrfld_gpio_driver = {
 511         .name           = "gpio-merrifield",
 512         .id_table       = mrfld_gpio_ids,
 513         .probe          = mrfld_gpio_probe,
 514 };
 515
 516 module_pci_driver(mrfld_gpio_driver);
 517
 518 MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
 519 MODULE_DESCRIPTION("Intel Merrifield SoC GPIO driver");
 520 MODULE_LICENSE("GPL v2");