1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
5 #include <linux/module.h>
6 #include <linux/kernel.h>
7 #include <linux/slab.h>
9 #include <linux/gpio/driver.h>
10 #include <linux/interrupt.h>
11 #include <linux/irq.h>
13 #define IOH_EDGE_FALLING 0
14 #define IOH_EDGE_RISING BIT(0)
15 #define IOH_LEVEL_L BIT(1)
16 #define IOH_LEVEL_H (BIT(0) | BIT(1))
17 #define IOH_EDGE_BOTH BIT(2)
18 #define IOH_IM_MASK (BIT(0) | BIT(1) | BIT(2))
20 #define IOH_IRQ_BASE 0
38 struct ioh_reg_comn regs
[8];
46 * struct ioh_gpio_reg_data - The register store data.
47 * @ien_reg: To store contents of interrupt enable register.
48 * @imask_reg: To store contents of interrupt mask regist
49 * @po_reg: To store contents of PO register.
50 * @pm_reg: To store contents of PM register.
51 * @im0_reg: To store contents of interrupt mode regist0
52 * @im1_reg: To store contents of interrupt mode regist1
53 * @use_sel_reg: To store contents of GPIO_USE_SEL0~3
55 struct ioh_gpio_reg_data
{
66 * struct ioh_gpio - GPIO private data structure.
67 * @base: PCI base address of Memory mapped I/O register.
68 * @reg: Memory mapped IOH GPIO register list.
69 * @dev: Pointer to device structure.
70 * @gpio: Data for GPIO infrastructure.
71 * @ioh_gpio_reg: Memory mapped Register data is saved here
73 * @gpio_use_sel: Save GPIO_USE_SEL1~4 register for PM
74 * @ch: Indicate GPIO channel
75 * @irq_base: Save base of IRQ number for interrupt
76 * @spinlock: Used for register access protection
80 struct ioh_regs __iomem
*reg
;
82 struct gpio_chip gpio
;
83 struct ioh_gpio_reg_data ioh_gpio_reg
;
90 static const int num_ports
[] = {6, 12, 16, 16, 15, 16, 16, 12};
92 static void ioh_gpio_set(struct gpio_chip
*gpio
, unsigned nr
, int val
)
95 struct ioh_gpio
*chip
= gpiochip_get_data(gpio
);
98 spin_lock_irqsave(&chip
->spinlock
, flags
);
99 reg_val
= ioread32(&chip
->reg
->regs
[chip
->ch
].po
);
101 reg_val
|= (1 << nr
);
103 reg_val
&= ~(1 << nr
);
105 iowrite32(reg_val
, &chip
->reg
->regs
[chip
->ch
].po
);
106 spin_unlock_irqrestore(&chip
->spinlock
, flags
);
109 static int ioh_gpio_get(struct gpio_chip
*gpio
, unsigned nr
)
111 struct ioh_gpio
*chip
= gpiochip_get_data(gpio
);
113 return !!(ioread32(&chip
->reg
->regs
[chip
->ch
].pi
) & (1 << nr
));
116 static int ioh_gpio_direction_output(struct gpio_chip
*gpio
, unsigned nr
,
119 struct ioh_gpio
*chip
= gpiochip_get_data(gpio
);
124 spin_lock_irqsave(&chip
->spinlock
, flags
);
125 pm
= ioread32(&chip
->reg
->regs
[chip
->ch
].pm
) &
126 ((1 << num_ports
[chip
->ch
]) - 1);
128 iowrite32(pm
, &chip
->reg
->regs
[chip
->ch
].pm
);
130 reg_val
= ioread32(&chip
->reg
->regs
[chip
->ch
].po
);
132 reg_val
|= (1 << nr
);
134 reg_val
&= ~(1 << nr
);
135 iowrite32(reg_val
, &chip
->reg
->regs
[chip
->ch
].po
);
137 spin_unlock_irqrestore(&chip
->spinlock
, flags
);
142 static int ioh_gpio_direction_input(struct gpio_chip
*gpio
, unsigned nr
)
144 struct ioh_gpio
*chip
= gpiochip_get_data(gpio
);
148 spin_lock_irqsave(&chip
->spinlock
, flags
);
149 pm
= ioread32(&chip
->reg
->regs
[chip
->ch
].pm
) &
150 ((1 << num_ports
[chip
->ch
]) - 1);
152 iowrite32(pm
, &chip
->reg
->regs
[chip
->ch
].pm
);
153 spin_unlock_irqrestore(&chip
->spinlock
, flags
);
160 * Save register configuration and disable interrupts.
162 static void ioh_gpio_save_reg_conf(struct ioh_gpio
*chip
)
166 for (i
= 0; i
< 8; i
++, chip
++) {
167 chip
->ioh_gpio_reg
.po_reg
=
168 ioread32(&chip
->reg
->regs
[chip
->ch
].po
);
169 chip
->ioh_gpio_reg
.pm_reg
=
170 ioread32(&chip
->reg
->regs
[chip
->ch
].pm
);
171 chip
->ioh_gpio_reg
.ien_reg
=
172 ioread32(&chip
->reg
->regs
[chip
->ch
].ien
);
173 chip
->ioh_gpio_reg
.imask_reg
=
174 ioread32(&chip
->reg
->regs
[chip
->ch
].imask
);
175 chip
->ioh_gpio_reg
.im0_reg
=
176 ioread32(&chip
->reg
->regs
[chip
->ch
].im_0
);
177 chip
->ioh_gpio_reg
.im1_reg
=
178 ioread32(&chip
->reg
->regs
[chip
->ch
].im_1
);
180 chip
->ioh_gpio_reg
.use_sel_reg
=
181 ioread32(&chip
->reg
->ioh_sel_reg
[i
]);
186 * This function restores the register configuration of the GPIO device.
188 static void ioh_gpio_restore_reg_conf(struct ioh_gpio
*chip
)
192 for (i
= 0; i
< 8; i
++, chip
++) {
193 iowrite32(chip
->ioh_gpio_reg
.po_reg
,
194 &chip
->reg
->regs
[chip
->ch
].po
);
195 iowrite32(chip
->ioh_gpio_reg
.pm_reg
,
196 &chip
->reg
->regs
[chip
->ch
].pm
);
197 iowrite32(chip
->ioh_gpio_reg
.ien_reg
,
198 &chip
->reg
->regs
[chip
->ch
].ien
);
199 iowrite32(chip
->ioh_gpio_reg
.imask_reg
,
200 &chip
->reg
->regs
[chip
->ch
].imask
);
201 iowrite32(chip
->ioh_gpio_reg
.im0_reg
,
202 &chip
->reg
->regs
[chip
->ch
].im_0
);
203 iowrite32(chip
->ioh_gpio_reg
.im1_reg
,
204 &chip
->reg
->regs
[chip
->ch
].im_1
);
206 iowrite32(chip
->ioh_gpio_reg
.use_sel_reg
,
207 &chip
->reg
->ioh_sel_reg
[i
]);
212 static int ioh_gpio_to_irq(struct gpio_chip
*gpio
, unsigned offset
)
214 struct ioh_gpio
*chip
= gpiochip_get_data(gpio
);
215 return chip
->irq_base
+ offset
;
218 static void ioh_gpio_setup(struct ioh_gpio
*chip
, int num_port
)
220 struct gpio_chip
*gpio
= &chip
->gpio
;
222 gpio
->label
= dev_name(chip
->dev
);
223 gpio
->owner
= THIS_MODULE
;
224 gpio
->direction_input
= ioh_gpio_direction_input
;
225 gpio
->get
= ioh_gpio_get
;
226 gpio
->direction_output
= ioh_gpio_direction_output
;
227 gpio
->set
= ioh_gpio_set
;
228 gpio
->dbg_show
= NULL
;
230 gpio
->ngpio
= num_port
;
231 gpio
->can_sleep
= false;
232 gpio
->to_irq
= ioh_gpio_to_irq
;
235 static int ioh_irq_type(struct irq_data
*d
, unsigned int type
)
238 void __iomem
*im_reg
;
245 struct irq_chip_generic
*gc
= irq_data_get_irq_chip_data(d
);
246 struct ioh_gpio
*chip
= gc
->private;
248 ch
= irq
- chip
->irq_base
;
249 if (irq
<= chip
->irq_base
+ 7) {
250 im_reg
= &chip
->reg
->regs
[chip
->ch
].im_0
;
253 im_reg
= &chip
->reg
->regs
[chip
->ch
].im_1
;
256 dev_dbg(chip
->dev
, "%s:irq=%d type=%d ch=%d pos=%d type=%d\n",
257 __func__
, irq
, type
, ch
, im_pos
, type
);
259 spin_lock_irqsave(&chip
->spinlock
, flags
);
262 case IRQ_TYPE_EDGE_RISING
:
263 val
= IOH_EDGE_RISING
;
265 case IRQ_TYPE_EDGE_FALLING
:
266 val
= IOH_EDGE_FALLING
;
268 case IRQ_TYPE_EDGE_BOTH
:
271 case IRQ_TYPE_LEVEL_HIGH
:
274 case IRQ_TYPE_LEVEL_LOW
:
280 dev_warn(chip
->dev
, "%s: unknown type(%dd)",
285 /* Set interrupt mode */
286 im
= ioread32(im_reg
) & ~(IOH_IM_MASK
<< (im_pos
* 4));
287 iowrite32(im
| (val
<< (im_pos
* 4)), im_reg
);
290 iowrite32(BIT(ch
), &chip
->reg
->regs
[chip
->ch
].iclr
);
293 iowrite32(BIT(ch
), &chip
->reg
->regs
[chip
->ch
].imaskclr
);
295 /* Enable interrupt */
296 ien
= ioread32(&chip
->reg
->regs
[chip
->ch
].ien
);
297 iowrite32(ien
| BIT(ch
), &chip
->reg
->regs
[chip
->ch
].ien
);
299 spin_unlock_irqrestore(&chip
->spinlock
, flags
);
304 static void ioh_irq_unmask(struct irq_data
*d
)
306 struct irq_chip_generic
*gc
= irq_data_get_irq_chip_data(d
);
307 struct ioh_gpio
*chip
= gc
->private;
309 iowrite32(1 << (d
->irq
- chip
->irq_base
),
310 &chip
->reg
->regs
[chip
->ch
].imaskclr
);
313 static void ioh_irq_mask(struct irq_data
*d
)
315 struct irq_chip_generic
*gc
= irq_data_get_irq_chip_data(d
);
316 struct ioh_gpio
*chip
= gc
->private;
318 iowrite32(1 << (d
->irq
- chip
->irq_base
),
319 &chip
->reg
->regs
[chip
->ch
].imask
);
322 static void ioh_irq_disable(struct irq_data
*d
)
324 struct irq_chip_generic
*gc
= irq_data_get_irq_chip_data(d
);
325 struct ioh_gpio
*chip
= gc
->private;
329 spin_lock_irqsave(&chip
->spinlock
, flags
);
330 ien
= ioread32(&chip
->reg
->regs
[chip
->ch
].ien
);
331 ien
&= ~(1 << (d
->irq
- chip
->irq_base
));
332 iowrite32(ien
, &chip
->reg
->regs
[chip
->ch
].ien
);
333 spin_unlock_irqrestore(&chip
->spinlock
, flags
);
336 static void ioh_irq_enable(struct irq_data
*d
)
338 struct irq_chip_generic
*gc
= irq_data_get_irq_chip_data(d
);
339 struct ioh_gpio
*chip
= gc
->private;
343 spin_lock_irqsave(&chip
->spinlock
, flags
);
344 ien
= ioread32(&chip
->reg
->regs
[chip
->ch
].ien
);
345 ien
|= 1 << (d
->irq
- chip
->irq_base
);
346 iowrite32(ien
, &chip
->reg
->regs
[chip
->ch
].ien
);
347 spin_unlock_irqrestore(&chip
->spinlock
, flags
);
350 static irqreturn_t
ioh_gpio_handler(int irq
, void *dev_id
)
352 struct ioh_gpio
*chip
= dev_id
;
357 for (i
= 0; i
< 8; i
++, chip
++) {
358 reg_val
= ioread32(&chip
->reg
->regs
[i
].istatus
);
359 for (j
= 0; j
< num_ports
[i
]; j
++) {
360 if (reg_val
& BIT(j
)) {
362 "%s:[%d]:irq=%d status=0x%x\n",
363 __func__
, j
, irq
, reg_val
);
365 &chip
->reg
->regs
[chip
->ch
].iclr
);
366 generic_handle_irq(chip
->irq_base
+ j
);
374 static int ioh_gpio_alloc_generic_chip(struct ioh_gpio
*chip
,
375 unsigned int irq_start
,
378 struct irq_chip_generic
*gc
;
379 struct irq_chip_type
*ct
;
382 gc
= devm_irq_alloc_generic_chip(chip
->dev
, "ioh_gpio", 1, irq_start
,
383 chip
->base
, handle_simple_irq
);
390 ct
->chip
.irq_mask
= ioh_irq_mask
;
391 ct
->chip
.irq_unmask
= ioh_irq_unmask
;
392 ct
->chip
.irq_set_type
= ioh_irq_type
;
393 ct
->chip
.irq_disable
= ioh_irq_disable
;
394 ct
->chip
.irq_enable
= ioh_irq_enable
;
396 rv
= devm_irq_setup_generic_chip(chip
->dev
, gc
, IRQ_MSK(num
),
397 IRQ_GC_INIT_MASK_CACHE
,
398 IRQ_NOREQUEST
| IRQ_NOPROBE
, 0);
403 static int ioh_gpio_probe(struct pci_dev
*pdev
,
404 const struct pci_device_id
*id
)
408 struct ioh_gpio
*chip
;
413 ret
= pci_enable_device(pdev
);
415 dev_err(&pdev
->dev
, "%s : pci_enable_device failed", __func__
);
419 ret
= pci_request_regions(pdev
, KBUILD_MODNAME
);
421 dev_err(&pdev
->dev
, "pci_request_regions failed-%d", ret
);
422 goto err_request_regions
;
425 base
= pci_iomap(pdev
, 1, 0);
427 dev_err(&pdev
->dev
, "%s : pci_iomap failed", __func__
);
432 chip_save
= kcalloc(8, sizeof(*chip
), GFP_KERNEL
);
433 if (chip_save
== NULL
) {
439 for (i
= 0; i
< 8; i
++, chip
++) {
440 chip
->dev
= &pdev
->dev
;
442 chip
->reg
= chip
->base
;
444 spin_lock_init(&chip
->spinlock
);
445 ioh_gpio_setup(chip
, num_ports
[i
]);
446 ret
= gpiochip_add_data(&chip
->gpio
, chip
);
448 dev_err(&pdev
->dev
, "IOH gpio: Failed to register GPIO\n");
449 goto err_gpiochip_add
;
454 for (j
= 0; j
< 8; j
++, chip
++) {
455 irq_base
= devm_irq_alloc_descs(&pdev
->dev
, -1, IOH_IRQ_BASE
,
456 num_ports
[j
], NUMA_NO_NODE
);
459 "ml_ioh_gpio: Failed to get IRQ base num\n");
461 goto err_gpiochip_add
;
463 chip
->irq_base
= irq_base
;
465 ret
= ioh_gpio_alloc_generic_chip(chip
,
466 irq_base
, num_ports
[j
]);
468 goto err_gpiochip_add
;
472 ret
= devm_request_irq(&pdev
->dev
, pdev
->irq
, ioh_gpio_handler
,
473 IRQF_SHARED
, KBUILD_MODNAME
, chip
);
476 "%s request_irq failed\n", __func__
);
477 goto err_gpiochip_add
;
480 pci_set_drvdata(pdev
, chip
);
487 gpiochip_remove(&chip
->gpio
);
493 pci_iounmap(pdev
, base
);
496 pci_release_regions(pdev
);
499 pci_disable_device(pdev
);
503 dev_err(&pdev
->dev
, "%s Failed returns %d\n", __func__
, ret
);
507 static void ioh_gpio_remove(struct pci_dev
*pdev
)
510 struct ioh_gpio
*chip
= pci_get_drvdata(pdev
);
515 for (i
= 0; i
< 8; i
++, chip
++)
516 gpiochip_remove(&chip
->gpio
);
519 pci_iounmap(pdev
, chip
->base
);
520 pci_release_regions(pdev
);
521 pci_disable_device(pdev
);
526 static int ioh_gpio_suspend(struct pci_dev
*pdev
, pm_message_t state
)
529 struct ioh_gpio
*chip
= pci_get_drvdata(pdev
);
532 spin_lock_irqsave(&chip
->spinlock
, flags
);
533 ioh_gpio_save_reg_conf(chip
);
534 spin_unlock_irqrestore(&chip
->spinlock
, flags
);
536 ret
= pci_save_state(pdev
);
538 dev_err(&pdev
->dev
, "pci_save_state Failed-%d\n", ret
);
541 pci_disable_device(pdev
);
542 pci_set_power_state(pdev
, PCI_D0
);
543 ret
= pci_enable_wake(pdev
, PCI_D0
, 1);
545 dev_err(&pdev
->dev
, "pci_enable_wake Failed -%d\n", ret
);
550 static int ioh_gpio_resume(struct pci_dev
*pdev
)
553 struct ioh_gpio
*chip
= pci_get_drvdata(pdev
);
556 ret
= pci_enable_wake(pdev
, PCI_D0
, 0);
558 pci_set_power_state(pdev
, PCI_D0
);
559 ret
= pci_enable_device(pdev
);
561 dev_err(&pdev
->dev
, "pci_enable_device Failed-%d ", ret
);
564 pci_restore_state(pdev
);
566 spin_lock_irqsave(&chip
->spinlock
, flags
);
567 iowrite32(0x01, &chip
->reg
->srst
);
568 iowrite32(0x00, &chip
->reg
->srst
);
569 ioh_gpio_restore_reg_conf(chip
);
570 spin_unlock_irqrestore(&chip
->spinlock
, flags
);
575 #define ioh_gpio_suspend NULL
576 #define ioh_gpio_resume NULL
579 static const struct pci_device_id ioh_gpio_pcidev_id
[] = {
580 { PCI_DEVICE(PCI_VENDOR_ID_ROHM
, 0x802E) },
583 MODULE_DEVICE_TABLE(pci
, ioh_gpio_pcidev_id
);
585 static struct pci_driver ioh_gpio_driver
= {
586 .name
= "ml_ioh_gpio",
587 .id_table
= ioh_gpio_pcidev_id
,
588 .probe
= ioh_gpio_probe
,
589 .remove
= ioh_gpio_remove
,
590 .suspend
= ioh_gpio_suspend
,
591 .resume
= ioh_gpio_resume
594 module_pci_driver(ioh_gpio_driver
);
596 MODULE_DESCRIPTION("OKI SEMICONDUCTOR ML-IOH series GPIO Driver");
597 MODULE_LICENSE("GPL");