drivers/gpio/gpio-mmio.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Generic driver for memory-mapped GPIO controllers.
   4  *
   5  * Copyright 2008 MontaVista Software, Inc.
   6  * Copyright 2008,2010 Anton Vorontsov <cbouatmailru@gmail.com>
   7  *
   8  * ....``.```~~~~````.`.`.`.`.```````'',,,.........`````......`.......
   9  * ...``                                                         ```````..
  10  * ..The simplest form of a GPIO controller that the driver supports is``
  11  *  `.just a single "data" register, where GPIO state can be read and/or `
  12  *    `,..written. ,,..``~~~~ .....``.`.`.~~.```.`.........``````.```````
  13  *        `````````
  14                                     ___
  15 _/~~|___/~|   . ```~~~~~~       ___/___\___     ,~.`.`.`.`````.~~...,,,,...
  16 __________|~$@~~~        %~    /o*o*o*o*o*o\   .. Implementing such a GPIO .
  17 o        `                     ~~~~\___/~~~~    ` controller in FPGA is ,.`
  18                                                  `....trivial..'~`.```.```
  19  *                                                    ```````
  20  *  .```````~~~~`..`.``.``.
  21  * .  The driver supports  `...       ,..```.`~~~```````````````....````.``,,
  22  * .   big-endian notation, just`.  .. A bit more sophisticated controllers ,
  23  *  . register the device with -be`. .with a pair of set/clear-bit registers ,
  24  *   `.. suffix.  ```~~`````....`.`   . affecting the data register and the .`
  25  *     ``.`.``...```                  ```.. output pins are also supported.`
  26  *                        ^^             `````.`````````.,``~``~``~~``````
  27  *                                                   .                  ^^
  28  *   ,..`.`.`...````````````......`.`.`.`.`.`..`.`.`..
  29  * .. The expectation is that in at least some cases .    ,-~~~-,
  30  *  .this will be used with roll-your-own ASIC/FPGA .`     \   /
  31  *  .logic in Verilog or VHDL. ~~~`````````..`````~~`       \ /
  32  *  ..````````......```````````                             \o_
  33  *                                                           |
  34  *                              ^^                          / \
  35  *
  36  *           ...`````~~`.....``.`..........``````.`.``.```........``.
  37  *            `  8, 16, 32 and 64 bits registers are supported, and``.
  38  *            . the number of GPIOs is determined by the width of   ~
  39  *             .. the registers. ,............```.`.`..`.`.~~~.`.`.`~
  40  *               `.......````.```
  41  */
  42
  43 #include <linux/init.h>
  44 #include <linux/err.h>
  45 #include <linux/bug.h>
  46 #include <linux/kernel.h>
  47 #include <linux/module.h>
  48 #include <linux/spinlock.h>
  49 #include <linux/compiler.h>
  50 #include <linux/types.h>
  51 #include <linux/errno.h>
  52 #include <linux/log2.h>
  53 #include <linux/ioport.h>
  54 #include <linux/io.h>
  55 #include <linux/gpio/driver.h>
  56 #include <linux/slab.h>
  57 #include <linux/bitops.h>
  58 #include <linux/platform_device.h>
  59 #include <linux/mod_devicetable.h>
  60 #include <linux/of.h>
  61 #include <linux/of_device.h>
  62
  63 static void bgpio_write8(void __iomem *reg, unsigned long data)
  64 {
  65         writeb(data, reg);
  66 }
  67
  68 static unsigned long bgpio_read8(void __iomem *reg)
  69 {
  70         return readb(reg);
  71 }
  72
  73 static void bgpio_write16(void __iomem *reg, unsigned long data)
  74 {
  75         writew(data, reg);
  76 }
  77
  78 static unsigned long bgpio_read16(void __iomem *reg)
  79 {
  80         return readw(reg);
  81 }
  82
  83 static void bgpio_write32(void __iomem *reg, unsigned long data)
  84 {
  85         writel(data, reg);
  86 }
  87
  88 static unsigned long bgpio_read32(void __iomem *reg)
  89 {
  90         return readl(reg);
  91 }
  92
  93 #if BITS_PER_LONG >= 64
  94 static void bgpio_write64(void __iomem *reg, unsigned long data)
  95 {
  96         writeq(data, reg);
  97 }
  98
  99 static unsigned long bgpio_read64(void __iomem *reg)
 100 {
 101         return readq(reg);
 102 }
 103 #endif /* BITS_PER_LONG >= 64 */
 104
 105 static void bgpio_write16be(void __iomem *reg, unsigned long data)
 106 {
 107         iowrite16be(data, reg);
 108 }
 109
 110 static unsigned long bgpio_read16be(void __iomem *reg)
 111 {
 112         return ioread16be(reg);
 113 }
 114
 115 static void bgpio_write32be(void __iomem *reg, unsigned long data)
 116 {
 117         iowrite32be(data, reg);
 118 }
 119
 120 static unsigned long bgpio_read32be(void __iomem *reg)
 121 {
 122         return ioread32be(reg);
 123 }
 124
 125 static unsigned long bgpio_line2mask(struct gpio_chip *gc, unsigned int line)
 126 {
 127         if (gc->be_bits)
 128                 return BIT(gc->bgpio_bits - 1 - line);
 129         return BIT(line);
 130 }
 131
 132 static int bgpio_get_set(struct gpio_chip *gc, unsigned int gpio)
 133 {
 134         unsigned long pinmask = bgpio_line2mask(gc, gpio);
 135         bool dir = !!(gc->bgpio_dir & pinmask);
 136
 137         if (dir)
 138                 return !!(gc->read_reg(gc->reg_set) & pinmask);
 139         else
 140                 return !!(gc->read_reg(gc->reg_dat) & pinmask);
 141 }
 142
 143 /*
 144  * This assumes that the bits in the GPIO register are in native endianness.
 145  * We only assign the function pointer if we have that.
 146  */
 147 static int bgpio_get_set_multiple(struct gpio_chip *gc, unsigned long *mask,
 148                                   unsigned long *bits)
 149 {
 150         unsigned long get_mask = 0;
 151         unsigned long set_mask = 0;
 152
 153         /* Make sure we first clear any bits that are zero when we read the register */
 154         *bits &= ~*mask;
 155
 156         set_mask = *mask & gc->bgpio_dir;
 157         get_mask = *mask & ~gc->bgpio_dir;
 158
 159         if (set_mask)
 160                 *bits |= gc->read_reg(gc->reg_set) & set_mask;
 161         if (get_mask)
 162                 *bits |= gc->read_reg(gc->reg_dat) & get_mask;
 163
 164         return 0;
 165 }
 166
 167 static int bgpio_get(struct gpio_chip *gc, unsigned int gpio)
 168 {
 169         return !!(gc->read_reg(gc->reg_dat) & bgpio_line2mask(gc, gpio));
 170 }
 171
 172 /*
 173  * This only works if the bits in the GPIO register are in native endianness.
 174  */
 175 static int bgpio_get_multiple(struct gpio_chip *gc, unsigned long *mask,
 176                               unsigned long *bits)
 177 {
 178         /* Make sure we first clear any bits that are zero when we read the register */
 179         *bits &= ~*mask;
 180         *bits |= gc->read_reg(gc->reg_dat) & *mask;
 181         return 0;
 182 }
 183
 184 /*
 185  * With big endian mirrored bit order it becomes more tedious.
 186  */
 187 static int bgpio_get_multiple_be(struct gpio_chip *gc, unsigned long *mask,
 188                                  unsigned long *bits)
 189 {
 190         unsigned long readmask = 0;
 191         unsigned long val;
 192         int bit;
 193
 194         /* Make sure we first clear any bits that are zero when we read the register */
 195         *bits &= ~*mask;
 196
 197         /* Create a mirrored mask */
 198         for_each_set_bit(bit, mask, gc->ngpio)
 199                 readmask |= bgpio_line2mask(gc, bit);
 200
 201         /* Read the register */
 202         val = gc->read_reg(gc->reg_dat) & readmask;
 203
 204         /*
 205          * Mirror the result into the "bits" result, this will give line 0
 206          * in bit 0 ... line 31 in bit 31 for a 32bit register.
 207          */
 208         for_each_set_bit(bit, &val, gc->ngpio)
 209                 *bits |= bgpio_line2mask(gc, bit);
 210
 211         return 0;
 212 }
 213
 214 static void bgpio_set_none(struct gpio_chip *gc, unsigned int gpio, int val)
 215 {
 216 }
 217
 218 static void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
 219 {
 220         unsigned long mask = bgpio_line2mask(gc, gpio);
 221         unsigned long flags;
 222
 223         spin_lock_irqsave(&gc->bgpio_lock, flags);
 224
 225         if (val)
 226                 gc->bgpio_data |= mask;
 227         else
 228                 gc->bgpio_data &= ~mask;
 229
 230         gc->write_reg(gc->reg_dat, gc->bgpio_data);
 231
 232         spin_unlock_irqrestore(&gc->bgpio_lock, flags);
 233 }
 234
 235 static void bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio,
 236                                  int val)
 237 {
 238         unsigned long mask = bgpio_line2mask(gc, gpio);
 239
 240         if (val)
 241                 gc->write_reg(gc->reg_set, mask);
 242         else
 243                 gc->write_reg(gc->reg_clr, mask);
 244 }
 245
 246 static void bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val)
 247 {
 248         unsigned long mask = bgpio_line2mask(gc, gpio);
 249         unsigned long flags;
 250
 251         spin_lock_irqsave(&gc->bgpio_lock, flags);
 252
 253         if (val)
 254                 gc->bgpio_data |= mask;
 255         else
 256                 gc->bgpio_data &= ~mask;
 257
 258         gc->write_reg(gc->reg_set, gc->bgpio_data);
 259
 260         spin_unlock_irqrestore(&gc->bgpio_lock, flags);
 261 }
 262
 263 static void bgpio_multiple_get_masks(struct gpio_chip *gc,
 264                                      unsigned long *mask, unsigned long *bits,
 265                                      unsigned long *set_mask,
 266                                      unsigned long *clear_mask)
 267 {
 268         int i;
 269
 270         *set_mask = 0;
 271         *clear_mask = 0;
 272
 273         for_each_set_bit(i, mask, gc->bgpio_bits) {
 274                 if (test_bit(i, bits))
 275                         *set_mask |= bgpio_line2mask(gc, i);
 276                 else
 277                         *clear_mask |= bgpio_line2mask(gc, i);
 278         }
 279 }
 280
 281 static void bgpio_set_multiple_single_reg(struct gpio_chip *gc,
 282                                           unsigned long *mask,
 283                                           unsigned long *bits,
 284                                           void __iomem *reg)
 285 {
 286         unsigned long flags;
 287         unsigned long set_mask, clear_mask;
 288
 289         spin_lock_irqsave(&gc->bgpio_lock, flags);
 290
 291         bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask);
 292
 293         gc->bgpio_data |= set_mask;
 294         gc->bgpio_data &= ~clear_mask;
 295
 296         gc->write_reg(reg, gc->bgpio_data);
 297
 298         spin_unlock_irqrestore(&gc->bgpio_lock, flags);
 299 }
 300
 301 static void bgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
 302                                unsigned long *bits)
 303 {
 304         bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_dat);
 305 }
 306
 307 static void bgpio_set_multiple_set(struct gpio_chip *gc, unsigned long *mask,
 308                                    unsigned long *bits)
 309 {
 310         bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_set);
 311 }
 312
 313 static void bgpio_set_multiple_with_clear(struct gpio_chip *gc,
 314                                           unsigned long *mask,
 315                                           unsigned long *bits)
 316 {
 317         unsigned long set_mask, clear_mask;
 318
 319         bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask);
 320
 321         if (set_mask)
 322                 gc->write_reg(gc->reg_set, set_mask);
 323         if (clear_mask)
 324                 gc->write_reg(gc->reg_clr, clear_mask);
 325 }
 326
 327 static int bgpio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio)
 328 {
 329         return 0;
 330 }
 331
 332 static int bgpio_dir_out_err(struct gpio_chip *gc, unsigned int gpio,
 333                                 int val)
 334 {
 335         return -EINVAL;
 336 }
 337
 338 static int bgpio_simple_dir_out(struct gpio_chip *gc, unsigned int gpio,
 339                                 int val)
 340 {
 341         gc->set(gc, gpio, val);
 342
 343         return 0;
 344 }
 345
 346 static int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
 347 {
 348         unsigned long flags;
 349
 350         spin_lock_irqsave(&gc->bgpio_lock, flags);
 351
 352         gc->bgpio_dir &= ~bgpio_line2mask(gc, gpio);
 353
 354         if (gc->reg_dir_in)
 355                 gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir);
 356         if (gc->reg_dir_out)
 357                 gc->write_reg(gc->reg_dir_out, gc->bgpio_dir);
 358
 359         spin_unlock_irqrestore(&gc->bgpio_lock, flags);
 360
 361         return 0;
 362 }
 363
 364 static int bgpio_get_dir(struct gpio_chip *gc, unsigned int gpio)
 365 {
 366         /* Return 0 if output, 1 if input */
 367         if (gc->bgpio_dir_unreadable) {
 368                 if (gc->bgpio_dir & bgpio_line2mask(gc, gpio))
 369                         return GPIO_LINE_DIRECTION_OUT;
 370                 return GPIO_LINE_DIRECTION_IN;
 371         }
 372
 373         if (gc->reg_dir_out) {
 374                 if (gc->read_reg(gc->reg_dir_out) & bgpio_line2mask(gc, gpio))
 375                         return GPIO_LINE_DIRECTION_OUT;
 376                 return GPIO_LINE_DIRECTION_IN;
 377         }
 378
 379         if (gc->reg_dir_in)
 380                 if (!(gc->read_reg(gc->reg_dir_in) & bgpio_line2mask(gc, gpio)))
 381                         return GPIO_LINE_DIRECTION_OUT;
 382
 383         return GPIO_LINE_DIRECTION_IN;
 384 }
 385
 386 static void bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
 387 {
 388         unsigned long flags;
 389
 390         spin_lock_irqsave(&gc->bgpio_lock, flags);
 391
 392         gc->bgpio_dir |= bgpio_line2mask(gc, gpio);
 393
 394         if (gc->reg_dir_in)
 395                 gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir);
 396         if (gc->reg_dir_out)
 397                 gc->write_reg(gc->reg_dir_out, gc->bgpio_dir);
 398
 399         spin_unlock_irqrestore(&gc->bgpio_lock, flags);
 400 }
 401
 402 static int bgpio_dir_out_dir_first(struct gpio_chip *gc, unsigned int gpio,
 403                                    int val)
 404 {
 405         bgpio_dir_out(gc, gpio, val);
 406         gc->set(gc, gpio, val);
 407         return 0;
 408 }
 409
 410 static int bgpio_dir_out_val_first(struct gpio_chip *gc, unsigned int gpio,
 411                                    int val)
 412 {
 413         gc->set(gc, gpio, val);
 414         bgpio_dir_out(gc, gpio, val);
 415         return 0;
 416 }
 417
 418 static int bgpio_setup_accessors(struct device *dev,
 419                                  struct gpio_chip *gc,
 420                                  bool byte_be)
 421 {
 422
 423         switch (gc->bgpio_bits) {
 424         case 8:
 425                 gc->read_reg    = bgpio_read8;
 426                 gc->write_reg   = bgpio_write8;
 427                 break;
 428         case 16:
 429                 if (byte_be) {
 430                         gc->read_reg    = bgpio_read16be;
 431                         gc->write_reg   = bgpio_write16be;
 432                 } else {
 433                         gc->read_reg    = bgpio_read16;
 434                         gc->write_reg   = bgpio_write16;
 435                 }
 436                 break;
 437         case 32:
 438                 if (byte_be) {
 439                         gc->read_reg    = bgpio_read32be;
 440                         gc->write_reg   = bgpio_write32be;
 441                 } else {
 442                         gc->read_reg    = bgpio_read32;
 443                         gc->write_reg   = bgpio_write32;
 444                 }
 445                 break;
 446 #if BITS_PER_LONG >= 64
 447         case 64:
 448                 if (byte_be) {
 449                         dev_err(dev,
 450                                 "64 bit big endian byte order unsupported\n");
 451                         return -EINVAL;
 452                 } else {
 453                         gc->read_reg    = bgpio_read64;
 454                         gc->write_reg   = bgpio_write64;
 455                 }
 456                 break;
 457 #endif /* BITS_PER_LONG >= 64 */
 458         default:
 459                 dev_err(dev, "unsupported data width %u bits\n", gc->bgpio_bits);
 460                 return -EINVAL;
 461         }
 462
 463         return 0;
 464 }
 465
 466 /*
 467  * Create the device and allocate the resources.  For setting GPIO's there are
 468  * three supported configurations:
 469  *
 470  *      - single input/output register resource (named "dat").
 471  *      - set/clear pair (named "set" and "clr").
 472  *      - single output register resource and single input resource ("set" and
 473  *      dat").
 474  *
 475  * For the single output register, this drives a 1 by setting a bit and a zero
 476  * by clearing a bit.  For the set clr pair, this drives a 1 by setting a bit
 477  * in the set register and clears it by setting a bit in the clear register.
 478  * The configuration is detected by which resources are present.
 479  *
 480  * For setting the GPIO direction, there are three supported configurations:
 481  *
 482  *      - simple bidirection GPIO that requires no configuration.
 483  *      - an output direction register (named "dirout") where a 1 bit
 484  *      indicates the GPIO is an output.
 485  *      - an input direction register (named "dirin") where a 1 bit indicates
 486  *      the GPIO is an input.
 487  */
 488 static int bgpio_setup_io(struct gpio_chip *gc,
 489                           void __iomem *dat,
 490                           void __iomem *set,
 491                           void __iomem *clr,
 492                           unsigned long flags)
 493 {
 494
 495         gc->reg_dat = dat;
 496         if (!gc->reg_dat)
 497                 return -EINVAL;
 498
 499         if (set && clr) {
 500                 gc->reg_set = set;
 501                 gc->reg_clr = clr;
 502                 gc->set = bgpio_set_with_clear;
 503                 gc->set_multiple = bgpio_set_multiple_with_clear;
 504         } else if (set && !clr) {
 505                 gc->reg_set = set;
 506                 gc->set = bgpio_set_set;
 507                 gc->set_multiple = bgpio_set_multiple_set;
 508         } else if (flags & BGPIOF_NO_OUTPUT) {
 509                 gc->set = bgpio_set_none;
 510                 gc->set_multiple = NULL;
 511         } else {
 512                 gc->set = bgpio_set;
 513                 gc->set_multiple = bgpio_set_multiple;
 514         }
 515
 516         if (!(flags & BGPIOF_UNREADABLE_REG_SET) &&
 517             (flags & BGPIOF_READ_OUTPUT_REG_SET)) {
 518                 gc->get = bgpio_get_set;
 519                 if (!gc->be_bits)
 520                         gc->get_multiple = bgpio_get_set_multiple;
 521                 /*
 522                  * We deliberately avoid assigning the ->get_multiple() call
 523                  * for big endian mirrored registers which are ALSO reflecting
 524                  * their value in the set register when used as output. It is
 525                  * simply too much complexity, let the GPIO core fall back to
 526                  * reading each line individually in that fringe case.
 527                  */
 528         } else {
 529                 gc->get = bgpio_get;
 530                 if (gc->be_bits)
 531                         gc->get_multiple = bgpio_get_multiple_be;
 532                 else
 533                         gc->get_multiple = bgpio_get_multiple;
 534         }
 535
 536         return 0;
 537 }
 538
 539 static int bgpio_setup_direction(struct gpio_chip *gc,
 540                                  void __iomem *dirout,
 541                                  void __iomem *dirin,
 542                                  unsigned long flags)
 543 {
 544         if (dirout || dirin) {
 545                 gc->reg_dir_out = dirout;
 546                 gc->reg_dir_in = dirin;
 547                 if (flags & BGPIOF_NO_SET_ON_INPUT)
 548                         gc->direction_output = bgpio_dir_out_dir_first;
 549                 else
 550                         gc->direction_output = bgpio_dir_out_val_first;
 551                 gc->direction_input = bgpio_dir_in;
 552                 gc->get_direction = bgpio_get_dir;
 553         } else {
 554                 if (flags & BGPIOF_NO_OUTPUT)
 555                         gc->direction_output = bgpio_dir_out_err;
 556                 else
 557                         gc->direction_output = bgpio_simple_dir_out;
 558                 gc->direction_input = bgpio_simple_dir_in;
 559         }
 560
 561         return 0;
 562 }
 563
 564 static int bgpio_request(struct gpio_chip *chip, unsigned gpio_pin)
 565 {
 566         if (gpio_pin < chip->ngpio)
 567                 return 0;
 568
 569         return -EINVAL;
 570 }
 571
 572 /**
 573  * bgpio_init() - Initialize generic GPIO accessor functions
 574  * @gc: the GPIO chip to set up
 575  * @dev: the parent device of the new GPIO chip (compulsory)
 576  * @sz: the size (width) of the MMIO registers in bytes, typically 1, 2 or 4
 577  * @dat: MMIO address for the register to READ the value of the GPIO lines, it
 578  *      is expected that a 1 in the corresponding bit in this register means the
 579  *      line is asserted
 580  * @set: MMIO address for the register to SET the value of the GPIO lines, it is
 581  *      expected that we write the line with 1 in this register to drive the GPIO line
 582  *      high.
 583  * @clr: MMIO address for the register to CLEAR the value of the GPIO lines, it is
 584  *      expected that we write the line with 1 in this register to drive the GPIO line
 585  *      low. It is allowed to leave this address as NULL, in that case the SET register
 586  *      will be assumed to also clear the GPIO lines, by actively writing the line
 587  *      with 0.
 588  * @dirout: MMIO address for the register to set the line as OUTPUT. It is assumed
 589  *      that setting a line to 1 in this register will turn that line into an
 590  *      output line. Conversely, setting the line to 0 will turn that line into
 591  *      an input.
 592  * @dirin: MMIO address for the register to set this line as INPUT. It is assumed
 593  *      that setting a line to 1 in this register will turn that line into an
 594  *      input line. Conversely, setting the line to 0 will turn that line into
 595  *      an output.
 596  * @flags: Different flags that will affect the behaviour of the device, such as
 597  *      endianness etc.
 598  */
 599 int bgpio_init(struct gpio_chip *gc, struct device *dev,
 600                unsigned long sz, void __iomem *dat, void __iomem *set,
 601                void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
 602                unsigned long flags)
 603 {
 604         int ret;
 605
 606         if (!is_power_of_2(sz))
 607                 return -EINVAL;
 608
 609         gc->bgpio_bits = sz * 8;
 610         if (gc->bgpio_bits > BITS_PER_LONG)
 611                 return -EINVAL;
 612
 613         spin_lock_init(&gc->bgpio_lock);
 614         gc->parent = dev;
 615         gc->label = dev_name(dev);
 616         gc->base = -1;
 617         gc->ngpio = gc->bgpio_bits;
 618         gc->request = bgpio_request;
 619         gc->be_bits = !!(flags & BGPIOF_BIG_ENDIAN);
 620
 621         ret = bgpio_setup_io(gc, dat, set, clr, flags);
 622         if (ret)
 623                 return ret;
 624
 625         ret = bgpio_setup_accessors(dev, gc, flags & BGPIOF_BIG_ENDIAN_BYTE_ORDER);
 626         if (ret)
 627                 return ret;
 628
 629         ret = bgpio_setup_direction(gc, dirout, dirin, flags);
 630         if (ret)
 631                 return ret;
 632
 633         gc->bgpio_data = gc->read_reg(gc->reg_dat);
 634         if (gc->set == bgpio_set_set &&
 635                         !(flags & BGPIOF_UNREADABLE_REG_SET))
 636                 gc->bgpio_data = gc->read_reg(gc->reg_set);
 637
 638         if (flags & BGPIOF_UNREADABLE_REG_DIR)
 639                 gc->bgpio_dir_unreadable = true;
 640
 641         /*
 642          * Inspect hardware to find initial direction setting.
 643          */
 644         if ((gc->reg_dir_out || gc->reg_dir_in) &&
 645             !(flags & BGPIOF_UNREADABLE_REG_DIR)) {
 646                 if (gc->reg_dir_out)
 647                         gc->bgpio_dir = gc->read_reg(gc->reg_dir_out);
 648                 else if (gc->reg_dir_in)
 649                         gc->bgpio_dir = ~gc->read_reg(gc->reg_dir_in);
 650                 /*
 651                  * If we have two direction registers, synchronise
 652                  * input setting to output setting, the library
 653                  * can not handle a line being input and output at
 654                  * the same time.
 655                  */
 656                 if (gc->reg_dir_out && gc->reg_dir_in)
 657                         gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir);
 658         }
 659
 660         return ret;
 661 }
 662 EXPORT_SYMBOL_GPL(bgpio_init);
 663
 664 #if IS_ENABLED(CONFIG_GPIO_GENERIC_PLATFORM)
 665
 666 static void __iomem *bgpio_map(struct platform_device *pdev,
 667                                const char *name,
 668                                resource_size_t sane_sz)
 669 {
 670         struct resource *r;
 671         resource_size_t sz;
 672
 673         r = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
 674         if (!r)
 675                 return NULL;
 676
 677         sz = resource_size(r);
 678         if (sz != sane_sz)
 679                 return IOMEM_ERR_PTR(-EINVAL);
 680
 681         return devm_ioremap_resource(&pdev->dev, r);
 682 }
 683
 684 #ifdef CONFIG_OF
 685 static const struct of_device_id bgpio_of_match[] = {
 686         { .compatible = "brcm,bcm6345-gpio" },
 687         { .compatible = "wd,mbl-gpio" },
 688         { .compatible = "ni,169445-nand-gpio" },
 689         { }
 690 };
 691 MODULE_DEVICE_TABLE(of, bgpio_of_match);
 692
 693 static struct bgpio_pdata *bgpio_parse_dt(struct platform_device *pdev,
 694                                           unsigned long *flags)
 695 {
 696         struct bgpio_pdata *pdata;
 697
 698         if (!of_match_device(bgpio_of_match, &pdev->dev))
 699                 return NULL;
 700
 701         pdata = devm_kzalloc(&pdev->dev, sizeof(struct bgpio_pdata),
 702                              GFP_KERNEL);
 703         if (!pdata)
 704                 return ERR_PTR(-ENOMEM);
 705
 706         pdata->base = -1;
 707
 708         if (of_device_is_big_endian(pdev->dev.of_node))
 709                 *flags |= BGPIOF_BIG_ENDIAN_BYTE_ORDER;
 710
 711         if (of_property_read_bool(pdev->dev.of_node, "no-output"))
 712                 *flags |= BGPIOF_NO_OUTPUT;
 713
 714         return pdata;
 715 }
 716 #else
 717 static struct bgpio_pdata *bgpio_parse_dt(struct platform_device *pdev,
 718                                           unsigned long *flags)
 719 {
 720         return NULL;
 721 }
 722 #endif /* CONFIG_OF */
 723
 724 static int bgpio_pdev_probe(struct platform_device *pdev)
 725 {
 726         struct device *dev = &pdev->dev;
 727         struct resource *r;
 728         void __iomem *dat;
 729         void __iomem *set;
 730         void __iomem *clr;
 731         void __iomem *dirout;
 732         void __iomem *dirin;
 733         unsigned long sz;
 734         unsigned long flags = 0;
 735         int err;
 736         struct gpio_chip *gc;
 737         struct bgpio_pdata *pdata;
 738
 739         pdata = bgpio_parse_dt(pdev, &flags);
 740         if (IS_ERR(pdata))
 741                 return PTR_ERR(pdata);
 742
 743         if (!pdata) {
 744                 pdata = dev_get_platdata(dev);
 745                 flags = pdev->id_entry->driver_data;
 746         }
 747
 748         r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
 749         if (!r)
 750                 return -EINVAL;
 751
 752         sz = resource_size(r);
 753
 754         dat = bgpio_map(pdev, "dat", sz);
 755         if (IS_ERR(dat))
 756                 return PTR_ERR(dat);
 757
 758         set = bgpio_map(pdev, "set", sz);
 759         if (IS_ERR(set))
 760                 return PTR_ERR(set);
 761
 762         clr = bgpio_map(pdev, "clr", sz);
 763         if (IS_ERR(clr))
 764                 return PTR_ERR(clr);
 765
 766         dirout = bgpio_map(pdev, "dirout", sz);
 767         if (IS_ERR(dirout))
 768                 return PTR_ERR(dirout);
 769
 770         dirin = bgpio_map(pdev, "dirin", sz);
 771         if (IS_ERR(dirin))
 772                 return PTR_ERR(dirin);
 773
 774         gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL);
 775         if (!gc)
 776                 return -ENOMEM;
 777
 778         err = bgpio_init(gc, dev, sz, dat, set, clr, dirout, dirin, flags);
 779         if (err)
 780                 return err;
 781
 782         if (pdata) {
 783                 if (pdata->label)
 784                         gc->label = pdata->label;
 785                 gc->base = pdata->base;
 786                 if (pdata->ngpio > 0)
 787                         gc->ngpio = pdata->ngpio;
 788         }
 789
 790         platform_set_drvdata(pdev, gc);
 791
 792         return devm_gpiochip_add_data(&pdev->dev, gc, NULL);
 793 }
 794
 795 static const struct platform_device_id bgpio_id_table[] = {
 796         {
 797                 .name           = "basic-mmio-gpio",
 798                 .driver_data    = 0,
 799         }, {
 800                 .name           = "basic-mmio-gpio-be",
 801                 .driver_data    = BGPIOF_BIG_ENDIAN,
 802         },
 803         { }
 804 };
 805 MODULE_DEVICE_TABLE(platform, bgpio_id_table);
 806
 807 static struct platform_driver bgpio_driver = {
 808         .driver = {
 809                 .name = "basic-mmio-gpio",
 810                 .of_match_table = of_match_ptr(bgpio_of_match),
 811         },
 812         .id_table = bgpio_id_table,
 813         .probe = bgpio_pdev_probe,
 814 };
 815
 816 module_platform_driver(bgpio_driver);
 817
 818 #endif /* CONFIG_GPIO_GENERIC_PLATFORM */
 819
 820 MODULE_DESCRIPTION("Driver for basic memory-mapped GPIO controllers");
 821 MODULE_AUTHOR("Anton Vorontsov <cbouatmailru@gmail.com>");
 822 MODULE_LICENSE("GPL");