1 // SPDX-License-Identifier: GPL-2.0
3 * GPIO interface for Intel Sodaville SoCs.
5 * Copyright (c) 2010, 2011 Intel Corporation
7 * Author: Hans J. Koch <hjk@linutronix.de>
10 #include <linux/errno.h>
11 #include <linux/gpio/driver.h>
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
15 #include <linux/irq.h>
16 #include <linux/kernel.h>
17 #include <linux/of_irq.h>
18 #include <linux/pci.h>
19 #include <linux/platform_device.h>
21 #define DRV_NAME "sdv_gpio"
22 #define SDV_NUM_PUB_GPIOS 12
23 #define PCI_DEVICE_ID_SDV_GPIO 0x2e67
37 struct sdv_gpio_chip_data
{
39 void __iomem
*gpio_pub_base
;
40 struct irq_domain
*id
;
41 struct irq_chip_generic
*gc
;
42 struct gpio_chip chip
;
45 static int sdv_gpio_pub_set_type(struct irq_data
*d
, unsigned int type
)
47 struct irq_chip_generic
*gc
= irq_data_get_irq_chip_data(d
);
48 struct sdv_gpio_chip_data
*sd
= gc
->private;
49 void __iomem
*type_reg
;
53 type_reg
= sd
->gpio_pub_base
+ GPIT1R0
;
55 type_reg
= sd
->gpio_pub_base
+ GPIT1R1
;
57 reg
= readl(type_reg
);
60 case IRQ_TYPE_LEVEL_HIGH
:
61 reg
&= ~BIT(4 * (d
->hwirq
% 8));
64 case IRQ_TYPE_LEVEL_LOW
:
65 reg
|= BIT(4 * (d
->hwirq
% 8));
72 writel(reg
, type_reg
);
76 static irqreturn_t
sdv_gpio_pub_irq_handler(int irq
, void *data
)
78 struct sdv_gpio_chip_data
*sd
= data
;
79 unsigned long irq_stat
= readl(sd
->gpio_pub_base
+ GPSTR
);
82 irq_stat
&= readl(sd
->gpio_pub_base
+ GPIO_INT
);
86 for_each_set_bit(irq_bit
, &irq_stat
, 32)
87 generic_handle_irq(irq_find_mapping(sd
->id
, irq_bit
));
92 static int sdv_xlate(struct irq_domain
*h
, struct device_node
*node
,
93 const u32
*intspec
, u32 intsize
, irq_hw_number_t
*out_hwirq
,
98 if (node
!= irq_domain_get_of_node(h
))
111 case IRQ_TYPE_LEVEL_LOW
:
112 case IRQ_TYPE_LEVEL_HIGH
:
121 static const struct irq_domain_ops irq_domain_sdv_ops
= {
125 static int sdv_register_irqsupport(struct sdv_gpio_chip_data
*sd
,
126 struct pci_dev
*pdev
)
128 struct irq_chip_type
*ct
;
131 sd
->irq_base
= devm_irq_alloc_descs(&pdev
->dev
, -1, 0,
132 SDV_NUM_PUB_GPIOS
, -1);
133 if (sd
->irq_base
< 0)
136 /* mask + ACK all interrupt sources */
137 writel(0, sd
->gpio_pub_base
+ GPIO_INT
);
138 writel((1 << 11) - 1, sd
->gpio_pub_base
+ GPSTR
);
140 ret
= devm_request_irq(&pdev
->dev
, pdev
->irq
,
141 sdv_gpio_pub_irq_handler
, IRQF_SHARED
,
147 * This gpio irq controller latches level irqs. Testing shows that if
148 * we unmask & ACK the IRQ before the source of the interrupt is gone
149 * then the interrupt is active again.
151 sd
->gc
= devm_irq_alloc_generic_chip(&pdev
->dev
, "sdv-gpio", 1,
158 sd
->gc
->private = sd
;
159 ct
= sd
->gc
->chip_types
;
160 ct
->type
= IRQ_TYPE_LEVEL_HIGH
| IRQ_TYPE_LEVEL_LOW
;
161 ct
->regs
.eoi
= GPSTR
;
162 ct
->regs
.mask
= GPIO_INT
;
163 ct
->chip
.irq_mask
= irq_gc_mask_clr_bit
;
164 ct
->chip
.irq_unmask
= irq_gc_mask_set_bit
;
165 ct
->chip
.irq_eoi
= irq_gc_eoi
;
166 ct
->chip
.irq_set_type
= sdv_gpio_pub_set_type
;
168 irq_setup_generic_chip(sd
->gc
, IRQ_MSK(SDV_NUM_PUB_GPIOS
),
169 IRQ_GC_INIT_MASK_CACHE
, IRQ_NOREQUEST
,
170 IRQ_LEVEL
| IRQ_NOPROBE
);
172 sd
->id
= irq_domain_add_legacy(pdev
->dev
.of_node
, SDV_NUM_PUB_GPIOS
,
173 sd
->irq_base
, 0, &irq_domain_sdv_ops
, sd
);
180 static int sdv_gpio_probe(struct pci_dev
*pdev
,
181 const struct pci_device_id
*pci_id
)
183 struct sdv_gpio_chip_data
*sd
;
187 sd
= devm_kzalloc(&pdev
->dev
, sizeof(*sd
), GFP_KERNEL
);
191 ret
= pcim_enable_device(pdev
);
193 dev_err(&pdev
->dev
, "can't enable device.\n");
197 ret
= pcim_iomap_regions(pdev
, 1 << GPIO_BAR
, DRV_NAME
);
199 dev_err(&pdev
->dev
, "can't alloc PCI BAR #%d\n", GPIO_BAR
);
203 sd
->gpio_pub_base
= pcim_iomap_table(pdev
)[GPIO_BAR
];
205 ret
= of_property_read_u32(pdev
->dev
.of_node
, "intel,muxctl", &mux_val
);
207 writel(mux_val
, sd
->gpio_pub_base
+ GPMUXCTL
);
209 ret
= bgpio_init(&sd
->chip
, &pdev
->dev
, 4,
210 sd
->gpio_pub_base
+ GPINR
, sd
->gpio_pub_base
+ GPOUTR
,
211 NULL
, sd
->gpio_pub_base
+ GPOER
, NULL
, 0);
215 sd
->chip
.ngpio
= SDV_NUM_PUB_GPIOS
;
217 ret
= devm_gpiochip_add_data(&pdev
->dev
, &sd
->chip
, sd
);
219 dev_err(&pdev
->dev
, "gpiochip_add() failed.\n");
223 ret
= sdv_register_irqsupport(sd
, pdev
);
227 pci_set_drvdata(pdev
, sd
);
228 dev_info(&pdev
->dev
, "Sodaville GPIO driver registered.\n");
232 static const struct pci_device_id sdv_gpio_pci_ids
[] = {
233 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_SDV_GPIO
) },
237 static struct pci_driver sdv_gpio_driver
= {
239 .suppress_bind_attrs
= true,
242 .id_table
= sdv_gpio_pci_ids
,
243 .probe
= sdv_gpio_probe
,
245 builtin_pci_driver(sdv_gpio_driver
);