drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-j721e.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * TI j721e Cadence MHDP8546 DP wrapper
   4  *
   5  * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
   6  * Author: Jyri Sarha <jsarha@ti.com>
   7  */
   8
   9 #include <linux/io.h>
  10 #include <linux/platform_device.h>
  11
  12 #include "cdns-mhdp8546-j721e.h"
  13
  14 #define REVISION                        0x00
  15 #define DPTX_IPCFG                      0x04
  16 #define ECC_MEM_CFG                     0x08
  17 #define DPTX_DSC_CFG                    0x0c
  18 #define DPTX_SRC_CFG                    0x10
  19 #define DPTX_VIF_SECURE_MODE_CFG        0x14
  20 #define DPTX_VIF_CONN_STATUS            0x18
  21 #define PHY_CLK_STATUS                  0x1c
  22
  23 #define DPTX_SRC_AIF_EN                 BIT(16)
  24 #define DPTX_SRC_VIF_3_IN30B            BIT(11)
  25 #define DPTX_SRC_VIF_2_IN30B            BIT(10)
  26 #define DPTX_SRC_VIF_1_IN30B            BIT(9)
  27 #define DPTX_SRC_VIF_0_IN30B            BIT(8)
  28 #define DPTX_SRC_VIF_3_SEL_DPI5         BIT(7)
  29 #define DPTX_SRC_VIF_3_SEL_DPI3         0
  30 #define DPTX_SRC_VIF_2_SEL_DPI4         BIT(6)
  31 #define DPTX_SRC_VIF_2_SEL_DPI2         0
  32 #define DPTX_SRC_VIF_1_SEL_DPI3         BIT(5)
  33 #define DPTX_SRC_VIF_1_SEL_DPI1         0
  34 #define DPTX_SRC_VIF_0_SEL_DPI2         BIT(4)
  35 #define DPTX_SRC_VIF_0_SEL_DPI0         0
  36 #define DPTX_SRC_VIF_3_EN               BIT(3)
  37 #define DPTX_SRC_VIF_2_EN               BIT(2)
  38 #define DPTX_SRC_VIF_1_EN               BIT(1)
  39 #define DPTX_SRC_VIF_0_EN               BIT(0)
  40
  41 /* TODO turn DPTX_IPCFG fw_mem_clk_en at pm_runtime_suspend. */
  42
  43 static int cdns_mhdp_j721e_init(struct cdns_mhdp_device *mhdp)
  44 {
  45         struct platform_device *pdev = to_platform_device(mhdp->dev);
  46
  47         mhdp->j721e_regs = devm_platform_ioremap_resource(pdev, 1);
  48         return PTR_ERR_OR_ZERO(mhdp->j721e_regs);
  49 }
  50
  51 static void cdns_mhdp_j721e_enable(struct cdns_mhdp_device *mhdp)
  52 {
  53         /*
  54          * Enable VIF_0 and select DPI2 as its input. DSS0 DPI0 is connected
  55          * to eDP DPI2. This is the only supported SST configuration on
  56          * J721E.
  57          */
  58         writel(DPTX_SRC_VIF_0_EN | DPTX_SRC_VIF_0_SEL_DPI2,
  59                mhdp->j721e_regs + DPTX_SRC_CFG);
  60 }
  61
  62 static void cdns_mhdp_j721e_disable(struct cdns_mhdp_device *mhdp)
  63 {
  64         /* Put everything to defaults  */
  65         writel(0, mhdp->j721e_regs + DPTX_DSC_CFG);
  66 }
  67
  68 const struct mhdp_platform_ops mhdp_ti_j721e_ops = {
  69         .init = cdns_mhdp_j721e_init,
  70         .enable = cdns_mhdp_j721e_enable,
  71         .disable = cdns_mhdp_j721e_disable,
  72 };
  73
  74 const struct drm_bridge_timings mhdp_ti_j721e_bridge_timings = {
  75         .input_bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
  76                            DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE |
  77                            DRM_BUS_FLAG_DE_HIGH,
  78 };