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Merge tag 'block-5.11-2021-01-10' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / gpu / drm / gma500 / cdv_intel_display.c
blob686385a66167ba49ff55028c97883dcb72faee61
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright © 2006-2011 Intel Corporation
4 *
5 * Authors:
6 * Eric Anholt <eric@anholt.net>
7 */
8
9 #include <linux/delay.h>
10 #include <linux/i2c.h>
11
12 #include <drm/drm_crtc.h>
13
14 #include "cdv_device.h"
15 #include "framebuffer.h"
16 #include "gma_display.h"
17 #include "power.h"
18 #include "psb_drv.h"
19 #include "psb_intel_drv.h"
20 #include "psb_intel_reg.h"
21
22 static bool cdv_intel_find_dp_pll(const struct gma_limit_t *limit,
23 struct drm_crtc *crtc, int target,
24 int refclk, struct gma_clock_t *best_clock);
25
26
27 #define CDV_LIMIT_SINGLE_LVDS_96 0
28 #define CDV_LIMIT_SINGLE_LVDS_100 1
29 #define CDV_LIMIT_DAC_HDMI_27 2
30 #define CDV_LIMIT_DAC_HDMI_96 3
31 #define CDV_LIMIT_DP_27 4
32 #define CDV_LIMIT_DP_100 5
33
34 static const struct gma_limit_t cdv_intel_limits[] = {
35 { /* CDV_SINGLE_LVDS_96MHz */
36 .dot = {.min = 20000, .max = 115500},
37 .vco = {.min = 1800000, .max = 3600000},
38 .n = {.min = 2, .max = 6},
39 .m = {.min = 60, .max = 160},
40 .m1 = {.min = 0, .max = 0},
41 .m2 = {.min = 58, .max = 158},
42 .p = {.min = 28, .max = 140},
43 .p1 = {.min = 2, .max = 10},
44 .p2 = {.dot_limit = 200000, .p2_slow = 14, .p2_fast = 14},
45 .find_pll = gma_find_best_pll,
46 },
47 { /* CDV_SINGLE_LVDS_100MHz */
48 .dot = {.min = 20000, .max = 115500},
49 .vco = {.min = 1800000, .max = 3600000},
50 .n = {.min = 2, .max = 6},
51 .m = {.min = 60, .max = 160},
52 .m1 = {.min = 0, .max = 0},
53 .m2 = {.min = 58, .max = 158},
54 .p = {.min = 28, .max = 140},
55 .p1 = {.min = 2, .max = 10},
56 /* The single-channel range is 25-112Mhz, and dual-channel
57 * is 80-224Mhz. Prefer single channel as much as possible.
58 */
59 .p2 = {.dot_limit = 200000, .p2_slow = 14, .p2_fast = 14},
60 .find_pll = gma_find_best_pll,
61 },
62 { /* CDV_DAC_HDMI_27MHz */
63 .dot = {.min = 20000, .max = 400000},
64 .vco = {.min = 1809000, .max = 3564000},
65 .n = {.min = 1, .max = 1},
66 .m = {.min = 67, .max = 132},
67 .m1 = {.min = 0, .max = 0},
68 .m2 = {.min = 65, .max = 130},
69 .p = {.min = 5, .max = 90},
70 .p1 = {.min = 1, .max = 9},
71 .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 5},
72 .find_pll = gma_find_best_pll,
73 },
74 { /* CDV_DAC_HDMI_96MHz */
75 .dot = {.min = 20000, .max = 400000},
76 .vco = {.min = 1800000, .max = 3600000},
77 .n = {.min = 2, .max = 6},
78 .m = {.min = 60, .max = 160},
79 .m1 = {.min = 0, .max = 0},
80 .m2 = {.min = 58, .max = 158},
81 .p = {.min = 5, .max = 100},
82 .p1 = {.min = 1, .max = 10},
83 .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 5},
84 .find_pll = gma_find_best_pll,
85 },
86 { /* CDV_DP_27MHz */
87 .dot = {.min = 160000, .max = 272000},
88 .vco = {.min = 1809000, .max = 3564000},
89 .n = {.min = 1, .max = 1},
90 .m = {.min = 67, .max = 132},
91 .m1 = {.min = 0, .max = 0},
92 .m2 = {.min = 65, .max = 130},
93 .p = {.min = 5, .max = 90},
94 .p1 = {.min = 1, .max = 9},
95 .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 10},
96 .find_pll = cdv_intel_find_dp_pll,
97 },
98 { /* CDV_DP_100MHz */
99 .dot = {.min = 160000, .max = 272000},
100 .vco = {.min = 1800000, .max = 3600000},
101 .n = {.min = 2, .max = 6},
102 .m = {.min = 60, .max = 164},
103 .m1 = {.min = 0, .max = 0},
104 .m2 = {.min = 58, .max = 162},
105 .p = {.min = 5, .max = 100},
106 .p1 = {.min = 1, .max = 10},
107 .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 10},
108 .find_pll = cdv_intel_find_dp_pll,
109 }
110 };
111
112 #define _wait_for(COND, MS, W) ({ \
113 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \
114 int ret__ = 0; \
115 while (!(COND)) { \
116 if (time_after(jiffies, timeout__)) { \
117 ret__ = -ETIMEDOUT; \
118 break; \
119 } \
120 if (W && !in_dbg_master()) \
121 msleep(W); \
122 } \
123 ret__; \
124 })
125
126 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
127
128
129 int cdv_sb_read(struct drm_device *dev, u32 reg, u32 *val)
130 {
131 int ret;
132
133 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
134 if (ret) {
135 DRM_ERROR("timeout waiting for SB to idle before read\n");
136 return ret;
137 }
138
139 REG_WRITE(SB_ADDR, reg);
140 REG_WRITE(SB_PCKT,
141 SET_FIELD(SB_OPCODE_READ, SB_OPCODE) |
142 SET_FIELD(SB_DEST_DPLL, SB_DEST) |
143 SET_FIELD(0xf, SB_BYTE_ENABLE));
144
145 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
146 if (ret) {
147 DRM_ERROR("timeout waiting for SB to idle after read\n");
148 return ret;
149 }
150
151 *val = REG_READ(SB_DATA);
152
153 return 0;
154 }
155
156 int cdv_sb_write(struct drm_device *dev, u32 reg, u32 val)
157 {
158 int ret;
159 static bool dpio_debug = true;
160 u32 temp;
161
162 if (dpio_debug) {
163 if (cdv_sb_read(dev, reg, &temp) == 0)
164 DRM_DEBUG_KMS("0x%08x: 0x%08x (before)\n", reg, temp);
165 DRM_DEBUG_KMS("0x%08x: 0x%08x\n", reg, val);
166 }
167
168 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
169 if (ret) {
170 DRM_ERROR("timeout waiting for SB to idle before write\n");
171 return ret;
172 }
173
174 REG_WRITE(SB_ADDR, reg);
175 REG_WRITE(SB_DATA, val);
176 REG_WRITE(SB_PCKT,
177 SET_FIELD(SB_OPCODE_WRITE, SB_OPCODE) |
178 SET_FIELD(SB_DEST_DPLL, SB_DEST) |
179 SET_FIELD(0xf, SB_BYTE_ENABLE));
180
181 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
182 if (ret) {
183 DRM_ERROR("timeout waiting for SB to idle after write\n");
184 return ret;
185 }
186
187 if (dpio_debug) {
188 if (cdv_sb_read(dev, reg, &temp) == 0)
189 DRM_DEBUG_KMS("0x%08x: 0x%08x (after)\n", reg, temp);
190 }
191
192 return 0;
193 }
194
195 /* Reset the DPIO configuration register. The BIOS does this at every
196 * mode set.
197 */
198 void cdv_sb_reset(struct drm_device *dev)
199 {
200
201 REG_WRITE(DPIO_CFG, 0);
202 REG_READ(DPIO_CFG);
203 REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 | DPIO_CMN_RESET_N);
204 }
205
206 /* Unlike most Intel display engines, on Cedarview the DPLL registers
207 * are behind this sideband bus. They must be programmed while the
208 * DPLL reference clock is on in the DPLL control register, but before
209 * the DPLL is enabled in the DPLL control register.
210 */
211 static int
212 cdv_dpll_set_clock_cdv(struct drm_device *dev, struct drm_crtc *crtc,
213 struct gma_clock_t *clock, bool is_lvds, u32 ddi_select)
214 {
215 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
216 int pipe = gma_crtc->pipe;
217 u32 m, n_vco, p;
218 int ret = 0;
219 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
220 int ref_sfr = (pipe == 0) ? SB_REF_DPLLA : SB_REF_DPLLB;
221 u32 ref_value;
222 u32 lane_reg, lane_value;
223
224 cdv_sb_reset(dev);
225
226 REG_WRITE(dpll_reg, DPLL_SYNCLOCK_ENABLE | DPLL_VGA_MODE_DIS);
227
228 udelay(100);
229
230 /* Follow the BIOS and write the REF/SFR Register. Hardcoded value */
231 ref_value = 0x68A701;
232
233 cdv_sb_write(dev, SB_REF_SFR(pipe), ref_value);
234
235 /* We don't know what the other fields of these regs are, so
236 * leave them in place.
237 */
238 /*
239 * The BIT 14:13 of 0x8010/0x8030 is used to select the ref clk
240 * for the pipe A/B. Display spec 1.06 has wrong definition.
241 * Correct definition is like below:
242 *
243 * refclka mean use clock from same PLL
244 *
245 * if DPLLA sets 01 and DPLLB sets 01, they use clock from their pll
246 *
247 * if DPLLA sets 01 and DPLLB sets 02, both use clk from DPLLA
248 *
249 */
250 ret = cdv_sb_read(dev, ref_sfr, &ref_value);
251 if (ret)
252 return ret;
253 ref_value &= ~(REF_CLK_MASK);
254
255 /* use DPLL_A for pipeB on CRT/HDMI */
256 if (pipe == 1 && !is_lvds && !(ddi_select & DP_MASK)) {
257 DRM_DEBUG_KMS("use DPLLA for pipe B\n");
258 ref_value |= REF_CLK_DPLLA;
259 } else {
260 DRM_DEBUG_KMS("use their DPLL for pipe A/B\n");
261 ref_value |= REF_CLK_DPLL;
262 }
263 ret = cdv_sb_write(dev, ref_sfr, ref_value);
264 if (ret)
265 return ret;
266
267 ret = cdv_sb_read(dev, SB_M(pipe), &m);
268 if (ret)
269 return ret;
270 m &= ~SB_M_DIVIDER_MASK;
271 m |= ((clock->m2) << SB_M_DIVIDER_SHIFT);
272 ret = cdv_sb_write(dev, SB_M(pipe), m);
273 if (ret)
274 return ret;
275
276 ret = cdv_sb_read(dev, SB_N_VCO(pipe), &n_vco);
277 if (ret)
278 return ret;
279
280 /* Follow the BIOS to program the N_DIVIDER REG */
281 n_vco &= 0xFFFF;
282 n_vco |= 0x107;
283 n_vco &= ~(SB_N_VCO_SEL_MASK |
284 SB_N_DIVIDER_MASK |
285 SB_N_CB_TUNE_MASK);
286
287 n_vco |= ((clock->n) << SB_N_DIVIDER_SHIFT);
288
289 if (clock->vco < 2250000) {
290 n_vco |= (2 << SB_N_CB_TUNE_SHIFT);
291 n_vco |= (0 << SB_N_VCO_SEL_SHIFT);
292 } else if (clock->vco < 2750000) {
293 n_vco |= (1 << SB_N_CB_TUNE_SHIFT);
294 n_vco |= (1 << SB_N_VCO_SEL_SHIFT);
295 } else if (clock->vco < 3300000) {
296 n_vco |= (0 << SB_N_CB_TUNE_SHIFT);
297 n_vco |= (2 << SB_N_VCO_SEL_SHIFT);
298 } else {
299 n_vco |= (0 << SB_N_CB_TUNE_SHIFT);
300 n_vco |= (3 << SB_N_VCO_SEL_SHIFT);
301 }
302
303 ret = cdv_sb_write(dev, SB_N_VCO(pipe), n_vco);
304 if (ret)
305 return ret;
306
307 ret = cdv_sb_read(dev, SB_P(pipe), &p);
308 if (ret)
309 return ret;
310 p &= ~(SB_P2_DIVIDER_MASK | SB_P1_DIVIDER_MASK);
311 p |= SET_FIELD(clock->p1, SB_P1_DIVIDER);
312 switch (clock->p2) {
313 case 5:
314 p |= SET_FIELD(SB_P2_5, SB_P2_DIVIDER);
315 break;
316 case 10:
317 p |= SET_FIELD(SB_P2_10, SB_P2_DIVIDER);
318 break;
319 case 14:
320 p |= SET_FIELD(SB_P2_14, SB_P2_DIVIDER);
321 break;
322 case 7:
323 p |= SET_FIELD(SB_P2_7, SB_P2_DIVIDER);
324 break;
325 default:
326 DRM_ERROR("Bad P2 clock: %d\n", clock->p2);
327 return -EINVAL;
328 }
329 ret = cdv_sb_write(dev, SB_P(pipe), p);
330 if (ret)
331 return ret;
332
333 if (ddi_select) {
334 if ((ddi_select & DDI_MASK) == DDI0_SELECT) {
335 lane_reg = PSB_LANE0;
336 cdv_sb_read(dev, lane_reg, &lane_value);
337 lane_value &= ~(LANE_PLL_MASK);
338 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
339 cdv_sb_write(dev, lane_reg, lane_value);
340
341 lane_reg = PSB_LANE1;
342 cdv_sb_read(dev, lane_reg, &lane_value);
343 lane_value &= ~(LANE_PLL_MASK);
344 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
345 cdv_sb_write(dev, lane_reg, lane_value);
346 } else {
347 lane_reg = PSB_LANE2;
348 cdv_sb_read(dev, lane_reg, &lane_value);
349 lane_value &= ~(LANE_PLL_MASK);
350 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
351 cdv_sb_write(dev, lane_reg, lane_value);
352
353 lane_reg = PSB_LANE3;
354 cdv_sb_read(dev, lane_reg, &lane_value);
355 lane_value &= ~(LANE_PLL_MASK);
356 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
357 cdv_sb_write(dev, lane_reg, lane_value);
358 }
359 }
360 return 0;
361 }
362
363 static const struct gma_limit_t *cdv_intel_limit(struct drm_crtc *crtc,
364 int refclk)
365 {
366 const struct gma_limit_t *limit;
367 if (gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
368 /*
369 * Now only single-channel LVDS is supported on CDV. If it is
370 * incorrect, please add the dual-channel LVDS.
371 */
372 if (refclk == 96000)
373 limit = &cdv_intel_limits[CDV_LIMIT_SINGLE_LVDS_96];
374 else
375 limit = &cdv_intel_limits[CDV_LIMIT_SINGLE_LVDS_100];
376 } else if (gma_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
377 gma_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
378 if (refclk == 27000)
379 limit = &cdv_intel_limits[CDV_LIMIT_DP_27];
380 else
381 limit = &cdv_intel_limits[CDV_LIMIT_DP_100];
382 } else {
383 if (refclk == 27000)
384 limit = &cdv_intel_limits[CDV_LIMIT_DAC_HDMI_27];
385 else
386 limit = &cdv_intel_limits[CDV_LIMIT_DAC_HDMI_96];
387 }
388 return limit;
389 }
390
391 /* m1 is reserved as 0 in CDV, n is a ring counter */
392 static void cdv_intel_clock(int refclk, struct gma_clock_t *clock)
393 {
394 clock->m = clock->m2 + 2;
395 clock->p = clock->p1 * clock->p2;
396 clock->vco = (refclk * clock->m) / clock->n;
397 clock->dot = clock->vco / clock->p;
398 }
399
400 static bool cdv_intel_find_dp_pll(const struct gma_limit_t *limit,
401 struct drm_crtc *crtc, int target,
402 int refclk,
403 struct gma_clock_t *best_clock)
404 {
405 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
406 struct gma_clock_t clock;
407
408 memset(&clock, 0, sizeof(clock));
409
410 switch (refclk) {
411 case 27000:
412 if (target < 200000) {
413 clock.p1 = 2;
414 clock.p2 = 10;
415 clock.n = 1;
416 clock.m1 = 0;
417 clock.m2 = 118;
418 } else {
419 clock.p1 = 1;
420 clock.p2 = 10;
421 clock.n = 1;
422 clock.m1 = 0;
423 clock.m2 = 98;
424 }
425 break;
426
427 case 100000:
428 if (target < 200000) {
429 clock.p1 = 2;
430 clock.p2 = 10;
431 clock.n = 5;
432 clock.m1 = 0;
433 clock.m2 = 160;
434 } else {
435 clock.p1 = 1;
436 clock.p2 = 10;
437 clock.n = 5;
438 clock.m1 = 0;
439 clock.m2 = 133;
440 }
441 break;
442
443 default:
444 return false;
445 }
446
447 gma_crtc->clock_funcs->clock(refclk, &clock);
448 memcpy(best_clock, &clock, sizeof(struct gma_clock_t));
449 return true;
450 }
451
452 #define FIFO_PIPEA (1 << 0)
453 #define FIFO_PIPEB (1 << 1)
454
455 static bool cdv_intel_pipe_enabled(struct drm_device *dev, int pipe)
456 {
457 struct drm_crtc *crtc;
458 struct drm_psb_private *dev_priv = dev->dev_private;
459 struct gma_crtc *gma_crtc = NULL;
460
461 crtc = dev_priv->pipe_to_crtc_mapping[pipe];
462 gma_crtc = to_gma_crtc(crtc);
463
464 if (crtc->primary->fb == NULL || !gma_crtc->active)
465 return false;
466 return true;
467 }
468
469 void cdv_disable_sr(struct drm_device *dev)
470 {
471 if (REG_READ(FW_BLC_SELF) & FW_BLC_SELF_EN) {
472
473 /* Disable self-refresh before adjust WM */
474 REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN));
475 REG_READ(FW_BLC_SELF);
476
477 gma_wait_for_vblank(dev);
478
479 /* Cedarview workaround to write ovelay plane, which force to leave
480 * MAX_FIFO state.
481 */
482 REG_WRITE(OV_OVADD, 0/*dev_priv->ovl_offset*/);
483 REG_READ(OV_OVADD);
484
485 gma_wait_for_vblank(dev);
486 }
487
488 }
489
490 void cdv_update_wm(struct drm_device *dev, struct drm_crtc *crtc)
491 {
492 struct drm_psb_private *dev_priv = dev->dev_private;
493 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
494
495 /* Is only one pipe enabled? */
496 if (cdv_intel_pipe_enabled(dev, 0) ^ cdv_intel_pipe_enabled(dev, 1)) {
497 u32 fw;
498
499 fw = REG_READ(DSPFW1);
500 fw &= ~DSP_FIFO_SR_WM_MASK;
501 fw |= (0x7e << DSP_FIFO_SR_WM_SHIFT);
502 fw &= ~CURSOR_B_FIFO_WM_MASK;
503 fw |= (0x4 << CURSOR_B_FIFO_WM_SHIFT);
504 REG_WRITE(DSPFW1, fw);
505
506 fw = REG_READ(DSPFW2);
507 fw &= ~CURSOR_A_FIFO_WM_MASK;
508 fw |= (0x6 << CURSOR_A_FIFO_WM_SHIFT);
509 fw &= ~DSP_PLANE_C_FIFO_WM_MASK;
510 fw |= (0x8 << DSP_PLANE_C_FIFO_WM_SHIFT);
511 REG_WRITE(DSPFW2, fw);
512
513 REG_WRITE(DSPFW3, 0x36000000);
514
515 /* ignore FW4 */
516
517 /* Is pipe b lvds ? */
518 if (gma_crtc->pipe == 1 &&
519 gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
520 REG_WRITE(DSPFW5, 0x00040330);
521 } else {
522 fw = (3 << DSP_PLANE_B_FIFO_WM1_SHIFT) |
523 (4 << DSP_PLANE_A_FIFO_WM1_SHIFT) |
524 (3 << CURSOR_B_FIFO_WM1_SHIFT) |
525 (4 << CURSOR_FIFO_SR_WM1_SHIFT);
526 REG_WRITE(DSPFW5, fw);
527 }
528
529 REG_WRITE(DSPFW6, 0x10);
530
531 gma_wait_for_vblank(dev);
532
533 /* enable self-refresh for single pipe active */
534 REG_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
535 REG_READ(FW_BLC_SELF);
536 gma_wait_for_vblank(dev);
537
538 } else {
539
540 /* HW team suggested values... */
541 REG_WRITE(DSPFW1, 0x3f880808);
542 REG_WRITE(DSPFW2, 0x0b020202);
543 REG_WRITE(DSPFW3, 0x24000000);
544 REG_WRITE(DSPFW4, 0x08030202);
545 REG_WRITE(DSPFW5, 0x01010101);
546 REG_WRITE(DSPFW6, 0x1d0);
547
548 gma_wait_for_vblank(dev);
549
550 dev_priv->ops->disable_sr(dev);
551 }
552 }
553
554 /**
555 * Return the pipe currently connected to the panel fitter,
556 * or -1 if the panel fitter is not present or not in use
557 */
558 static int cdv_intel_panel_fitter_pipe(struct drm_device *dev)
559 {
560 u32 pfit_control;
561
562 pfit_control = REG_READ(PFIT_CONTROL);
563
564 /* See if the panel fitter is in use */
565 if ((pfit_control & PFIT_ENABLE) == 0)
566 return -1;
567 return (pfit_control >> 29) & 0x3;
568 }
569
570 static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc,
571 struct drm_display_mode *mode,
572 struct drm_display_mode *adjusted_mode,
573 int x, int y,
574 struct drm_framebuffer *old_fb)
575 {
576 struct drm_device *dev = crtc->dev;
577 struct drm_psb_private *dev_priv = dev->dev_private;
578 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
579 int pipe = gma_crtc->pipe;
580 const struct psb_offset *map = &dev_priv->regmap[pipe];
581 int refclk;
582 struct gma_clock_t clock;
583 u32 dpll = 0, dspcntr, pipeconf;
584 bool ok;
585 bool is_lvds = false, is_tv = false;
586 bool is_dp = false;
587 struct drm_mode_config *mode_config = &dev->mode_config;
588 struct drm_connector *connector;
589 const struct gma_limit_t *limit;
590 u32 ddi_select = 0;
591 bool is_edp = false;
592
593 list_for_each_entry(connector, &mode_config->connector_list, head) {
594 struct gma_encoder *gma_encoder =
595 gma_attached_encoder(connector);
596
597 if (!connector->encoder
598 || connector->encoder->crtc != crtc)
599 continue;
600
601 ddi_select = gma_encoder->ddi_select;
602 switch (gma_encoder->type) {
603 case INTEL_OUTPUT_LVDS:
604 is_lvds = true;
605 break;
606 case INTEL_OUTPUT_TVOUT:
607 is_tv = true;
608 break;
609 case INTEL_OUTPUT_ANALOG:
610 case INTEL_OUTPUT_HDMI:
611 break;
612 case INTEL_OUTPUT_DISPLAYPORT:
613 is_dp = true;
614 break;
615 case INTEL_OUTPUT_EDP:
616 is_edp = true;
617 break;
618 default:
619 DRM_ERROR("invalid output type.\n");
620 return 0;
621 }
622 }
623
624 if (dev_priv->dplla_96mhz)
625 /* low-end sku, 96/100 mhz */
626 refclk = 96000;
627 else
628 /* high-end sku, 27/100 mhz */
629 refclk = 27000;
630 if (is_dp || is_edp) {
631 /*
632 * Based on the spec the low-end SKU has only CRT/LVDS. So it is
633 * unnecessary to consider it for DP/eDP.
634 * On the high-end SKU, it will use the 27/100M reference clk
635 * for DP/eDP. When using SSC clock, the ref clk is 100MHz.Otherwise
636 * it will be 27MHz. From the VBIOS code it seems that the pipe A choose
637 * 27MHz for DP/eDP while the Pipe B chooses the 100MHz.
638 */
639 if (pipe == 0)
640 refclk = 27000;
641 else
642 refclk = 100000;
643 }
644
645 if (is_lvds && dev_priv->lvds_use_ssc) {
646 refclk = dev_priv->lvds_ssc_freq * 1000;
647 DRM_DEBUG_KMS("Use SSC reference clock %d Mhz\n", dev_priv->lvds_ssc_freq);
648 }
649
650 drm_mode_debug_printmodeline(adjusted_mode);
651
652 limit = gma_crtc->clock_funcs->limit(crtc, refclk);
653
654 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk,
655 &clock);
656 if (!ok) {
657 DRM_ERROR("Couldn't find PLL settings for mode! target: %d, actual: %d",
658 adjusted_mode->clock, clock.dot);
659 return 0;
660 }
661
662 dpll = DPLL_VGA_MODE_DIS;
663 if (is_tv) {
664 /* XXX: just matching BIOS for now */
665 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
666 dpll |= 3;
667 }
668 /* dpll |= PLL_REF_INPUT_DREFCLK; */
669
670 if (is_dp || is_edp) {
671 cdv_intel_dp_set_m_n(crtc, mode, adjusted_mode);
672 } else {
673 REG_WRITE(PIPE_GMCH_DATA_M(pipe), 0);
674 REG_WRITE(PIPE_GMCH_DATA_N(pipe), 0);
675 REG_WRITE(PIPE_DP_LINK_M(pipe), 0);
676 REG_WRITE(PIPE_DP_LINK_N(pipe), 0);
677 }
678
679 dpll |= DPLL_SYNCLOCK_ENABLE;
680 /* if (is_lvds)
681 dpll |= DPLLB_MODE_LVDS;
682 else
683 dpll |= DPLLB_MODE_DAC_SERIAL; */
684 /* dpll |= (2 << 11); */
685
686 /* setup pipeconf */
687 pipeconf = REG_READ(map->conf);
688
689 pipeconf &= ~(PIPE_BPC_MASK);
690 if (is_edp) {
691 switch (dev_priv->edp.bpp) {
692 case 24:
693 pipeconf |= PIPE_8BPC;
694 break;
695 case 18:
696 pipeconf |= PIPE_6BPC;
697 break;
698 case 30:
699 pipeconf |= PIPE_10BPC;
700 break;
701 default:
702 pipeconf |= PIPE_8BPC;
703 break;
704 }
705 } else if (is_lvds) {
706 /* the BPC will be 6 if it is 18-bit LVDS panel */
707 if ((REG_READ(LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
708 pipeconf |= PIPE_8BPC;
709 else
710 pipeconf |= PIPE_6BPC;
711 } else
712 pipeconf |= PIPE_8BPC;
713
714 /* Set up the display plane register */
715 dspcntr = DISPPLANE_GAMMA_ENABLE;
716
717 if (pipe == 0)
718 dspcntr |= DISPPLANE_SEL_PIPE_A;
719 else
720 dspcntr |= DISPPLANE_SEL_PIPE_B;
721
722 dspcntr |= DISPLAY_PLANE_ENABLE;
723 pipeconf |= PIPEACONF_ENABLE;
724
725 REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE);
726 REG_READ(map->dpll);
727
728 cdv_dpll_set_clock_cdv(dev, crtc, &clock, is_lvds, ddi_select);
729
730 udelay(150);
731
732
733 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
734 * This is an exception to the general rule that mode_set doesn't turn
735 * things on.
736 */
737 if (is_lvds) {
738 u32 lvds = REG_READ(LVDS);
739
740 lvds |=
741 LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP |
742 LVDS_PIPEB_SELECT;
743 /* Set the B0-B3 data pairs corresponding to
744 * whether we're going to
745 * set the DPLLs for dual-channel mode or not.
746 */
747 if (clock.p2 == 7)
748 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
749 else
750 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
751
752 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
753 * appropriately here, but we need to look more
754 * thoroughly into how panels behave in the two modes.
755 */
756
757 REG_WRITE(LVDS, lvds);
758 REG_READ(LVDS);
759 }
760
761 dpll |= DPLL_VCO_ENABLE;
762
763 /* Disable the panel fitter if it was on our pipe */
764 if (cdv_intel_panel_fitter_pipe(dev) == pipe)
765 REG_WRITE(PFIT_CONTROL, 0);
766
767 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
768 drm_mode_debug_printmodeline(mode);
769
770 REG_WRITE(map->dpll,
771 (REG_READ(map->dpll) & ~DPLL_LOCK) | DPLL_VCO_ENABLE);
772 REG_READ(map->dpll);
773 /* Wait for the clocks to stabilize. */
774 udelay(150); /* 42 usec w/o calibration, 110 with. rounded up. */
775
776 if (!(REG_READ(map->dpll) & DPLL_LOCK)) {
777 dev_err(dev->dev, "Failed to get DPLL lock\n");
778 return -EBUSY;
779 }
780
781 {
782 int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
783 REG_WRITE(map->dpll_md, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
784 }
785
786 REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) |
787 ((adjusted_mode->crtc_htotal - 1) << 16));
788 REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) |
789 ((adjusted_mode->crtc_hblank_end - 1) << 16));
790 REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) |
791 ((adjusted_mode->crtc_hsync_end - 1) << 16));
792 REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) |
793 ((adjusted_mode->crtc_vtotal - 1) << 16));
794 REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) |
795 ((adjusted_mode->crtc_vblank_end - 1) << 16));
796 REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) |
797 ((adjusted_mode->crtc_vsync_end - 1) << 16));
798 /* pipesrc and dspsize control the size that is scaled from,
799 * which should always be the user's requested size.
800 */
801 REG_WRITE(map->size,
802 ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1));
803 REG_WRITE(map->pos, 0);
804 REG_WRITE(map->src,
805 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
806 REG_WRITE(map->conf, pipeconf);
807 REG_READ(map->conf);
808
809 gma_wait_for_vblank(dev);
810
811 REG_WRITE(map->cntr, dspcntr);
812
813 /* Flush the plane changes */
814 {
815 const struct drm_crtc_helper_funcs *crtc_funcs =
816 crtc->helper_private;
817 crtc_funcs->mode_set_base(crtc, x, y, old_fb);
818 }
819
820 gma_wait_for_vblank(dev);
821
822 return 0;
823 }
824
825 /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
826
827 /* FIXME: why are we using this, should it be cdv_ in this tree ? */
828
829 static void i8xx_clock(int refclk, struct gma_clock_t *clock)
830 {
831 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
832 clock->p = clock->p1 * clock->p2;
833 clock->vco = refclk * clock->m / (clock->n + 2);
834 clock->dot = clock->vco / clock->p;
835 }
836
837 /* Returns the clock of the currently programmed mode of the given pipe. */
838 static int cdv_intel_crtc_clock_get(struct drm_device *dev,
839 struct drm_crtc *crtc)
840 {
841 struct drm_psb_private *dev_priv = dev->dev_private;
842 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
843 int pipe = gma_crtc->pipe;
844 const struct psb_offset *map = &dev_priv->regmap[pipe];
845 u32 dpll;
846 u32 fp;
847 struct gma_clock_t clock;
848 bool is_lvds;
849 struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
850
851 if (gma_power_begin(dev, false)) {
852 dpll = REG_READ(map->dpll);
853 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
854 fp = REG_READ(map->fp0);
855 else
856 fp = REG_READ(map->fp1);
857 is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN);
858 gma_power_end(dev);
859 } else {
860 dpll = p->dpll;
861 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
862 fp = p->fp0;
863 else
864 fp = p->fp1;
865
866 is_lvds = (pipe == 1) &&
867 (dev_priv->regs.psb.saveLVDS & LVDS_PORT_EN);
868 }
869
870 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
871 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
872 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
873
874 if (is_lvds) {
875 clock.p1 =
876 ffs((dpll &
877 DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
878 DPLL_FPA01_P1_POST_DIV_SHIFT);
879 if (clock.p1 == 0) {
880 clock.p1 = 4;
881 dev_err(dev->dev, "PLL %d\n", dpll);
882 }
883 clock.p2 = 14;
884
885 if ((dpll & PLL_REF_INPUT_MASK) ==
886 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
887 /* XXX: might not be 66MHz */
888 i8xx_clock(66000, &clock);
889 } else
890 i8xx_clock(48000, &clock);
891 } else {
892 if (dpll & PLL_P1_DIVIDE_BY_TWO)
893 clock.p1 = 2;
894 else {
895 clock.p1 =
896 ((dpll &
897 DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
898 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
899 }
900 if (dpll & PLL_P2_DIVIDE_BY_4)
901 clock.p2 = 4;
902 else
903 clock.p2 = 2;
904
905 i8xx_clock(48000, &clock);
906 }
907
908 /* XXX: It would be nice to validate the clocks, but we can't reuse
909 * i830PllIsValid() because it relies on the xf86_config connector
910 * configuration being accurate, which it isn't necessarily.
911 */
912
913 return clock.dot;
914 }
915
916 /** Returns the currently programmed mode of the given pipe. */
917 struct drm_display_mode *cdv_intel_crtc_mode_get(struct drm_device *dev,
918 struct drm_crtc *crtc)
919 {
920 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
921 int pipe = gma_crtc->pipe;
922 struct drm_psb_private *dev_priv = dev->dev_private;
923 struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
924 const struct psb_offset *map = &dev_priv->regmap[pipe];
925 struct drm_display_mode *mode;
926 int htot;
927 int hsync;
928 int vtot;
929 int vsync;
930
931 if (gma_power_begin(dev, false)) {
932 htot = REG_READ(map->htotal);
933 hsync = REG_READ(map->hsync);
934 vtot = REG_READ(map->vtotal);
935 vsync = REG_READ(map->vsync);
936 gma_power_end(dev);
937 } else {
938 htot = p->htotal;
939 hsync = p->hsync;
940 vtot = p->vtotal;
941 vsync = p->vsync;
942 }
943
944 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
945 if (!mode)
946 return NULL;
947
948 mode->clock = cdv_intel_crtc_clock_get(dev, crtc);
949 mode->hdisplay = (htot & 0xffff) + 1;
950 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
951 mode->hsync_start = (hsync & 0xffff) + 1;
952 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
953 mode->vdisplay = (vtot & 0xffff) + 1;
954 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
955 mode->vsync_start = (vsync & 0xffff) + 1;
956 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
957
958 drm_mode_set_name(mode);
959 drm_mode_set_crtcinfo(mode, 0);
960
961 return mode;
962 }
963
964 const struct drm_crtc_helper_funcs cdv_intel_helper_funcs = {
965 .dpms = gma_crtc_dpms,
966 .mode_set = cdv_intel_crtc_mode_set,
967 .mode_set_base = gma_pipe_set_base,
968 .prepare = gma_crtc_prepare,
969 .commit = gma_crtc_commit,
970 .disable = gma_crtc_disable,
971 };
972
973 const struct drm_crtc_funcs cdv_intel_crtc_funcs = {
974 .cursor_set = gma_crtc_cursor_set,
975 .cursor_move = gma_crtc_cursor_move,
976 .gamma_set = gma_crtc_gamma_set,
977 .set_config = gma_crtc_set_config,
978 .destroy = gma_crtc_destroy,
979 .page_flip = gma_crtc_page_flip,
980 .enable_vblank = psb_enable_vblank,
981 .disable_vblank = psb_disable_vblank,
982 .get_vblank_counter = psb_get_vblank_counter,
983 };
984
985 const struct gma_clock_funcs cdv_clock_funcs = {
986 .clock = cdv_intel_clock,
987 .limit = cdv_intel_limit,
988 .pll_is_valid = gma_pll_is_valid,
989 };
Linux with added FPC-III support