drivers/gpu/drm/i915/gt/intel_mocs.c

   1 /*
   2  * Copyright (c) 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions: *
  10  * The above copyright notice and this permission notice (including the next
  11  * paragraph) shall be included in all copies or substantial portions of the
  12  * Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  19  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  */
  22
  23 #include "i915_drv.h"
  24
  25 #include "intel_engine.h"
  26 #include "intel_gt.h"
  27 #include "intel_mocs.h"
  28 #include "intel_lrc.h"
  29 #include "intel_ring.h"
  30
  31 /* structures required */
  32 struct drm_i915_mocs_entry {
  33         u32 control_value;
  34         u16 l3cc_value;
  35         u16 used;
  36 };
  37
  38 struct drm_i915_mocs_table {
  39         unsigned int size;
  40         unsigned int n_entries;
  41         const struct drm_i915_mocs_entry *table;
  42 };
  43
  44 /* Defines for the tables (XXX_MOCS_0 - XXX_MOCS_63) */
  45 #define _LE_CACHEABILITY(value) ((value) << 0)
  46 #define _LE_TGT_CACHE(value)    ((value) << 2)
  47 #define LE_LRUM(value)          ((value) << 4)
  48 #define LE_AOM(value)           ((value) << 6)
  49 #define LE_RSC(value)           ((value) << 7)
  50 #define LE_SCC(value)           ((value) << 8)
  51 #define LE_PFM(value)           ((value) << 11)
  52 #define LE_SCF(value)           ((value) << 14)
  53 #define LE_COS(value)           ((value) << 15)
  54 #define LE_SSE(value)           ((value) << 17)
  55
  56 /* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */
  57 #define L3_ESC(value)           ((value) << 0)
  58 #define L3_SCC(value)           ((value) << 1)
  59 #define _L3_CACHEABILITY(value) ((value) << 4)
  60
  61 /* Helper defines */
  62 #define GEN9_NUM_MOCS_ENTRIES   64  /* 63-64 are reserved, but configured. */
  63
  64 /* (e)LLC caching options */
  65 /*
  66  * Note: LE_0_PAGETABLE works only up to Gen11; for newer gens it means
  67  * the same as LE_UC
  68  */
  69 #define LE_0_PAGETABLE          _LE_CACHEABILITY(0)
  70 #define LE_1_UC                 _LE_CACHEABILITY(1)
  71 #define LE_2_WT                 _LE_CACHEABILITY(2)
  72 #define LE_3_WB                 _LE_CACHEABILITY(3)
  73
  74 /* Target cache */
  75 #define LE_TC_0_PAGETABLE       _LE_TGT_CACHE(0)
  76 #define LE_TC_1_LLC             _LE_TGT_CACHE(1)
  77 #define LE_TC_2_LLC_ELLC        _LE_TGT_CACHE(2)
  78 #define LE_TC_3_LLC_ELLC_ALT    _LE_TGT_CACHE(3)
  79
  80 /* L3 caching options */
  81 #define L3_0_DIRECT             _L3_CACHEABILITY(0)
  82 #define L3_1_UC                 _L3_CACHEABILITY(1)
  83 #define L3_2_RESERVED           _L3_CACHEABILITY(2)
  84 #define L3_3_WB                 _L3_CACHEABILITY(3)
  85
  86 #define MOCS_ENTRY(__idx, __control_value, __l3cc_value) \
  87         [__idx] = { \
  88                 .control_value = __control_value, \
  89                 .l3cc_value = __l3cc_value, \
  90                 .used = 1, \
  91         }
  92
  93 /*
  94  * MOCS tables
  95  *
  96  * These are the MOCS tables that are programmed across all the rings.
  97  * The control value is programmed to all the rings that support the
  98  * MOCS registers. While the l3cc_values are only programmed to the
  99  * LNCFCMOCS0 - LNCFCMOCS32 registers.
 100  *
 101  * These tables are intended to be kept reasonably consistent across
 102  * HW platforms, and for ICL+, be identical across OSes. To achieve
 103  * that, for Icelake and above, list of entries is published as part
 104  * of bspec.
 105  *
 106  * Entries not part of the following tables are undefined as far as
 107  * userspace is concerned and shouldn't be relied upon.  For Gen < 12
 108  * they will be initialized to PTE. Gen >= 12 onwards don't have a setting for
 109  * PTE and will be initialized to an invalid value.
 110  *
 111  * The last few entries are reserved by the hardware. For ICL+ they
 112  * should be initialized according to bspec and never used, for older
 113  * platforms they should never be written to.
 114  *
 115  * NOTE: These tables are part of bspec and defined as part of hardware
 116  *       interface for ICL+. For older platforms, they are part of kernel
 117  *       ABI. It is expected that, for specific hardware platform, existing
 118  *       entries will remain constant and the table will only be updated by
 119  *       adding new entries, filling unused positions.
 120  */
 121 #define GEN9_MOCS_ENTRIES \
 122         MOCS_ENTRY(I915_MOCS_UNCACHED, \
 123                    LE_1_UC | LE_TC_2_LLC_ELLC, \
 124                    L3_1_UC), \
 125         MOCS_ENTRY(I915_MOCS_PTE, \
 126                    LE_0_PAGETABLE | LE_TC_0_PAGETABLE | LE_LRUM(3), \
 127                    L3_3_WB)
 128
 129 static const struct drm_i915_mocs_entry skl_mocs_table[] = {
 130         GEN9_MOCS_ENTRIES,
 131         MOCS_ENTRY(I915_MOCS_CACHED,
 132                    LE_3_WB | LE_TC_2_LLC_ELLC | LE_LRUM(3),
 133                    L3_3_WB),
 134
 135         /*
 136          * mocs:63
 137          * - used by the L3 for all of its evictions.
 138          *   Thus it is expected to allow LLC cacheability to enable coherent
 139          *   flows to be maintained.
 140          * - used to force L3 uncachable cycles.
 141          *   Thus it is expected to make the surface L3 uncacheable.
 142          */
 143         MOCS_ENTRY(63,
 144                    LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
 145                    L3_1_UC)
 146 };
 147
 148 /* NOTE: the LE_TGT_CACHE is not used on Broxton */
 149 static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
 150         GEN9_MOCS_ENTRIES,
 151         MOCS_ENTRY(I915_MOCS_CACHED,
 152                    LE_1_UC | LE_TC_2_LLC_ELLC | LE_LRUM(3),
 153                    L3_3_WB)
 154 };
 155
 156 #define GEN11_MOCS_ENTRIES \
 157         /* Entries 0 and 1 are defined per-platform */ \
 158         /* Base - L3 + LLC */ \
 159         MOCS_ENTRY(2, \
 160                    LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
 161                    L3_3_WB), \
 162         /* Base - Uncached */ \
 163         MOCS_ENTRY(3, \
 164                    LE_1_UC | LE_TC_1_LLC, \
 165                    L3_1_UC), \
 166         /* Base - L3 */ \
 167         MOCS_ENTRY(4, \
 168                    LE_1_UC | LE_TC_1_LLC, \
 169                    L3_3_WB), \
 170         /* Base - LLC */ \
 171         MOCS_ENTRY(5, \
 172                    LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
 173                    L3_1_UC), \
 174         /* Age 0 - LLC */ \
 175         MOCS_ENTRY(6, \
 176                    LE_3_WB | LE_TC_1_LLC | LE_LRUM(1), \
 177                    L3_1_UC), \
 178         /* Age 0 - L3 + LLC */ \
 179         MOCS_ENTRY(7, \
 180                    LE_3_WB | LE_TC_1_LLC | LE_LRUM(1), \
 181                    L3_3_WB), \
 182         /* Age: Don't Chg. - LLC */ \
 183         MOCS_ENTRY(8, \
 184                    LE_3_WB | LE_TC_1_LLC | LE_LRUM(2), \
 185                    L3_1_UC), \
 186         /* Age: Don't Chg. - L3 + LLC */ \
 187         MOCS_ENTRY(9, \
 188                    LE_3_WB | LE_TC_1_LLC | LE_LRUM(2), \
 189                    L3_3_WB), \
 190         /* No AOM - LLC */ \
 191         MOCS_ENTRY(10, \
 192                    LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_AOM(1), \
 193                    L3_1_UC), \
 194         /* No AOM - L3 + LLC */ \
 195         MOCS_ENTRY(11, \
 196                    LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_AOM(1), \
 197                    L3_3_WB), \
 198         /* No AOM; Age 0 - LLC */ \
 199         MOCS_ENTRY(12, \
 200                    LE_3_WB | LE_TC_1_LLC | LE_LRUM(1) | LE_AOM(1), \
 201                    L3_1_UC), \
 202         /* No AOM; Age 0 - L3 + LLC */ \
 203         MOCS_ENTRY(13, \
 204                    LE_3_WB | LE_TC_1_LLC | LE_LRUM(1) | LE_AOM(1), \
 205                    L3_3_WB), \
 206         /* No AOM; Age:DC - LLC */ \
 207         MOCS_ENTRY(14, \
 208                    LE_3_WB | LE_TC_1_LLC | LE_LRUM(2) | LE_AOM(1), \
 209                    L3_1_UC), \
 210         /* No AOM; Age:DC - L3 + LLC */ \
 211         MOCS_ENTRY(15, \
 212                    LE_3_WB | LE_TC_1_LLC | LE_LRUM(2) | LE_AOM(1), \
 213                    L3_3_WB), \
 214         /* Self-Snoop - L3 + LLC */ \
 215         MOCS_ENTRY(18, \
 216                    LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SSE(3), \
 217                    L3_3_WB), \
 218         /* Skip Caching - L3 + LLC(12.5%) */ \
 219         MOCS_ENTRY(19, \
 220                    LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SCC(7), \
 221                    L3_3_WB), \
 222         /* Skip Caching - L3 + LLC(25%) */ \
 223         MOCS_ENTRY(20, \
 224                    LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SCC(3), \
 225                    L3_3_WB), \
 226         /* Skip Caching - L3 + LLC(50%) */ \
 227         MOCS_ENTRY(21, \
 228                    LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SCC(1), \
 229                    L3_3_WB), \
 230         /* Skip Caching - L3 + LLC(75%) */ \
 231         MOCS_ENTRY(22, \
 232                    LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_RSC(1) | LE_SCC(3), \
 233                    L3_3_WB), \
 234         /* Skip Caching - L3 + LLC(87.5%) */ \
 235         MOCS_ENTRY(23, \
 236                    LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_RSC(1) | LE_SCC(7), \
 237                    L3_3_WB), \
 238         /* HW Reserved - SW program but never use */ \
 239         MOCS_ENTRY(62, \
 240                    LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
 241                    L3_1_UC), \
 242         /* HW Reserved - SW program but never use */ \
 243         MOCS_ENTRY(63, \
 244                    LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
 245                    L3_1_UC)
 246
 247 static const struct drm_i915_mocs_entry tgl_mocs_table[] = {
 248         /*
 249          * NOTE:
 250          * Reserved and unspecified MOCS indices have been set to (L3 + LCC).
 251          * These reserved entries should never be used, they may be changed
 252          * to low performant variants with better coherency in the future if
 253          * more entries are needed. We are programming index I915_MOCS_PTE(1)
 254          * only, __init_mocs_table() take care to program unused index with
 255          * this entry.
 256          */
 257         MOCS_ENTRY(I915_MOCS_PTE,
 258                    LE_0_PAGETABLE | LE_TC_0_PAGETABLE,
 259                    L3_1_UC),
 260         GEN11_MOCS_ENTRIES,
 261
 262         /* Implicitly enable L1 - HDC:L1 + L3 + LLC */
 263         MOCS_ENTRY(48,
 264                    LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
 265                    L3_3_WB),
 266         /* Implicitly enable L1 - HDC:L1 + L3 */
 267         MOCS_ENTRY(49,
 268                    LE_1_UC | LE_TC_1_LLC,
 269                    L3_3_WB),
 270         /* Implicitly enable L1 - HDC:L1 + LLC */
 271         MOCS_ENTRY(50,
 272                    LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
 273                    L3_1_UC),
 274         /* Implicitly enable L1 - HDC:L1 */
 275         MOCS_ENTRY(51,
 276                    LE_1_UC | LE_TC_1_LLC,
 277                    L3_1_UC),
 278         /* HW Special Case (CCS) */
 279         MOCS_ENTRY(60,
 280                    LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
 281                    L3_1_UC),
 282         /* HW Special Case (Displayable) */
 283         MOCS_ENTRY(61,
 284                    LE_1_UC | LE_TC_1_LLC,
 285                    L3_3_WB),
 286 };
 287
 288 static const struct drm_i915_mocs_entry icl_mocs_table[] = {
 289         /* Base - Uncached (Deprecated) */
 290         MOCS_ENTRY(I915_MOCS_UNCACHED,
 291                    LE_1_UC | LE_TC_1_LLC,
 292                    L3_1_UC),
 293         /* Base - L3 + LeCC:PAT (Deprecated) */
 294         MOCS_ENTRY(I915_MOCS_PTE,
 295                    LE_0_PAGETABLE | LE_TC_0_PAGETABLE,
 296                    L3_3_WB),
 297
 298         GEN11_MOCS_ENTRIES
 299 };
 300
 301 static const struct drm_i915_mocs_entry dg1_mocs_table[] = {
 302         /* Error */
 303         MOCS_ENTRY(0, 0, L3_0_DIRECT),
 304
 305         /* UC */
 306         MOCS_ENTRY(1, 0, L3_1_UC),
 307
 308         /* Reserved */
 309         MOCS_ENTRY(2, 0, L3_0_DIRECT),
 310         MOCS_ENTRY(3, 0, L3_0_DIRECT),
 311         MOCS_ENTRY(4, 0, L3_0_DIRECT),
 312
 313         /* WB - L3 */
 314         MOCS_ENTRY(5, 0, L3_3_WB),
 315         /* WB - L3 50% */
 316         MOCS_ENTRY(6, 0, L3_ESC(1) | L3_SCC(1) | L3_3_WB),
 317         /* WB - L3 25% */
 318         MOCS_ENTRY(7, 0, L3_ESC(1) | L3_SCC(3) | L3_3_WB),
 319         /* WB - L3 12.5% */
 320         MOCS_ENTRY(8, 0, L3_ESC(1) | L3_SCC(7) | L3_3_WB),
 321
 322         /* HDC:L1 + L3 */
 323         MOCS_ENTRY(48, 0, L3_3_WB),
 324         /* HDC:L1 */
 325         MOCS_ENTRY(49, 0, L3_1_UC),
 326
 327         /* HW Reserved */
 328         MOCS_ENTRY(60, 0, L3_1_UC),
 329         MOCS_ENTRY(61, 0, L3_1_UC),
 330         MOCS_ENTRY(62, 0, L3_1_UC),
 331         MOCS_ENTRY(63, 0, L3_1_UC),
 332 };
 333
 334 enum {
 335         HAS_GLOBAL_MOCS = BIT(0),
 336         HAS_ENGINE_MOCS = BIT(1),
 337         HAS_RENDER_L3CC = BIT(2),
 338 };
 339
 340 static bool has_l3cc(const struct drm_i915_private *i915)
 341 {
 342         return true;
 343 }
 344
 345 static bool has_global_mocs(const struct drm_i915_private *i915)
 346 {
 347         return HAS_GLOBAL_MOCS_REGISTERS(i915);
 348 }
 349
 350 static bool has_mocs(const struct drm_i915_private *i915)
 351 {
 352         return !IS_DGFX(i915);
 353 }
 354
 355 static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
 356                                       struct drm_i915_mocs_table *table)
 357 {
 358         unsigned int flags;
 359
 360         if (IS_DG1(i915)) {
 361                 table->size = ARRAY_SIZE(dg1_mocs_table);
 362                 table->table = dg1_mocs_table;
 363                 table->n_entries = GEN9_NUM_MOCS_ENTRIES;
 364         } else if (INTEL_GEN(i915) >= 12) {
 365                 table->size  = ARRAY_SIZE(tgl_mocs_table);
 366                 table->table = tgl_mocs_table;
 367                 table->n_entries = GEN9_NUM_MOCS_ENTRIES;
 368         } else if (IS_GEN(i915, 11)) {
 369                 table->size  = ARRAY_SIZE(icl_mocs_table);
 370                 table->table = icl_mocs_table;
 371                 table->n_entries = GEN9_NUM_MOCS_ENTRIES;
 372         } else if (IS_GEN9_BC(i915) || IS_CANNONLAKE(i915)) {
 373                 table->size  = ARRAY_SIZE(skl_mocs_table);
 374                 table->n_entries = GEN9_NUM_MOCS_ENTRIES;
 375                 table->table = skl_mocs_table;
 376         } else if (IS_GEN9_LP(i915)) {
 377                 table->size  = ARRAY_SIZE(broxton_mocs_table);
 378                 table->n_entries = GEN9_NUM_MOCS_ENTRIES;
 379                 table->table = broxton_mocs_table;
 380         } else {
 381                 drm_WARN_ONCE(&i915->drm, INTEL_GEN(i915) >= 9,
 382                               "Platform that should have a MOCS table does not.\n");
 383                 return 0;
 384         }
 385
 386         if (GEM_DEBUG_WARN_ON(table->size > table->n_entries))
 387                 return 0;
 388
 389         /* WaDisableSkipCaching:skl,bxt,kbl,glk */
 390         if (IS_GEN(i915, 9)) {
 391                 int i;
 392
 393                 for (i = 0; i < table->size; i++)
 394                         if (GEM_DEBUG_WARN_ON(table->table[i].l3cc_value &
 395                                               (L3_ESC(1) | L3_SCC(0x7))))
 396                                 return 0;
 397         }
 398
 399         flags = 0;
 400         if (has_mocs(i915)) {
 401                 if (has_global_mocs(i915))
 402                         flags |= HAS_GLOBAL_MOCS;
 403                 else
 404                         flags |= HAS_ENGINE_MOCS;
 405         }
 406         if (has_l3cc(i915))
 407                 flags |= HAS_RENDER_L3CC;
 408
 409         return flags;
 410 }
 411
 412 /*
 413  * Get control_value from MOCS entry taking into account when it's not used:
 414  * I915_MOCS_PTE's value is returned in this case.
 415  */
 416 static u32 get_entry_control(const struct drm_i915_mocs_table *table,
 417                              unsigned int index)
 418 {
 419         if (index < table->size && table->table[index].used)
 420                 return table->table[index].control_value;
 421
 422         return table->table[I915_MOCS_PTE].control_value;
 423 }
 424
 425 #define for_each_mocs(mocs, t, i) \
 426         for (i = 0; \
 427              i < (t)->n_entries ? (mocs = get_entry_control((t), i)), 1 : 0;\
 428              i++)
 429
 430 static void __init_mocs_table(struct intel_uncore *uncore,
 431                               const struct drm_i915_mocs_table *table,
 432                               u32 addr)
 433 {
 434         unsigned int i;
 435         u32 mocs;
 436
 437         for_each_mocs(mocs, table, i)
 438                 intel_uncore_write_fw(uncore, _MMIO(addr + i * 4), mocs);
 439 }
 440
 441 static u32 mocs_offset(const struct intel_engine_cs *engine)
 442 {
 443         static const u32 offset[] = {
 444                 [RCS0]  =  __GEN9_RCS0_MOCS0,
 445                 [VCS0]  =  __GEN9_VCS0_MOCS0,
 446                 [VCS1]  =  __GEN9_VCS1_MOCS0,
 447                 [VECS0] =  __GEN9_VECS0_MOCS0,
 448                 [BCS0]  =  __GEN9_BCS0_MOCS0,
 449                 [VCS2]  = __GEN11_VCS2_MOCS0,
 450         };
 451
 452         GEM_BUG_ON(engine->id >= ARRAY_SIZE(offset));
 453         return offset[engine->id];
 454 }
 455
 456 static void init_mocs_table(struct intel_engine_cs *engine,
 457                             const struct drm_i915_mocs_table *table)
 458 {
 459         __init_mocs_table(engine->uncore, table, mocs_offset(engine));
 460 }
 461
 462 /*
 463  * Get l3cc_value from MOCS entry taking into account when it's not used:
 464  * I915_MOCS_PTE's value is returned in this case.
 465  */
 466 static u16 get_entry_l3cc(const struct drm_i915_mocs_table *table,
 467                           unsigned int index)
 468 {
 469         if (index < table->size && table->table[index].used)
 470                 return table->table[index].l3cc_value;
 471
 472         return table->table[I915_MOCS_PTE].l3cc_value;
 473 }
 474
 475 static inline u32 l3cc_combine(u16 low, u16 high)
 476 {
 477         return low | (u32)high << 16;
 478 }
 479
 480 #define for_each_l3cc(l3cc, t, i) \
 481         for (i = 0; \
 482              i < ((t)->n_entries + 1) / 2 ? \
 483              (l3cc = l3cc_combine(get_entry_l3cc((t), 2 * i), \
 484                                   get_entry_l3cc((t), 2 * i + 1))), 1 : \
 485              0; \
 486              i++)
 487
 488 static void init_l3cc_table(struct intel_engine_cs *engine,
 489                             const struct drm_i915_mocs_table *table)
 490 {
 491         struct intel_uncore *uncore = engine->uncore;
 492         unsigned int i;
 493         u32 l3cc;
 494
 495         for_each_l3cc(l3cc, table, i)
 496                 intel_uncore_write_fw(uncore, GEN9_LNCFCMOCS(i), l3cc);
 497 }
 498
 499 void intel_mocs_init_engine(struct intel_engine_cs *engine)
 500 {
 501         struct drm_i915_mocs_table table;
 502         unsigned int flags;
 503
 504         /* Called under a blanket forcewake */
 505         assert_forcewakes_active(engine->uncore, FORCEWAKE_ALL);
 506
 507         flags = get_mocs_settings(engine->i915, &table);
 508         if (!flags)
 509                 return;
 510
 511         /* Platforms with global MOCS do not need per-engine initialization. */
 512         if (flags & HAS_ENGINE_MOCS)
 513                 init_mocs_table(engine, &table);
 514
 515         if (flags & HAS_RENDER_L3CC && engine->class == RENDER_CLASS)
 516                 init_l3cc_table(engine, &table);
 517 }
 518
 519 static u32 global_mocs_offset(void)
 520 {
 521         return i915_mmio_reg_offset(GEN12_GLOBAL_MOCS(0));
 522 }
 523
 524 void intel_mocs_init(struct intel_gt *gt)
 525 {
 526         struct drm_i915_mocs_table table;
 527         unsigned int flags;
 528
 529         /*
 530          * LLC and eDRAM control values are not applicable to dgfx
 531          */
 532         flags = get_mocs_settings(gt->i915, &table);
 533         if (flags & HAS_GLOBAL_MOCS)
 534                 __init_mocs_table(gt->uncore, &table, global_mocs_offset());
 535 }
 536
 537 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
 538 #include "selftest_mocs.c"
 539 #endif