2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Eddie Dong <eddie.dong@intel.com>
25 * Jike Song <jike.song@intel.com>
28 * Zhi Wang <zhi.a.wang@intel.com>
29 * Min He <min.he@intel.com>
30 * Bing Niu <bing.niu@intel.com>
38 INTEL_GVT_PCI_BAR_GTTMMIO
= 0,
39 INTEL_GVT_PCI_BAR_APERTURE
,
40 INTEL_GVT_PCI_BAR_PIO
,
41 INTEL_GVT_PCI_BAR_MAX
,
44 /* bitmap for writable bits (RW or RW1C bits, but cannot co-exist in one
45 * byte) byte by byte in standard pci configuration space. (not the full
48 static const u8 pci_cfg_space_rw_bmp
[PCI_INTERRUPT_LINE
+ 4] = {
49 [PCI_COMMAND
] = 0xff, 0x07,
50 [PCI_STATUS
] = 0x00, 0xf9, /* the only one RW1C byte */
51 [PCI_CACHE_LINE_SIZE
] = 0xff,
52 [PCI_BASE_ADDRESS_0
... PCI_CARDBUS_CIS
- 1] = 0xff,
53 [PCI_ROM_ADDRESS
] = 0x01, 0xf8, 0xff, 0xff,
54 [PCI_INTERRUPT_LINE
] = 0xff,
58 * vgpu_pci_cfg_mem_write - write virtual cfg space memory
61 * @src: src ptr to write
62 * @bytes: number of bytes
64 * Use this function to write virtual cfg space memory.
65 * For standard cfg space, only RW bits can be changed,
66 * and we emulates the RW1C behavior of PCI_STATUS register.
68 static void vgpu_pci_cfg_mem_write(struct intel_vgpu
*vgpu
, unsigned int off
,
69 u8
*src
, unsigned int bytes
)
71 u8
*cfg_base
= vgpu_cfg_space(vgpu
);
76 for (; i
< bytes
&& (off
+ i
< sizeof(pci_cfg_space_rw_bmp
)); i
++) {
77 mask
= pci_cfg_space_rw_bmp
[off
+ i
];
78 old
= cfg_base
[off
+ i
];
82 * The PCI_STATUS high byte has RW1C bits, here
83 * emulates clear by writing 1 for these bits.
84 * Writing a 0b to RW1C bits has no effect.
86 if (off
+ i
== PCI_STATUS
+ 1)
87 new = (~new & old
) & mask
;
89 cfg_base
[off
+ i
] = (old
& ~mask
) | new;
92 /* For other configuration space directly copy as it is. */
94 memcpy(cfg_base
+ off
+ i
, src
+ i
, bytes
- i
);
96 if (off
== vgpu
->cfg_space
.pmcsr_off
&& vgpu
->cfg_space
.pmcsr_off
) {
97 pwr
= (pci_power_t __force
)(*(u16
*)(&vgpu_cfg_space(vgpu
)[off
])
98 & PCI_PM_CTRL_STATE_MASK
);
100 vgpu
->d3_entered
= true;
101 gvt_dbg_core("vgpu-%d power status changed to %d\n",
107 * intel_vgpu_emulate_cfg_read - emulate vGPU configuration space read
110 * @p_data: return data ptr
111 * @bytes: number of bytes to read
114 * Zero on success, negative error code if failed.
116 int intel_vgpu_emulate_cfg_read(struct intel_vgpu
*vgpu
, unsigned int offset
,
117 void *p_data
, unsigned int bytes
)
119 struct drm_i915_private
*i915
= vgpu
->gvt
->gt
->i915
;
121 if (drm_WARN_ON(&i915
->drm
, bytes
> 4))
124 if (drm_WARN_ON(&i915
->drm
,
125 offset
+ bytes
> vgpu
->gvt
->device_info
.cfg_space_size
))
128 memcpy(p_data
, vgpu_cfg_space(vgpu
) + offset
, bytes
);
132 static int map_aperture(struct intel_vgpu
*vgpu
, bool map
)
134 phys_addr_t aperture_pa
= vgpu_aperture_pa_base(vgpu
);
135 unsigned long aperture_sz
= vgpu_aperture_sz(vgpu
);
140 if (map
== vgpu
->cfg_space
.bar
[INTEL_GVT_PCI_BAR_APERTURE
].tracked
)
143 val
= vgpu_cfg_space(vgpu
)[PCI_BASE_ADDRESS_2
];
144 if (val
& PCI_BASE_ADDRESS_MEM_TYPE_64
)
145 val
= *(u64
*)(vgpu_cfg_space(vgpu
) + PCI_BASE_ADDRESS_2
);
147 val
= *(u32
*)(vgpu_cfg_space(vgpu
) + PCI_BASE_ADDRESS_2
);
149 first_gfn
= (val
+ vgpu_aperture_offset(vgpu
)) >> PAGE_SHIFT
;
151 ret
= intel_gvt_hypervisor_map_gfn_to_mfn(vgpu
, first_gfn
,
152 aperture_pa
>> PAGE_SHIFT
,
153 aperture_sz
>> PAGE_SHIFT
,
158 vgpu
->cfg_space
.bar
[INTEL_GVT_PCI_BAR_APERTURE
].tracked
= map
;
162 static int trap_gttmmio(struct intel_vgpu
*vgpu
, bool trap
)
168 if (trap
== vgpu
->cfg_space
.bar
[INTEL_GVT_PCI_BAR_GTTMMIO
].tracked
)
171 val
= vgpu_cfg_space(vgpu
)[PCI_BASE_ADDRESS_0
];
172 if (val
& PCI_BASE_ADDRESS_MEM_TYPE_64
)
173 start
= *(u64
*)(vgpu_cfg_space(vgpu
) + PCI_BASE_ADDRESS_0
);
175 start
= *(u32
*)(vgpu_cfg_space(vgpu
) + PCI_BASE_ADDRESS_0
);
177 start
&= ~GENMASK(3, 0);
178 end
= start
+ vgpu
->cfg_space
.bar
[INTEL_GVT_PCI_BAR_GTTMMIO
].size
- 1;
180 ret
= intel_gvt_hypervisor_set_trap_area(vgpu
, start
, end
, trap
);
184 vgpu
->cfg_space
.bar
[INTEL_GVT_PCI_BAR_GTTMMIO
].tracked
= trap
;
188 static int emulate_pci_command_write(struct intel_vgpu
*vgpu
,
189 unsigned int offset
, void *p_data
, unsigned int bytes
)
191 u8 old
= vgpu_cfg_space(vgpu
)[offset
];
192 u8
new = *(u8
*)p_data
;
193 u8 changed
= old
^ new;
196 vgpu_pci_cfg_mem_write(vgpu
, offset
, p_data
, bytes
);
197 if (!(changed
& PCI_COMMAND_MEMORY
))
200 if (old
& PCI_COMMAND_MEMORY
) {
201 ret
= trap_gttmmio(vgpu
, false);
204 ret
= map_aperture(vgpu
, false);
208 ret
= trap_gttmmio(vgpu
, true);
211 ret
= map_aperture(vgpu
, true);
219 static int emulate_pci_rom_bar_write(struct intel_vgpu
*vgpu
,
220 unsigned int offset
, void *p_data
, unsigned int bytes
)
222 u32
*pval
= (u32
*)(vgpu_cfg_space(vgpu
) + offset
);
223 u32
new = *(u32
*)(p_data
);
225 if ((new & PCI_ROM_ADDRESS_MASK
) == PCI_ROM_ADDRESS_MASK
)
226 /* We don't have rom, return size of 0. */
229 vgpu_pci_cfg_mem_write(vgpu
, offset
, p_data
, bytes
);
233 static int emulate_pci_bar_write(struct intel_vgpu
*vgpu
, unsigned int offset
,
234 void *p_data
, unsigned int bytes
)
236 u32
new = *(u32
*)(p_data
);
237 bool lo
= IS_ALIGNED(offset
, 8);
241 vgpu_cfg_space(vgpu
)[PCI_COMMAND
] & PCI_COMMAND_MEMORY
;
242 struct intel_vgpu_pci_bar
*bars
= vgpu
->cfg_space
.bar
;
245 * Power-up software can determine how much address
246 * space the device requires by writing a value of
247 * all 1's to the register and then reading the value
248 * back. The device will return 0's in all don't-care
251 if (new == 0xffffffff) {
253 case PCI_BASE_ADDRESS_0
:
254 case PCI_BASE_ADDRESS_1
:
255 size
= ~(bars
[INTEL_GVT_PCI_BAR_GTTMMIO
].size
-1);
256 intel_vgpu_write_pci_bar(vgpu
, offset
,
257 size
>> (lo
? 0 : 32), lo
);
259 * Untrap the BAR, since guest hasn't configured a
262 ret
= trap_gttmmio(vgpu
, false);
264 case PCI_BASE_ADDRESS_2
:
265 case PCI_BASE_ADDRESS_3
:
266 size
= ~(bars
[INTEL_GVT_PCI_BAR_APERTURE
].size
-1);
267 intel_vgpu_write_pci_bar(vgpu
, offset
,
268 size
>> (lo
? 0 : 32), lo
);
269 ret
= map_aperture(vgpu
, false);
272 /* Unimplemented BARs */
273 intel_vgpu_write_pci_bar(vgpu
, offset
, 0x0, false);
277 case PCI_BASE_ADDRESS_0
:
278 case PCI_BASE_ADDRESS_1
:
280 * Untrap the old BAR first, since guest has
281 * re-configured the BAR
283 trap_gttmmio(vgpu
, false);
284 intel_vgpu_write_pci_bar(vgpu
, offset
, new, lo
);
285 ret
= trap_gttmmio(vgpu
, mmio_enabled
);
287 case PCI_BASE_ADDRESS_2
:
288 case PCI_BASE_ADDRESS_3
:
289 map_aperture(vgpu
, false);
290 intel_vgpu_write_pci_bar(vgpu
, offset
, new, lo
);
291 ret
= map_aperture(vgpu
, mmio_enabled
);
294 intel_vgpu_write_pci_bar(vgpu
, offset
, new, lo
);
301 * intel_vgpu_emulate_cfg_read - emulate vGPU configuration space write
304 * @p_data: write data ptr
305 * @bytes: number of bytes to write
308 * Zero on success, negative error code if failed.
310 int intel_vgpu_emulate_cfg_write(struct intel_vgpu
*vgpu
, unsigned int offset
,
311 void *p_data
, unsigned int bytes
)
313 struct drm_i915_private
*i915
= vgpu
->gvt
->gt
->i915
;
316 if (drm_WARN_ON(&i915
->drm
, bytes
> 4))
319 if (drm_WARN_ON(&i915
->drm
,
320 offset
+ bytes
> vgpu
->gvt
->device_info
.cfg_space_size
))
323 /* First check if it's PCI_COMMAND */
324 if (IS_ALIGNED(offset
, 2) && offset
== PCI_COMMAND
) {
325 if (drm_WARN_ON(&i915
->drm
, bytes
> 2))
327 return emulate_pci_command_write(vgpu
, offset
, p_data
, bytes
);
330 switch (rounddown(offset
, 4)) {
331 case PCI_ROM_ADDRESS
:
332 if (drm_WARN_ON(&i915
->drm
, !IS_ALIGNED(offset
, 4)))
334 return emulate_pci_rom_bar_write(vgpu
, offset
, p_data
, bytes
);
336 case PCI_BASE_ADDRESS_0
... PCI_BASE_ADDRESS_5
:
337 if (drm_WARN_ON(&i915
->drm
, !IS_ALIGNED(offset
, 4)))
339 return emulate_pci_bar_write(vgpu
, offset
, p_data
, bytes
);
341 case INTEL_GVT_PCI_SWSCI
:
342 if (drm_WARN_ON(&i915
->drm
, !IS_ALIGNED(offset
, 4)))
344 ret
= intel_vgpu_emulate_opregion_request(vgpu
, *(u32
*)p_data
);
349 case INTEL_GVT_PCI_OPREGION
:
350 if (drm_WARN_ON(&i915
->drm
, !IS_ALIGNED(offset
, 4)))
352 ret
= intel_vgpu_opregion_base_write_handler(vgpu
,
357 vgpu_pci_cfg_mem_write(vgpu
, offset
, p_data
, bytes
);
360 vgpu_pci_cfg_mem_write(vgpu
, offset
, p_data
, bytes
);
367 * intel_vgpu_init_cfg_space - init vGPU configuration space when create vGPU
370 * @primary: is the vGPU presented as primary
373 void intel_vgpu_init_cfg_space(struct intel_vgpu
*vgpu
,
376 struct intel_gvt
*gvt
= vgpu
->gvt
;
377 const struct intel_gvt_device_info
*info
= &gvt
->device_info
;
381 memcpy(vgpu_cfg_space(vgpu
), gvt
->firmware
.cfg_space
,
382 info
->cfg_space_size
);
385 vgpu_cfg_space(vgpu
)[PCI_CLASS_DEVICE
] =
386 INTEL_GVT_PCI_CLASS_VGA_OTHER
;
387 vgpu_cfg_space(vgpu
)[PCI_CLASS_PROG
] =
388 INTEL_GVT_PCI_CLASS_VGA_OTHER
;
391 /* Show guest that there isn't any stolen memory.*/
392 gmch_ctl
= (u16
*)(vgpu_cfg_space(vgpu
) + INTEL_GVT_PCI_GMCH_CONTROL
);
393 *gmch_ctl
&= ~(BDW_GMCH_GMS_MASK
<< BDW_GMCH_GMS_SHIFT
);
395 intel_vgpu_write_pci_bar(vgpu
, PCI_BASE_ADDRESS_2
,
396 gvt_aperture_pa_base(gvt
), true);
398 vgpu_cfg_space(vgpu
)[PCI_COMMAND
] &= ~(PCI_COMMAND_IO
400 | PCI_COMMAND_MASTER
);
402 * Clear the bar upper 32bit and let guest to assign the new value
404 memset(vgpu_cfg_space(vgpu
) + PCI_BASE_ADDRESS_1
, 0, 4);
405 memset(vgpu_cfg_space(vgpu
) + PCI_BASE_ADDRESS_3
, 0, 4);
406 memset(vgpu_cfg_space(vgpu
) + PCI_BASE_ADDRESS_4
, 0, 8);
407 memset(vgpu_cfg_space(vgpu
) + INTEL_GVT_PCI_OPREGION
, 0, 4);
409 vgpu
->cfg_space
.bar
[INTEL_GVT_PCI_BAR_GTTMMIO
].size
=
410 pci_resource_len(gvt
->gt
->i915
->drm
.pdev
, 0);
411 vgpu
->cfg_space
.bar
[INTEL_GVT_PCI_BAR_APERTURE
].size
=
412 pci_resource_len(gvt
->gt
->i915
->drm
.pdev
, 2);
414 memset(vgpu_cfg_space(vgpu
) + PCI_ROM_ADDRESS
, 0, 4);
417 vgpu
->cfg_space
.pmcsr_off
= 0;
418 if (vgpu_cfg_space(vgpu
)[PCI_STATUS
] & PCI_STATUS_CAP_LIST
) {
419 next
= vgpu_cfg_space(vgpu
)[PCI_CAPABILITY_LIST
];
421 if (vgpu_cfg_space(vgpu
)[next
+ PCI_CAP_LIST_ID
] == PCI_CAP_ID_PM
) {
422 vgpu
->cfg_space
.pmcsr_off
= next
+ PCI_PM_CTRL
;
425 next
= vgpu_cfg_space(vgpu
)[next
+ PCI_CAP_LIST_NEXT
];
431 * intel_vgpu_reset_cfg_space - reset vGPU configuration space
436 void intel_vgpu_reset_cfg_space(struct intel_vgpu
*vgpu
)
438 u8 cmd
= vgpu_cfg_space(vgpu
)[PCI_COMMAND
];
439 bool primary
= vgpu_cfg_space(vgpu
)[PCI_CLASS_DEVICE
] !=
440 INTEL_GVT_PCI_CLASS_VGA_OTHER
;
442 if (cmd
& PCI_COMMAND_MEMORY
) {
443 trap_gttmmio(vgpu
, false);
444 map_aperture(vgpu
, false);
448 * Currently we only do such reset when vGPU is not
449 * owned by any VM, so we simply restore entire cfg
450 * space to default value.
452 intel_vgpu_init_cfg_space(vgpu
, primary
);