drivers/gpu/drm/i915/i915_pci.c

   1 /*
   2  * Copyright © 2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <linux/console.h>
  26 #include <linux/vga_switcheroo.h>
  27
  28 #include <drm/drm_drv.h>
  29 #include <drm/i915_pciids.h>
  30
  31 #include "display/intel_fbdev.h"
  32
  33 #include "i915_drv.h"
  34 #include "i915_perf.h"
  35 #include "i915_globals.h"
  36 #include "i915_selftest.h"
  37
  38 #define PLATFORM(x) .platform = (x)
  39 #define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1)
  40
  41 #define I845_PIPE_OFFSETS \
  42         .pipe_offsets = { \
  43                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  44         }, \
  45         .trans_offsets = { \
  46                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  47         }
  48
  49 #define I9XX_PIPE_OFFSETS \
  50         .pipe_offsets = { \
  51                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  52                 [TRANSCODER_B] = PIPE_B_OFFSET, \
  53         }, \
  54         .trans_offsets = { \
  55                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  56                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
  57         }
  58
  59 #define IVB_PIPE_OFFSETS \
  60         .pipe_offsets = { \
  61                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  62                 [TRANSCODER_B] = PIPE_B_OFFSET, \
  63                 [TRANSCODER_C] = PIPE_C_OFFSET, \
  64         }, \
  65         .trans_offsets = { \
  66                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  67                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
  68                 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
  69         }
  70
  71 #define HSW_PIPE_OFFSETS \
  72         .pipe_offsets = { \
  73                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  74                 [TRANSCODER_B] = PIPE_B_OFFSET, \
  75                 [TRANSCODER_C] = PIPE_C_OFFSET, \
  76                 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
  77         }, \
  78         .trans_offsets = { \
  79                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  80                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
  81                 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
  82                 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
  83         }
  84
  85 #define CHV_PIPE_OFFSETS \
  86         .pipe_offsets = { \
  87                 [TRANSCODER_A] = PIPE_A_OFFSET, \
  88                 [TRANSCODER_B] = PIPE_B_OFFSET, \
  89                 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
  90         }, \
  91         .trans_offsets = { \
  92                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
  93                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
  94                 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
  95         }
  96
  97 #define I845_CURSOR_OFFSETS \
  98         .cursor_offsets = { \
  99                 [PIPE_A] = CURSOR_A_OFFSET, \
 100         }
 101
 102 #define I9XX_CURSOR_OFFSETS \
 103         .cursor_offsets = { \
 104                 [PIPE_A] = CURSOR_A_OFFSET, \
 105                 [PIPE_B] = CURSOR_B_OFFSET, \
 106         }
 107
 108 #define CHV_CURSOR_OFFSETS \
 109         .cursor_offsets = { \
 110                 [PIPE_A] = CURSOR_A_OFFSET, \
 111                 [PIPE_B] = CURSOR_B_OFFSET, \
 112                 [PIPE_C] = CHV_CURSOR_C_OFFSET, \
 113         }
 114
 115 #define IVB_CURSOR_OFFSETS \
 116         .cursor_offsets = { \
 117                 [PIPE_A] = CURSOR_A_OFFSET, \
 118                 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
 119                 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
 120         }
 121
 122 #define TGL_CURSOR_OFFSETS \
 123         .cursor_offsets = { \
 124                 [PIPE_A] = CURSOR_A_OFFSET, \
 125                 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
 126                 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
 127                 [PIPE_D] = TGL_CURSOR_D_OFFSET, \
 128         }
 129
 130 #define I9XX_COLORS \
 131         .color = { .gamma_lut_size = 256 }
 132 #define I965_COLORS \
 133         .color = { .gamma_lut_size = 129, \
 134                    .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
 135         }
 136 #define ILK_COLORS \
 137         .color = { .gamma_lut_size = 1024 }
 138 #define IVB_COLORS \
 139         .color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
 140 #define CHV_COLORS \
 141         .color = { .degamma_lut_size = 65, .gamma_lut_size = 257, \
 142                    .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
 143                    .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
 144         }
 145 #define GLK_COLORS \
 146         .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024, \
 147                    .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
 148                                         DRM_COLOR_LUT_EQUAL_CHANNELS, \
 149         }
 150
 151 /* Keep in gen based order, and chronological order within a gen */
 152
 153 #define GEN_DEFAULT_PAGE_SIZES \
 154         .page_sizes = I915_GTT_PAGE_SIZE_4K
 155
 156 #define GEN_DEFAULT_REGIONS \
 157         .memory_regions = REGION_SMEM | REGION_STOLEN
 158
 159 #define I830_FEATURES \
 160         GEN(2), \
 161         .is_mobile = 1, \
 162         .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
 163         .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
 164         .display.has_overlay = 1, \
 165         .display.cursor_needs_physical = 1, \
 166         .display.overlay_needs_physical = 1, \
 167         .display.has_gmch = 1, \
 168         .gpu_reset_clobbers_display = true, \
 169         .hws_needs_physical = 1, \
 170         .unfenced_needs_alignment = 1, \
 171         .platform_engine_mask = BIT(RCS0), \
 172         .has_snoop = true, \
 173         .has_coherent_ggtt = false, \
 174         .dma_mask_size = 32, \
 175         I9XX_PIPE_OFFSETS, \
 176         I9XX_CURSOR_OFFSETS, \
 177         I9XX_COLORS, \
 178         GEN_DEFAULT_PAGE_SIZES, \
 179         GEN_DEFAULT_REGIONS
 180
 181 #define I845_FEATURES \
 182         GEN(2), \
 183         .pipe_mask = BIT(PIPE_A), \
 184         .cpu_transcoder_mask = BIT(TRANSCODER_A), \
 185         .display.has_overlay = 1, \
 186         .display.overlay_needs_physical = 1, \
 187         .display.has_gmch = 1, \
 188         .gpu_reset_clobbers_display = true, \
 189         .hws_needs_physical = 1, \
 190         .unfenced_needs_alignment = 1, \
 191         .platform_engine_mask = BIT(RCS0), \
 192         .has_snoop = true, \
 193         .has_coherent_ggtt = false, \
 194         .dma_mask_size = 32, \
 195         I845_PIPE_OFFSETS, \
 196         I845_CURSOR_OFFSETS, \
 197         I9XX_COLORS, \
 198         GEN_DEFAULT_PAGE_SIZES, \
 199         GEN_DEFAULT_REGIONS
 200
 201 static const struct intel_device_info i830_info = {
 202         I830_FEATURES,
 203         PLATFORM(INTEL_I830),
 204 };
 205
 206 static const struct intel_device_info i845g_info = {
 207         I845_FEATURES,
 208         PLATFORM(INTEL_I845G),
 209 };
 210
 211 static const struct intel_device_info i85x_info = {
 212         I830_FEATURES,
 213         PLATFORM(INTEL_I85X),
 214         .display.has_fbc = 1,
 215 };
 216
 217 static const struct intel_device_info i865g_info = {
 218         I845_FEATURES,
 219         PLATFORM(INTEL_I865G),
 220         .display.has_fbc = 1,
 221 };
 222
 223 #define GEN3_FEATURES \
 224         GEN(3), \
 225         .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
 226         .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
 227         .display.has_gmch = 1, \
 228         .gpu_reset_clobbers_display = true, \
 229         .platform_engine_mask = BIT(RCS0), \
 230         .has_snoop = true, \
 231         .has_coherent_ggtt = true, \
 232         .dma_mask_size = 32, \
 233         I9XX_PIPE_OFFSETS, \
 234         I9XX_CURSOR_OFFSETS, \
 235         I9XX_COLORS, \
 236         GEN_DEFAULT_PAGE_SIZES, \
 237         GEN_DEFAULT_REGIONS
 238
 239 static const struct intel_device_info i915g_info = {
 240         GEN3_FEATURES,
 241         PLATFORM(INTEL_I915G),
 242         .has_coherent_ggtt = false,
 243         .display.cursor_needs_physical = 1,
 244         .display.has_overlay = 1,
 245         .display.overlay_needs_physical = 1,
 246         .hws_needs_physical = 1,
 247         .unfenced_needs_alignment = 1,
 248 };
 249
 250 static const struct intel_device_info i915gm_info = {
 251         GEN3_FEATURES,
 252         PLATFORM(INTEL_I915GM),
 253         .is_mobile = 1,
 254         .display.cursor_needs_physical = 1,
 255         .display.has_overlay = 1,
 256         .display.overlay_needs_physical = 1,
 257         .display.supports_tv = 1,
 258         .display.has_fbc = 1,
 259         .hws_needs_physical = 1,
 260         .unfenced_needs_alignment = 1,
 261 };
 262
 263 static const struct intel_device_info i945g_info = {
 264         GEN3_FEATURES,
 265         PLATFORM(INTEL_I945G),
 266         .display.has_hotplug = 1,
 267         .display.cursor_needs_physical = 1,
 268         .display.has_overlay = 1,
 269         .display.overlay_needs_physical = 1,
 270         .hws_needs_physical = 1,
 271         .unfenced_needs_alignment = 1,
 272 };
 273
 274 static const struct intel_device_info i945gm_info = {
 275         GEN3_FEATURES,
 276         PLATFORM(INTEL_I945GM),
 277         .is_mobile = 1,
 278         .display.has_hotplug = 1,
 279         .display.cursor_needs_physical = 1,
 280         .display.has_overlay = 1,
 281         .display.overlay_needs_physical = 1,
 282         .display.supports_tv = 1,
 283         .display.has_fbc = 1,
 284         .hws_needs_physical = 1,
 285         .unfenced_needs_alignment = 1,
 286 };
 287
 288 static const struct intel_device_info g33_info = {
 289         GEN3_FEATURES,
 290         PLATFORM(INTEL_G33),
 291         .display.has_hotplug = 1,
 292         .display.has_overlay = 1,
 293         .dma_mask_size = 36,
 294 };
 295
 296 static const struct intel_device_info pnv_g_info = {
 297         GEN3_FEATURES,
 298         PLATFORM(INTEL_PINEVIEW),
 299         .display.has_hotplug = 1,
 300         .display.has_overlay = 1,
 301         .dma_mask_size = 36,
 302 };
 303
 304 static const struct intel_device_info pnv_m_info = {
 305         GEN3_FEATURES,
 306         PLATFORM(INTEL_PINEVIEW),
 307         .is_mobile = 1,
 308         .display.has_hotplug = 1,
 309         .display.has_overlay = 1,
 310         .dma_mask_size = 36,
 311 };
 312
 313 #define GEN4_FEATURES \
 314         GEN(4), \
 315         .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
 316         .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
 317         .display.has_hotplug = 1, \
 318         .display.has_gmch = 1, \
 319         .gpu_reset_clobbers_display = true, \
 320         .platform_engine_mask = BIT(RCS0), \
 321         .has_snoop = true, \
 322         .has_coherent_ggtt = true, \
 323         .dma_mask_size = 36, \
 324         I9XX_PIPE_OFFSETS, \
 325         I9XX_CURSOR_OFFSETS, \
 326         I965_COLORS, \
 327         GEN_DEFAULT_PAGE_SIZES, \
 328         GEN_DEFAULT_REGIONS
 329
 330 static const struct intel_device_info i965g_info = {
 331         GEN4_FEATURES,
 332         PLATFORM(INTEL_I965G),
 333         .display.has_overlay = 1,
 334         .hws_needs_physical = 1,
 335         .has_snoop = false,
 336 };
 337
 338 static const struct intel_device_info i965gm_info = {
 339         GEN4_FEATURES,
 340         PLATFORM(INTEL_I965GM),
 341         .is_mobile = 1,
 342         .display.has_fbc = 1,
 343         .display.has_overlay = 1,
 344         .display.supports_tv = 1,
 345         .hws_needs_physical = 1,
 346         .has_snoop = false,
 347 };
 348
 349 static const struct intel_device_info g45_info = {
 350         GEN4_FEATURES,
 351         PLATFORM(INTEL_G45),
 352         .platform_engine_mask = BIT(RCS0) | BIT(VCS0),
 353         .gpu_reset_clobbers_display = false,
 354 };
 355
 356 static const struct intel_device_info gm45_info = {
 357         GEN4_FEATURES,
 358         PLATFORM(INTEL_GM45),
 359         .is_mobile = 1,
 360         .display.has_fbc = 1,
 361         .display.supports_tv = 1,
 362         .platform_engine_mask = BIT(RCS0) | BIT(VCS0),
 363         .gpu_reset_clobbers_display = false,
 364 };
 365
 366 #define GEN5_FEATURES \
 367         GEN(5), \
 368         .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
 369         .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
 370         .display.has_hotplug = 1, \
 371         .platform_engine_mask = BIT(RCS0) | BIT(VCS0), \
 372         .has_snoop = true, \
 373         .has_coherent_ggtt = true, \
 374         /* ilk does support rc6, but we do not implement [power] contexts */ \
 375         .has_rc6 = 0, \
 376         .dma_mask_size = 36, \
 377         I9XX_PIPE_OFFSETS, \
 378         I9XX_CURSOR_OFFSETS, \
 379         ILK_COLORS, \
 380         GEN_DEFAULT_PAGE_SIZES, \
 381         GEN_DEFAULT_REGIONS
 382
 383 static const struct intel_device_info ilk_d_info = {
 384         GEN5_FEATURES,
 385         PLATFORM(INTEL_IRONLAKE),
 386 };
 387
 388 static const struct intel_device_info ilk_m_info = {
 389         GEN5_FEATURES,
 390         PLATFORM(INTEL_IRONLAKE),
 391         .is_mobile = 1,
 392         .has_rps = true,
 393         .display.has_fbc = 1,
 394 };
 395
 396 #define GEN6_FEATURES \
 397         GEN(6), \
 398         .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
 399         .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
 400         .display.has_hotplug = 1, \
 401         .display.has_fbc = 1, \
 402         .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
 403         .has_coherent_ggtt = true, \
 404         .has_llc = 1, \
 405         .has_rc6 = 1, \
 406         .has_rc6p = 1, \
 407         .has_rps = true, \
 408         .dma_mask_size = 40, \
 409         .ppgtt_type = INTEL_PPGTT_ALIASING, \
 410         .ppgtt_size = 31, \
 411         I9XX_PIPE_OFFSETS, \
 412         I9XX_CURSOR_OFFSETS, \
 413         ILK_COLORS, \
 414         GEN_DEFAULT_PAGE_SIZES, \
 415         GEN_DEFAULT_REGIONS
 416
 417 #define SNB_D_PLATFORM \
 418         GEN6_FEATURES, \
 419         PLATFORM(INTEL_SANDYBRIDGE)
 420
 421 static const struct intel_device_info snb_d_gt1_info = {
 422         SNB_D_PLATFORM,
 423         .gt = 1,
 424 };
 425
 426 static const struct intel_device_info snb_d_gt2_info = {
 427         SNB_D_PLATFORM,
 428         .gt = 2,
 429 };
 430
 431 #define SNB_M_PLATFORM \
 432         GEN6_FEATURES, \
 433         PLATFORM(INTEL_SANDYBRIDGE), \
 434         .is_mobile = 1
 435
 436
 437 static const struct intel_device_info snb_m_gt1_info = {
 438         SNB_M_PLATFORM,
 439         .gt = 1,
 440 };
 441
 442 static const struct intel_device_info snb_m_gt2_info = {
 443         SNB_M_PLATFORM,
 444         .gt = 2,
 445 };
 446
 447 #define GEN7_FEATURES  \
 448         GEN(7), \
 449         .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
 450         .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \
 451         .display.has_hotplug = 1, \
 452         .display.has_fbc = 1, \
 453         .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
 454         .has_coherent_ggtt = true, \
 455         .has_llc = 1, \
 456         .has_rc6 = 1, \
 457         .has_rc6p = 1, \
 458         .has_rps = true, \
 459         .dma_mask_size = 40, \
 460         .ppgtt_type = INTEL_PPGTT_ALIASING, \
 461         .ppgtt_size = 31, \
 462         IVB_PIPE_OFFSETS, \
 463         IVB_CURSOR_OFFSETS, \
 464         IVB_COLORS, \
 465         GEN_DEFAULT_PAGE_SIZES, \
 466         GEN_DEFAULT_REGIONS
 467
 468 #define IVB_D_PLATFORM \
 469         GEN7_FEATURES, \
 470         PLATFORM(INTEL_IVYBRIDGE), \
 471         .has_l3_dpf = 1
 472
 473 static const struct intel_device_info ivb_d_gt1_info = {
 474         IVB_D_PLATFORM,
 475         .gt = 1,
 476 };
 477
 478 static const struct intel_device_info ivb_d_gt2_info = {
 479         IVB_D_PLATFORM,
 480         .gt = 2,
 481 };
 482
 483 #define IVB_M_PLATFORM \
 484         GEN7_FEATURES, \
 485         PLATFORM(INTEL_IVYBRIDGE), \
 486         .is_mobile = 1, \
 487         .has_l3_dpf = 1
 488
 489 static const struct intel_device_info ivb_m_gt1_info = {
 490         IVB_M_PLATFORM,
 491         .gt = 1,
 492 };
 493
 494 static const struct intel_device_info ivb_m_gt2_info = {
 495         IVB_M_PLATFORM,
 496         .gt = 2,
 497 };
 498
 499 static const struct intel_device_info ivb_q_info = {
 500         GEN7_FEATURES,
 501         PLATFORM(INTEL_IVYBRIDGE),
 502         .gt = 2,
 503         .pipe_mask = 0, /* legal, last one wins */
 504         .cpu_transcoder_mask = 0,
 505         .has_l3_dpf = 1,
 506 };
 507
 508 static const struct intel_device_info vlv_info = {
 509         PLATFORM(INTEL_VALLEYVIEW),
 510         GEN(7),
 511         .is_lp = 1,
 512         .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
 513         .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
 514         .has_runtime_pm = 1,
 515         .has_rc6 = 1,
 516         .has_rps = true,
 517         .display.has_gmch = 1,
 518         .display.has_hotplug = 1,
 519         .dma_mask_size = 40,
 520         .ppgtt_type = INTEL_PPGTT_ALIASING,
 521         .ppgtt_size = 31,
 522         .has_snoop = true,
 523         .has_coherent_ggtt = false,
 524         .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
 525         .display_mmio_offset = VLV_DISPLAY_BASE,
 526         I9XX_PIPE_OFFSETS,
 527         I9XX_CURSOR_OFFSETS,
 528         I965_COLORS,
 529         GEN_DEFAULT_PAGE_SIZES,
 530         GEN_DEFAULT_REGIONS,
 531 };
 532
 533 #define G75_FEATURES  \
 534         GEN7_FEATURES, \
 535         .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
 536         .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
 537                 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \
 538         .display.has_ddi = 1, \
 539         .has_fpga_dbg = 1, \
 540         .display.has_psr = 1, \
 541         .display.has_psr_hw_tracking = 1, \
 542         .display.has_dp_mst = 1, \
 543         .has_rc6p = 0 /* RC6p removed-by HSW */, \
 544         HSW_PIPE_OFFSETS, \
 545         .has_runtime_pm = 1
 546
 547 #define HSW_PLATFORM \
 548         G75_FEATURES, \
 549         PLATFORM(INTEL_HASWELL), \
 550         .has_l3_dpf = 1
 551
 552 static const struct intel_device_info hsw_gt1_info = {
 553         HSW_PLATFORM,
 554         .gt = 1,
 555 };
 556
 557 static const struct intel_device_info hsw_gt2_info = {
 558         HSW_PLATFORM,
 559         .gt = 2,
 560 };
 561
 562 static const struct intel_device_info hsw_gt3_info = {
 563         HSW_PLATFORM,
 564         .gt = 3,
 565 };
 566
 567 #define GEN8_FEATURES \
 568         G75_FEATURES, \
 569         GEN(8), \
 570         .has_logical_ring_contexts = 1, \
 571         .dma_mask_size = 39, \
 572         .ppgtt_type = INTEL_PPGTT_FULL, \
 573         .ppgtt_size = 48, \
 574         .has_64bit_reloc = 1, \
 575         .has_reset_engine = 1
 576
 577 #define BDW_PLATFORM \
 578         GEN8_FEATURES, \
 579         PLATFORM(INTEL_BROADWELL)
 580
 581 static const struct intel_device_info bdw_gt1_info = {
 582         BDW_PLATFORM,
 583         .gt = 1,
 584 };
 585
 586 static const struct intel_device_info bdw_gt2_info = {
 587         BDW_PLATFORM,
 588         .gt = 2,
 589 };
 590
 591 static const struct intel_device_info bdw_rsvd_info = {
 592         BDW_PLATFORM,
 593         .gt = 3,
 594         /* According to the device ID those devices are GT3, they were
 595          * previously treated as not GT3, keep it like that.
 596          */
 597 };
 598
 599 static const struct intel_device_info bdw_gt3_info = {
 600         BDW_PLATFORM,
 601         .gt = 3,
 602         .platform_engine_mask =
 603                 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
 604 };
 605
 606 static const struct intel_device_info chv_info = {
 607         PLATFORM(INTEL_CHERRYVIEW),
 608         GEN(8),
 609         .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
 610         .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
 611         .display.has_hotplug = 1,
 612         .is_lp = 1,
 613         .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
 614         .has_64bit_reloc = 1,
 615         .has_runtime_pm = 1,
 616         .has_rc6 = 1,
 617         .has_rps = true,
 618         .has_logical_ring_contexts = 1,
 619         .display.has_gmch = 1,
 620         .dma_mask_size = 39,
 621         .ppgtt_type = INTEL_PPGTT_FULL,
 622         .ppgtt_size = 32,
 623         .has_reset_engine = 1,
 624         .has_snoop = true,
 625         .has_coherent_ggtt = false,
 626         .display_mmio_offset = VLV_DISPLAY_BASE,
 627         CHV_PIPE_OFFSETS,
 628         CHV_CURSOR_OFFSETS,
 629         CHV_COLORS,
 630         GEN_DEFAULT_PAGE_SIZES,
 631         GEN_DEFAULT_REGIONS,
 632 };
 633
 634 #define GEN9_DEFAULT_PAGE_SIZES \
 635         .page_sizes = I915_GTT_PAGE_SIZE_4K | \
 636                       I915_GTT_PAGE_SIZE_64K
 637
 638 #define GEN9_FEATURES \
 639         GEN8_FEATURES, \
 640         GEN(9), \
 641         GEN9_DEFAULT_PAGE_SIZES, \
 642         .has_logical_ring_preemption = 1, \
 643         .display.has_csr = 1, \
 644         .has_gt_uc = 1, \
 645         .display.has_hdcp = 1, \
 646         .display.has_ipc = 1, \
 647         .ddb_size = 896, \
 648         .num_supported_dbuf_slices = 1
 649
 650 #define SKL_PLATFORM \
 651         GEN9_FEATURES, \
 652         PLATFORM(INTEL_SKYLAKE)
 653
 654 static const struct intel_device_info skl_gt1_info = {
 655         SKL_PLATFORM,
 656         .gt = 1,
 657 };
 658
 659 static const struct intel_device_info skl_gt2_info = {
 660         SKL_PLATFORM,
 661         .gt = 2,
 662 };
 663
 664 #define SKL_GT3_PLUS_PLATFORM \
 665         SKL_PLATFORM, \
 666         .platform_engine_mask = \
 667                 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
 668
 669
 670 static const struct intel_device_info skl_gt3_info = {
 671         SKL_GT3_PLUS_PLATFORM,
 672         .gt = 3,
 673 };
 674
 675 static const struct intel_device_info skl_gt4_info = {
 676         SKL_GT3_PLUS_PLATFORM,
 677         .gt = 4,
 678 };
 679
 680 #define GEN9_LP_FEATURES \
 681         GEN(9), \
 682         .is_lp = 1, \
 683         .num_supported_dbuf_slices = 1, \
 684         .display.has_hotplug = 1, \
 685         .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
 686         .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
 687         .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
 688                 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
 689                 BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \
 690         .has_64bit_reloc = 1, \
 691         .display.has_ddi = 1, \
 692         .has_fpga_dbg = 1, \
 693         .display.has_fbc = 1, \
 694         .display.has_hdcp = 1, \
 695         .display.has_psr = 1, \
 696         .display.has_psr_hw_tracking = 1, \
 697         .has_runtime_pm = 1, \
 698         .display.has_csr = 1, \
 699         .has_rc6 = 1, \
 700         .has_rps = true, \
 701         .display.has_dp_mst = 1, \
 702         .has_logical_ring_contexts = 1, \
 703         .has_logical_ring_preemption = 1, \
 704         .has_gt_uc = 1, \
 705         .dma_mask_size = 39, \
 706         .ppgtt_type = INTEL_PPGTT_FULL, \
 707         .ppgtt_size = 48, \
 708         .has_reset_engine = 1, \
 709         .has_snoop = true, \
 710         .has_coherent_ggtt = false, \
 711         .display.has_ipc = 1, \
 712         HSW_PIPE_OFFSETS, \
 713         IVB_CURSOR_OFFSETS, \
 714         IVB_COLORS, \
 715         GEN9_DEFAULT_PAGE_SIZES, \
 716         GEN_DEFAULT_REGIONS
 717
 718 static const struct intel_device_info bxt_info = {
 719         GEN9_LP_FEATURES,
 720         PLATFORM(INTEL_BROXTON),
 721         .ddb_size = 512,
 722 };
 723
 724 static const struct intel_device_info glk_info = {
 725         GEN9_LP_FEATURES,
 726         PLATFORM(INTEL_GEMINILAKE),
 727         .ddb_size = 1024,
 728         GLK_COLORS,
 729 };
 730
 731 #define KBL_PLATFORM \
 732         GEN9_FEATURES, \
 733         PLATFORM(INTEL_KABYLAKE)
 734
 735 static const struct intel_device_info kbl_gt1_info = {
 736         KBL_PLATFORM,
 737         .gt = 1,
 738 };
 739
 740 static const struct intel_device_info kbl_gt2_info = {
 741         KBL_PLATFORM,
 742         .gt = 2,
 743 };
 744
 745 static const struct intel_device_info kbl_gt3_info = {
 746         KBL_PLATFORM,
 747         .gt = 3,
 748         .platform_engine_mask =
 749                 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
 750 };
 751
 752 #define CFL_PLATFORM \
 753         GEN9_FEATURES, \
 754         PLATFORM(INTEL_COFFEELAKE)
 755
 756 static const struct intel_device_info cfl_gt1_info = {
 757         CFL_PLATFORM,
 758         .gt = 1,
 759 };
 760
 761 static const struct intel_device_info cfl_gt2_info = {
 762         CFL_PLATFORM,
 763         .gt = 2,
 764 };
 765
 766 static const struct intel_device_info cfl_gt3_info = {
 767         CFL_PLATFORM,
 768         .gt = 3,
 769         .platform_engine_mask =
 770                 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
 771 };
 772
 773 #define CML_PLATFORM \
 774         GEN9_FEATURES, \
 775         PLATFORM(INTEL_COMETLAKE)
 776
 777 static const struct intel_device_info cml_gt1_info = {
 778         CML_PLATFORM,
 779         .gt = 1,
 780 };
 781
 782 static const struct intel_device_info cml_gt2_info = {
 783         CML_PLATFORM,
 784         .gt = 2,
 785 };
 786
 787 #define GEN10_FEATURES \
 788         GEN9_FEATURES, \
 789         GEN(10), \
 790         .ddb_size = 1024, \
 791         .display.has_dsc = 1, \
 792         .has_coherent_ggtt = false, \
 793         GLK_COLORS
 794
 795 static const struct intel_device_info cnl_info = {
 796         GEN10_FEATURES,
 797         PLATFORM(INTEL_CANNONLAKE),
 798         .gt = 2,
 799 };
 800
 801 #define GEN11_DEFAULT_PAGE_SIZES \
 802         .page_sizes = I915_GTT_PAGE_SIZE_4K | \
 803                       I915_GTT_PAGE_SIZE_64K | \
 804                       I915_GTT_PAGE_SIZE_2M
 805
 806 #define GEN11_FEATURES \
 807         GEN10_FEATURES, \
 808         GEN11_DEFAULT_PAGE_SIZES, \
 809         .abox_mask = BIT(0), \
 810         .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
 811                 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
 812                 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
 813         .pipe_offsets = { \
 814                 [TRANSCODER_A] = PIPE_A_OFFSET, \
 815                 [TRANSCODER_B] = PIPE_B_OFFSET, \
 816                 [TRANSCODER_C] = PIPE_C_OFFSET, \
 817                 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
 818                 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
 819                 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
 820         }, \
 821         .trans_offsets = { \
 822                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
 823                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
 824                 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
 825                 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
 826                 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
 827                 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
 828         }, \
 829         GEN(11), \
 830         .ddb_size = 2048, \
 831         .num_supported_dbuf_slices = 2, \
 832         .has_logical_ring_elsq = 1, \
 833         .color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 }
 834
 835 static const struct intel_device_info icl_info = {
 836         GEN11_FEATURES,
 837         PLATFORM(INTEL_ICELAKE),
 838         .platform_engine_mask =
 839                 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
 840 };
 841
 842 static const struct intel_device_info ehl_info = {
 843         GEN11_FEATURES,
 844         PLATFORM(INTEL_ELKHARTLAKE),
 845         .require_force_probe = 1,
 846         .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
 847         .ppgtt_size = 36,
 848 };
 849
 850 static const struct intel_device_info jsl_info = {
 851         GEN11_FEATURES,
 852         PLATFORM(INTEL_JASPERLAKE),
 853         .require_force_probe = 1,
 854         .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
 855         .ppgtt_size = 36,
 856 };
 857
 858 #define GEN12_FEATURES \
 859         GEN11_FEATURES, \
 860         GEN(12), \
 861         .abox_mask = GENMASK(2, 1), \
 862         .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
 863         .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
 864                 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
 865                 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
 866         .pipe_offsets = { \
 867                 [TRANSCODER_A] = PIPE_A_OFFSET, \
 868                 [TRANSCODER_B] = PIPE_B_OFFSET, \
 869                 [TRANSCODER_C] = PIPE_C_OFFSET, \
 870                 [TRANSCODER_D] = PIPE_D_OFFSET, \
 871                 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
 872                 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
 873         }, \
 874         .trans_offsets = { \
 875                 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
 876                 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
 877                 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
 878                 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
 879                 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
 880                 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
 881         }, \
 882         TGL_CURSOR_OFFSETS, \
 883         .has_global_mocs = 1, \
 884         .display.has_dsb = 1
 885
 886 static const struct intel_device_info tgl_info = {
 887         GEN12_FEATURES,
 888         PLATFORM(INTEL_TIGERLAKE),
 889         .display.has_modular_fia = 1,
 890         .platform_engine_mask =
 891                 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
 892 };
 893
 894 static const struct intel_device_info rkl_info = {
 895         GEN12_FEATURES,
 896         PLATFORM(INTEL_ROCKETLAKE),
 897         .abox_mask = BIT(0),
 898         .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
 899         .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
 900                 BIT(TRANSCODER_C),
 901         .require_force_probe = 1,
 902         .display.has_hti = 1,
 903         .display.has_psr_hw_tracking = 0,
 904         .platform_engine_mask =
 905                 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
 906 };
 907
 908 #define GEN12_DGFX_FEATURES \
 909         GEN12_FEATURES, \
 910         .memory_regions = REGION_SMEM | REGION_LMEM, \
 911         .has_master_unit_irq = 1, \
 912         .has_llc = 0, \
 913         .has_snoop = 1, \
 914         .is_dgfx = 1
 915
 916 static const struct intel_device_info dg1_info __maybe_unused = {
 917         GEN12_DGFX_FEATURES,
 918         PLATFORM(INTEL_DG1),
 919         .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
 920         .require_force_probe = 1,
 921         .platform_engine_mask =
 922                 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
 923                 BIT(VCS0) | BIT(VCS2),
 924         /* Wa_16011227922 */
 925         .ppgtt_size = 47,
 926 };
 927
 928 #undef GEN
 929 #undef PLATFORM
 930
 931 /*
 932  * Make sure any device matches here are from most specific to most
 933  * general.  For example, since the Quanta match is based on the subsystem
 934  * and subvendor IDs, we need it to come before the more general IVB
 935  * PCI ID matches, otherwise we'll use the wrong info struct above.
 936  */
 937 static const struct pci_device_id pciidlist[] = {
 938         INTEL_I830_IDS(&i830_info),
 939         INTEL_I845G_IDS(&i845g_info),
 940         INTEL_I85X_IDS(&i85x_info),
 941         INTEL_I865G_IDS(&i865g_info),
 942         INTEL_I915G_IDS(&i915g_info),
 943         INTEL_I915GM_IDS(&i915gm_info),
 944         INTEL_I945G_IDS(&i945g_info),
 945         INTEL_I945GM_IDS(&i945gm_info),
 946         INTEL_I965G_IDS(&i965g_info),
 947         INTEL_G33_IDS(&g33_info),
 948         INTEL_I965GM_IDS(&i965gm_info),
 949         INTEL_GM45_IDS(&gm45_info),
 950         INTEL_G45_IDS(&g45_info),
 951         INTEL_PINEVIEW_G_IDS(&pnv_g_info),
 952         INTEL_PINEVIEW_M_IDS(&pnv_m_info),
 953         INTEL_IRONLAKE_D_IDS(&ilk_d_info),
 954         INTEL_IRONLAKE_M_IDS(&ilk_m_info),
 955         INTEL_SNB_D_GT1_IDS(&snb_d_gt1_info),
 956         INTEL_SNB_D_GT2_IDS(&snb_d_gt2_info),
 957         INTEL_SNB_M_GT1_IDS(&snb_m_gt1_info),
 958         INTEL_SNB_M_GT2_IDS(&snb_m_gt2_info),
 959         INTEL_IVB_Q_IDS(&ivb_q_info), /* must be first IVB */
 960         INTEL_IVB_M_GT1_IDS(&ivb_m_gt1_info),
 961         INTEL_IVB_M_GT2_IDS(&ivb_m_gt2_info),
 962         INTEL_IVB_D_GT1_IDS(&ivb_d_gt1_info),
 963         INTEL_IVB_D_GT2_IDS(&ivb_d_gt2_info),
 964         INTEL_HSW_GT1_IDS(&hsw_gt1_info),
 965         INTEL_HSW_GT2_IDS(&hsw_gt2_info),
 966         INTEL_HSW_GT3_IDS(&hsw_gt3_info),
 967         INTEL_VLV_IDS(&vlv_info),
 968         INTEL_BDW_GT1_IDS(&bdw_gt1_info),
 969         INTEL_BDW_GT2_IDS(&bdw_gt2_info),
 970         INTEL_BDW_GT3_IDS(&bdw_gt3_info),
 971         INTEL_BDW_RSVD_IDS(&bdw_rsvd_info),
 972         INTEL_CHV_IDS(&chv_info),
 973         INTEL_SKL_GT1_IDS(&skl_gt1_info),
 974         INTEL_SKL_GT2_IDS(&skl_gt2_info),
 975         INTEL_SKL_GT3_IDS(&skl_gt3_info),
 976         INTEL_SKL_GT4_IDS(&skl_gt4_info),
 977         INTEL_BXT_IDS(&bxt_info),
 978         INTEL_GLK_IDS(&glk_info),
 979         INTEL_KBL_GT1_IDS(&kbl_gt1_info),
 980         INTEL_KBL_GT2_IDS(&kbl_gt2_info),
 981         INTEL_KBL_GT3_IDS(&kbl_gt3_info),
 982         INTEL_KBL_GT4_IDS(&kbl_gt3_info),
 983         INTEL_AML_KBL_GT2_IDS(&kbl_gt2_info),
 984         INTEL_CFL_S_GT1_IDS(&cfl_gt1_info),
 985         INTEL_CFL_S_GT2_IDS(&cfl_gt2_info),
 986         INTEL_CFL_H_GT1_IDS(&cfl_gt1_info),
 987         INTEL_CFL_H_GT2_IDS(&cfl_gt2_info),
 988         INTEL_CFL_U_GT2_IDS(&cfl_gt2_info),
 989         INTEL_CFL_U_GT3_IDS(&cfl_gt3_info),
 990         INTEL_WHL_U_GT1_IDS(&cfl_gt1_info),
 991         INTEL_WHL_U_GT2_IDS(&cfl_gt2_info),
 992         INTEL_AML_CFL_GT2_IDS(&cfl_gt2_info),
 993         INTEL_WHL_U_GT3_IDS(&cfl_gt3_info),
 994         INTEL_CML_GT1_IDS(&cml_gt1_info),
 995         INTEL_CML_GT2_IDS(&cml_gt2_info),
 996         INTEL_CML_U_GT1_IDS(&cml_gt1_info),
 997         INTEL_CML_U_GT2_IDS(&cml_gt2_info),
 998         INTEL_CNL_IDS(&cnl_info),
 999         INTEL_ICL_11_IDS(&icl_info),
1000         INTEL_EHL_IDS(&ehl_info),
1001         INTEL_JSL_IDS(&jsl_info),
1002         INTEL_TGL_12_IDS(&tgl_info),
1003         INTEL_RKL_IDS(&rkl_info),
1004         {0, 0, 0}
1005 };
1006 MODULE_DEVICE_TABLE(pci, pciidlist);
1007
1008 static void i915_pci_remove(struct pci_dev *pdev)
1009 {
1010         struct drm_i915_private *i915;
1011
1012         i915 = pci_get_drvdata(pdev);
1013         if (!i915) /* driver load aborted, nothing to cleanup */
1014                 return;
1015
1016         i915_driver_remove(i915);
1017         pci_set_drvdata(pdev, NULL);
1018 }
1019
1020 /* is device_id present in comma separated list of ids */
1021 static bool force_probe(u16 device_id, const char *devices)
1022 {
1023         char *s, *p, *tok;
1024         bool ret;
1025
1026         if (!devices || !*devices)
1027                 return false;
1028
1029         /* match everything */
1030         if (strcmp(devices, "*") == 0)
1031                 return true;
1032
1033         s = kstrdup(devices, GFP_KERNEL);
1034         if (!s)
1035                 return false;
1036
1037         for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) {
1038                 u16 val;
1039
1040                 if (kstrtou16(tok, 16, &val) == 0 && val == device_id) {
1041                         ret = true;
1042                         break;
1043                 }
1044         }
1045
1046         kfree(s);
1047
1048         return ret;
1049 }
1050
1051 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1052 {
1053         struct intel_device_info *intel_info =
1054                 (struct intel_device_info *) ent->driver_data;
1055         int err;
1056
1057         if (intel_info->require_force_probe &&
1058             !force_probe(pdev->device, i915_modparams.force_probe)) {
1059                 dev_info(&pdev->dev,
1060                          "Your graphics device %04x is not properly supported by the driver in this\n"
1061                          "kernel version. To force driver probe anyway, use i915.force_probe=%04x\n"
1062                          "module parameter or CONFIG_DRM_I915_FORCE_PROBE=%04x configuration option,\n"
1063                          "or (recommended) check for kernel updates.\n",
1064                          pdev->device, pdev->device, pdev->device);
1065                 return -ENODEV;
1066         }
1067
1068         /* Only bind to function 0 of the device. Early generations
1069          * used function 1 as a placeholder for multi-head. This causes
1070          * us confusion instead, especially on the systems where both
1071          * functions have the same PCI-ID!
1072          */
1073         if (PCI_FUNC(pdev->devfn))
1074                 return -ENODEV;
1075
1076         /*
1077          * apple-gmux is needed on dual GPU MacBook Pro
1078          * to probe the panel if we're the inactive GPU.
1079          */
1080         if (vga_switcheroo_client_probe_defer(pdev))
1081                 return -EPROBE_DEFER;
1082
1083         err = i915_driver_probe(pdev, ent);
1084         if (err)
1085                 return err;
1086
1087         if (i915_inject_probe_failure(pci_get_drvdata(pdev))) {
1088                 i915_pci_remove(pdev);
1089                 return -ENODEV;
1090         }
1091
1092         err = i915_live_selftests(pdev);
1093         if (err) {
1094                 i915_pci_remove(pdev);
1095                 return err > 0 ? -ENOTTY : err;
1096         }
1097
1098         err = i915_perf_selftests(pdev);
1099         if (err) {
1100                 i915_pci_remove(pdev);
1101                 return err > 0 ? -ENOTTY : err;
1102         }
1103
1104         return 0;
1105 }
1106
1107 static void i915_pci_shutdown(struct pci_dev *pdev)
1108 {
1109         struct drm_i915_private *i915 = pci_get_drvdata(pdev);
1110
1111         i915_driver_shutdown(i915);
1112 }
1113
1114 static struct pci_driver i915_pci_driver = {
1115         .name = DRIVER_NAME,
1116         .id_table = pciidlist,
1117         .probe = i915_pci_probe,
1118         .remove = i915_pci_remove,
1119         .shutdown = i915_pci_shutdown,
1120         .driver.pm = &i915_pm_ops,
1121 };
1122
1123 static int __init i915_init(void)
1124 {
1125         bool use_kms = true;
1126         int err;
1127
1128         err = i915_globals_init();
1129         if (err)
1130                 return err;
1131
1132         err = i915_mock_selftests();
1133         if (err)
1134                 return err > 0 ? 0 : err;
1135
1136         /*
1137          * Enable KMS by default, unless explicitly overriden by
1138          * either the i915.modeset prarameter or by the
1139          * vga_text_mode_force boot option.
1140          */
1141
1142         if (i915_modparams.modeset == 0)
1143                 use_kms = false;
1144
1145         if (vgacon_text_force() && i915_modparams.modeset == -1)
1146                 use_kms = false;
1147
1148         if (!use_kms) {
1149                 /* Silently fail loading to not upset userspace. */
1150                 DRM_DEBUG_DRIVER("KMS disabled.\n");
1151                 return 0;
1152         }
1153
1154         i915_pmu_init();
1155
1156         err = pci_register_driver(&i915_pci_driver);
1157         if (err) {
1158                 i915_pmu_exit();
1159                 return err;
1160         }
1161
1162         i915_perf_sysctl_register();
1163         return 0;
1164 }
1165
1166 static void __exit i915_exit(void)
1167 {
1168         if (!i915_pci_driver.driver.owner)
1169                 return;
1170
1171         i915_perf_sysctl_unregister();
1172         pci_unregister_driver(&i915_pci_driver);
1173         i915_globals_exit();
1174         i915_pmu_exit();
1175 }
1176
1177 module_init(i915_init);
1178 module_exit(i915_exit);
1179
1180 MODULE_AUTHOR("Tungsten Graphics, Inc.");
1181 MODULE_AUTHOR("Intel Corporation");
1182
1183 MODULE_DESCRIPTION(DRIVER_DESC);
1184 MODULE_LICENSE("GPL and additional rights");