drivers/gpu/drm/i915/i915_pmu.h

   1 /*
   2  * SPDX-License-Identifier: MIT
   3  *
   4  * Copyright © 2017-2018 Intel Corporation
   5  */
   6
   7 #ifndef __I915_PMU_H__
   8 #define __I915_PMU_H__
   9
  10 #include <linux/hrtimer.h>
  11 #include <linux/perf_event.h>
  12 #include <linux/spinlock_types.h>
  13 #include <uapi/drm/i915_drm.h>
  14
  15 struct drm_i915_private;
  16
  17 enum {
  18         __I915_SAMPLE_FREQ_ACT = 0,
  19         __I915_SAMPLE_FREQ_REQ,
  20         __I915_SAMPLE_RC6,
  21         __I915_SAMPLE_RC6_LAST_REPORTED,
  22         __I915_NUM_PMU_SAMPLERS
  23 };
  24
  25 /**
  26  * How many different events we track in the global PMU mask.
  27  *
  28  * It is also used to know to needed number of event reference counters.
  29  */
  30 #define I915_PMU_MASK_BITS \
  31         ((1 << I915_PMU_SAMPLE_BITS) + \
  32          (I915_PMU_LAST + 1 - __I915_PMU_OTHER(0)))
  33
  34 #define I915_ENGINE_SAMPLE_COUNT (I915_SAMPLE_SEMA + 1)
  35
  36 struct i915_pmu_sample {
  37         u64 cur;
  38 };
  39
  40 struct i915_pmu {
  41         /**
  42          * @cpuhp: Struct used for CPU hotplug handling.
  43          */
  44         struct {
  45                 struct hlist_node node;
  46                 unsigned int cpu;
  47         } cpuhp;
  48         /**
  49          * @base: PMU base.
  50          */
  51         struct pmu base;
  52         /**
  53          * @closed: i915 is unregistering.
  54          */
  55         bool closed;
  56         /**
  57          * @name: Name as registered with perf core.
  58          */
  59         const char *name;
  60         /**
  61          * @lock: Lock protecting enable mask and ref count handling.
  62          */
  63         spinlock_t lock;
  64         /**
  65          * @timer: Timer for internal i915 PMU sampling.
  66          */
  67         struct hrtimer timer;
  68         /**
  69          * @enable: Bitmask of all currently enabled events.
  70          *
  71          * Bits are derived from uAPI event numbers in a way that low 16 bits
  72          * correspond to engine event _sample_ _type_ (I915_SAMPLE_QUEUED is
  73          * bit 0), and higher bits correspond to other events (for instance
  74          * I915_PMU_ACTUAL_FREQUENCY is bit 16 etc).
  75          *
  76          * In other words, low 16 bits are not per engine but per engine
  77          * sampler type, while the upper bits are directly mapped to other
  78          * event types.
  79          */
  80         u64 enable;
  81
  82         /**
  83          * @timer_last:
  84          *
  85          * Timestmap of the previous timer invocation.
  86          */
  87         ktime_t timer_last;
  88
  89         /**
  90          * @enable_count: Reference counts for the enabled events.
  91          *
  92          * Array indices are mapped in the same way as bits in the @enable field
  93          * and they are used to control sampling on/off when multiple clients
  94          * are using the PMU API.
  95          */
  96         unsigned int enable_count[I915_PMU_MASK_BITS];
  97         /**
  98          * @timer_enabled: Should the internal sampling timer be running.
  99          */
 100         bool timer_enabled;
 101         /**
 102          * @sample: Current and previous (raw) counters for sampling events.
 103          *
 104          * These counters are updated from the i915 PMU sampling timer.
 105          *
 106          * Only global counters are held here, while the per-engine ones are in
 107          * struct intel_engine_cs.
 108          */
 109         struct i915_pmu_sample sample[__I915_NUM_PMU_SAMPLERS];
 110         /**
 111          * @sleep_last: Last time GT parked for RC6 estimation.
 112          */
 113         ktime_t sleep_last;
 114         /**
 115          * @irq_count: Number of interrupts
 116          *
 117          * Intentionally unsigned long to avoid atomics or heuristics on 32bit.
 118          * 4e9 interrupts are a lot and postprocessing can really deal with an
 119          * occasional wraparound easily. It's 32bit after all.
 120          */
 121         unsigned long irq_count;
 122         /**
 123          * @events_attr_group: Device events attribute group.
 124          */
 125         struct attribute_group events_attr_group;
 126         /**
 127          * @i915_attr: Memory block holding device attributes.
 128          */
 129         void *i915_attr;
 130         /**
 131          * @pmu_attr: Memory block holding device attributes.
 132          */
 133         void *pmu_attr;
 134 };
 135
 136 #ifdef CONFIG_PERF_EVENTS
 137 void i915_pmu_init(void);
 138 void i915_pmu_exit(void);
 139 void i915_pmu_register(struct drm_i915_private *i915);
 140 void i915_pmu_unregister(struct drm_i915_private *i915);
 141 void i915_pmu_gt_parked(struct drm_i915_private *i915);
 142 void i915_pmu_gt_unparked(struct drm_i915_private *i915);
 143 #else
 144 static inline void i915_pmu_init(void) {}
 145 static inline void i915_pmu_exit(void) {}
 146 static inline void i915_pmu_register(struct drm_i915_private *i915) {}
 147 static inline void i915_pmu_unregister(struct drm_i915_private *i915) {}
 148 static inline void i915_pmu_gt_parked(struct drm_i915_private *i915) {}
 149 static inline void i915_pmu_gt_unparked(struct drm_i915_private *i915) {}
 150 #endif
 151
 152 #endif