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Merge tag 'block-5.11-2021-01-10' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / gpu / drm / i915 / i915_reg.h
blob5375b219cc3b7c6f7a45046e5e778edc8fe1c866
1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
2 * All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
14 * of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #ifndef _I915_REG_H_
26 #define _I915_REG_H_
27
28 #include <linux/bitfield.h>
29 #include <linux/bits.h>
30
31 /**
32 * DOC: The i915 register macro definition style guide
33 *
34 * Follow the style described here for new macros, and while changing existing
35 * macros. Do **not** mass change existing definitions just to update the style.
36 *
37 * File Layout
38 * ~~~~~~~~~~~
39 *
40 * Keep helper macros near the top. For example, _PIPE() and friends.
41 *
42 * Prefix macros that generally should not be used outside of this file with
43 * underscore '_'. For example, _PIPE() and friends, single instances of
44 * registers that are defined solely for the use by function-like macros.
45 *
46 * Avoid using the underscore prefixed macros outside of this file. There are
47 * exceptions, but keep them to a minimum.
48 *
49 * There are two basic types of register definitions: Single registers and
50 * register groups. Register groups are registers which have two or more
51 * instances, for example one per pipe, port, transcoder, etc. Register groups
52 * should be defined using function-like macros.
53 *
54 * For single registers, define the register offset first, followed by register
55 * contents.
56 *
57 * For register groups, define the register instance offsets first, prefixed
58 * with underscore, followed by a function-like macro choosing the right
59 * instance based on the parameter, followed by register contents.
60 *
61 * Define the register contents (i.e. bit and bit field macros) from most
62 * significant to least significant bit. Indent the register content macros
63 * using two extra spaces between ``#define`` and the macro name.
64 *
65 * Define bit fields using ``REG_GENMASK(h, l)``. Define bit field contents
66 * using ``REG_FIELD_PREP(mask, value)``. This will define the values already
67 * shifted in place, so they can be directly OR'd together. For convenience,
68 * function-like macros may be used to define bit fields, but do note that the
69 * macros may be needed to read as well as write the register contents.
70 *
71 * Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the name.
72 *
73 * Group the register and its contents together without blank lines, separate
74 * from other registers and their contents with one blank line.
75 *
76 * Indent macro values from macro names using TABs. Align values vertically. Use
77 * braces in macro values as needed to avoid unintended precedence after macro
78 * substitution. Use spaces in macro values according to kernel coding
79 * style. Use lower case in hexadecimal values.
80 *
81 * Naming
82 * ~~~~~~
83 *
84 * Try to name registers according to the specs. If the register name changes in
85 * the specs from platform to another, stick to the original name.
86 *
87 * Try to re-use existing register macro definitions. Only add new macros for
88 * new register offsets, or when the register contents have changed enough to
89 * warrant a full redefinition.
90 *
91 * When a register macro changes for a new platform, prefix the new macro using
92 * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The
93 * prefix signifies the start platform/generation using the register.
94 *
95 * When a bit (field) macro changes or gets added for a new platform, while
96 * retaining the existing register macro, add a platform acronym or generation
97 * suffix to the name. For example, ``_SKL`` or ``_GEN8``.
98 *
99 * Examples
100 * ~~~~~~~~
101 *
102 * (Note that the values in the example are indented using spaces instead of
103 * TABs to avoid misalignment in generated documentation. Use TABs in the
104 * definitions.)::
105 *
106 * #define _FOO_A 0xf000
107 * #define _FOO_B 0xf001
108 * #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B)
109 * #define FOO_ENABLE REG_BIT(31)
110 * #define FOO_MODE_MASK REG_GENMASK(19, 16)
111 * #define FOO_MODE_BAR REG_FIELD_PREP(FOO_MODE_MASK, 0)
112 * #define FOO_MODE_BAZ REG_FIELD_PREP(FOO_MODE_MASK, 1)
113 * #define FOO_MODE_QUX_SNB REG_FIELD_PREP(FOO_MODE_MASK, 2)
114 *
115 * #define BAR _MMIO(0xb000)
116 * #define GEN8_BAR _MMIO(0xb888)
117 */
118
119 /**
120 * REG_BIT() - Prepare a u32 bit value
121 * @__n: 0-based bit number
122 *
123 * Local wrapper for BIT() to force u32, with compile time checks.
124 *
125 * @return: Value with bit @__n set.
126 */
127 #define REG_BIT(__n) \
128 ((u32)(BIT(__n) + \
129 BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \
130 ((__n) < 0 || (__n) > 31))))
131
132 /**
133 * REG_GENMASK() - Prepare a continuous u32 bitmask
134 * @__high: 0-based high bit
135 * @__low: 0-based low bit
136 *
137 * Local wrapper for GENMASK() to force u32, with compile time checks.
138 *
139 * @return: Continuous bitmask from @__high to @__low, inclusive.
140 */
141 #define REG_GENMASK(__high, __low) \
142 ((u32)(GENMASK(__high, __low) + \
143 BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \
144 __is_constexpr(__low) && \
145 ((__low) < 0 || (__high) > 31 || (__low) > (__high)))))
146
147 /*
148 * Local integer constant expression version of is_power_of_2().
149 */
150 #define IS_POWER_OF_2(__x) ((__x) && (((__x) & ((__x) - 1)) == 0))
151
152 /**
153 * REG_FIELD_PREP() - Prepare a u32 bitfield value
154 * @__mask: shifted mask defining the field's length and position
155 * @__val: value to put in the field
156 *
157 * Local copy of FIELD_PREP() to generate an integer constant expression, force
158 * u32 and for consistency with REG_FIELD_GET(), REG_BIT() and REG_GENMASK().
159 *
160 * @return: @__val masked and shifted into the field defined by @__mask.
161 */
162 #define REG_FIELD_PREP(__mask, __val) \
163 ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
164 BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
165 BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) + \
166 BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
167 BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
168
169 /**
170 * REG_FIELD_GET() - Extract a u32 bitfield value
171 * @__mask: shifted mask defining the field's length and position
172 * @__val: value to extract the bitfield value from
173 *
174 * Local wrapper for FIELD_GET() to force u32 and for consistency with
175 * REG_FIELD_PREP(), REG_BIT() and REG_GENMASK().
176 *
177 * @return: Masked and shifted value of the field defined by @__mask in @__val.
178 */
179 #define REG_FIELD_GET(__mask, __val) ((u32)FIELD_GET(__mask, __val))
180
181 typedef struct {
182 u32 reg;
183 } i915_reg_t;
184
185 #define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
186
187 #define INVALID_MMIO_REG _MMIO(0)
188
189 static __always_inline u32 i915_mmio_reg_offset(i915_reg_t reg)
190 {
191 return reg.reg;
192 }
193
194 static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b)
195 {
196 return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b);
197 }
198
199 static inline bool i915_mmio_reg_valid(i915_reg_t reg)
200 {
201 return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG);
202 }
203
204 #define VLV_DISPLAY_BASE 0x180000
205 #define VLV_MIPI_BASE VLV_DISPLAY_BASE
206 #define BXT_MIPI_BASE 0x60000
207
208 #define DISPLAY_MMIO_BASE(dev_priv) (INTEL_INFO(dev_priv)->display_mmio_offset)
209
210 /*
211 * Given the first two numbers __a and __b of arbitrarily many evenly spaced
212 * numbers, pick the 0-based __index'th value.
213 *
214 * Always prefer this over _PICK() if the numbers are evenly spaced.
215 */
216 #define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
217
218 /*
219 * Given the arbitrary numbers in varargs, pick the 0-based __index'th number.
220 *
221 * Always prefer _PICK_EVEN() over this if the numbers are evenly spaced.
222 */
223 #define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index])
224
225 /*
226 * Named helper wrappers around _PICK_EVEN() and _PICK().
227 */
228 #define _PIPE(pipe, a, b) _PICK_EVEN(pipe, a, b)
229 #define _PLANE(plane, a, b) _PICK_EVEN(plane, a, b)
230 #define _TRANS(tran, a, b) _PICK_EVEN(tran, a, b)
231 #define _PORT(port, a, b) _PICK_EVEN(port, a, b)
232 #define _PLL(pll, a, b) _PICK_EVEN(pll, a, b)
233 #define _PHY(phy, a, b) _PICK_EVEN(phy, a, b)
234
235 #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b))
236 #define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b))
237 #define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b))
238 #define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b))
239 #define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b))
240 #define _MMIO_PHY(phy, a, b) _MMIO(_PHY(phy, a, b))
241
242 #define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__)
243
244 #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
245 #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
246 #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
247 #define _MMIO_PLL3(pll, ...) _MMIO(_PICK(pll, __VA_ARGS__))
248
249
250 /*
251 * Device info offset array based helpers for groups of registers with unevenly
252 * spaced base offsets.
253 */
254 #define _MMIO_PIPE2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->pipe_offsets[pipe] - \
255 INTEL_INFO(dev_priv)->pipe_offsets[PIPE_A] + (reg) + \
256 DISPLAY_MMIO_BASE(dev_priv))
257 #define _TRANS2(tran, reg) (INTEL_INFO(dev_priv)->trans_offsets[(tran)] - \
258 INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_A] + (reg) + \
259 DISPLAY_MMIO_BASE(dev_priv))
260 #define _MMIO_TRANS2(tran, reg) _MMIO(_TRANS2(tran, reg))
261 #define _CURSOR2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->cursor_offsets[(pipe)] - \
262 INTEL_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \
263 DISPLAY_MMIO_BASE(dev_priv))
264
265 #define __MASKED_FIELD(mask, value) ((mask) << 16 | (value))
266 #define _MASKED_FIELD(mask, value) ({ \
267 if (__builtin_constant_p(mask)) \
268 BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \
269 if (__builtin_constant_p(value)) \
270 BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \
271 if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \
272 BUILD_BUG_ON_MSG((value) & ~(mask), \
273 "Incorrect value for mask"); \
274 __MASKED_FIELD(mask, value); })
275 #define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
276 #define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0))
277
278 /* PCI config space */
279
280 #define MCHBAR_I915 0x44
281 #define MCHBAR_I965 0x48
282 #define MCHBAR_SIZE (4 * 4096)
283
284 #define DEVEN 0x54
285 #define DEVEN_MCHBAR_EN (1 << 28)
286
287 /* BSM in include/drm/i915_drm.h */
288
289 #define HPLLCC 0xc0 /* 85x only */
290 #define GC_CLOCK_CONTROL_MASK (0x7 << 0)
291 #define GC_CLOCK_133_200 (0 << 0)
292 #define GC_CLOCK_100_200 (1 << 0)
293 #define GC_CLOCK_100_133 (2 << 0)
294 #define GC_CLOCK_133_266 (3 << 0)
295 #define GC_CLOCK_133_200_2 (4 << 0)
296 #define GC_CLOCK_133_266_2 (5 << 0)
297 #define GC_CLOCK_166_266 (6 << 0)
298 #define GC_CLOCK_166_250 (7 << 0)
299
300 #define I915_GDRST 0xc0 /* PCI config register */
301 #define GRDOM_FULL (0 << 2)
302 #define GRDOM_RENDER (1 << 2)
303 #define GRDOM_MEDIA (3 << 2)
304 #define GRDOM_MASK (3 << 2)
305 #define GRDOM_RESET_STATUS (1 << 1)
306 #define GRDOM_RESET_ENABLE (1 << 0)
307
308 /* BSpec only has register offset, PCI device and bit found empirically */
309 #define I830_CLOCK_GATE 0xc8 /* device 0 */
310 #define I830_L2_CACHE_CLOCK_GATE_DISABLE (1 << 2)
311
312 #define GCDGMBUS 0xcc
313
314 #define GCFGC2 0xda
315 #define GCFGC 0xf0 /* 915+ only */
316 #define GC_LOW_FREQUENCY_ENABLE (1 << 7)
317 #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
318 #define GC_DISPLAY_CLOCK_333_320_MHZ (4 << 4)
319 #define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4)
320 #define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4)
321 #define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4)
322 #define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4)
323 #define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4)
324 #define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4)
325 #define GC_DISPLAY_CLOCK_MASK (7 << 4)
326 #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
327 #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
328 #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
329 #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
330 #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
331 #define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
332 #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
333 #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
334 #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
335 #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
336 #define I945_GC_RENDER_CLOCK_MASK (7 << 0)
337 #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
338 #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
339 #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
340 #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
341 #define I915_GC_RENDER_CLOCK_MASK (7 << 0)
342 #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
343 #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
344 #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
345
346 #define ASLE 0xe4
347 #define ASLS 0xfc
348
349 #define SWSCI 0xe8
350 #define SWSCI_SCISEL (1 << 15)
351 #define SWSCI_GSSCIE (1 << 0)
352
353 #define LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */
354
355
356 #define ILK_GDSR _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4)
357 #define ILK_GRDOM_FULL (0 << 1)
358 #define ILK_GRDOM_RENDER (1 << 1)
359 #define ILK_GRDOM_MEDIA (3 << 1)
360 #define ILK_GRDOM_MASK (3 << 1)
361 #define ILK_GRDOM_RESET_ENABLE (1 << 0)
362
363 #define GEN6_MBCUNIT_SNPCR _MMIO(0x900c) /* for LLC config */
364 #define GEN6_MBC_SNPCR_SHIFT 21
365 #define GEN6_MBC_SNPCR_MASK (3 << 21)
366 #define GEN6_MBC_SNPCR_MAX (0 << 21)
367 #define GEN6_MBC_SNPCR_MED (1 << 21)
368 #define GEN6_MBC_SNPCR_LOW (2 << 21)
369 #define GEN6_MBC_SNPCR_MIN (3 << 21) /* only 1/16th of the cache is shared */
370
371 #define VLV_G3DCTL _MMIO(0x9024)
372 #define VLV_GSCKGCTL _MMIO(0x9028)
373
374 #define GEN6_MBCTL _MMIO(0x0907c)
375 #define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4)
376 #define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3)
377 #define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2)
378 #define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1)
379 #define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0)
380
381 #define GEN6_GDRST _MMIO(0x941c)
382 #define GEN6_GRDOM_FULL (1 << 0)
383 #define GEN6_GRDOM_RENDER (1 << 1)
384 #define GEN6_GRDOM_MEDIA (1 << 2)
385 #define GEN6_GRDOM_BLT (1 << 3)
386 #define GEN6_GRDOM_VECS (1 << 4)
387 #define GEN9_GRDOM_GUC (1 << 5)
388 #define GEN8_GRDOM_MEDIA2 (1 << 7)
389 /* GEN11 changed all bit defs except for FULL & RENDER */
390 #define GEN11_GRDOM_FULL GEN6_GRDOM_FULL
391 #define GEN11_GRDOM_RENDER GEN6_GRDOM_RENDER
392 #define GEN11_GRDOM_BLT (1 << 2)
393 #define GEN11_GRDOM_GUC (1 << 3)
394 #define GEN11_GRDOM_MEDIA (1 << 5)
395 #define GEN11_GRDOM_MEDIA2 (1 << 6)
396 #define GEN11_GRDOM_MEDIA3 (1 << 7)
397 #define GEN11_GRDOM_MEDIA4 (1 << 8)
398 #define GEN11_GRDOM_VECS (1 << 13)
399 #define GEN11_GRDOM_VECS2 (1 << 14)
400 #define GEN11_GRDOM_SFC0 (1 << 17)
401 #define GEN11_GRDOM_SFC1 (1 << 18)
402
403 #define GEN11_VCS_SFC_RESET_BIT(instance) (GEN11_GRDOM_SFC0 << ((instance) >> 1))
404 #define GEN11_VECS_SFC_RESET_BIT(instance) (GEN11_GRDOM_SFC0 << (instance))
405
406 #define GEN11_VCS_SFC_FORCED_LOCK(engine) _MMIO((engine)->mmio_base + 0x88C)
407 #define GEN11_VCS_SFC_FORCED_LOCK_BIT (1 << 0)
408 #define GEN11_VCS_SFC_LOCK_STATUS(engine) _MMIO((engine)->mmio_base + 0x890)
409 #define GEN11_VCS_SFC_USAGE_BIT (1 << 0)
410 #define GEN11_VCS_SFC_LOCK_ACK_BIT (1 << 1)
411
412 #define GEN11_VECS_SFC_FORCED_LOCK(engine) _MMIO((engine)->mmio_base + 0x201C)
413 #define GEN11_VECS_SFC_FORCED_LOCK_BIT (1 << 0)
414 #define GEN11_VECS_SFC_LOCK_ACK(engine) _MMIO((engine)->mmio_base + 0x2018)
415 #define GEN11_VECS_SFC_LOCK_ACK_BIT (1 << 0)
416 #define GEN11_VECS_SFC_USAGE(engine) _MMIO((engine)->mmio_base + 0x2014)
417 #define GEN11_VECS_SFC_USAGE_BIT (1 << 0)
418
419 #define GEN12_SFC_DONE(n) _MMIO(0x1cc00 + (n) * 0x100)
420 #define GEN12_SFC_DONE_MAX 4
421
422 #define RING_PP_DIR_BASE(base) _MMIO((base) + 0x228)
423 #define RING_PP_DIR_BASE_READ(base) _MMIO((base) + 0x518)
424 #define RING_PP_DIR_DCLV(base) _MMIO((base) + 0x220)
425 #define PP_DIR_DCLV_2G 0xffffffff
426
427 #define GEN8_RING_PDP_UDW(base, n) _MMIO((base) + 0x270 + (n) * 8 + 4)
428 #define GEN8_RING_PDP_LDW(base, n) _MMIO((base) + 0x270 + (n) * 8)
429
430 #define GEN8_R_PWR_CLK_STATE _MMIO(0x20C8)
431 #define GEN8_RPCS_ENABLE (1 << 31)
432 #define GEN8_RPCS_S_CNT_ENABLE (1 << 18)
433 #define GEN8_RPCS_S_CNT_SHIFT 15
434 #define GEN8_RPCS_S_CNT_MASK (0x7 << GEN8_RPCS_S_CNT_SHIFT)
435 #define GEN11_RPCS_S_CNT_SHIFT 12
436 #define GEN11_RPCS_S_CNT_MASK (0x3f << GEN11_RPCS_S_CNT_SHIFT)
437 #define GEN8_RPCS_SS_CNT_ENABLE (1 << 11)
438 #define GEN8_RPCS_SS_CNT_SHIFT 8
439 #define GEN8_RPCS_SS_CNT_MASK (0x7 << GEN8_RPCS_SS_CNT_SHIFT)
440 #define GEN8_RPCS_EU_MAX_SHIFT 4
441 #define GEN8_RPCS_EU_MAX_MASK (0xf << GEN8_RPCS_EU_MAX_SHIFT)
442 #define GEN8_RPCS_EU_MIN_SHIFT 0
443 #define GEN8_RPCS_EU_MIN_MASK (0xf << GEN8_RPCS_EU_MIN_SHIFT)
444
445 #define WAIT_FOR_RC6_EXIT _MMIO(0x20CC)
446 /* HSW only */
447 #define HSW_SELECTIVE_READ_ADDRESSING_SHIFT 2
448 #define HSW_SELECTIVE_READ_ADDRESSING_MASK (0x3 << HSW_SLECTIVE_READ_ADDRESSING_SHIFT)
449 #define HSW_SELECTIVE_WRITE_ADDRESS_SHIFT 4
450 #define HSW_SELECTIVE_WRITE_ADDRESS_MASK (0x7 << HSW_SELECTIVE_WRITE_ADDRESS_SHIFT)
451 /* HSW+ */
452 #define HSW_WAIT_FOR_RC6_EXIT_ENABLE (1 << 0)
453 #define HSW_RCS_CONTEXT_ENABLE (1 << 7)
454 #define HSW_RCS_INHIBIT (1 << 8)
455 /* Gen8 */
456 #define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT 4
457 #define GEN8_SELECTIVE_WRITE_ADDRESS_MASK (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT)
458 #define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT 4
459 #define GEN8_SELECTIVE_WRITE_ADDRESS_MASK (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT)
460 #define GEN8_SELECTIVE_WRITE_ADDRESSING_ENABLE (1 << 6)
461 #define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT 9
462 #define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT)
463 #define GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT 11
464 #define GEN8_SELECTIVE_READ_SLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT)
465 #define GEN8_SELECTIVE_READ_ADDRESSING_ENABLE (1 << 13)
466
467 #define GAM_ECOCHK _MMIO(0x4090)
468 #define BDW_DISABLE_HDC_INVALIDATION (1 << 25)
469 #define ECOCHK_SNB_BIT (1 << 10)
470 #define ECOCHK_DIS_TLB (1 << 8)
471 #define HSW_ECOCHK_ARB_PRIO_SOL (1 << 6)
472 #define ECOCHK_PPGTT_CACHE64B (0x3 << 3)
473 #define ECOCHK_PPGTT_CACHE4B (0x0 << 3)
474 #define ECOCHK_PPGTT_GFDT_IVB (0x1 << 4)
475 #define ECOCHK_PPGTT_LLC_IVB (0x1 << 3)
476 #define ECOCHK_PPGTT_UC_HSW (0x1 << 3)
477 #define ECOCHK_PPGTT_WT_HSW (0x2 << 3)
478 #define ECOCHK_PPGTT_WB_HSW (0x3 << 3)
479
480 #define GEN8_RC6_CTX_INFO _MMIO(0x8504)
481
482 #define GAC_ECO_BITS _MMIO(0x14090)
483 #define ECOBITS_SNB_BIT (1 << 13)
484 #define ECOBITS_PPGTT_CACHE64B (3 << 8)
485 #define ECOBITS_PPGTT_CACHE4B (0 << 8)
486
487 #define GAB_CTL _MMIO(0x24000)
488 #define GAB_CTL_CONT_AFTER_PAGEFAULT (1 << 8)
489
490 #define GEN6_STOLEN_RESERVED _MMIO(0x1082C0)
491 #define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20)
492 #define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18)
493 #define GEN6_STOLEN_RESERVED_SIZE_MASK (3 << 4)
494 #define GEN6_STOLEN_RESERVED_1M (0 << 4)
495 #define GEN6_STOLEN_RESERVED_512K (1 << 4)
496 #define GEN6_STOLEN_RESERVED_256K (2 << 4)
497 #define GEN6_STOLEN_RESERVED_128K (3 << 4)
498 #define GEN7_STOLEN_RESERVED_SIZE_MASK (1 << 5)
499 #define GEN7_STOLEN_RESERVED_1M (0 << 5)
500 #define GEN7_STOLEN_RESERVED_256K (1 << 5)
501 #define GEN8_STOLEN_RESERVED_SIZE_MASK (3 << 7)
502 #define GEN8_STOLEN_RESERVED_1M (0 << 7)
503 #define GEN8_STOLEN_RESERVED_2M (1 << 7)
504 #define GEN8_STOLEN_RESERVED_4M (2 << 7)
505 #define GEN8_STOLEN_RESERVED_8M (3 << 7)
506 #define GEN6_STOLEN_RESERVED_ENABLE (1 << 0)
507 #define GEN11_STOLEN_RESERVED_ADDR_MASK (0xFFFFFFFFFFFULL << 20)
508
509 /* VGA stuff */
510
511 #define VGA_ST01_MDA 0x3ba
512 #define VGA_ST01_CGA 0x3da
513
514 #define _VGA_MSR_WRITE _MMIO(0x3c2)
515 #define VGA_MSR_WRITE 0x3c2
516 #define VGA_MSR_READ 0x3cc
517 #define VGA_MSR_MEM_EN (1 << 1)
518 #define VGA_MSR_CGA_MODE (1 << 0)
519
520 #define VGA_SR_INDEX 0x3c4
521 #define SR01 1
522 #define VGA_SR_DATA 0x3c5
523
524 #define VGA_AR_INDEX 0x3c0
525 #define VGA_AR_VID_EN (1 << 5)
526 #define VGA_AR_DATA_WRITE 0x3c0
527 #define VGA_AR_DATA_READ 0x3c1
528
529 #define VGA_GR_INDEX 0x3ce
530 #define VGA_GR_DATA 0x3cf
531 /* GR05 */
532 #define VGA_GR_MEM_READ_MODE_SHIFT 3
533 #define VGA_GR_MEM_READ_MODE_PLANE 1
534 /* GR06 */
535 #define VGA_GR_MEM_MODE_MASK 0xc
536 #define VGA_GR_MEM_MODE_SHIFT 2
537 #define VGA_GR_MEM_A0000_AFFFF 0
538 #define VGA_GR_MEM_A0000_BFFFF 1
539 #define VGA_GR_MEM_B0000_B7FFF 2
540 #define VGA_GR_MEM_B0000_BFFFF 3
541
542 #define VGA_DACMASK 0x3c6
543 #define VGA_DACRX 0x3c7
544 #define VGA_DACWX 0x3c8
545 #define VGA_DACDATA 0x3c9
546
547 #define VGA_CR_INDEX_MDA 0x3b4
548 #define VGA_CR_DATA_MDA 0x3b5
549 #define VGA_CR_INDEX_CGA 0x3d4
550 #define VGA_CR_DATA_CGA 0x3d5
551
552 #define MI_PREDICATE_SRC0 _MMIO(0x2400)
553 #define MI_PREDICATE_SRC0_UDW _MMIO(0x2400 + 4)
554 #define MI_PREDICATE_SRC1 _MMIO(0x2408)
555 #define MI_PREDICATE_SRC1_UDW _MMIO(0x2408 + 4)
556 #define MI_PREDICATE_DATA _MMIO(0x2410)
557 #define MI_PREDICATE_RESULT _MMIO(0x2418)
558 #define MI_PREDICATE_RESULT_1 _MMIO(0x241c)
559 #define MI_PREDICATE_RESULT_2 _MMIO(0x2214)
560 #define LOWER_SLICE_ENABLED (1 << 0)
561 #define LOWER_SLICE_DISABLED (0 << 0)
562
563 /*
564 * Registers used only by the command parser
565 */
566 #define BCS_SWCTRL _MMIO(0x22200)
567 #define BCS_SRC_Y REG_BIT(0)
568 #define BCS_DST_Y REG_BIT(1)
569
570 /* There are 16 GPR registers */
571 #define BCS_GPR(n) _MMIO(0x22600 + (n) * 8)
572 #define BCS_GPR_UDW(n) _MMIO(0x22600 + (n) * 8 + 4)
573
574 #define GPGPU_THREADS_DISPATCHED _MMIO(0x2290)
575 #define GPGPU_THREADS_DISPATCHED_UDW _MMIO(0x2290 + 4)
576 #define HS_INVOCATION_COUNT _MMIO(0x2300)
577 #define HS_INVOCATION_COUNT_UDW _MMIO(0x2300 + 4)
578 #define DS_INVOCATION_COUNT _MMIO(0x2308)
579 #define DS_INVOCATION_COUNT_UDW _MMIO(0x2308 + 4)
580 #define IA_VERTICES_COUNT _MMIO(0x2310)
581 #define IA_VERTICES_COUNT_UDW _MMIO(0x2310 + 4)
582 #define IA_PRIMITIVES_COUNT _MMIO(0x2318)
583 #define IA_PRIMITIVES_COUNT_UDW _MMIO(0x2318 + 4)
584 #define VS_INVOCATION_COUNT _MMIO(0x2320)
585 #define VS_INVOCATION_COUNT_UDW _MMIO(0x2320 + 4)
586 #define GS_INVOCATION_COUNT _MMIO(0x2328)
587 #define GS_INVOCATION_COUNT_UDW _MMIO(0x2328 + 4)
588 #define GS_PRIMITIVES_COUNT _MMIO(0x2330)
589 #define GS_PRIMITIVES_COUNT_UDW _MMIO(0x2330 + 4)
590 #define CL_INVOCATION_COUNT _MMIO(0x2338)
591 #define CL_INVOCATION_COUNT_UDW _MMIO(0x2338 + 4)
592 #define CL_PRIMITIVES_COUNT _MMIO(0x2340)
593 #define CL_PRIMITIVES_COUNT_UDW _MMIO(0x2340 + 4)
594 #define PS_INVOCATION_COUNT _MMIO(0x2348)
595 #define PS_INVOCATION_COUNT_UDW _MMIO(0x2348 + 4)
596 #define PS_DEPTH_COUNT _MMIO(0x2350)
597 #define PS_DEPTH_COUNT_UDW _MMIO(0x2350 + 4)
598
599 /* There are the 4 64-bit counter registers, one for each stream output */
600 #define GEN7_SO_NUM_PRIMS_WRITTEN(n) _MMIO(0x5200 + (n) * 8)
601 #define GEN7_SO_NUM_PRIMS_WRITTEN_UDW(n) _MMIO(0x5200 + (n) * 8 + 4)
602
603 #define GEN7_SO_PRIM_STORAGE_NEEDED(n) _MMIO(0x5240 + (n) * 8)
604 #define GEN7_SO_PRIM_STORAGE_NEEDED_UDW(n) _MMIO(0x5240 + (n) * 8 + 4)
605
606 #define GEN7_3DPRIM_END_OFFSET _MMIO(0x2420)
607 #define GEN7_3DPRIM_START_VERTEX _MMIO(0x2430)
608 #define GEN7_3DPRIM_VERTEX_COUNT _MMIO(0x2434)
609 #define GEN7_3DPRIM_INSTANCE_COUNT _MMIO(0x2438)
610 #define GEN7_3DPRIM_START_INSTANCE _MMIO(0x243C)
611 #define GEN7_3DPRIM_BASE_VERTEX _MMIO(0x2440)
612
613 #define GEN7_GPGPU_DISPATCHDIMX _MMIO(0x2500)
614 #define GEN7_GPGPU_DISPATCHDIMY _MMIO(0x2504)
615 #define GEN7_GPGPU_DISPATCHDIMZ _MMIO(0x2508)
616
617 /* There are the 16 64-bit CS General Purpose Registers */
618 #define HSW_CS_GPR(n) _MMIO(0x2600 + (n) * 8)
619 #define HSW_CS_GPR_UDW(n) _MMIO(0x2600 + (n) * 8 + 4)
620
621 #define GEN7_OACONTROL _MMIO(0x2360)
622 #define GEN7_OACONTROL_CTX_MASK 0xFFFFF000
623 #define GEN7_OACONTROL_TIMER_PERIOD_MASK 0x3F
624 #define GEN7_OACONTROL_TIMER_PERIOD_SHIFT 6
625 #define GEN7_OACONTROL_TIMER_ENABLE (1 << 5)
626 #define GEN7_OACONTROL_FORMAT_A13 (0 << 2)
627 #define GEN7_OACONTROL_FORMAT_A29 (1 << 2)
628 #define GEN7_OACONTROL_FORMAT_A13_B8_C8 (2 << 2)
629 #define GEN7_OACONTROL_FORMAT_A29_B8_C8 (3 << 2)
630 #define GEN7_OACONTROL_FORMAT_B4_C8 (4 << 2)
631 #define GEN7_OACONTROL_FORMAT_A45_B8_C8 (5 << 2)
632 #define GEN7_OACONTROL_FORMAT_B4_C8_A16 (6 << 2)
633 #define GEN7_OACONTROL_FORMAT_C4_B8 (7 << 2)
634 #define GEN7_OACONTROL_FORMAT_SHIFT 2
635 #define GEN7_OACONTROL_PER_CTX_ENABLE (1 << 1)
636 #define GEN7_OACONTROL_ENABLE (1 << 0)
637
638 #define GEN8_OACTXID _MMIO(0x2364)
639
640 #define GEN8_OA_DEBUG _MMIO(0x2B04)
641 #define GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS (1 << 5)
642 #define GEN9_OA_DEBUG_INCLUDE_CLK_RATIO (1 << 6)
643 #define GEN9_OA_DEBUG_DISABLE_GO_1_0_REPORTS (1 << 2)
644 #define GEN9_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS (1 << 1)
645
646 #define GEN8_OACONTROL _MMIO(0x2B00)
647 #define GEN8_OA_REPORT_FORMAT_A12 (0 << 2)
648 #define GEN8_OA_REPORT_FORMAT_A12_B8_C8 (2 << 2)
649 #define GEN8_OA_REPORT_FORMAT_A36_B8_C8 (5 << 2)
650 #define GEN8_OA_REPORT_FORMAT_C4_B8 (7 << 2)
651 #define GEN8_OA_REPORT_FORMAT_SHIFT 2
652 #define GEN8_OA_SPECIFIC_CONTEXT_ENABLE (1 << 1)
653 #define GEN8_OA_COUNTER_ENABLE (1 << 0)
654
655 #define GEN8_OACTXCONTROL _MMIO(0x2360)
656 #define GEN8_OA_TIMER_PERIOD_MASK 0x3F
657 #define GEN8_OA_TIMER_PERIOD_SHIFT 2
658 #define GEN8_OA_TIMER_ENABLE (1 << 1)
659 #define GEN8_OA_COUNTER_RESUME (1 << 0)
660
661 #define GEN7_OABUFFER _MMIO(0x23B0) /* R/W */
662 #define GEN7_OABUFFER_OVERRUN_DISABLE (1 << 3)
663 #define GEN7_OABUFFER_EDGE_TRIGGER (1 << 2)
664 #define GEN7_OABUFFER_STOP_RESUME_ENABLE (1 << 1)
665 #define GEN7_OABUFFER_RESUME (1 << 0)
666
667 #define GEN8_OABUFFER_UDW _MMIO(0x23b4)
668 #define GEN8_OABUFFER _MMIO(0x2b14)
669 #define GEN8_OABUFFER_MEM_SELECT_GGTT (1 << 0) /* 0: PPGTT, 1: GGTT */
670
671 #define GEN7_OASTATUS1 _MMIO(0x2364)
672 #define GEN7_OASTATUS1_TAIL_MASK 0xffffffc0
673 #define GEN7_OASTATUS1_COUNTER_OVERFLOW (1 << 2)
674 #define GEN7_OASTATUS1_OABUFFER_OVERFLOW (1 << 1)
675 #define GEN7_OASTATUS1_REPORT_LOST (1 << 0)
676
677 #define GEN7_OASTATUS2 _MMIO(0x2368)
678 #define GEN7_OASTATUS2_HEAD_MASK 0xffffffc0
679 #define GEN7_OASTATUS2_MEM_SELECT_GGTT (1 << 0) /* 0: PPGTT, 1: GGTT */
680
681 #define GEN8_OASTATUS _MMIO(0x2b08)
682 #define GEN8_OASTATUS_TAIL_POINTER_WRAP (1 << 17)
683 #define GEN8_OASTATUS_HEAD_POINTER_WRAP (1 << 16)
684 #define GEN8_OASTATUS_OVERRUN_STATUS (1 << 3)
685 #define GEN8_OASTATUS_COUNTER_OVERFLOW (1 << 2)
686 #define GEN8_OASTATUS_OABUFFER_OVERFLOW (1 << 1)
687 #define GEN8_OASTATUS_REPORT_LOST (1 << 0)
688
689 #define GEN8_OAHEADPTR _MMIO(0x2B0C)
690 #define GEN8_OAHEADPTR_MASK 0xffffffc0
691 #define GEN8_OATAILPTR _MMIO(0x2B10)
692 #define GEN8_OATAILPTR_MASK 0xffffffc0
693
694 #define OABUFFER_SIZE_128K (0 << 3)
695 #define OABUFFER_SIZE_256K (1 << 3)
696 #define OABUFFER_SIZE_512K (2 << 3)
697 #define OABUFFER_SIZE_1M (3 << 3)
698 #define OABUFFER_SIZE_2M (4 << 3)
699 #define OABUFFER_SIZE_4M (5 << 3)
700 #define OABUFFER_SIZE_8M (6 << 3)
701 #define OABUFFER_SIZE_16M (7 << 3)
702
703 #define GEN12_OA_TLB_INV_CR _MMIO(0xceec)
704
705 /* Gen12 OAR unit */
706 #define GEN12_OAR_OACONTROL _MMIO(0x2960)
707 #define GEN12_OAR_OACONTROL_COUNTER_FORMAT_SHIFT 1
708 #define GEN12_OAR_OACONTROL_COUNTER_ENABLE (1 << 0)
709
710 #define GEN12_OACTXCONTROL _MMIO(0x2360)
711 #define GEN12_OAR_OASTATUS _MMIO(0x2968)
712
713 /* Gen12 OAG unit */
714 #define GEN12_OAG_OAHEADPTR _MMIO(0xdb00)
715 #define GEN12_OAG_OAHEADPTR_MASK 0xffffffc0
716 #define GEN12_OAG_OATAILPTR _MMIO(0xdb04)
717 #define GEN12_OAG_OATAILPTR_MASK 0xffffffc0
718
719 #define GEN12_OAG_OABUFFER _MMIO(0xdb08)
720 #define GEN12_OAG_OABUFFER_BUFFER_SIZE_MASK (0x7)
721 #define GEN12_OAG_OABUFFER_BUFFER_SIZE_SHIFT (3)
722 #define GEN12_OAG_OABUFFER_MEMORY_SELECT (1 << 0) /* 0: PPGTT, 1: GGTT */
723
724 #define GEN12_OAG_OAGLBCTXCTRL _MMIO(0x2b28)
725 #define GEN12_OAG_OAGLBCTXCTRL_TIMER_PERIOD_SHIFT 2
726 #define GEN12_OAG_OAGLBCTXCTRL_TIMER_ENABLE (1 << 1)
727 #define GEN12_OAG_OAGLBCTXCTRL_COUNTER_RESUME (1 << 0)
728
729 #define GEN12_OAG_OACONTROL _MMIO(0xdaf4)
730 #define GEN12_OAG_OACONTROL_OA_COUNTER_FORMAT_SHIFT 2
731 #define GEN12_OAG_OACONTROL_OA_COUNTER_ENABLE (1 << 0)
732
733 #define GEN12_OAG_OA_DEBUG _MMIO(0xdaf8)
734 #define GEN12_OAG_OA_DEBUG_INCLUDE_CLK_RATIO (1 << 6)
735 #define GEN12_OAG_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS (1 << 5)
736 #define GEN12_OAG_OA_DEBUG_DISABLE_GO_1_0_REPORTS (1 << 2)
737 #define GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS (1 << 1)
738
739 #define GEN12_OAG_OASTATUS _MMIO(0xdafc)
740 #define GEN12_OAG_OASTATUS_COUNTER_OVERFLOW (1 << 2)
741 #define GEN12_OAG_OASTATUS_BUFFER_OVERFLOW (1 << 1)
742 #define GEN12_OAG_OASTATUS_REPORT_LOST (1 << 0)
743
744 /*
745 * Flexible, Aggregate EU Counter Registers.
746 * Note: these aren't contiguous
747 */
748 #define EU_PERF_CNTL0 _MMIO(0xe458)
749 #define EU_PERF_CNTL1 _MMIO(0xe558)
750 #define EU_PERF_CNTL2 _MMIO(0xe658)
751 #define EU_PERF_CNTL3 _MMIO(0xe758)
752 #define EU_PERF_CNTL4 _MMIO(0xe45c)
753 #define EU_PERF_CNTL5 _MMIO(0xe55c)
754 #define EU_PERF_CNTL6 _MMIO(0xe65c)
755
756 /*
757 * OA Boolean state
758 */
759
760 #define OASTARTTRIG1 _MMIO(0x2710)
761 #define OASTARTTRIG1_THRESHOLD_COUNT_MASK_MBZ 0xffff0000
762 #define OASTARTTRIG1_THRESHOLD_MASK 0xffff
763
764 #define OASTARTTRIG2 _MMIO(0x2714)
765 #define OASTARTTRIG2_INVERT_A_0 (1 << 0)
766 #define OASTARTTRIG2_INVERT_A_1 (1 << 1)
767 #define OASTARTTRIG2_INVERT_A_2 (1 << 2)
768 #define OASTARTTRIG2_INVERT_A_3 (1 << 3)
769 #define OASTARTTRIG2_INVERT_A_4 (1 << 4)
770 #define OASTARTTRIG2_INVERT_A_5 (1 << 5)
771 #define OASTARTTRIG2_INVERT_A_6 (1 << 6)
772 #define OASTARTTRIG2_INVERT_A_7 (1 << 7)
773 #define OASTARTTRIG2_INVERT_A_8 (1 << 8)
774 #define OASTARTTRIG2_INVERT_A_9 (1 << 9)
775 #define OASTARTTRIG2_INVERT_A_10 (1 << 10)
776 #define OASTARTTRIG2_INVERT_A_11 (1 << 11)
777 #define OASTARTTRIG2_INVERT_A_12 (1 << 12)
778 #define OASTARTTRIG2_INVERT_A_13 (1 << 13)
779 #define OASTARTTRIG2_INVERT_A_14 (1 << 14)
780 #define OASTARTTRIG2_INVERT_A_15 (1 << 15)
781 #define OASTARTTRIG2_INVERT_B_0 (1 << 16)
782 #define OASTARTTRIG2_INVERT_B_1 (1 << 17)
783 #define OASTARTTRIG2_INVERT_B_2 (1 << 18)
784 #define OASTARTTRIG2_INVERT_B_3 (1 << 19)
785 #define OASTARTTRIG2_INVERT_C_0 (1 << 20)
786 #define OASTARTTRIG2_INVERT_C_1 (1 << 21)
787 #define OASTARTTRIG2_INVERT_D_0 (1 << 22)
788 #define OASTARTTRIG2_THRESHOLD_ENABLE (1 << 23)
789 #define OASTARTTRIG2_START_TRIG_FLAG_MBZ (1 << 24)
790 #define OASTARTTRIG2_EVENT_SELECT_0 (1 << 28)
791 #define OASTARTTRIG2_EVENT_SELECT_1 (1 << 29)
792 #define OASTARTTRIG2_EVENT_SELECT_2 (1 << 30)
793 #define OASTARTTRIG2_EVENT_SELECT_3 (1 << 31)
794
795 #define OASTARTTRIG3 _MMIO(0x2718)
796 #define OASTARTTRIG3_NOA_SELECT_MASK 0xf
797 #define OASTARTTRIG3_NOA_SELECT_8_SHIFT 0
798 #define OASTARTTRIG3_NOA_SELECT_9_SHIFT 4
799 #define OASTARTTRIG3_NOA_SELECT_10_SHIFT 8
800 #define OASTARTTRIG3_NOA_SELECT_11_SHIFT 12
801 #define OASTARTTRIG3_NOA_SELECT_12_SHIFT 16
802 #define OASTARTTRIG3_NOA_SELECT_13_SHIFT 20
803 #define OASTARTTRIG3_NOA_SELECT_14_SHIFT 24
804 #define OASTARTTRIG3_NOA_SELECT_15_SHIFT 28
805
806 #define OASTARTTRIG4 _MMIO(0x271c)
807 #define OASTARTTRIG4_NOA_SELECT_MASK 0xf
808 #define OASTARTTRIG4_NOA_SELECT_0_SHIFT 0
809 #define OASTARTTRIG4_NOA_SELECT_1_SHIFT 4
810 #define OASTARTTRIG4_NOA_SELECT_2_SHIFT 8
811 #define OASTARTTRIG4_NOA_SELECT_3_SHIFT 12
812 #define OASTARTTRIG4_NOA_SELECT_4_SHIFT 16
813 #define OASTARTTRIG4_NOA_SELECT_5_SHIFT 20
814 #define OASTARTTRIG4_NOA_SELECT_6_SHIFT 24
815 #define OASTARTTRIG4_NOA_SELECT_7_SHIFT 28
816
817 #define OASTARTTRIG5 _MMIO(0x2720)
818 #define OASTARTTRIG5_THRESHOLD_COUNT_MASK_MBZ 0xffff0000
819 #define OASTARTTRIG5_THRESHOLD_MASK 0xffff
820
821 #define OASTARTTRIG6 _MMIO(0x2724)
822 #define OASTARTTRIG6_INVERT_A_0 (1 << 0)
823 #define OASTARTTRIG6_INVERT_A_1 (1 << 1)
824 #define OASTARTTRIG6_INVERT_A_2 (1 << 2)
825 #define OASTARTTRIG6_INVERT_A_3 (1 << 3)
826 #define OASTARTTRIG6_INVERT_A_4 (1 << 4)
827 #define OASTARTTRIG6_INVERT_A_5 (1 << 5)
828 #define OASTARTTRIG6_INVERT_A_6 (1 << 6)
829 #define OASTARTTRIG6_INVERT_A_7 (1 << 7)
830 #define OASTARTTRIG6_INVERT_A_8 (1 << 8)
831 #define OASTARTTRIG6_INVERT_A_9 (1 << 9)
832 #define OASTARTTRIG6_INVERT_A_10 (1 << 10)
833 #define OASTARTTRIG6_INVERT_A_11 (1 << 11)
834 #define OASTARTTRIG6_INVERT_A_12 (1 << 12)
835 #define OASTARTTRIG6_INVERT_A_13 (1 << 13)
836 #define OASTARTTRIG6_INVERT_A_14 (1 << 14)
837 #define OASTARTTRIG6_INVERT_A_15 (1 << 15)
838 #define OASTARTTRIG6_INVERT_B_0 (1 << 16)
839 #define OASTARTTRIG6_INVERT_B_1 (1 << 17)
840 #define OASTARTTRIG6_INVERT_B_2 (1 << 18)
841 #define OASTARTTRIG6_INVERT_B_3 (1 << 19)
842 #define OASTARTTRIG6_INVERT_C_0 (1 << 20)
843 #define OASTARTTRIG6_INVERT_C_1 (1 << 21)
844 #define OASTARTTRIG6_INVERT_D_0 (1 << 22)
845 #define OASTARTTRIG6_THRESHOLD_ENABLE (1 << 23)
846 #define OASTARTTRIG6_START_TRIG_FLAG_MBZ (1 << 24)
847 #define OASTARTTRIG6_EVENT_SELECT_4 (1 << 28)
848 #define OASTARTTRIG6_EVENT_SELECT_5 (1 << 29)
849 #define OASTARTTRIG6_EVENT_SELECT_6 (1 << 30)
850 #define OASTARTTRIG6_EVENT_SELECT_7 (1 << 31)
851
852 #define OASTARTTRIG7 _MMIO(0x2728)
853 #define OASTARTTRIG7_NOA_SELECT_MASK 0xf
854 #define OASTARTTRIG7_NOA_SELECT_8_SHIFT 0
855 #define OASTARTTRIG7_NOA_SELECT_9_SHIFT 4
856 #define OASTARTTRIG7_NOA_SELECT_10_SHIFT 8
857 #define OASTARTTRIG7_NOA_SELECT_11_SHIFT 12
858 #define OASTARTTRIG7_NOA_SELECT_12_SHIFT 16
859 #define OASTARTTRIG7_NOA_SELECT_13_SHIFT 20
860 #define OASTARTTRIG7_NOA_SELECT_14_SHIFT 24
861 #define OASTARTTRIG7_NOA_SELECT_15_SHIFT 28
862
863 #define OASTARTTRIG8 _MMIO(0x272c)
864 #define OASTARTTRIG8_NOA_SELECT_MASK 0xf
865 #define OASTARTTRIG8_NOA_SELECT_0_SHIFT 0
866 #define OASTARTTRIG8_NOA_SELECT_1_SHIFT 4
867 #define OASTARTTRIG8_NOA_SELECT_2_SHIFT 8
868 #define OASTARTTRIG8_NOA_SELECT_3_SHIFT 12
869 #define OASTARTTRIG8_NOA_SELECT_4_SHIFT 16
870 #define OASTARTTRIG8_NOA_SELECT_5_SHIFT 20
871 #define OASTARTTRIG8_NOA_SELECT_6_SHIFT 24
872 #define OASTARTTRIG8_NOA_SELECT_7_SHIFT 28
873
874 #define OAREPORTTRIG1 _MMIO(0x2740)
875 #define OAREPORTTRIG1_THRESHOLD_MASK 0xffff
876 #define OAREPORTTRIG1_EDGE_LEVEL_TRIGGER_SELECT_MASK 0xffff0000 /* 0=level */
877
878 #define OAREPORTTRIG2 _MMIO(0x2744)
879 #define OAREPORTTRIG2_INVERT_A_0 (1 << 0)
880 #define OAREPORTTRIG2_INVERT_A_1 (1 << 1)
881 #define OAREPORTTRIG2_INVERT_A_2 (1 << 2)
882 #define OAREPORTTRIG2_INVERT_A_3 (1 << 3)
883 #define OAREPORTTRIG2_INVERT_A_4 (1 << 4)
884 #define OAREPORTTRIG2_INVERT_A_5 (1 << 5)
885 #define OAREPORTTRIG2_INVERT_A_6 (1 << 6)
886 #define OAREPORTTRIG2_INVERT_A_7 (1 << 7)
887 #define OAREPORTTRIG2_INVERT_A_8 (1 << 8)
888 #define OAREPORTTRIG2_INVERT_A_9 (1 << 9)
889 #define OAREPORTTRIG2_INVERT_A_10 (1 << 10)
890 #define OAREPORTTRIG2_INVERT_A_11 (1 << 11)
891 #define OAREPORTTRIG2_INVERT_A_12 (1 << 12)
892 #define OAREPORTTRIG2_INVERT_A_13 (1 << 13)
893 #define OAREPORTTRIG2_INVERT_A_14 (1 << 14)
894 #define OAREPORTTRIG2_INVERT_A_15 (1 << 15)
895 #define OAREPORTTRIG2_INVERT_B_0 (1 << 16)
896 #define OAREPORTTRIG2_INVERT_B_1 (1 << 17)
897 #define OAREPORTTRIG2_INVERT_B_2 (1 << 18)
898 #define OAREPORTTRIG2_INVERT_B_3 (1 << 19)
899 #define OAREPORTTRIG2_INVERT_C_0 (1 << 20)
900 #define OAREPORTTRIG2_INVERT_C_1 (1 << 21)
901 #define OAREPORTTRIG2_INVERT_D_0 (1 << 22)
902 #define OAREPORTTRIG2_THRESHOLD_ENABLE (1 << 23)
903 #define OAREPORTTRIG2_REPORT_TRIGGER_ENABLE (1 << 31)
904
905 #define OAREPORTTRIG3 _MMIO(0x2748)
906 #define OAREPORTTRIG3_NOA_SELECT_MASK 0xf
907 #define OAREPORTTRIG3_NOA_SELECT_8_SHIFT 0
908 #define OAREPORTTRIG3_NOA_SELECT_9_SHIFT 4
909 #define OAREPORTTRIG3_NOA_SELECT_10_SHIFT 8
910 #define OAREPORTTRIG3_NOA_SELECT_11_SHIFT 12
911 #define OAREPORTTRIG3_NOA_SELECT_12_SHIFT 16
912 #define OAREPORTTRIG3_NOA_SELECT_13_SHIFT 20
913 #define OAREPORTTRIG3_NOA_SELECT_14_SHIFT 24
914 #define OAREPORTTRIG3_NOA_SELECT_15_SHIFT 28
915
916 #define OAREPORTTRIG4 _MMIO(0x274c)
917 #define OAREPORTTRIG4_NOA_SELECT_MASK 0xf
918 #define OAREPORTTRIG4_NOA_SELECT_0_SHIFT 0
919 #define OAREPORTTRIG4_NOA_SELECT_1_SHIFT 4
920 #define OAREPORTTRIG4_NOA_SELECT_2_SHIFT 8
921 #define OAREPORTTRIG4_NOA_SELECT_3_SHIFT 12
922 #define OAREPORTTRIG4_NOA_SELECT_4_SHIFT 16
923 #define OAREPORTTRIG4_NOA_SELECT_5_SHIFT 20
924 #define OAREPORTTRIG4_NOA_SELECT_6_SHIFT 24
925 #define OAREPORTTRIG4_NOA_SELECT_7_SHIFT 28
926
927 #define OAREPORTTRIG5 _MMIO(0x2750)
928 #define OAREPORTTRIG5_THRESHOLD_MASK 0xffff
929 #define OAREPORTTRIG5_EDGE_LEVEL_TRIGGER_SELECT_MASK 0xffff0000 /* 0=level */
930
931 #define OAREPORTTRIG6 _MMIO(0x2754)
932 #define OAREPORTTRIG6_INVERT_A_0 (1 << 0)
933 #define OAREPORTTRIG6_INVERT_A_1 (1 << 1)
934 #define OAREPORTTRIG6_INVERT_A_2 (1 << 2)
935 #define OAREPORTTRIG6_INVERT_A_3 (1 << 3)
936 #define OAREPORTTRIG6_INVERT_A_4 (1 << 4)
937 #define OAREPORTTRIG6_INVERT_A_5 (1 << 5)
938 #define OAREPORTTRIG6_INVERT_A_6 (1 << 6)
939 #define OAREPORTTRIG6_INVERT_A_7 (1 << 7)
940 #define OAREPORTTRIG6_INVERT_A_8 (1 << 8)
941 #define OAREPORTTRIG6_INVERT_A_9 (1 << 9)
942 #define OAREPORTTRIG6_INVERT_A_10 (1 << 10)
943 #define OAREPORTTRIG6_INVERT_A_11 (1 << 11)
944 #define OAREPORTTRIG6_INVERT_A_12 (1 << 12)
945 #define OAREPORTTRIG6_INVERT_A_13 (1 << 13)
946 #define OAREPORTTRIG6_INVERT_A_14 (1 << 14)
947 #define OAREPORTTRIG6_INVERT_A_15 (1 << 15)
948 #define OAREPORTTRIG6_INVERT_B_0 (1 << 16)
949 #define OAREPORTTRIG6_INVERT_B_1 (1 << 17)
950 #define OAREPORTTRIG6_INVERT_B_2 (1 << 18)
951 #define OAREPORTTRIG6_INVERT_B_3 (1 << 19)
952 #define OAREPORTTRIG6_INVERT_C_0 (1 << 20)
953 #define OAREPORTTRIG6_INVERT_C_1 (1 << 21)
954 #define OAREPORTTRIG6_INVERT_D_0 (1 << 22)
955 #define OAREPORTTRIG6_THRESHOLD_ENABLE (1 << 23)
956 #define OAREPORTTRIG6_REPORT_TRIGGER_ENABLE (1 << 31)
957
958 #define OAREPORTTRIG7 _MMIO(0x2758)
959 #define OAREPORTTRIG7_NOA_SELECT_MASK 0xf
960 #define OAREPORTTRIG7_NOA_SELECT_8_SHIFT 0
961 #define OAREPORTTRIG7_NOA_SELECT_9_SHIFT 4
962 #define OAREPORTTRIG7_NOA_SELECT_10_SHIFT 8
963 #define OAREPORTTRIG7_NOA_SELECT_11_SHIFT 12
964 #define OAREPORTTRIG7_NOA_SELECT_12_SHIFT 16
965 #define OAREPORTTRIG7_NOA_SELECT_13_SHIFT 20
966 #define OAREPORTTRIG7_NOA_SELECT_14_SHIFT 24
967 #define OAREPORTTRIG7_NOA_SELECT_15_SHIFT 28
968
969 #define OAREPORTTRIG8 _MMIO(0x275c)
970 #define OAREPORTTRIG8_NOA_SELECT_MASK 0xf
971 #define OAREPORTTRIG8_NOA_SELECT_0_SHIFT 0
972 #define OAREPORTTRIG8_NOA_SELECT_1_SHIFT 4
973 #define OAREPORTTRIG8_NOA_SELECT_2_SHIFT 8
974 #define OAREPORTTRIG8_NOA_SELECT_3_SHIFT 12
975 #define OAREPORTTRIG8_NOA_SELECT_4_SHIFT 16
976 #define OAREPORTTRIG8_NOA_SELECT_5_SHIFT 20
977 #define OAREPORTTRIG8_NOA_SELECT_6_SHIFT 24
978 #define OAREPORTTRIG8_NOA_SELECT_7_SHIFT 28
979
980 /* Same layout as OASTARTTRIGX */
981 #define GEN12_OAG_OASTARTTRIG1 _MMIO(0xd900)
982 #define GEN12_OAG_OASTARTTRIG2 _MMIO(0xd904)
983 #define GEN12_OAG_OASTARTTRIG3 _MMIO(0xd908)
984 #define GEN12_OAG_OASTARTTRIG4 _MMIO(0xd90c)
985 #define GEN12_OAG_OASTARTTRIG5 _MMIO(0xd910)
986 #define GEN12_OAG_OASTARTTRIG6 _MMIO(0xd914)
987 #define GEN12_OAG_OASTARTTRIG7 _MMIO(0xd918)
988 #define GEN12_OAG_OASTARTTRIG8 _MMIO(0xd91c)
989
990 /* Same layout as OAREPORTTRIGX */
991 #define GEN12_OAG_OAREPORTTRIG1 _MMIO(0xd920)
992 #define GEN12_OAG_OAREPORTTRIG2 _MMIO(0xd924)
993 #define GEN12_OAG_OAREPORTTRIG3 _MMIO(0xd928)
994 #define GEN12_OAG_OAREPORTTRIG4 _MMIO(0xd92c)
995 #define GEN12_OAG_OAREPORTTRIG5 _MMIO(0xd930)
996 #define GEN12_OAG_OAREPORTTRIG6 _MMIO(0xd934)
997 #define GEN12_OAG_OAREPORTTRIG7 _MMIO(0xd938)
998 #define GEN12_OAG_OAREPORTTRIG8 _MMIO(0xd93c)
999
1000 /* CECX_0 */
1001 #define OACEC_COMPARE_LESS_OR_EQUAL 6
1002 #define OACEC_COMPARE_NOT_EQUAL 5
1003 #define OACEC_COMPARE_LESS_THAN 4
1004 #define OACEC_COMPARE_GREATER_OR_EQUAL 3
1005 #define OACEC_COMPARE_EQUAL 2
1006 #define OACEC_COMPARE_GREATER_THAN 1
1007 #define OACEC_COMPARE_ANY_EQUAL 0
1008
1009 #define OACEC_COMPARE_VALUE_MASK 0xffff
1010 #define OACEC_COMPARE_VALUE_SHIFT 3
1011
1012 #define OACEC_SELECT_NOA (0 << 19)
1013 #define OACEC_SELECT_PREV (1 << 19)
1014 #define OACEC_SELECT_BOOLEAN (2 << 19)
1015
1016 /* 11-bit array 0: pass-through, 1: negated */
1017 #define GEN12_OASCEC_NEGATE_MASK 0x7ff
1018 #define GEN12_OASCEC_NEGATE_SHIFT 21
1019
1020 /* CECX_1 */
1021 #define OACEC_MASK_MASK 0xffff
1022 #define OACEC_CONSIDERATIONS_MASK 0xffff
1023 #define OACEC_CONSIDERATIONS_SHIFT 16
1024
1025 #define OACEC0_0 _MMIO(0x2770)
1026 #define OACEC0_1 _MMIO(0x2774)
1027 #define OACEC1_0 _MMIO(0x2778)
1028 #define OACEC1_1 _MMIO(0x277c)
1029 #define OACEC2_0 _MMIO(0x2780)
1030 #define OACEC2_1 _MMIO(0x2784)
1031 #define OACEC3_0 _MMIO(0x2788)
1032 #define OACEC3_1 _MMIO(0x278c)
1033 #define OACEC4_0 _MMIO(0x2790)
1034 #define OACEC4_1 _MMIO(0x2794)
1035 #define OACEC5_0 _MMIO(0x2798)
1036 #define OACEC5_1 _MMIO(0x279c)
1037 #define OACEC6_0 _MMIO(0x27a0)
1038 #define OACEC6_1 _MMIO(0x27a4)
1039 #define OACEC7_0 _MMIO(0x27a8)
1040 #define OACEC7_1 _MMIO(0x27ac)
1041
1042 /* Same layout as CECX_Y */
1043 #define GEN12_OAG_CEC0_0 _MMIO(0xd940)
1044 #define GEN12_OAG_CEC0_1 _MMIO(0xd944)
1045 #define GEN12_OAG_CEC1_0 _MMIO(0xd948)
1046 #define GEN12_OAG_CEC1_1 _MMIO(0xd94c)
1047 #define GEN12_OAG_CEC2_0 _MMIO(0xd950)
1048 #define GEN12_OAG_CEC2_1 _MMIO(0xd954)
1049 #define GEN12_OAG_CEC3_0 _MMIO(0xd958)
1050 #define GEN12_OAG_CEC3_1 _MMIO(0xd95c)
1051 #define GEN12_OAG_CEC4_0 _MMIO(0xd960)
1052 #define GEN12_OAG_CEC4_1 _MMIO(0xd964)
1053 #define GEN12_OAG_CEC5_0 _MMIO(0xd968)
1054 #define GEN12_OAG_CEC5_1 _MMIO(0xd96c)
1055 #define GEN12_OAG_CEC6_0 _MMIO(0xd970)
1056 #define GEN12_OAG_CEC6_1 _MMIO(0xd974)
1057 #define GEN12_OAG_CEC7_0 _MMIO(0xd978)
1058 #define GEN12_OAG_CEC7_1 _MMIO(0xd97c)
1059
1060 /* Same layout as CECX_Y + negate 11-bit array */
1061 #define GEN12_OAG_SCEC0_0 _MMIO(0xdc00)
1062 #define GEN12_OAG_SCEC0_1 _MMIO(0xdc04)
1063 #define GEN12_OAG_SCEC1_0 _MMIO(0xdc08)
1064 #define GEN12_OAG_SCEC1_1 _MMIO(0xdc0c)
1065 #define GEN12_OAG_SCEC2_0 _MMIO(0xdc10)
1066 #define GEN12_OAG_SCEC2_1 _MMIO(0xdc14)
1067 #define GEN12_OAG_SCEC3_0 _MMIO(0xdc18)
1068 #define GEN12_OAG_SCEC3_1 _MMIO(0xdc1c)
1069 #define GEN12_OAG_SCEC4_0 _MMIO(0xdc20)
1070 #define GEN12_OAG_SCEC4_1 _MMIO(0xdc24)
1071 #define GEN12_OAG_SCEC5_0 _MMIO(0xdc28)
1072 #define GEN12_OAG_SCEC5_1 _MMIO(0xdc2c)
1073 #define GEN12_OAG_SCEC6_0 _MMIO(0xdc30)
1074 #define GEN12_OAG_SCEC6_1 _MMIO(0xdc34)
1075 #define GEN12_OAG_SCEC7_0 _MMIO(0xdc38)
1076 #define GEN12_OAG_SCEC7_1 _MMIO(0xdc3c)
1077
1078 /* OA perf counters */
1079 #define OA_PERFCNT1_LO _MMIO(0x91B8)
1080 #define OA_PERFCNT1_HI _MMIO(0x91BC)
1081 #define OA_PERFCNT2_LO _MMIO(0x91C0)
1082 #define OA_PERFCNT2_HI _MMIO(0x91C4)
1083 #define OA_PERFCNT3_LO _MMIO(0x91C8)
1084 #define OA_PERFCNT3_HI _MMIO(0x91CC)
1085 #define OA_PERFCNT4_LO _MMIO(0x91D8)
1086 #define OA_PERFCNT4_HI _MMIO(0x91DC)
1087
1088 #define OA_PERFMATRIX_LO _MMIO(0x91C8)
1089 #define OA_PERFMATRIX_HI _MMIO(0x91CC)
1090
1091 /* RPM unit config (Gen8+) */
1092 #define RPM_CONFIG0 _MMIO(0x0D00)
1093 #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3
1094 #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (1 << GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
1095 #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 0
1096 #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 1
1097 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3
1098 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (0x7 << GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
1099 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 0
1100 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 1
1101 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ 2
1102 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ 3
1103 #define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT 1
1104 #define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK (0x3 << GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT)
1105
1106 #define RPM_CONFIG1 _MMIO(0x0D04)
1107 #define GEN10_GT_NOA_ENABLE (1 << 9)
1108
1109 /* GPM unit config (Gen9+) */
1110 #define CTC_MODE _MMIO(0xA26C)
1111 #define CTC_SOURCE_PARAMETER_MASK 1
1112 #define CTC_SOURCE_CRYSTAL_CLOCK 0
1113 #define CTC_SOURCE_DIVIDE_LOGIC 1
1114 #define CTC_SHIFT_PARAMETER_SHIFT 1
1115 #define CTC_SHIFT_PARAMETER_MASK (0x3 << CTC_SHIFT_PARAMETER_SHIFT)
1116
1117 /* RCP unit config (Gen8+) */
1118 #define RCP_CONFIG _MMIO(0x0D08)
1119
1120 /* NOA (HSW) */
1121 #define HSW_MBVID2_NOA0 _MMIO(0x9E80)
1122 #define HSW_MBVID2_NOA1 _MMIO(0x9E84)
1123 #define HSW_MBVID2_NOA2 _MMIO(0x9E88)
1124 #define HSW_MBVID2_NOA3 _MMIO(0x9E8C)
1125 #define HSW_MBVID2_NOA4 _MMIO(0x9E90)
1126 #define HSW_MBVID2_NOA5 _MMIO(0x9E94)
1127 #define HSW_MBVID2_NOA6 _MMIO(0x9E98)
1128 #define HSW_MBVID2_NOA7 _MMIO(0x9E9C)
1129 #define HSW_MBVID2_NOA8 _MMIO(0x9EA0)
1130 #define HSW_MBVID2_NOA9 _MMIO(0x9EA4)
1131
1132 #define HSW_MBVID2_MISR0 _MMIO(0x9EC0)
1133
1134 /* NOA (Gen8+) */
1135 #define NOA_CONFIG(i) _MMIO(0x0D0C + (i) * 4)
1136
1137 #define MICRO_BP0_0 _MMIO(0x9800)
1138 #define MICRO_BP0_2 _MMIO(0x9804)
1139 #define MICRO_BP0_1 _MMIO(0x9808)
1140
1141 #define MICRO_BP1_0 _MMIO(0x980C)
1142 #define MICRO_BP1_2 _MMIO(0x9810)
1143 #define MICRO_BP1_1 _MMIO(0x9814)
1144
1145 #define MICRO_BP2_0 _MMIO(0x9818)
1146 #define MICRO_BP2_2 _MMIO(0x981C)
1147 #define MICRO_BP2_1 _MMIO(0x9820)
1148
1149 #define MICRO_BP3_0 _MMIO(0x9824)
1150 #define MICRO_BP3_2 _MMIO(0x9828)
1151 #define MICRO_BP3_1 _MMIO(0x982C)
1152
1153 #define MICRO_BP_TRIGGER _MMIO(0x9830)
1154 #define MICRO_BP3_COUNT_STATUS01 _MMIO(0x9834)
1155 #define MICRO_BP3_COUNT_STATUS23 _MMIO(0x9838)
1156 #define MICRO_BP_FIRED_ARMED _MMIO(0x983C)
1157
1158 #define GEN12_OAA_DBG_REG _MMIO(0xdc44)
1159 #define GEN12_OAG_OA_PESS _MMIO(0x2b2c)
1160 #define GEN12_OAG_SPCTR_CNF _MMIO(0xdc40)
1161
1162 #define GDT_CHICKEN_BITS _MMIO(0x9840)
1163 #define GT_NOA_ENABLE 0x00000080
1164
1165 #define NOA_DATA _MMIO(0x986C)
1166 #define NOA_WRITE _MMIO(0x9888)
1167 #define GEN10_NOA_WRITE_HIGH _MMIO(0x9884)
1168
1169 #define _GEN7_PIPEA_DE_LOAD_SL 0x70068
1170 #define _GEN7_PIPEB_DE_LOAD_SL 0x71068
1171 #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL)
1172
1173 /*
1174 * Reset registers
1175 */
1176 #define DEBUG_RESET_I830 _MMIO(0x6070)
1177 #define DEBUG_RESET_FULL (1 << 7)
1178 #define DEBUG_RESET_RENDER (1 << 8)
1179 #define DEBUG_RESET_DISPLAY (1 << 9)
1180
1181 /*
1182 * IOSF sideband
1183 */
1184 #define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100)
1185 #define IOSF_DEVFN_SHIFT 24
1186 #define IOSF_OPCODE_SHIFT 16
1187 #define IOSF_PORT_SHIFT 8
1188 #define IOSF_BYTE_ENABLES_SHIFT 4
1189 #define IOSF_BAR_SHIFT 1
1190 #define IOSF_SB_BUSY (1 << 0)
1191 #define IOSF_PORT_BUNIT 0x03
1192 #define IOSF_PORT_PUNIT 0x04
1193 #define IOSF_PORT_NC 0x11
1194 #define IOSF_PORT_DPIO 0x12
1195 #define IOSF_PORT_GPIO_NC 0x13
1196 #define IOSF_PORT_CCK 0x14
1197 #define IOSF_PORT_DPIO_2 0x1a
1198 #define IOSF_PORT_FLISDSI 0x1b
1199 #define IOSF_PORT_GPIO_SC 0x48
1200 #define IOSF_PORT_GPIO_SUS 0xa8
1201 #define IOSF_PORT_CCU 0xa9
1202 #define CHV_IOSF_PORT_GPIO_N 0x13
1203 #define CHV_IOSF_PORT_GPIO_SE 0x48
1204 #define CHV_IOSF_PORT_GPIO_E 0xa8
1205 #define CHV_IOSF_PORT_GPIO_SW 0xb2
1206 #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104)
1207 #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108)
1208
1209 /* See configdb bunit SB addr map */
1210 #define BUNIT_REG_BISOC 0x11
1211
1212 /* PUNIT_REG_*SSPM0 */
1213 #define _SSPM0_SSC(val) ((val) << 0)
1214 #define SSPM0_SSC_MASK _SSPM0_SSC(0x3)
1215 #define SSPM0_SSC_PWR_ON _SSPM0_SSC(0x0)
1216 #define SSPM0_SSC_CLK_GATE _SSPM0_SSC(0x1)
1217 #define SSPM0_SSC_RESET _SSPM0_SSC(0x2)
1218 #define SSPM0_SSC_PWR_GATE _SSPM0_SSC(0x3)
1219 #define _SSPM0_SSS(val) ((val) << 24)
1220 #define SSPM0_SSS_MASK _SSPM0_SSS(0x3)
1221 #define SSPM0_SSS_PWR_ON _SSPM0_SSS(0x0)
1222 #define SSPM0_SSS_CLK_GATE _SSPM0_SSS(0x1)
1223 #define SSPM0_SSS_RESET _SSPM0_SSS(0x2)
1224 #define SSPM0_SSS_PWR_GATE _SSPM0_SSS(0x3)
1225
1226 /* PUNIT_REG_*SSPM1 */
1227 #define SSPM1_FREQSTAT_SHIFT 24
1228 #define SSPM1_FREQSTAT_MASK (0x1f << SSPM1_FREQSTAT_SHIFT)
1229 #define SSPM1_FREQGUAR_SHIFT 8
1230 #define SSPM1_FREQGUAR_MASK (0x1f << SSPM1_FREQGUAR_SHIFT)
1231 #define SSPM1_FREQ_SHIFT 0
1232 #define SSPM1_FREQ_MASK (0x1f << SSPM1_FREQ_SHIFT)
1233
1234 #define PUNIT_REG_VEDSSPM0 0x32
1235 #define PUNIT_REG_VEDSSPM1 0x33
1236
1237 #define PUNIT_REG_DSPSSPM 0x36
1238 #define DSPFREQSTAT_SHIFT_CHV 24
1239 #define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV)
1240 #define DSPFREQGUAR_SHIFT_CHV 8
1241 #define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV)
1242 #define DSPFREQSTAT_SHIFT 30
1243 #define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT)
1244 #define DSPFREQGUAR_SHIFT 14
1245 #define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT)
1246 #define DSP_MAXFIFO_PM5_STATUS (1 << 22) /* chv */
1247 #define DSP_AUTO_CDCLK_GATE_DISABLE (1 << 7) /* chv */
1248 #define DSP_MAXFIFO_PM5_ENABLE (1 << 6) /* chv */
1249 #define _DP_SSC(val, pipe) ((val) << (2 * (pipe)))
1250 #define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe))
1251 #define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe))
1252 #define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe))
1253 #define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe))
1254 #define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe))
1255 #define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16))
1256 #define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe))
1257 #define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe))
1258 #define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe))
1259 #define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe))
1260 #define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe))
1261
1262 #define PUNIT_REG_ISPSSPM0 0x39
1263 #define PUNIT_REG_ISPSSPM1 0x3a
1264
1265 #define PUNIT_REG_PWRGT_CTRL 0x60
1266 #define PUNIT_REG_PWRGT_STATUS 0x61
1267 #define PUNIT_PWRGT_MASK(pw_idx) (3 << ((pw_idx) * 2))
1268 #define PUNIT_PWRGT_PWR_ON(pw_idx) (0 << ((pw_idx) * 2))
1269 #define PUNIT_PWRGT_CLK_GATE(pw_idx) (1 << ((pw_idx) * 2))
1270 #define PUNIT_PWRGT_RESET(pw_idx) (2 << ((pw_idx) * 2))
1271 #define PUNIT_PWRGT_PWR_GATE(pw_idx) (3 << ((pw_idx) * 2))
1272
1273 #define PUNIT_PWGT_IDX_RENDER 0
1274 #define PUNIT_PWGT_IDX_MEDIA 1
1275 #define PUNIT_PWGT_IDX_DISP2D 3
1276 #define PUNIT_PWGT_IDX_DPIO_CMN_BC 5
1277 #define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01 6
1278 #define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23 7
1279 #define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01 8
1280 #define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23 9
1281 #define PUNIT_PWGT_IDX_DPIO_RX0 10
1282 #define PUNIT_PWGT_IDX_DPIO_RX1 11
1283 #define PUNIT_PWGT_IDX_DPIO_CMN_D 12
1284
1285 #define PUNIT_REG_GPU_LFM 0xd3
1286 #define PUNIT_REG_GPU_FREQ_REQ 0xd4
1287 #define PUNIT_REG_GPU_FREQ_STS 0xd8
1288 #define GPLLENABLE (1 << 4)
1289 #define GENFREQSTATUS (1 << 0)
1290 #define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc
1291 #define PUNIT_REG_CZ_TIMESTAMP 0xce
1292
1293 #define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
1294 #define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
1295
1296 #define FB_GFX_FMAX_AT_VMAX_FUSE 0x136
1297 #define FB_GFX_FREQ_FUSE_MASK 0xff
1298 #define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24
1299 #define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16
1300 #define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8
1301
1302 #define FB_GFX_FMIN_AT_VMIN_FUSE 0x137
1303 #define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8
1304
1305 #define PUNIT_REG_DDR_SETUP2 0x139
1306 #define FORCE_DDR_FREQ_REQ_ACK (1 << 8)
1307 #define FORCE_DDR_LOW_FREQ (1 << 1)
1308 #define FORCE_DDR_HIGH_FREQ (1 << 0)
1309
1310 #define PUNIT_GPU_STATUS_REG 0xdb
1311 #define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16
1312 #define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
1313 #define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8
1314 #define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff
1315
1316 #define PUNIT_GPU_DUTYCYCLE_REG 0xdf
1317 #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8
1318 #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff
1319
1320 #define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
1321 #define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
1322 #define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8
1323 #define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11
1324 #define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800
1325 #define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34
1326 #define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007
1327 #define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30
1328 #define FB_FMAX_VMIN_FREQ_LO_SHIFT 27
1329 #define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000
1330
1331 #define VLV_TURBO_SOC_OVERRIDE 0x04
1332 #define VLV_OVERRIDE_EN 1
1333 #define VLV_SOC_TDP_EN (1 << 1)
1334 #define VLV_BIAS_CPU_125_SOC_875 (6 << 2)
1335 #define CHV_BIAS_CPU_50_SOC_50 (3 << 2)
1336
1337 /* vlv2 north clock has */
1338 #define CCK_FUSE_REG 0x8
1339 #define CCK_FUSE_HPLL_FREQ_MASK 0x3
1340 #define CCK_REG_DSI_PLL_FUSE 0x44
1341 #define CCK_REG_DSI_PLL_CONTROL 0x48
1342 #define DSI_PLL_VCO_EN (1 << 31)
1343 #define DSI_PLL_LDO_GATE (1 << 30)
1344 #define DSI_PLL_P1_POST_DIV_SHIFT 17
1345 #define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17)
1346 #define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13)
1347 #define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12)
1348 #define DSI_PLL_MUX_MASK (3 << 9)
1349 #define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10)
1350 #define DSI_PLL_MUX_DSI0_CCK (1 << 10)
1351 #define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9)
1352 #define DSI_PLL_MUX_DSI1_CCK (1 << 9)
1353 #define DSI_PLL_CLK_GATE_MASK (0xf << 5)
1354 #define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8)
1355 #define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7)
1356 #define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6)
1357 #define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5)
1358 #define DSI_PLL_LOCK (1 << 0)
1359 #define CCK_REG_DSI_PLL_DIVIDER 0x4c
1360 #define DSI_PLL_LFSR (1 << 31)
1361 #define DSI_PLL_FRACTION_EN (1 << 30)
1362 #define DSI_PLL_FRAC_COUNTER_SHIFT 27
1363 #define DSI_PLL_FRAC_COUNTER_MASK (7 << 27)
1364 #define DSI_PLL_USYNC_CNT_SHIFT 18
1365 #define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18)
1366 #define DSI_PLL_N1_DIV_SHIFT 16
1367 #define DSI_PLL_N1_DIV_MASK (3 << 16)
1368 #define DSI_PLL_M1_DIV_SHIFT 0
1369 #define DSI_PLL_M1_DIV_MASK (0x1ff << 0)
1370 #define CCK_CZ_CLOCK_CONTROL 0x62
1371 #define CCK_GPLL_CLOCK_CONTROL 0x67
1372 #define CCK_DISPLAY_CLOCK_CONTROL 0x6b
1373 #define CCK_DISPLAY_REF_CLOCK_CONTROL 0x6c
1374 #define CCK_TRUNK_FORCE_ON (1 << 17)
1375 #define CCK_TRUNK_FORCE_OFF (1 << 16)
1376 #define CCK_FREQUENCY_STATUS (0x1f << 8)
1377 #define CCK_FREQUENCY_STATUS_SHIFT 8
1378 #define CCK_FREQUENCY_VALUES (0x1f << 0)
1379
1380 /* DPIO registers */
1381 #define DPIO_DEVFN 0
1382
1383 #define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110)
1384 #define DPIO_MODSEL1 (1 << 3) /* if ref clk b == 27 */
1385 #define DPIO_MODSEL0 (1 << 2) /* if ref clk a == 27 */
1386 #define DPIO_SFR_BYPASS (1 << 1)
1387 #define DPIO_CMNRST (1 << 0)
1388
1389 #define DPIO_PHY(pipe) ((pipe) >> 1)
1390
1391 /*
1392 * Per pipe/PLL DPIO regs
1393 */
1394 #define _VLV_PLL_DW3_CH0 0x800c
1395 #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */
1396 #define DPIO_POST_DIV_DAC 0
1397 #define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */
1398 #define DPIO_POST_DIV_LVDS1 2
1399 #define DPIO_POST_DIV_LVDS2 3
1400 #define DPIO_K_SHIFT (24) /* 4 bits */
1401 #define DPIO_P1_SHIFT (21) /* 3 bits */
1402 #define DPIO_P2_SHIFT (16) /* 5 bits */
1403 #define DPIO_N_SHIFT (12) /* 4 bits */
1404 #define DPIO_ENABLE_CALIBRATION (1 << 11)
1405 #define DPIO_M1DIV_SHIFT (8) /* 3 bits */
1406 #define DPIO_M2DIV_MASK 0xff
1407 #define _VLV_PLL_DW3_CH1 0x802c
1408 #define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)
1409
1410 #define _VLV_PLL_DW5_CH0 0x8014
1411 #define DPIO_REFSEL_OVERRIDE 27
1412 #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */
1413 #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */
1414 #define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */
1415 #define DPIO_PLL_REFCLK_SEL_MASK 3
1416 #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */
1417 #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */
1418 #define _VLV_PLL_DW5_CH1 0x8034
1419 #define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)
1420
1421 #define _VLV_PLL_DW7_CH0 0x801c
1422 #define _VLV_PLL_DW7_CH1 0x803c
1423 #define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
1424
1425 #define _VLV_PLL_DW8_CH0 0x8040
1426 #define _VLV_PLL_DW8_CH1 0x8060
1427 #define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
1428
1429 #define VLV_PLL_DW9_BCAST 0xc044
1430 #define _VLV_PLL_DW9_CH0 0x8044
1431 #define _VLV_PLL_DW9_CH1 0x8064
1432 #define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
1433
1434 #define _VLV_PLL_DW10_CH0 0x8048
1435 #define _VLV_PLL_DW10_CH1 0x8068
1436 #define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1)
1437
1438 #define _VLV_PLL_DW11_CH0 0x804c
1439 #define _VLV_PLL_DW11_CH1 0x806c
1440 #define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)
1441
1442 /* Spec for ref block start counts at DW10 */
1443 #define VLV_REF_DW13 0x80ac
1444
1445 #define VLV_CMN_DW0 0x8100
1446
1447 /*
1448 * Per DDI channel DPIO regs
1449 */
1450
1451 #define _VLV_PCS_DW0_CH0 0x8200
1452 #define _VLV_PCS_DW0_CH1 0x8400
1453 #define DPIO_PCS_TX_LANE2_RESET (1 << 16)
1454 #define DPIO_PCS_TX_LANE1_RESET (1 << 7)
1455 #define DPIO_LEFT_TXFIFO_RST_MASTER2 (1 << 4)
1456 #define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1 << 3)
1457 #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
1458
1459 #define _VLV_PCS01_DW0_CH0 0x200
1460 #define _VLV_PCS23_DW0_CH0 0x400
1461 #define _VLV_PCS01_DW0_CH1 0x2600
1462 #define _VLV_PCS23_DW0_CH1 0x2800
1463 #define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
1464 #define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
1465
1466 #define _VLV_PCS_DW1_CH0 0x8204
1467 #define _VLV_PCS_DW1_CH1 0x8404
1468 #define CHV_PCS_REQ_SOFTRESET_EN (1 << 23)
1469 #define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1 << 22)
1470 #define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1 << 21)
1471 #define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6)
1472 #define DPIO_PCS_CLK_SOFT_RESET (1 << 5)
1473 #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
1474
1475 #define _VLV_PCS01_DW1_CH0 0x204
1476 #define _VLV_PCS23_DW1_CH0 0x404
1477 #define _VLV_PCS01_DW1_CH1 0x2604
1478 #define _VLV_PCS23_DW1_CH1 0x2804
1479 #define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
1480 #define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)
1481
1482 #define _VLV_PCS_DW8_CH0 0x8220
1483 #define _VLV_PCS_DW8_CH1 0x8420
1484 #define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20)
1485 #define CHV_PCS_USEDCLKCHANNEL (1 << 21)
1486 #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
1487
1488 #define _VLV_PCS01_DW8_CH0 0x0220
1489 #define _VLV_PCS23_DW8_CH0 0x0420
1490 #define _VLV_PCS01_DW8_CH1 0x2620
1491 #define _VLV_PCS23_DW8_CH1 0x2820
1492 #define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
1493 #define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)
1494
1495 #define _VLV_PCS_DW9_CH0 0x8224
1496 #define _VLV_PCS_DW9_CH1 0x8424
1497 #define DPIO_PCS_TX2MARGIN_MASK (0x7 << 13)
1498 #define DPIO_PCS_TX2MARGIN_000 (0 << 13)
1499 #define DPIO_PCS_TX2MARGIN_101 (1 << 13)
1500 #define DPIO_PCS_TX1MARGIN_MASK (0x7 << 10)
1501 #define DPIO_PCS_TX1MARGIN_000 (0 << 10)
1502 #define DPIO_PCS_TX1MARGIN_101 (1 << 10)
1503 #define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
1504
1505 #define _VLV_PCS01_DW9_CH0 0x224
1506 #define _VLV_PCS23_DW9_CH0 0x424
1507 #define _VLV_PCS01_DW9_CH1 0x2624
1508 #define _VLV_PCS23_DW9_CH1 0x2824
1509 #define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1)
1510 #define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1)
1511
1512 #define _CHV_PCS_DW10_CH0 0x8228
1513 #define _CHV_PCS_DW10_CH1 0x8428
1514 #define DPIO_PCS_SWING_CALC_TX0_TX2 (1 << 30)
1515 #define DPIO_PCS_SWING_CALC_TX1_TX3 (1 << 31)
1516 #define DPIO_PCS_TX2DEEMP_MASK (0xf << 24)
1517 #define DPIO_PCS_TX2DEEMP_9P5 (0 << 24)
1518 #define DPIO_PCS_TX2DEEMP_6P0 (2 << 24)
1519 #define DPIO_PCS_TX1DEEMP_MASK (0xf << 16)
1520 #define DPIO_PCS_TX1DEEMP_9P5 (0 << 16)
1521 #define DPIO_PCS_TX1DEEMP_6P0 (2 << 16)
1522 #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
1523
1524 #define _VLV_PCS01_DW10_CH0 0x0228
1525 #define _VLV_PCS23_DW10_CH0 0x0428
1526 #define _VLV_PCS01_DW10_CH1 0x2628
1527 #define _VLV_PCS23_DW10_CH1 0x2828
1528 #define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)
1529 #define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)
1530
1531 #define _VLV_PCS_DW11_CH0 0x822c
1532 #define _VLV_PCS_DW11_CH1 0x842c
1533 #define DPIO_TX2_STAGGER_MASK(x) ((x) << 24)
1534 #define DPIO_LANEDESKEW_STRAP_OVRD (1 << 3)
1535 #define DPIO_LEFT_TXFIFO_RST_MASTER (1 << 1)
1536 #define DPIO_RIGHT_TXFIFO_RST_MASTER (1 << 0)
1537 #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
1538
1539 #define _VLV_PCS01_DW11_CH0 0x022c
1540 #define _VLV_PCS23_DW11_CH0 0x042c
1541 #define _VLV_PCS01_DW11_CH1 0x262c
1542 #define _VLV_PCS23_DW11_CH1 0x282c
1543 #define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1)
1544 #define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1)
1545
1546 #define _VLV_PCS01_DW12_CH0 0x0230
1547 #define _VLV_PCS23_DW12_CH0 0x0430
1548 #define _VLV_PCS01_DW12_CH1 0x2630
1549 #define _VLV_PCS23_DW12_CH1 0x2830
1550 #define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1)
1551 #define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1)
1552
1553 #define _VLV_PCS_DW12_CH0 0x8230
1554 #define _VLV_PCS_DW12_CH1 0x8430
1555 #define DPIO_TX2_STAGGER_MULT(x) ((x) << 20)
1556 #define DPIO_TX1_STAGGER_MULT(x) ((x) << 16)
1557 #define DPIO_TX1_STAGGER_MASK(x) ((x) << 8)
1558 #define DPIO_LANESTAGGER_STRAP_OVRD (1 << 6)
1559 #define DPIO_LANESTAGGER_STRAP(x) ((x) << 0)
1560 #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
1561
1562 #define _VLV_PCS_DW14_CH0 0x8238
1563 #define _VLV_PCS_DW14_CH1 0x8438
1564 #define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)
1565
1566 #define _VLV_PCS_DW23_CH0 0x825c
1567 #define _VLV_PCS_DW23_CH1 0x845c
1568 #define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)
1569
1570 #define _VLV_TX_DW2_CH0 0x8288
1571 #define _VLV_TX_DW2_CH1 0x8488
1572 #define DPIO_SWING_MARGIN000_SHIFT 16
1573 #define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT)
1574 #define DPIO_UNIQ_TRANS_SCALE_SHIFT 8
1575 #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
1576
1577 #define _VLV_TX_DW3_CH0 0x828c
1578 #define _VLV_TX_DW3_CH1 0x848c
1579 /* The following bit for CHV phy */
1580 #define DPIO_TX_UNIQ_TRANS_SCALE_EN (1 << 27)
1581 #define DPIO_SWING_MARGIN101_SHIFT 16
1582 #define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT)
1583 #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
1584
1585 #define _VLV_TX_DW4_CH0 0x8290
1586 #define _VLV_TX_DW4_CH1 0x8490
1587 #define DPIO_SWING_DEEMPH9P5_SHIFT 24
1588 #define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
1589 #define DPIO_SWING_DEEMPH6P0_SHIFT 16
1590 #define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
1591 #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
1592
1593 #define _VLV_TX3_DW4_CH0 0x690
1594 #define _VLV_TX3_DW4_CH1 0x2a90
1595 #define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)
1596
1597 #define _VLV_TX_DW5_CH0 0x8294
1598 #define _VLV_TX_DW5_CH1 0x8494
1599 #define DPIO_TX_OCALINIT_EN (1 << 31)
1600 #define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)
1601
1602 #define _VLV_TX_DW11_CH0 0x82ac
1603 #define _VLV_TX_DW11_CH1 0x84ac
1604 #define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)
1605
1606 #define _VLV_TX_DW14_CH0 0x82b8
1607 #define _VLV_TX_DW14_CH1 0x84b8
1608 #define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)
1609
1610 /* CHV dpPhy registers */
1611 #define _CHV_PLL_DW0_CH0 0x8000
1612 #define _CHV_PLL_DW0_CH1 0x8180
1613 #define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1)
1614
1615 #define _CHV_PLL_DW1_CH0 0x8004
1616 #define _CHV_PLL_DW1_CH1 0x8184
1617 #define DPIO_CHV_N_DIV_SHIFT 8
1618 #define DPIO_CHV_M1_DIV_BY_2 (0 << 0)
1619 #define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1)
1620
1621 #define _CHV_PLL_DW2_CH0 0x8008
1622 #define _CHV_PLL_DW2_CH1 0x8188
1623 #define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1)
1624
1625 #define _CHV_PLL_DW3_CH0 0x800c
1626 #define _CHV_PLL_DW3_CH1 0x818c
1627 #define DPIO_CHV_FRAC_DIV_EN (1 << 16)
1628 #define DPIO_CHV_FIRST_MOD (0 << 8)
1629 #define DPIO_CHV_SECOND_MOD (1 << 8)
1630 #define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0
1631 #define DPIO_CHV_FEEDFWD_GAIN_MASK (0xF << 0)
1632 #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
1633
1634 #define _CHV_PLL_DW6_CH0 0x8018
1635 #define _CHV_PLL_DW6_CH1 0x8198
1636 #define DPIO_CHV_GAIN_CTRL_SHIFT 16
1637 #define DPIO_CHV_INT_COEFF_SHIFT 8
1638 #define DPIO_CHV_PROP_COEFF_SHIFT 0
1639 #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
1640
1641 #define _CHV_PLL_DW8_CH0 0x8020
1642 #define _CHV_PLL_DW8_CH1 0x81A0
1643 #define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
1644 #define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0)
1645 #define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
1646
1647 #define _CHV_PLL_DW9_CH0 0x8024
1648 #define _CHV_PLL_DW9_CH1 0x81A4
1649 #define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */
1650 #define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1)
1651 #define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine */
1652 #define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
1653
1654 #define _CHV_CMN_DW0_CH0 0x8100
1655 #define DPIO_ALLDL_POWERDOWN_SHIFT_CH0 19
1656 #define DPIO_ANYDL_POWERDOWN_SHIFT_CH0 18
1657 #define DPIO_ALLDL_POWERDOWN (1 << 1)
1658 #define DPIO_ANYDL_POWERDOWN (1 << 0)
1659
1660 #define _CHV_CMN_DW5_CH0 0x8114
1661 #define CHV_BUFRIGHTENA1_DISABLE (0 << 20)
1662 #define CHV_BUFRIGHTENA1_NORMAL (1 << 20)
1663 #define CHV_BUFRIGHTENA1_FORCE (3 << 20)
1664 #define CHV_BUFRIGHTENA1_MASK (3 << 20)
1665 #define CHV_BUFLEFTENA1_DISABLE (0 << 22)
1666 #define CHV_BUFLEFTENA1_NORMAL (1 << 22)
1667 #define CHV_BUFLEFTENA1_FORCE (3 << 22)
1668 #define CHV_BUFLEFTENA1_MASK (3 << 22)
1669
1670 #define _CHV_CMN_DW13_CH0 0x8134
1671 #define _CHV_CMN_DW0_CH1 0x8080
1672 #define DPIO_CHV_S1_DIV_SHIFT 21
1673 #define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */
1674 #define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */
1675 #define DPIO_CHV_K_DIV_SHIFT 4
1676 #define DPIO_PLL_FREQLOCK (1 << 1)
1677 #define DPIO_PLL_LOCK (1 << 0)
1678 #define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1)
1679
1680 #define _CHV_CMN_DW14_CH0 0x8138
1681 #define _CHV_CMN_DW1_CH1 0x8084
1682 #define DPIO_AFC_RECAL (1 << 14)
1683 #define DPIO_DCLKP_EN (1 << 13)
1684 #define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */
1685 #define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */
1686 #define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */
1687 #define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */
1688 #define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */
1689 #define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */
1690 #define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */
1691 #define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */
1692 #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)
1693
1694 #define _CHV_CMN_DW19_CH0 0x814c
1695 #define _CHV_CMN_DW6_CH1 0x8098
1696 #define DPIO_ALLDL_POWERDOWN_SHIFT_CH1 30 /* CL2 DW6 only */
1697 #define DPIO_ANYDL_POWERDOWN_SHIFT_CH1 29 /* CL2 DW6 only */
1698 #define DPIO_DYNPWRDOWNEN_CH1 (1 << 28) /* CL2 DW6 only */
1699 #define CHV_CMN_USEDCLKCHANNEL (1 << 13)
1700
1701 #define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1)
1702
1703 #define CHV_CMN_DW28 0x8170
1704 #define DPIO_CL1POWERDOWNEN (1 << 23)
1705 #define DPIO_DYNPWRDOWNEN_CH0 (1 << 22)
1706 #define DPIO_SUS_CLK_CONFIG_ON (0 << 0)
1707 #define DPIO_SUS_CLK_CONFIG_CLKREQ (1 << 0)
1708 #define DPIO_SUS_CLK_CONFIG_GATE (2 << 0)
1709 #define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ (3 << 0)
1710
1711 #define CHV_CMN_DW30 0x8178
1712 #define DPIO_CL2_LDOFUSE_PWRENB (1 << 6)
1713 #define DPIO_LRC_BYPASS (1 << 3)
1714
1715 #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
1716 (lane) * 0x200 + (offset))
1717
1718 #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80)
1719 #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84)
1720 #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88)
1721 #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c)
1722 #define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90)
1723 #define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94)
1724 #define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98)
1725 #define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c)
1726 #define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0)
1727 #define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4)
1728 #define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8)
1729 #define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac)
1730 #define DPIO_FRC_LATENCY_SHFIT 8
1731 #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
1732 #define DPIO_UPAR_SHIFT 30
1733
1734 /* BXT PHY registers */
1735 #define _BXT_PHY0_BASE 0x6C000
1736 #define _BXT_PHY1_BASE 0x162000
1737 #define _BXT_PHY2_BASE 0x163000
1738 #define BXT_PHY_BASE(phy) _PHY3((phy), _BXT_PHY0_BASE, \
1739 _BXT_PHY1_BASE, \
1740 _BXT_PHY2_BASE)
1741
1742 #define _BXT_PHY(phy, reg) \
1743 _MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg))
1744
1745 #define _BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \
1746 (BXT_PHY_BASE(phy) + _PIPE((ch), (reg_ch0) - _BXT_PHY0_BASE, \
1747 (reg_ch1) - _BXT_PHY0_BASE))
1748 #define _MMIO_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \
1749 _MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1))
1750
1751 #define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090)
1752 #define MIPIO_RST_CTRL (1 << 2)
1753
1754 #define _BXT_PHY_CTL_DDI_A 0x64C00
1755 #define _BXT_PHY_CTL_DDI_B 0x64C10
1756 #define _BXT_PHY_CTL_DDI_C 0x64C20
1757 #define BXT_PHY_CMNLANE_POWERDOWN_ACK (1 << 10)
1758 #define BXT_PHY_LANE_POWERDOWN_ACK (1 << 9)
1759 #define BXT_PHY_LANE_ENABLED (1 << 8)
1760 #define BXT_PHY_CTL(port) _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \
1761 _BXT_PHY_CTL_DDI_B)
1762
1763 #define _PHY_CTL_FAMILY_EDP 0x64C80
1764 #define _PHY_CTL_FAMILY_DDI 0x64C90
1765 #define _PHY_CTL_FAMILY_DDI_C 0x64CA0
1766 #define COMMON_RESET_DIS (1 << 31)
1767 #define BXT_PHY_CTL_FAMILY(phy) _MMIO_PHY3((phy), _PHY_CTL_FAMILY_DDI, \
1768 _PHY_CTL_FAMILY_EDP, \
1769 _PHY_CTL_FAMILY_DDI_C)
1770
1771 /* BXT PHY PLL registers */
1772 #define _PORT_PLL_A 0x46074
1773 #define _PORT_PLL_B 0x46078
1774 #define _PORT_PLL_C 0x4607c
1775 #define PORT_PLL_ENABLE (1 << 31)
1776 #define PORT_PLL_LOCK (1 << 30)
1777 #define PORT_PLL_REF_SEL (1 << 27)
1778 #define PORT_PLL_POWER_ENABLE (1 << 26)
1779 #define PORT_PLL_POWER_STATE (1 << 25)
1780 #define BXT_PORT_PLL_ENABLE(port) _MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B)
1781
1782 #define _PORT_PLL_EBB_0_A 0x162034
1783 #define _PORT_PLL_EBB_0_B 0x6C034
1784 #define _PORT_PLL_EBB_0_C 0x6C340
1785 #define PORT_PLL_P1_SHIFT 13
1786 #define PORT_PLL_P1_MASK (0x07 << PORT_PLL_P1_SHIFT)
1787 #define PORT_PLL_P1(x) ((x) << PORT_PLL_P1_SHIFT)
1788 #define PORT_PLL_P2_SHIFT 8
1789 #define PORT_PLL_P2_MASK (0x1f << PORT_PLL_P2_SHIFT)
1790 #define PORT_PLL_P2(x) ((x) << PORT_PLL_P2_SHIFT)
1791 #define BXT_PORT_PLL_EBB_0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
1792 _PORT_PLL_EBB_0_B, \
1793 _PORT_PLL_EBB_0_C)
1794
1795 #define _PORT_PLL_EBB_4_A 0x162038
1796 #define _PORT_PLL_EBB_4_B 0x6C038
1797 #define _PORT_PLL_EBB_4_C 0x6C344
1798 #define PORT_PLL_10BIT_CLK_ENABLE (1 << 13)
1799 #define PORT_PLL_RECALIBRATE (1 << 14)
1800 #define BXT_PORT_PLL_EBB_4(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
1801 _PORT_PLL_EBB_4_B, \
1802 _PORT_PLL_EBB_4_C)
1803
1804 #define _PORT_PLL_0_A 0x162100
1805 #define _PORT_PLL_0_B 0x6C100
1806 #define _PORT_PLL_0_C 0x6C380
1807 /* PORT_PLL_0_A */
1808 #define PORT_PLL_M2_MASK 0xFF
1809 /* PORT_PLL_1_A */
1810 #define PORT_PLL_N_SHIFT 8
1811 #define PORT_PLL_N_MASK (0x0F << PORT_PLL_N_SHIFT)
1812 #define PORT_PLL_N(x) ((x) << PORT_PLL_N_SHIFT)
1813 /* PORT_PLL_2_A */
1814 #define PORT_PLL_M2_FRAC_MASK 0x3FFFFF
1815 /* PORT_PLL_3_A */
1816 #define PORT_PLL_M2_FRAC_ENABLE (1 << 16)
1817 /* PORT_PLL_6_A */
1818 #define PORT_PLL_PROP_COEFF_MASK 0xF
1819 #define PORT_PLL_INT_COEFF_MASK (0x1F << 8)
1820 #define PORT_PLL_INT_COEFF(x) ((x) << 8)
1821 #define PORT_PLL_GAIN_CTL_MASK (0x07 << 16)
1822 #define PORT_PLL_GAIN_CTL(x) ((x) << 16)
1823 /* PORT_PLL_8_A */
1824 #define PORT_PLL_TARGET_CNT_MASK 0x3FF
1825 /* PORT_PLL_9_A */
1826 #define PORT_PLL_LOCK_THRESHOLD_SHIFT 1
1827 #define PORT_PLL_LOCK_THRESHOLD_MASK (0x7 << PORT_PLL_LOCK_THRESHOLD_SHIFT)
1828 /* PORT_PLL_10_A */
1829 #define PORT_PLL_DCO_AMP_OVR_EN_H (1 << 27)
1830 #define PORT_PLL_DCO_AMP_DEFAULT 15
1831 #define PORT_PLL_DCO_AMP_MASK 0x3c00
1832 #define PORT_PLL_DCO_AMP(x) ((x) << 10)
1833 #define _PORT_PLL_BASE(phy, ch) _BXT_PHY_CH(phy, ch, \
1834 _PORT_PLL_0_B, \
1835 _PORT_PLL_0_C)
1836 #define BXT_PORT_PLL(phy, ch, idx) _MMIO(_PORT_PLL_BASE(phy, ch) + \
1837 (idx) * 4)
1838
1839 /* BXT PHY common lane registers */
1840 #define _PORT_CL1CM_DW0_A 0x162000
1841 #define _PORT_CL1CM_DW0_BC 0x6C000
1842 #define PHY_POWER_GOOD (1 << 16)
1843 #define PHY_RESERVED (1 << 7)
1844 #define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC)
1845
1846 #define _PORT_CL1CM_DW9_A 0x162024
1847 #define _PORT_CL1CM_DW9_BC 0x6C024
1848 #define IREF0RC_OFFSET_SHIFT 8
1849 #define IREF0RC_OFFSET_MASK (0xFF << IREF0RC_OFFSET_SHIFT)
1850 #define BXT_PORT_CL1CM_DW9(phy) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC)
1851
1852 #define _PORT_CL1CM_DW10_A 0x162028
1853 #define _PORT_CL1CM_DW10_BC 0x6C028
1854 #define IREF1RC_OFFSET_SHIFT 8
1855 #define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT)
1856 #define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC)
1857
1858 #define _PORT_CL1CM_DW28_A 0x162070
1859 #define _PORT_CL1CM_DW28_BC 0x6C070
1860 #define OCL1_POWER_DOWN_EN (1 << 23)
1861 #define DW28_OLDO_DYN_PWR_DOWN_EN (1 << 22)
1862 #define SUS_CLK_CONFIG 0x3
1863 #define BXT_PORT_CL1CM_DW28(phy) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC)
1864
1865 #define _PORT_CL1CM_DW30_A 0x162078
1866 #define _PORT_CL1CM_DW30_BC 0x6C078
1867 #define OCL2_LDOFUSE_PWR_DIS (1 << 6)
1868 #define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
1869
1870 /*
1871 * CNL/ICL Port/COMBO-PHY Registers
1872 */
1873 #define _ICL_COMBOPHY_A 0x162000
1874 #define _ICL_COMBOPHY_B 0x6C000
1875 #define _EHL_COMBOPHY_C 0x160000
1876 #define _RKL_COMBOPHY_D 0x161000
1877 #define _ICL_COMBOPHY(phy) _PICK(phy, _ICL_COMBOPHY_A, \
1878 _ICL_COMBOPHY_B, \
1879 _EHL_COMBOPHY_C, \
1880 _RKL_COMBOPHY_D)
1881
1882 /* CNL/ICL Port CL_DW registers */
1883 #define _ICL_PORT_CL_DW(dw, phy) (_ICL_COMBOPHY(phy) + \
1884 4 * (dw))
1885
1886 #define CNL_PORT_CL1CM_DW5 _MMIO(0x162014)
1887 #define ICL_PORT_CL_DW5(phy) _MMIO(_ICL_PORT_CL_DW(5, phy))
1888 #define CL_POWER_DOWN_ENABLE (1 << 4)
1889 #define SUS_CLOCK_CONFIG (3 << 0)
1890
1891 #define ICL_PORT_CL_DW10(phy) _MMIO(_ICL_PORT_CL_DW(10, phy))
1892 #define PG_SEQ_DELAY_OVERRIDE_MASK (3 << 25)
1893 #define PG_SEQ_DELAY_OVERRIDE_SHIFT 25
1894 #define PG_SEQ_DELAY_OVERRIDE_ENABLE (1 << 24)
1895 #define PWR_UP_ALL_LANES (0x0 << 4)
1896 #define PWR_DOWN_LN_3_2_1 (0xe << 4)
1897 #define PWR_DOWN_LN_3_2 (0xc << 4)
1898 #define PWR_DOWN_LN_3 (0x8 << 4)
1899 #define PWR_DOWN_LN_2_1_0 (0x7 << 4)
1900 #define PWR_DOWN_LN_1_0 (0x3 << 4)
1901 #define PWR_DOWN_LN_3_1 (0xa << 4)
1902 #define PWR_DOWN_LN_3_1_0 (0xb << 4)
1903 #define PWR_DOWN_LN_MASK (0xf << 4)
1904 #define PWR_DOWN_LN_SHIFT 4
1905 #define EDP4K2K_MODE_OVRD_EN (1 << 3)
1906 #define EDP4K2K_MODE_OVRD_OPTIMIZED (1 << 2)
1907
1908 #define ICL_PORT_CL_DW12(phy) _MMIO(_ICL_PORT_CL_DW(12, phy))
1909 #define ICL_LANE_ENABLE_AUX (1 << 0)
1910
1911 /* CNL/ICL Port COMP_DW registers */
1912 #define _ICL_PORT_COMP 0x100
1913 #define _ICL_PORT_COMP_DW(dw, phy) (_ICL_COMBOPHY(phy) + \
1914 _ICL_PORT_COMP + 4 * (dw))
1915
1916 #define CNL_PORT_COMP_DW0 _MMIO(0x162100)
1917 #define ICL_PORT_COMP_DW0(phy) _MMIO(_ICL_PORT_COMP_DW(0, phy))
1918 #define COMP_INIT (1 << 31)
1919
1920 #define CNL_PORT_COMP_DW1 _MMIO(0x162104)
1921 #define ICL_PORT_COMP_DW1(phy) _MMIO(_ICL_PORT_COMP_DW(1, phy))
1922
1923 #define CNL_PORT_COMP_DW3 _MMIO(0x16210c)
1924 #define ICL_PORT_COMP_DW3(phy) _MMIO(_ICL_PORT_COMP_DW(3, phy))
1925 #define PROCESS_INFO_DOT_0 (0 << 26)
1926 #define PROCESS_INFO_DOT_1 (1 << 26)
1927 #define PROCESS_INFO_DOT_4 (2 << 26)
1928 #define PROCESS_INFO_MASK (7 << 26)
1929 #define PROCESS_INFO_SHIFT 26
1930 #define VOLTAGE_INFO_0_85V (0 << 24)
1931 #define VOLTAGE_INFO_0_95V (1 << 24)
1932 #define VOLTAGE_INFO_1_05V (2 << 24)
1933 #define VOLTAGE_INFO_MASK (3 << 24)
1934 #define VOLTAGE_INFO_SHIFT 24
1935
1936 #define ICL_PORT_COMP_DW8(phy) _MMIO(_ICL_PORT_COMP_DW(8, phy))
1937 #define IREFGEN (1 << 24)
1938
1939 #define CNL_PORT_COMP_DW9 _MMIO(0x162124)
1940 #define ICL_PORT_COMP_DW9(phy) _MMIO(_ICL_PORT_COMP_DW(9, phy))
1941
1942 #define CNL_PORT_COMP_DW10 _MMIO(0x162128)
1943 #define ICL_PORT_COMP_DW10(phy) _MMIO(_ICL_PORT_COMP_DW(10, phy))
1944
1945 /* CNL/ICL Port PCS registers */
1946 #define _CNL_PORT_PCS_DW1_GRP_AE 0x162304
1947 #define _CNL_PORT_PCS_DW1_GRP_B 0x162384
1948 #define _CNL_PORT_PCS_DW1_GRP_C 0x162B04
1949 #define _CNL_PORT_PCS_DW1_GRP_D 0x162B84
1950 #define _CNL_PORT_PCS_DW1_GRP_F 0x162A04
1951 #define _CNL_PORT_PCS_DW1_LN0_AE 0x162404
1952 #define _CNL_PORT_PCS_DW1_LN0_B 0x162604
1953 #define _CNL_PORT_PCS_DW1_LN0_C 0x162C04
1954 #define _CNL_PORT_PCS_DW1_LN0_D 0x162E04
1955 #define _CNL_PORT_PCS_DW1_LN0_F 0x162804
1956 #define CNL_PORT_PCS_DW1_GRP(phy) _MMIO(_PICK(phy, \
1957 _CNL_PORT_PCS_DW1_GRP_AE, \
1958 _CNL_PORT_PCS_DW1_GRP_B, \
1959 _CNL_PORT_PCS_DW1_GRP_C, \
1960 _CNL_PORT_PCS_DW1_GRP_D, \
1961 _CNL_PORT_PCS_DW1_GRP_AE, \
1962 _CNL_PORT_PCS_DW1_GRP_F))
1963 #define CNL_PORT_PCS_DW1_LN0(phy) _MMIO(_PICK(phy, \
1964 _CNL_PORT_PCS_DW1_LN0_AE, \
1965 _CNL_PORT_PCS_DW1_LN0_B, \
1966 _CNL_PORT_PCS_DW1_LN0_C, \
1967 _CNL_PORT_PCS_DW1_LN0_D, \
1968 _CNL_PORT_PCS_DW1_LN0_AE, \
1969 _CNL_PORT_PCS_DW1_LN0_F))
1970
1971 #define _ICL_PORT_PCS_AUX 0x300
1972 #define _ICL_PORT_PCS_GRP 0x600
1973 #define _ICL_PORT_PCS_LN(ln) (0x800 + (ln) * 0x100)
1974 #define _ICL_PORT_PCS_DW_AUX(dw, phy) (_ICL_COMBOPHY(phy) + \
1975 _ICL_PORT_PCS_AUX + 4 * (dw))
1976 #define _ICL_PORT_PCS_DW_GRP(dw, phy) (_ICL_COMBOPHY(phy) + \
1977 _ICL_PORT_PCS_GRP + 4 * (dw))
1978 #define _ICL_PORT_PCS_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \
1979 _ICL_PORT_PCS_LN(ln) + 4 * (dw))
1980 #define ICL_PORT_PCS_DW1_AUX(phy) _MMIO(_ICL_PORT_PCS_DW_AUX(1, phy))
1981 #define ICL_PORT_PCS_DW1_GRP(phy) _MMIO(_ICL_PORT_PCS_DW_GRP(1, phy))
1982 #define ICL_PORT_PCS_DW1_LN0(phy) _MMIO(_ICL_PORT_PCS_DW_LN(1, 0, phy))
1983 #define DCC_MODE_SELECT_MASK (0x3 << 20)
1984 #define DCC_MODE_SELECT_CONTINUOSLY (0x3 << 20)
1985 #define COMMON_KEEPER_EN (1 << 26)
1986 #define LATENCY_OPTIM_MASK (0x3 << 2)
1987 #define LATENCY_OPTIM_VAL(x) ((x) << 2)
1988
1989 /* CNL/ICL Port TX registers */
1990 #define _CNL_PORT_TX_AE_GRP_OFFSET 0x162340
1991 #define _CNL_PORT_TX_B_GRP_OFFSET 0x1623C0
1992 #define _CNL_PORT_TX_C_GRP_OFFSET 0x162B40
1993 #define _CNL_PORT_TX_D_GRP_OFFSET 0x162BC0
1994 #define _CNL_PORT_TX_F_GRP_OFFSET 0x162A40
1995 #define _CNL_PORT_TX_AE_LN0_OFFSET 0x162440
1996 #define _CNL_PORT_TX_B_LN0_OFFSET 0x162640
1997 #define _CNL_PORT_TX_C_LN0_OFFSET 0x162C40
1998 #define _CNL_PORT_TX_D_LN0_OFFSET 0x162E40
1999 #define _CNL_PORT_TX_F_LN0_OFFSET 0x162840
2000 #define _CNL_PORT_TX_DW_GRP(dw, port) (_PICK((port), \
2001 _CNL_PORT_TX_AE_GRP_OFFSET, \
2002 _CNL_PORT_TX_B_GRP_OFFSET, \
2003 _CNL_PORT_TX_B_GRP_OFFSET, \
2004 _CNL_PORT_TX_D_GRP_OFFSET, \
2005 _CNL_PORT_TX_AE_GRP_OFFSET, \
2006 _CNL_PORT_TX_F_GRP_OFFSET) + \
2007 4 * (dw))
2008 #define _CNL_PORT_TX_DW_LN0(dw, port) (_PICK((port), \
2009 _CNL_PORT_TX_AE_LN0_OFFSET, \
2010 _CNL_PORT_TX_B_LN0_OFFSET, \
2011 _CNL_PORT_TX_B_LN0_OFFSET, \
2012 _CNL_PORT_TX_D_LN0_OFFSET, \
2013 _CNL_PORT_TX_AE_LN0_OFFSET, \
2014 _CNL_PORT_TX_F_LN0_OFFSET) + \
2015 4 * (dw))
2016
2017 #define _ICL_PORT_TX_AUX 0x380
2018 #define _ICL_PORT_TX_GRP 0x680
2019 #define _ICL_PORT_TX_LN(ln) (0x880 + (ln) * 0x100)
2020
2021 #define _ICL_PORT_TX_DW_AUX(dw, phy) (_ICL_COMBOPHY(phy) + \
2022 _ICL_PORT_TX_AUX + 4 * (dw))
2023 #define _ICL_PORT_TX_DW_GRP(dw, phy) (_ICL_COMBOPHY(phy) + \
2024 _ICL_PORT_TX_GRP + 4 * (dw))
2025 #define _ICL_PORT_TX_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \
2026 _ICL_PORT_TX_LN(ln) + 4 * (dw))
2027
2028 #define CNL_PORT_TX_DW2_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(2, port))
2029 #define CNL_PORT_TX_DW2_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(2, port))
2030 #define ICL_PORT_TX_DW2_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(2, phy))
2031 #define ICL_PORT_TX_DW2_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(2, phy))
2032 #define ICL_PORT_TX_DW2_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(2, 0, phy))
2033 #define SWING_SEL_UPPER(x) (((x) >> 3) << 15)
2034 #define SWING_SEL_UPPER_MASK (1 << 15)
2035 #define SWING_SEL_LOWER(x) (((x) & 0x7) << 11)
2036 #define SWING_SEL_LOWER_MASK (0x7 << 11)
2037 #define FRC_LATENCY_OPTIM_MASK (0x7 << 8)
2038 #define FRC_LATENCY_OPTIM_VAL(x) ((x) << 8)
2039 #define RCOMP_SCALAR(x) ((x) << 0)
2040 #define RCOMP_SCALAR_MASK (0xFF << 0)
2041
2042 #define _CNL_PORT_TX_DW4_LN0_AE 0x162450
2043 #define _CNL_PORT_TX_DW4_LN1_AE 0x1624D0
2044 #define CNL_PORT_TX_DW4_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(4, (port)))
2045 #define CNL_PORT_TX_DW4_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(4, (port)))
2046 #define CNL_PORT_TX_DW4_LN(ln, port) _MMIO(_CNL_PORT_TX_DW_LN0(4, (port)) + \
2047 ((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \
2048 _CNL_PORT_TX_DW4_LN0_AE)))
2049 #define ICL_PORT_TX_DW4_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(4, phy))
2050 #define ICL_PORT_TX_DW4_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(4, phy))
2051 #define ICL_PORT_TX_DW4_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(4, 0, phy))
2052 #define ICL_PORT_TX_DW4_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(4, ln, phy))
2053 #define LOADGEN_SELECT (1 << 31)
2054 #define POST_CURSOR_1(x) ((x) << 12)
2055 #define POST_CURSOR_1_MASK (0x3F << 12)
2056 #define POST_CURSOR_2(x) ((x) << 6)
2057 #define POST_CURSOR_2_MASK (0x3F << 6)
2058 #define CURSOR_COEFF(x) ((x) << 0)
2059 #define CURSOR_COEFF_MASK (0x3F << 0)
2060
2061 #define CNL_PORT_TX_DW5_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(5, port))
2062 #define CNL_PORT_TX_DW5_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(5, port))
2063 #define ICL_PORT_TX_DW5_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(5, phy))
2064 #define ICL_PORT_TX_DW5_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(5, phy))
2065 #define ICL_PORT_TX_DW5_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(5, 0, phy))
2066 #define TX_TRAINING_EN (1 << 31)
2067 #define TAP2_DISABLE (1 << 30)
2068 #define TAP3_DISABLE (1 << 29)
2069 #define SCALING_MODE_SEL(x) ((x) << 18)
2070 #define SCALING_MODE_SEL_MASK (0x7 << 18)
2071 #define RTERM_SELECT(x) ((x) << 3)
2072 #define RTERM_SELECT_MASK (0x7 << 3)
2073
2074 #define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(7, (port)))
2075 #define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(7, (port)))
2076 #define ICL_PORT_TX_DW7_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(7, phy))
2077 #define ICL_PORT_TX_DW7_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(7, phy))
2078 #define ICL_PORT_TX_DW7_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, phy))
2079 #define ICL_PORT_TX_DW7_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, phy))
2080 #define N_SCALAR(x) ((x) << 24)
2081 #define N_SCALAR_MASK (0x7F << 24)
2082
2083 #define ICL_PORT_TX_DW8_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(8, phy))
2084 #define ICL_PORT_TX_DW8_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(8, phy))
2085 #define ICL_PORT_TX_DW8_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(8, 0, phy))
2086 #define ICL_PORT_TX_DW8_ODCC_CLK_SEL REG_BIT(31)
2087 #define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK REG_GENMASK(30, 29)
2088 #define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2 REG_FIELD_PREP(ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK, 0x1)
2089
2090 #define _ICL_DPHY_CHKN_REG 0x194
2091 #define ICL_DPHY_CHKN(port) _MMIO(_ICL_COMBOPHY(port) + _ICL_DPHY_CHKN_REG)
2092 #define ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP REG_BIT(7)
2093
2094 #define MG_PHY_PORT_LN(ln, tc_port, ln0p1, ln0p2, ln1p1) \
2095 _MMIO(_PORT(tc_port, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
2096
2097 #define MG_TX_LINK_PARAMS_TX1LN0_PORT1 0x16812C
2098 #define MG_TX_LINK_PARAMS_TX1LN1_PORT1 0x16852C
2099 #define MG_TX_LINK_PARAMS_TX1LN0_PORT2 0x16912C
2100 #define MG_TX_LINK_PARAMS_TX1LN1_PORT2 0x16952C
2101 #define MG_TX_LINK_PARAMS_TX1LN0_PORT3 0x16A12C
2102 #define MG_TX_LINK_PARAMS_TX1LN1_PORT3 0x16A52C
2103 #define MG_TX_LINK_PARAMS_TX1LN0_PORT4 0x16B12C
2104 #define MG_TX_LINK_PARAMS_TX1LN1_PORT4 0x16B52C
2105 #define MG_TX1_LINK_PARAMS(ln, tc_port) \
2106 MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
2107 MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
2108 MG_TX_LINK_PARAMS_TX1LN1_PORT1)
2109
2110 #define MG_TX_LINK_PARAMS_TX2LN0_PORT1 0x1680AC
2111 #define MG_TX_LINK_PARAMS_TX2LN1_PORT1 0x1684AC
2112 #define MG_TX_LINK_PARAMS_TX2LN0_PORT2 0x1690AC
2113 #define MG_TX_LINK_PARAMS_TX2LN1_PORT2 0x1694AC
2114 #define MG_TX_LINK_PARAMS_TX2LN0_PORT3 0x16A0AC
2115 #define MG_TX_LINK_PARAMS_TX2LN1_PORT3 0x16A4AC
2116 #define MG_TX_LINK_PARAMS_TX2LN0_PORT4 0x16B0AC
2117 #define MG_TX_LINK_PARAMS_TX2LN1_PORT4 0x16B4AC
2118 #define MG_TX2_LINK_PARAMS(ln, tc_port) \
2119 MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
2120 MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
2121 MG_TX_LINK_PARAMS_TX2LN1_PORT1)
2122 #define CRI_USE_FS32 (1 << 5)
2123
2124 #define MG_TX_PISO_READLOAD_TX1LN0_PORT1 0x16814C
2125 #define MG_TX_PISO_READLOAD_TX1LN1_PORT1 0x16854C
2126 #define MG_TX_PISO_READLOAD_TX1LN0_PORT2 0x16914C
2127 #define MG_TX_PISO_READLOAD_TX1LN1_PORT2 0x16954C
2128 #define MG_TX_PISO_READLOAD_TX1LN0_PORT3 0x16A14C
2129 #define MG_TX_PISO_READLOAD_TX1LN1_PORT3 0x16A54C
2130 #define MG_TX_PISO_READLOAD_TX1LN0_PORT4 0x16B14C
2131 #define MG_TX_PISO_READLOAD_TX1LN1_PORT4 0x16B54C
2132 #define MG_TX1_PISO_READLOAD(ln, tc_port) \
2133 MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
2134 MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
2135 MG_TX_PISO_READLOAD_TX1LN1_PORT1)
2136
2137 #define MG_TX_PISO_READLOAD_TX2LN0_PORT1 0x1680CC
2138 #define MG_TX_PISO_READLOAD_TX2LN1_PORT1 0x1684CC
2139 #define MG_TX_PISO_READLOAD_TX2LN0_PORT2 0x1690CC
2140 #define MG_TX_PISO_READLOAD_TX2LN1_PORT2 0x1694CC
2141 #define MG_TX_PISO_READLOAD_TX2LN0_PORT3 0x16A0CC
2142 #define MG_TX_PISO_READLOAD_TX2LN1_PORT3 0x16A4CC
2143 #define MG_TX_PISO_READLOAD_TX2LN0_PORT4 0x16B0CC
2144 #define MG_TX_PISO_READLOAD_TX2LN1_PORT4 0x16B4CC
2145 #define MG_TX2_PISO_READLOAD(ln, tc_port) \
2146 MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
2147 MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
2148 MG_TX_PISO_READLOAD_TX2LN1_PORT1)
2149 #define CRI_CALCINIT (1 << 1)
2150
2151 #define MG_TX_SWINGCTRL_TX1LN0_PORT1 0x168148
2152 #define MG_TX_SWINGCTRL_TX1LN1_PORT1 0x168548
2153 #define MG_TX_SWINGCTRL_TX1LN0_PORT2 0x169148
2154 #define MG_TX_SWINGCTRL_TX1LN1_PORT2 0x169548
2155 #define MG_TX_SWINGCTRL_TX1LN0_PORT3 0x16A148
2156 #define MG_TX_SWINGCTRL_TX1LN1_PORT3 0x16A548
2157 #define MG_TX_SWINGCTRL_TX1LN0_PORT4 0x16B148
2158 #define MG_TX_SWINGCTRL_TX1LN1_PORT4 0x16B548
2159 #define MG_TX1_SWINGCTRL(ln, tc_port) \
2160 MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX1LN0_PORT1, \
2161 MG_TX_SWINGCTRL_TX1LN0_PORT2, \
2162 MG_TX_SWINGCTRL_TX1LN1_PORT1)
2163
2164 #define MG_TX_SWINGCTRL_TX2LN0_PORT1 0x1680C8
2165 #define MG_TX_SWINGCTRL_TX2LN1_PORT1 0x1684C8
2166 #define MG_TX_SWINGCTRL_TX2LN0_PORT2 0x1690C8
2167 #define MG_TX_SWINGCTRL_TX2LN1_PORT2 0x1694C8
2168 #define MG_TX_SWINGCTRL_TX2LN0_PORT3 0x16A0C8
2169 #define MG_TX_SWINGCTRL_TX2LN1_PORT3 0x16A4C8
2170 #define MG_TX_SWINGCTRL_TX2LN0_PORT4 0x16B0C8
2171 #define MG_TX_SWINGCTRL_TX2LN1_PORT4 0x16B4C8
2172 #define MG_TX2_SWINGCTRL(ln, tc_port) \
2173 MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX2LN0_PORT1, \
2174 MG_TX_SWINGCTRL_TX2LN0_PORT2, \
2175 MG_TX_SWINGCTRL_TX2LN1_PORT1)
2176 #define CRI_TXDEEMPH_OVERRIDE_17_12(x) ((x) << 0)
2177 #define CRI_TXDEEMPH_OVERRIDE_17_12_MASK (0x3F << 0)
2178
2179 #define MG_TX_DRVCTRL_TX1LN0_TXPORT1 0x168144
2180 #define MG_TX_DRVCTRL_TX1LN1_TXPORT1 0x168544
2181 #define MG_TX_DRVCTRL_TX1LN0_TXPORT2 0x169144
2182 #define MG_TX_DRVCTRL_TX1LN1_TXPORT2 0x169544
2183 #define MG_TX_DRVCTRL_TX1LN0_TXPORT3 0x16A144
2184 #define MG_TX_DRVCTRL_TX1LN1_TXPORT3 0x16A544
2185 #define MG_TX_DRVCTRL_TX1LN0_TXPORT4 0x16B144
2186 #define MG_TX_DRVCTRL_TX1LN1_TXPORT4 0x16B544
2187 #define MG_TX1_DRVCTRL(ln, tc_port) \
2188 MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \
2189 MG_TX_DRVCTRL_TX1LN0_TXPORT2, \
2190 MG_TX_DRVCTRL_TX1LN1_TXPORT1)
2191
2192 #define MG_TX_DRVCTRL_TX2LN0_PORT1 0x1680C4
2193 #define MG_TX_DRVCTRL_TX2LN1_PORT1 0x1684C4
2194 #define MG_TX_DRVCTRL_TX2LN0_PORT2 0x1690C4
2195 #define MG_TX_DRVCTRL_TX2LN1_PORT2 0x1694C4
2196 #define MG_TX_DRVCTRL_TX2LN0_PORT3 0x16A0C4
2197 #define MG_TX_DRVCTRL_TX2LN1_PORT3 0x16A4C4
2198 #define MG_TX_DRVCTRL_TX2LN0_PORT4 0x16B0C4
2199 #define MG_TX_DRVCTRL_TX2LN1_PORT4 0x16B4C4
2200 #define MG_TX2_DRVCTRL(ln, tc_port) \
2201 MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX2LN0_PORT1, \
2202 MG_TX_DRVCTRL_TX2LN0_PORT2, \
2203 MG_TX_DRVCTRL_TX2LN1_PORT1)
2204 #define CRI_TXDEEMPH_OVERRIDE_11_6(x) ((x) << 24)
2205 #define CRI_TXDEEMPH_OVERRIDE_11_6_MASK (0x3F << 24)
2206 #define CRI_TXDEEMPH_OVERRIDE_EN (1 << 22)
2207 #define CRI_TXDEEMPH_OVERRIDE_5_0(x) ((x) << 16)
2208 #define CRI_TXDEEMPH_OVERRIDE_5_0_MASK (0x3F << 16)
2209 #define CRI_LOADGEN_SEL(x) ((x) << 12)
2210 #define CRI_LOADGEN_SEL_MASK (0x3 << 12)
2211
2212 #define MG_CLKHUB_LN0_PORT1 0x16839C
2213 #define MG_CLKHUB_LN1_PORT1 0x16879C
2214 #define MG_CLKHUB_LN0_PORT2 0x16939C
2215 #define MG_CLKHUB_LN1_PORT2 0x16979C
2216 #define MG_CLKHUB_LN0_PORT3 0x16A39C
2217 #define MG_CLKHUB_LN1_PORT3 0x16A79C
2218 #define MG_CLKHUB_LN0_PORT4 0x16B39C
2219 #define MG_CLKHUB_LN1_PORT4 0x16B79C
2220 #define MG_CLKHUB(ln, tc_port) \
2221 MG_PHY_PORT_LN(ln, tc_port, MG_CLKHUB_LN0_PORT1, \
2222 MG_CLKHUB_LN0_PORT2, \
2223 MG_CLKHUB_LN1_PORT1)
2224 #define CFG_LOW_RATE_LKREN_EN (1 << 11)
2225
2226 #define MG_TX_DCC_TX1LN0_PORT1 0x168110
2227 #define MG_TX_DCC_TX1LN1_PORT1 0x168510
2228 #define MG_TX_DCC_TX1LN0_PORT2 0x169110
2229 #define MG_TX_DCC_TX1LN1_PORT2 0x169510
2230 #define MG_TX_DCC_TX1LN0_PORT3 0x16A110
2231 #define MG_TX_DCC_TX1LN1_PORT3 0x16A510
2232 #define MG_TX_DCC_TX1LN0_PORT4 0x16B110
2233 #define MG_TX_DCC_TX1LN1_PORT4 0x16B510
2234 #define MG_TX1_DCC(ln, tc_port) \
2235 MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX1LN0_PORT1, \
2236 MG_TX_DCC_TX1LN0_PORT2, \
2237 MG_TX_DCC_TX1LN1_PORT1)
2238 #define MG_TX_DCC_TX2LN0_PORT1 0x168090
2239 #define MG_TX_DCC_TX2LN1_PORT1 0x168490
2240 #define MG_TX_DCC_TX2LN0_PORT2 0x169090
2241 #define MG_TX_DCC_TX2LN1_PORT2 0x169490
2242 #define MG_TX_DCC_TX2LN0_PORT3 0x16A090
2243 #define MG_TX_DCC_TX2LN1_PORT3 0x16A490
2244 #define MG_TX_DCC_TX2LN0_PORT4 0x16B090
2245 #define MG_TX_DCC_TX2LN1_PORT4 0x16B490
2246 #define MG_TX2_DCC(ln, tc_port) \
2247 MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX2LN0_PORT1, \
2248 MG_TX_DCC_TX2LN0_PORT2, \
2249 MG_TX_DCC_TX2LN1_PORT1)
2250 #define CFG_AMI_CK_DIV_OVERRIDE_VAL(x) ((x) << 25)
2251 #define CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK (0x3 << 25)
2252 #define CFG_AMI_CK_DIV_OVERRIDE_EN (1 << 24)
2253
2254 #define MG_DP_MODE_LN0_ACU_PORT1 0x1683A0
2255 #define MG_DP_MODE_LN1_ACU_PORT1 0x1687A0
2256 #define MG_DP_MODE_LN0_ACU_PORT2 0x1693A0
2257 #define MG_DP_MODE_LN1_ACU_PORT2 0x1697A0
2258 #define MG_DP_MODE_LN0_ACU_PORT3 0x16A3A0
2259 #define MG_DP_MODE_LN1_ACU_PORT3 0x16A7A0
2260 #define MG_DP_MODE_LN0_ACU_PORT4 0x16B3A0
2261 #define MG_DP_MODE_LN1_ACU_PORT4 0x16B7A0
2262 #define MG_DP_MODE(ln, tc_port) \
2263 MG_PHY_PORT_LN(ln, tc_port, MG_DP_MODE_LN0_ACU_PORT1, \
2264 MG_DP_MODE_LN0_ACU_PORT2, \
2265 MG_DP_MODE_LN1_ACU_PORT1)
2266 #define MG_DP_MODE_CFG_DP_X2_MODE (1 << 7)
2267 #define MG_DP_MODE_CFG_DP_X1_MODE (1 << 6)
2268
2269 /* The spec defines this only for BXT PHY0, but lets assume that this
2270 * would exist for PHY1 too if it had a second channel.
2271 */
2272 #define _PORT_CL2CM_DW6_A 0x162358
2273 #define _PORT_CL2CM_DW6_BC 0x6C358
2274 #define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
2275 #define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
2276
2277 #define FIA1_BASE 0x163000
2278 #define FIA2_BASE 0x16E000
2279 #define FIA3_BASE 0x16F000
2280 #define _FIA(fia) _PICK((fia), FIA1_BASE, FIA2_BASE, FIA3_BASE)
2281 #define _MMIO_FIA(fia, off) _MMIO(_FIA(fia) + (off))
2282
2283 /* ICL PHY DFLEX registers */
2284 #define PORT_TX_DFLEXDPMLE1(fia) _MMIO_FIA((fia), 0x008C0)
2285 #define DFLEXDPMLE1_DPMLETC_MASK(idx) (0xf << (4 * (idx)))
2286 #define DFLEXDPMLE1_DPMLETC_ML0(idx) (1 << (4 * (idx)))
2287 #define DFLEXDPMLE1_DPMLETC_ML1_0(idx) (3 << (4 * (idx)))
2288 #define DFLEXDPMLE1_DPMLETC_ML3(idx) (8 << (4 * (idx)))
2289 #define DFLEXDPMLE1_DPMLETC_ML3_2(idx) (12 << (4 * (idx)))
2290 #define DFLEXDPMLE1_DPMLETC_ML3_0(idx) (15 << (4 * (idx)))
2291
2292 /* BXT PHY Ref registers */
2293 #define _PORT_REF_DW3_A 0x16218C
2294 #define _PORT_REF_DW3_BC 0x6C18C
2295 #define GRC_DONE (1 << 22)
2296 #define BXT_PORT_REF_DW3(phy) _BXT_PHY((phy), _PORT_REF_DW3_BC)
2297
2298 #define _PORT_REF_DW6_A 0x162198
2299 #define _PORT_REF_DW6_BC 0x6C198
2300 #define GRC_CODE_SHIFT 24
2301 #define GRC_CODE_MASK (0xFF << GRC_CODE_SHIFT)
2302 #define GRC_CODE_FAST_SHIFT 16
2303 #define GRC_CODE_FAST_MASK (0xFF << GRC_CODE_FAST_SHIFT)
2304 #define GRC_CODE_SLOW_SHIFT 8
2305 #define GRC_CODE_SLOW_MASK (0xFF << GRC_CODE_SLOW_SHIFT)
2306 #define GRC_CODE_NOM_MASK 0xFF
2307 #define BXT_PORT_REF_DW6(phy) _BXT_PHY((phy), _PORT_REF_DW6_BC)
2308
2309 #define _PORT_REF_DW8_A 0x1621A0
2310 #define _PORT_REF_DW8_BC 0x6C1A0
2311 #define GRC_DIS (1 << 15)
2312 #define GRC_RDY_OVRD (1 << 1)
2313 #define BXT_PORT_REF_DW8(phy) _BXT_PHY((phy), _PORT_REF_DW8_BC)
2314
2315 /* BXT PHY PCS registers */
2316 #define _PORT_PCS_DW10_LN01_A 0x162428
2317 #define _PORT_PCS_DW10_LN01_B 0x6C428
2318 #define _PORT_PCS_DW10_LN01_C 0x6C828
2319 #define _PORT_PCS_DW10_GRP_A 0x162C28
2320 #define _PORT_PCS_DW10_GRP_B 0x6CC28
2321 #define _PORT_PCS_DW10_GRP_C 0x6CE28
2322 #define BXT_PORT_PCS_DW10_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2323 _PORT_PCS_DW10_LN01_B, \
2324 _PORT_PCS_DW10_LN01_C)
2325 #define BXT_PORT_PCS_DW10_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2326 _PORT_PCS_DW10_GRP_B, \
2327 _PORT_PCS_DW10_GRP_C)
2328
2329 #define TX2_SWING_CALC_INIT (1 << 31)
2330 #define TX1_SWING_CALC_INIT (1 << 30)
2331
2332 #define _PORT_PCS_DW12_LN01_A 0x162430
2333 #define _PORT_PCS_DW12_LN01_B 0x6C430
2334 #define _PORT_PCS_DW12_LN01_C 0x6C830
2335 #define _PORT_PCS_DW12_LN23_A 0x162630
2336 #define _PORT_PCS_DW12_LN23_B 0x6C630
2337 #define _PORT_PCS_DW12_LN23_C 0x6CA30
2338 #define _PORT_PCS_DW12_GRP_A 0x162c30
2339 #define _PORT_PCS_DW12_GRP_B 0x6CC30
2340 #define _PORT_PCS_DW12_GRP_C 0x6CE30
2341 #define LANESTAGGER_STRAP_OVRD (1 << 6)
2342 #define LANE_STAGGER_MASK 0x1F
2343 #define BXT_PORT_PCS_DW12_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2344 _PORT_PCS_DW12_LN01_B, \
2345 _PORT_PCS_DW12_LN01_C)
2346 #define BXT_PORT_PCS_DW12_LN23(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2347 _PORT_PCS_DW12_LN23_B, \
2348 _PORT_PCS_DW12_LN23_C)
2349 #define BXT_PORT_PCS_DW12_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2350 _PORT_PCS_DW12_GRP_B, \
2351 _PORT_PCS_DW12_GRP_C)
2352
2353 /* BXT PHY TX registers */
2354 #define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \
2355 ((lane) & 1) * 0x80)
2356
2357 #define _PORT_TX_DW2_LN0_A 0x162508
2358 #define _PORT_TX_DW2_LN0_B 0x6C508
2359 #define _PORT_TX_DW2_LN0_C 0x6C908
2360 #define _PORT_TX_DW2_GRP_A 0x162D08
2361 #define _PORT_TX_DW2_GRP_B 0x6CD08
2362 #define _PORT_TX_DW2_GRP_C 0x6CF08
2363 #define BXT_PORT_TX_DW2_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2364 _PORT_TX_DW2_LN0_B, \
2365 _PORT_TX_DW2_LN0_C)
2366 #define BXT_PORT_TX_DW2_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2367 _PORT_TX_DW2_GRP_B, \
2368 _PORT_TX_DW2_GRP_C)
2369 #define MARGIN_000_SHIFT 16
2370 #define MARGIN_000 (0xFF << MARGIN_000_SHIFT)
2371 #define UNIQ_TRANS_SCALE_SHIFT 8
2372 #define UNIQ_TRANS_SCALE (0xFF << UNIQ_TRANS_SCALE_SHIFT)
2373
2374 #define _PORT_TX_DW3_LN0_A 0x16250C
2375 #define _PORT_TX_DW3_LN0_B 0x6C50C
2376 #define _PORT_TX_DW3_LN0_C 0x6C90C
2377 #define _PORT_TX_DW3_GRP_A 0x162D0C
2378 #define _PORT_TX_DW3_GRP_B 0x6CD0C
2379 #define _PORT_TX_DW3_GRP_C 0x6CF0C
2380 #define BXT_PORT_TX_DW3_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2381 _PORT_TX_DW3_LN0_B, \
2382 _PORT_TX_DW3_LN0_C)
2383 #define BXT_PORT_TX_DW3_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2384 _PORT_TX_DW3_GRP_B, \
2385 _PORT_TX_DW3_GRP_C)
2386 #define SCALE_DCOMP_METHOD (1 << 26)
2387 #define UNIQUE_TRANGE_EN_METHOD (1 << 27)
2388
2389 #define _PORT_TX_DW4_LN0_A 0x162510
2390 #define _PORT_TX_DW4_LN0_B 0x6C510
2391 #define _PORT_TX_DW4_LN0_C 0x6C910
2392 #define _PORT_TX_DW4_GRP_A 0x162D10
2393 #define _PORT_TX_DW4_GRP_B 0x6CD10
2394 #define _PORT_TX_DW4_GRP_C 0x6CF10
2395 #define BXT_PORT_TX_DW4_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2396 _PORT_TX_DW4_LN0_B, \
2397 _PORT_TX_DW4_LN0_C)
2398 #define BXT_PORT_TX_DW4_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2399 _PORT_TX_DW4_GRP_B, \
2400 _PORT_TX_DW4_GRP_C)
2401 #define DEEMPH_SHIFT 24
2402 #define DE_EMPHASIS (0xFF << DEEMPH_SHIFT)
2403
2404 #define _PORT_TX_DW5_LN0_A 0x162514
2405 #define _PORT_TX_DW5_LN0_B 0x6C514
2406 #define _PORT_TX_DW5_LN0_C 0x6C914
2407 #define _PORT_TX_DW5_GRP_A 0x162D14
2408 #define _PORT_TX_DW5_GRP_B 0x6CD14
2409 #define _PORT_TX_DW5_GRP_C 0x6CF14
2410 #define BXT_PORT_TX_DW5_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2411 _PORT_TX_DW5_LN0_B, \
2412 _PORT_TX_DW5_LN0_C)
2413 #define BXT_PORT_TX_DW5_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2414 _PORT_TX_DW5_GRP_B, \
2415 _PORT_TX_DW5_GRP_C)
2416 #define DCC_DELAY_RANGE_1 (1 << 9)
2417 #define DCC_DELAY_RANGE_2 (1 << 8)
2418
2419 #define _PORT_TX_DW14_LN0_A 0x162538
2420 #define _PORT_TX_DW14_LN0_B 0x6C538
2421 #define _PORT_TX_DW14_LN0_C 0x6C938
2422 #define LATENCY_OPTIM_SHIFT 30
2423 #define LATENCY_OPTIM (1 << LATENCY_OPTIM_SHIFT)
2424 #define BXT_PORT_TX_DW14_LN(phy, ch, lane) \
2425 _MMIO(_BXT_PHY_CH(phy, ch, _PORT_TX_DW14_LN0_B, \
2426 _PORT_TX_DW14_LN0_C) + \
2427 _BXT_LANE_OFFSET(lane))
2428
2429 /* UAIMI scratch pad register 1 */
2430 #define UAIMI_SPR1 _MMIO(0x4F074)
2431 /* SKL VccIO mask */
2432 #define SKL_VCCIO_MASK 0x1
2433 /* SKL balance leg register */
2434 #define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C)
2435 /* I_boost values */
2436 #define BALANCE_LEG_SHIFT(port) (8 + 3 * (port))
2437 #define BALANCE_LEG_MASK(port) (7 << (8 + 3 * (port)))
2438 /* Balance leg disable bits */
2439 #define BALANCE_LEG_DISABLE_SHIFT 23
2440 #define BALANCE_LEG_DISABLE(port) (1 << (23 + (port)))
2441
2442 /*
2443 * Fence registers
2444 * [0-7] @ 0x2000 gen2,gen3
2445 * [8-15] @ 0x3000 945,g33,pnv
2446 *
2447 * [0-15] @ 0x3000 gen4,gen5
2448 *
2449 * [0-15] @ 0x100000 gen6,vlv,chv
2450 * [0-31] @ 0x100000 gen7+
2451 */
2452 #define FENCE_REG(i) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4)
2453 #define I830_FENCE_START_MASK 0x07f80000
2454 #define I830_FENCE_TILING_Y_SHIFT 12
2455 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
2456 #define I830_FENCE_PITCH_SHIFT 4
2457 #define I830_FENCE_REG_VALID (1 << 0)
2458 #define I915_FENCE_MAX_PITCH_VAL 4
2459 #define I830_FENCE_MAX_PITCH_VAL 6
2460 #define I830_FENCE_MAX_SIZE_VAL (1 << 8)
2461
2462 #define I915_FENCE_START_MASK 0x0ff00000
2463 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
2464
2465 #define FENCE_REG_965_LO(i) _MMIO(0x03000 + (i) * 8)
2466 #define FENCE_REG_965_HI(i) _MMIO(0x03000 + (i) * 8 + 4)
2467 #define I965_FENCE_PITCH_SHIFT 2
2468 #define I965_FENCE_TILING_Y_SHIFT 1
2469 #define I965_FENCE_REG_VALID (1 << 0)
2470 #define I965_FENCE_MAX_PITCH_VAL 0x0400
2471
2472 #define FENCE_REG_GEN6_LO(i) _MMIO(0x100000 + (i) * 8)
2473 #define FENCE_REG_GEN6_HI(i) _MMIO(0x100000 + (i) * 8 + 4)
2474 #define GEN6_FENCE_PITCH_SHIFT 32
2475 #define GEN7_FENCE_MAX_PITCH_VAL 0x0800
2476
2477
2478 /* control register for cpu gtt access */
2479 #define TILECTL _MMIO(0x101000)
2480 #define TILECTL_SWZCTL (1 << 0)
2481 #define TILECTL_TLBPF (1 << 1)
2482 #define TILECTL_TLB_PREFETCH_DIS (1 << 2)
2483 #define TILECTL_BACKSNOOP_DIS (1 << 3)
2484
2485 /*
2486 * Instruction and interrupt control regs
2487 */
2488 #define PGTBL_CTL _MMIO(0x02020)
2489 #define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */
2490 #define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */
2491 #define PGTBL_ER _MMIO(0x02024)
2492 #define PRB0_BASE (0x2030 - 0x30)
2493 #define PRB1_BASE (0x2040 - 0x30) /* 830,gen3 */
2494 #define PRB2_BASE (0x2050 - 0x30) /* gen3 */
2495 #define SRB0_BASE (0x2100 - 0x30) /* gen2 */
2496 #define SRB1_BASE (0x2110 - 0x30) /* gen2 */
2497 #define SRB2_BASE (0x2120 - 0x30) /* 830 */
2498 #define SRB3_BASE (0x2130 - 0x30) /* 830 */
2499 #define RENDER_RING_BASE 0x02000
2500 #define BSD_RING_BASE 0x04000
2501 #define GEN6_BSD_RING_BASE 0x12000
2502 #define GEN8_BSD2_RING_BASE 0x1c000
2503 #define GEN11_BSD_RING_BASE 0x1c0000
2504 #define GEN11_BSD2_RING_BASE 0x1c4000
2505 #define GEN11_BSD3_RING_BASE 0x1d0000
2506 #define GEN11_BSD4_RING_BASE 0x1d4000
2507 #define VEBOX_RING_BASE 0x1a000
2508 #define GEN11_VEBOX_RING_BASE 0x1c8000
2509 #define GEN11_VEBOX2_RING_BASE 0x1d8000
2510 #define BLT_RING_BASE 0x22000
2511 #define RING_TAIL(base) _MMIO((base) + 0x30)
2512 #define RING_HEAD(base) _MMIO((base) + 0x34)
2513 #define RING_START(base) _MMIO((base) + 0x38)
2514 #define RING_CTL(base) _MMIO((base) + 0x3c)
2515 #define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */
2516 #define RING_SYNC_0(base) _MMIO((base) + 0x40)
2517 #define RING_SYNC_1(base) _MMIO((base) + 0x44)
2518 #define RING_SYNC_2(base) _MMIO((base) + 0x48)
2519 #define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
2520 #define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
2521 #define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE))
2522 #define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
2523 #define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
2524 #define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE))
2525 #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
2526 #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
2527 #define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE))
2528 #define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE))
2529 #define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE))
2530 #define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE))
2531 #define GEN6_NOSYNC INVALID_MMIO_REG
2532 #define RING_PSMI_CTL(base) _MMIO((base) + 0x50)
2533 #define RING_MAX_IDLE(base) _MMIO((base) + 0x54)
2534 #define RING_HWS_PGA(base) _MMIO((base) + 0x80)
2535 #define RING_ID(base) _MMIO((base) + 0x8c)
2536 #define RING_HWS_PGA_GEN6(base) _MMIO((base) + 0x2080)
2537 #define RING_RESET_CTL(base) _MMIO((base) + 0xd0)
2538 #define RESET_CTL_CAT_ERROR REG_BIT(2)
2539 #define RESET_CTL_READY_TO_RESET REG_BIT(1)
2540 #define RESET_CTL_REQUEST_RESET REG_BIT(0)
2541
2542 #define RING_SEMA_WAIT_POLL(base) _MMIO((base) + 0x24c)
2543
2544 #define HSW_GTT_CACHE_EN _MMIO(0x4024)
2545 #define GTT_CACHE_EN_ALL 0xF0007FFF
2546 #define GEN7_WR_WATERMARK _MMIO(0x4028)
2547 #define GEN7_GFX_PRIO_CTRL _MMIO(0x402C)
2548 #define ARB_MODE _MMIO(0x4030)
2549 #define ARB_MODE_SWIZZLE_SNB (1 << 4)
2550 #define ARB_MODE_SWIZZLE_IVB (1 << 5)
2551 #define GEN7_GFX_PEND_TLB0 _MMIO(0x4034)
2552 #define GEN7_GFX_PEND_TLB1 _MMIO(0x4038)
2553 /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */
2554 #define GEN7_LRA_LIMITS(i) _MMIO(0x403C + (i) * 4)
2555 #define GEN7_LRA_LIMITS_REG_NUM 13
2556 #define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070)
2557 #define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074)
2558
2559 #define GAMTARBMODE _MMIO(0x04a08)
2560 #define ARB_MODE_BWGTLB_DISABLE (1 << 9)
2561 #define ARB_MODE_SWIZZLE_BDW (1 << 1)
2562 #define RENDER_HWS_PGA_GEN7 _MMIO(0x04080)
2563 #define RING_FAULT_REG(engine) _MMIO(0x4094 + 0x100 * (engine)->hw_id)
2564 #define GEN8_RING_FAULT_REG _MMIO(0x4094)
2565 #define GEN12_RING_FAULT_REG _MMIO(0xcec4)
2566 #define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x7)
2567 #define RING_FAULT_GTTSEL_MASK (1 << 11)
2568 #define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff)
2569 #define RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3)
2570 #define RING_FAULT_VALID (1 << 0)
2571 #define DONE_REG _MMIO(0x40b0)
2572 #define GEN12_GAM_DONE _MMIO(0xcf68)
2573 #define GEN8_PRIVATE_PAT_LO _MMIO(0x40e0)
2574 #define GEN8_PRIVATE_PAT_HI _MMIO(0x40e0 + 4)
2575 #define GEN10_PAT_INDEX(index) _MMIO(0x40e0 + (index) * 4)
2576 #define GEN12_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4)
2577 #define BSD_HWS_PGA_GEN7 _MMIO(0x04180)
2578 #define GEN12_GFX_CCS_AUX_NV _MMIO(0x4208)
2579 #define GEN12_VD0_AUX_NV _MMIO(0x4218)
2580 #define GEN12_VD1_AUX_NV _MMIO(0x4228)
2581 #define GEN12_VD2_AUX_NV _MMIO(0x4298)
2582 #define GEN12_VD3_AUX_NV _MMIO(0x42A8)
2583 #define GEN12_VE0_AUX_NV _MMIO(0x4238)
2584 #define GEN12_VE1_AUX_NV _MMIO(0x42B8)
2585 #define AUX_INV REG_BIT(0)
2586 #define BLT_HWS_PGA_GEN7 _MMIO(0x04280)
2587 #define VEBOX_HWS_PGA_GEN7 _MMIO(0x04380)
2588 #define RING_ACTHD(base) _MMIO((base) + 0x74)
2589 #define RING_ACTHD_UDW(base) _MMIO((base) + 0x5c)
2590 #define RING_NOPID(base) _MMIO((base) + 0x94)
2591 #define RING_IMR(base) _MMIO((base) + 0xa8)
2592 #define RING_HWSTAM(base) _MMIO((base) + 0x98)
2593 #define RING_TIMESTAMP(base) _MMIO((base) + 0x358)
2594 #define RING_TIMESTAMP_UDW(base) _MMIO((base) + 0x358 + 4)
2595 #define TAIL_ADDR 0x001FFFF8
2596 #define HEAD_WRAP_COUNT 0xFFE00000
2597 #define HEAD_WRAP_ONE 0x00200000
2598 #define HEAD_ADDR 0x001FFFFC
2599 #define RING_NR_PAGES 0x001FF000
2600 #define RING_REPORT_MASK 0x00000006
2601 #define RING_REPORT_64K 0x00000002
2602 #define RING_REPORT_128K 0x00000004
2603 #define RING_NO_REPORT 0x00000000
2604 #define RING_VALID_MASK 0x00000001
2605 #define RING_VALID 0x00000001
2606 #define RING_INVALID 0x00000000
2607 #define RING_WAIT_I8XX (1 << 0) /* gen2, PRBx_HEAD */
2608 #define RING_WAIT (1 << 11) /* gen3+, PRBx_CTL */
2609 #define RING_WAIT_SEMAPHORE (1 << 10) /* gen6+ */
2610
2611 /* There are 16 64-bit CS General Purpose Registers per-engine on Gen8+ */
2612 #define GEN8_RING_CS_GPR(base, n) _MMIO((base) + 0x600 + (n) * 8)
2613 #define GEN8_RING_CS_GPR_UDW(base, n) _MMIO((base) + 0x600 + (n) * 8 + 4)
2614
2615 #define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) + (i) * 4)
2616 #define RING_FORCE_TO_NONPRIV_ADDRESS_MASK REG_GENMASK(25, 2)
2617 #define RING_FORCE_TO_NONPRIV_ACCESS_RW (0 << 28) /* CFL+ & Gen11+ */
2618 #define RING_FORCE_TO_NONPRIV_ACCESS_RD (1 << 28)
2619 #define RING_FORCE_TO_NONPRIV_ACCESS_WR (2 << 28)
2620 #define RING_FORCE_TO_NONPRIV_ACCESS_INVALID (3 << 28)
2621 #define RING_FORCE_TO_NONPRIV_ACCESS_MASK (3 << 28)
2622 #define RING_FORCE_TO_NONPRIV_RANGE_1 (0 << 0) /* CFL+ & Gen11+ */
2623 #define RING_FORCE_TO_NONPRIV_RANGE_4 (1 << 0)
2624 #define RING_FORCE_TO_NONPRIV_RANGE_16 (2 << 0)
2625 #define RING_FORCE_TO_NONPRIV_RANGE_64 (3 << 0)
2626 #define RING_FORCE_TO_NONPRIV_RANGE_MASK (3 << 0)
2627 #define RING_FORCE_TO_NONPRIV_MASK_VALID \
2628 (RING_FORCE_TO_NONPRIV_RANGE_MASK \
2629 | RING_FORCE_TO_NONPRIV_ACCESS_MASK)
2630 #define RING_MAX_NONPRIV_SLOTS 12
2631
2632 #define GEN7_TLB_RD_ADDR _MMIO(0x4700)
2633
2634 #define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0)
2635 #define GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS (1 << 18)
2636
2637 #define GEN8_GAMW_ECO_DEV_RW_IA _MMIO(0x4080)
2638 #define GAMW_ECO_ENABLE_64K_IPS_FIELD 0xF
2639 #define GAMW_ECO_DEV_CTX_RELOAD_DISABLE (1 << 7)
2640
2641 #define GAMT_CHKN_BIT_REG _MMIO(0x4ab8)
2642 #define GAMT_CHKN_DISABLE_L3_COH_PIPE (1 << 31)
2643 #define GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING (1 << 28)
2644 #define GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT (1 << 24)
2645
2646 #if 0
2647 #define PRB0_TAIL _MMIO(0x2030)
2648 #define PRB0_HEAD _MMIO(0x2034)
2649 #define PRB0_START _MMIO(0x2038)
2650 #define PRB0_CTL _MMIO(0x203c)
2651 #define PRB1_TAIL _MMIO(0x2040) /* 915+ only */
2652 #define PRB1_HEAD _MMIO(0x2044) /* 915+ only */
2653 #define PRB1_START _MMIO(0x2048) /* 915+ only */
2654 #define PRB1_CTL _MMIO(0x204c) /* 915+ only */
2655 #endif
2656 #define IPEIR_I965 _MMIO(0x2064)
2657 #define IPEHR_I965 _MMIO(0x2068)
2658 #define GEN7_SC_INSTDONE _MMIO(0x7100)
2659 #define GEN12_SC_INSTDONE_EXTRA _MMIO(0x7104)
2660 #define GEN12_SC_INSTDONE_EXTRA2 _MMIO(0x7108)
2661 #define GEN7_SAMPLER_INSTDONE _MMIO(0xe160)
2662 #define GEN7_ROW_INSTDONE _MMIO(0xe164)
2663 #define GEN8_MCR_SELECTOR _MMIO(0xfdc)
2664 #define GEN8_MCR_SLICE(slice) (((slice) & 3) << 26)
2665 #define GEN8_MCR_SLICE_MASK GEN8_MCR_SLICE(3)
2666 #define GEN8_MCR_SUBSLICE(subslice) (((subslice) & 3) << 24)
2667 #define GEN8_MCR_SUBSLICE_MASK GEN8_MCR_SUBSLICE(3)
2668 #define GEN11_MCR_SLICE(slice) (((slice) & 0xf) << 27)
2669 #define GEN11_MCR_SLICE_MASK GEN11_MCR_SLICE(0xf)
2670 #define GEN11_MCR_SUBSLICE(subslice) (((subslice) & 0x7) << 24)
2671 #define GEN11_MCR_SUBSLICE_MASK GEN11_MCR_SUBSLICE(0x7)
2672 #define RING_IPEIR(base) _MMIO((base) + 0x64)
2673 #define RING_IPEHR(base) _MMIO((base) + 0x68)
2674 #define RING_EIR(base) _MMIO((base) + 0xb0)
2675 #define RING_EMR(base) _MMIO((base) + 0xb4)
2676 #define RING_ESR(base) _MMIO((base) + 0xb8)
2677 /*
2678 * On GEN4, only the render ring INSTDONE exists and has a different
2679 * layout than the GEN7+ version.
2680 * The GEN2 counterpart of this register is GEN2_INSTDONE.
2681 */
2682 #define RING_INSTDONE(base) _MMIO((base) + 0x6c)
2683 #define RING_INSTPS(base) _MMIO((base) + 0x70)
2684 #define RING_DMA_FADD(base) _MMIO((base) + 0x78)
2685 #define RING_DMA_FADD_UDW(base) _MMIO((base) + 0x60) /* gen8+ */
2686 #define RING_INSTPM(base) _MMIO((base) + 0xc0)
2687 #define RING_MI_MODE(base) _MMIO((base) + 0x9c)
2688 #define RING_CMD_BUF_CCTL(base) _MMIO((base) + 0x84)
2689 #define INSTPS _MMIO(0x2070) /* 965+ only */
2690 #define GEN4_INSTDONE1 _MMIO(0x207c) /* 965+ only, aka INSTDONE_2 on SNB */
2691 #define ACTHD_I965 _MMIO(0x2074)
2692 #define HWS_PGA _MMIO(0x2080)
2693 #define HWS_ADDRESS_MASK 0xfffff000
2694 #define HWS_START_ADDRESS_SHIFT 4
2695 #define PWRCTXA _MMIO(0x2088) /* 965GM+ only */
2696 #define PWRCTX_EN (1 << 0)
2697 #define IPEIR(base) _MMIO((base) + 0x88)
2698 #define IPEHR(base) _MMIO((base) + 0x8c)
2699 #define GEN2_INSTDONE _MMIO(0x2090)
2700 #define NOPID _MMIO(0x2094)
2701 #define HWSTAM _MMIO(0x2098)
2702 #define DMA_FADD_I8XX(base) _MMIO((base) + 0xd0)
2703 #define RING_BBSTATE(base) _MMIO((base) + 0x110)
2704 #define RING_BB_PPGTT (1 << 5)
2705 #define RING_SBBADDR(base) _MMIO((base) + 0x114) /* hsw+ */
2706 #define RING_SBBSTATE(base) _MMIO((base) + 0x118) /* hsw+ */
2707 #define RING_SBBADDR_UDW(base) _MMIO((base) + 0x11c) /* gen8+ */
2708 #define RING_BBADDR(base) _MMIO((base) + 0x140)
2709 #define RING_BBADDR_UDW(base) _MMIO((base) + 0x168) /* gen8+ */
2710 #define RING_BB_PER_CTX_PTR(base) _MMIO((base) + 0x1c0) /* gen8+ */
2711 #define RING_INDIRECT_CTX(base) _MMIO((base) + 0x1c4) /* gen8+ */
2712 #define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base) + 0x1c8) /* gen8+ */
2713 #define RING_CTX_TIMESTAMP(base) _MMIO((base) + 0x3a8) /* gen8+ */
2714
2715 #define ERROR_GEN6 _MMIO(0x40a0)
2716 #define GEN7_ERR_INT _MMIO(0x44040)
2717 #define ERR_INT_POISON (1 << 31)
2718 #define ERR_INT_MMIO_UNCLAIMED (1 << 13)
2719 #define ERR_INT_PIPE_CRC_DONE_C (1 << 8)
2720 #define ERR_INT_FIFO_UNDERRUN_C (1 << 6)
2721 #define ERR_INT_PIPE_CRC_DONE_B (1 << 5)
2722 #define ERR_INT_FIFO_UNDERRUN_B (1 << 3)
2723 #define ERR_INT_PIPE_CRC_DONE_A (1 << 2)
2724 #define ERR_INT_PIPE_CRC_DONE(pipe) (1 << (2 + (pipe) * 3))
2725 #define ERR_INT_FIFO_UNDERRUN_A (1 << 0)
2726 #define ERR_INT_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3))
2727
2728 #define GEN8_FAULT_TLB_DATA0 _MMIO(0x4b10)
2729 #define GEN8_FAULT_TLB_DATA1 _MMIO(0x4b14)
2730 #define GEN12_FAULT_TLB_DATA0 _MMIO(0xceb8)
2731 #define GEN12_FAULT_TLB_DATA1 _MMIO(0xcebc)
2732 #define FAULT_VA_HIGH_BITS (0xf << 0)
2733 #define FAULT_GTT_SEL (1 << 4)
2734
2735 #define GEN12_AUX_ERR_DBG _MMIO(0x43f4)
2736
2737 #define FPGA_DBG _MMIO(0x42300)
2738 #define FPGA_DBG_RM_NOCLAIM (1 << 31)
2739
2740 #define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028)
2741 #define CLAIM_ER_CLR (1 << 31)
2742 #define CLAIM_ER_OVERFLOW (1 << 16)
2743 #define CLAIM_ER_CTR_MASK 0xffff
2744
2745 #define DERRMR _MMIO(0x44050)
2746 /* Note that HBLANK events are reserved on bdw+ */
2747 #define DERRMR_PIPEA_SCANLINE (1 << 0)
2748 #define DERRMR_PIPEA_PRI_FLIP_DONE (1 << 1)
2749 #define DERRMR_PIPEA_SPR_FLIP_DONE (1 << 2)
2750 #define DERRMR_PIPEA_VBLANK (1 << 3)
2751 #define DERRMR_PIPEA_HBLANK (1 << 5)
2752 #define DERRMR_PIPEB_SCANLINE (1 << 8)
2753 #define DERRMR_PIPEB_PRI_FLIP_DONE (1 << 9)
2754 #define DERRMR_PIPEB_SPR_FLIP_DONE (1 << 10)
2755 #define DERRMR_PIPEB_VBLANK (1 << 11)
2756 #define DERRMR_PIPEB_HBLANK (1 << 13)
2757 /* Note that PIPEC is not a simple translation of PIPEA/PIPEB */
2758 #define DERRMR_PIPEC_SCANLINE (1 << 14)
2759 #define DERRMR_PIPEC_PRI_FLIP_DONE (1 << 15)
2760 #define DERRMR_PIPEC_SPR_FLIP_DONE (1 << 20)
2761 #define DERRMR_PIPEC_VBLANK (1 << 21)
2762 #define DERRMR_PIPEC_HBLANK (1 << 22)
2763
2764
2765 /* GM45+ chicken bits -- debug workaround bits that may be required
2766 * for various sorts of correct behavior. The top 16 bits of each are
2767 * the enables for writing to the corresponding low bit.
2768 */
2769 #define _3D_CHICKEN _MMIO(0x2084)
2770 #define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10)
2771 #define _3D_CHICKEN2 _MMIO(0x208c)
2772
2773 #define FF_SLICE_CHICKEN _MMIO(0x2088)
2774 #define FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX (1 << 1)
2775
2776 /* Disables pipelining of read flushes past the SF-WIZ interface.
2777 * Required on all Ironlake steppings according to the B-Spec, but the
2778 * particular danger of not doing so is not specified.
2779 */
2780 # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14)
2781 #define _3D_CHICKEN3 _MMIO(0x2090)
2782 #define _3D_CHICKEN_SF_PROVOKING_VERTEX_FIX (1 << 12)
2783 #define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10)
2784 #define _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE (1 << 5)
2785 #define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5)
2786 #define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x) << 1) /* gen8+ */
2787 #define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6 */
2788
2789 #define MI_MODE _MMIO(0x209c)
2790 # define VS_TIMER_DISPATCH (1 << 6)
2791 # define MI_FLUSH_ENABLE (1 << 12)
2792 # define ASYNC_FLIP_PERF_DISABLE (1 << 14)
2793 # define MODE_IDLE (1 << 9)
2794 # define STOP_RING (1 << 8)
2795
2796 #define GEN6_GT_MODE _MMIO(0x20d0)
2797 #define GEN7_GT_MODE _MMIO(0x7008)
2798 #define GEN6_WIZ_HASHING(hi, lo) (((hi) << 9) | ((lo) << 7))
2799 #define GEN6_WIZ_HASHING_8x8 GEN6_WIZ_HASHING(0, 0)
2800 #define GEN6_WIZ_HASHING_8x4 GEN6_WIZ_HASHING(0, 1)
2801 #define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0)
2802 #define GEN6_WIZ_HASHING_MASK GEN6_WIZ_HASHING(1, 1)
2803 #define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5)
2804 #define GEN9_IZ_HASHING_MASK(slice) (0x3 << ((slice) * 2))
2805 #define GEN9_IZ_HASHING(slice, val) ((val) << ((slice) * 2))
2806
2807 /* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */
2808 #define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4)
2809 #define GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2)
2810 #define GEN11_ENABLE_32_PLANE_MODE (1 << 7)
2811
2812 /* WaClearTdlStateAckDirtyBits */
2813 #define GEN8_STATE_ACK _MMIO(0x20F0)
2814 #define GEN9_STATE_ACK_SLICE1 _MMIO(0x20F8)
2815 #define GEN9_STATE_ACK_SLICE2 _MMIO(0x2100)
2816 #define GEN9_STATE_ACK_TDL0 (1 << 12)
2817 #define GEN9_STATE_ACK_TDL1 (1 << 13)
2818 #define GEN9_STATE_ACK_TDL2 (1 << 14)
2819 #define GEN9_STATE_ACK_TDL3 (1 << 15)
2820 #define GEN9_SUBSLICE_TDL_ACK_BITS \
2821 (GEN9_STATE_ACK_TDL3 | GEN9_STATE_ACK_TDL2 | \
2822 GEN9_STATE_ACK_TDL1 | GEN9_STATE_ACK_TDL0)
2823
2824 #define GFX_MODE _MMIO(0x2520)
2825 #define GFX_MODE_GEN7 _MMIO(0x229c)
2826 #define RING_MODE_GEN7(base) _MMIO((base) + 0x29c)
2827 #define GFX_RUN_LIST_ENABLE (1 << 15)
2828 #define GFX_INTERRUPT_STEERING (1 << 14)
2829 #define GFX_TLB_INVALIDATE_EXPLICIT (1 << 13)
2830 #define GFX_SURFACE_FAULT_ENABLE (1 << 12)
2831 #define GFX_REPLAY_MODE (1 << 11)
2832 #define GFX_PSMI_GRANULARITY (1 << 10)
2833 #define GFX_PPGTT_ENABLE (1 << 9)
2834 #define GEN8_GFX_PPGTT_48B (1 << 7)
2835
2836 #define GFX_FORWARD_VBLANK_MASK (3 << 5)
2837 #define GFX_FORWARD_VBLANK_NEVER (0 << 5)
2838 #define GFX_FORWARD_VBLANK_ALWAYS (1 << 5)
2839 #define GFX_FORWARD_VBLANK_COND (2 << 5)
2840
2841 #define GEN11_GFX_DISABLE_LEGACY_MODE (1 << 3)
2842
2843 #define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030)
2844 #define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034)
2845 #define SCPD0 _MMIO(0x209c) /* 915+ only */
2846 #define SCPD_FBC_IGNORE_3D (1 << 6)
2847 #define CSTATE_RENDER_CLOCK_GATE_DISABLE (1 << 5)
2848 #define GEN2_IER _MMIO(0x20a0)
2849 #define GEN2_IIR _MMIO(0x20a4)
2850 #define GEN2_IMR _MMIO(0x20a8)
2851 #define GEN2_ISR _MMIO(0x20ac)
2852 #define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060)
2853 #define GINT_DIS (1 << 22)
2854 #define GCFG_DIS (1 << 8)
2855 #define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064)
2856 #define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084)
2857 #define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0)
2858 #define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4)
2859 #define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8)
2860 #define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac)
2861 #define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120)
2862 #define VLV_PCBR_ADDR_SHIFT 12
2863
2864 #define DISPLAY_PLANE_FLIP_PENDING(plane) (1 << (11 - (plane))) /* A and B only */
2865 #define EIR _MMIO(0x20b0)
2866 #define EMR _MMIO(0x20b4)
2867 #define ESR _MMIO(0x20b8)
2868 #define GM45_ERROR_PAGE_TABLE (1 << 5)
2869 #define GM45_ERROR_MEM_PRIV (1 << 4)
2870 #define I915_ERROR_PAGE_TABLE (1 << 4)
2871 #define GM45_ERROR_CP_PRIV (1 << 3)
2872 #define I915_ERROR_MEMORY_REFRESH (1 << 1)
2873 #define I915_ERROR_INSTRUCTION (1 << 0)
2874 #define INSTPM _MMIO(0x20c0)
2875 #define INSTPM_SELF_EN (1 << 12) /* 915GM only */
2876 #define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts
2877 will not assert AGPBUSY# and will only
2878 be delivered when out of C3. */
2879 #define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */
2880 #define INSTPM_TLB_INVALIDATE (1 << 9)
2881 #define INSTPM_SYNC_FLUSH (1 << 5)
2882 #define ACTHD(base) _MMIO((base) + 0xc8)
2883 #define MEM_MODE _MMIO(0x20cc)
2884 #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */
2885 #define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */
2886 #define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) /* 85x only */
2887 #define FW_BLC _MMIO(0x20d8)
2888 #define FW_BLC2 _MMIO(0x20dc)
2889 #define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */
2890 #define FW_BLC_SELF_EN_MASK (1 << 31)
2891 #define FW_BLC_SELF_FIFO_MASK (1 << 16) /* 945 only */
2892 #define FW_BLC_SELF_EN (1 << 15) /* 945 only */
2893 #define MM_BURST_LENGTH 0x00700000
2894 #define MM_FIFO_WATERMARK 0x0001F000
2895 #define LM_BURST_LENGTH 0x00000700
2896 #define LM_FIFO_WATERMARK 0x0000001F
2897 #define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */
2898
2899 #define _MBUS_ABOX0_CTL 0x45038
2900 #define _MBUS_ABOX1_CTL 0x45048
2901 #define _MBUS_ABOX2_CTL 0x4504C
2902 #define MBUS_ABOX_CTL(x) _MMIO(_PICK(x, _MBUS_ABOX0_CTL, \
2903 _MBUS_ABOX1_CTL, \
2904 _MBUS_ABOX2_CTL))
2905 #define MBUS_ABOX_BW_CREDIT_MASK (3 << 20)
2906 #define MBUS_ABOX_BW_CREDIT(x) ((x) << 20)
2907 #define MBUS_ABOX_B_CREDIT_MASK (0xF << 16)
2908 #define MBUS_ABOX_B_CREDIT(x) ((x) << 16)
2909 #define MBUS_ABOX_BT_CREDIT_POOL2_MASK (0x1F << 8)
2910 #define MBUS_ABOX_BT_CREDIT_POOL2(x) ((x) << 8)
2911 #define MBUS_ABOX_BT_CREDIT_POOL1_MASK (0x1F << 0)
2912 #define MBUS_ABOX_BT_CREDIT_POOL1(x) ((x) << 0)
2913
2914 #define _PIPEA_MBUS_DBOX_CTL 0x7003C
2915 #define _PIPEB_MBUS_DBOX_CTL 0x7103C
2916 #define PIPE_MBUS_DBOX_CTL(pipe) _MMIO_PIPE(pipe, _PIPEA_MBUS_DBOX_CTL, \
2917 _PIPEB_MBUS_DBOX_CTL)
2918 #define MBUS_DBOX_BW_CREDIT_MASK (3 << 14)
2919 #define MBUS_DBOX_BW_CREDIT(x) ((x) << 14)
2920 #define MBUS_DBOX_B_CREDIT_MASK (0x1F << 8)
2921 #define MBUS_DBOX_B_CREDIT(x) ((x) << 8)
2922 #define MBUS_DBOX_A_CREDIT_MASK (0xF << 0)
2923 #define MBUS_DBOX_A_CREDIT(x) ((x) << 0)
2924
2925 #define MBUS_UBOX_CTL _MMIO(0x4503C)
2926 #define MBUS_BBOX_CTL_S1 _MMIO(0x45040)
2927 #define MBUS_BBOX_CTL_S2 _MMIO(0x45044)
2928
2929 #define HDPORT_STATE _MMIO(0x45050)
2930 #define HDPORT_DPLL_USED_MASK REG_GENMASK(14, 12)
2931 #define HDPORT_PHY_USED_DP(phy) REG_BIT(2 * (phy) + 2)
2932 #define HDPORT_PHY_USED_HDMI(phy) REG_BIT(2 * (phy) + 1)
2933 #define HDPORT_ENABLED REG_BIT(0)
2934
2935 /* Make render/texture TLB fetches lower priorty than associated data
2936 * fetches. This is not turned on by default
2937 */
2938 #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
2939
2940 /* Isoch request wait on GTT enable (Display A/B/C streams).
2941 * Make isoch requests stall on the TLB update. May cause
2942 * display underruns (test mode only)
2943 */
2944 #define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
2945
2946 /* Block grant count for isoch requests when block count is
2947 * set to a finite value.
2948 */
2949 #define MI_ARB_BLOCK_GRANT_MASK (3 << 12)
2950 #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */
2951 #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */
2952 #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */
2953 #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */
2954
2955 /* Enable render writes to complete in C2/C3/C4 power states.
2956 * If this isn't enabled, render writes are prevented in low
2957 * power states. That seems bad to me.
2958 */
2959 #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
2960
2961 /* This acknowledges an async flip immediately instead
2962 * of waiting for 2TLB fetches.
2963 */
2964 #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
2965
2966 /* Enables non-sequential data reads through arbiter
2967 */
2968 #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
2969
2970 /* Disable FSB snooping of cacheable write cycles from binner/render
2971 * command stream
2972 */
2973 #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
2974
2975 /* Arbiter time slice for non-isoch streams */
2976 #define MI_ARB_TIME_SLICE_MASK (7 << 5)
2977 #define MI_ARB_TIME_SLICE_1 (0 << 5)
2978 #define MI_ARB_TIME_SLICE_2 (1 << 5)
2979 #define MI_ARB_TIME_SLICE_4 (2 << 5)
2980 #define MI_ARB_TIME_SLICE_6 (3 << 5)
2981 #define MI_ARB_TIME_SLICE_8 (4 << 5)
2982 #define MI_ARB_TIME_SLICE_10 (5 << 5)
2983 #define MI_ARB_TIME_SLICE_14 (6 << 5)
2984 #define MI_ARB_TIME_SLICE_16 (7 << 5)
2985
2986 /* Low priority grace period page size */
2987 #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
2988 #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
2989
2990 /* Disable display A/B trickle feed */
2991 #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
2992
2993 /* Set display plane priority */
2994 #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
2995 #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
2996
2997 #define MI_STATE _MMIO(0x20e4) /* gen2 only */
2998 #define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */
2999 #define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */
3000
3001 #define CACHE_MODE_0 _MMIO(0x2120) /* 915+ only */
3002 #define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1 << 8)
3003 #define CM0_IZ_OPT_DISABLE (1 << 6)
3004 #define CM0_ZR_OPT_DISABLE (1 << 5)
3005 #define CM0_STC_EVICT_DISABLE_LRA_SNB (1 << 5)
3006 #define CM0_DEPTH_EVICT_DISABLE (1 << 4)
3007 #define CM0_COLOR_EVICT_DISABLE (1 << 3)
3008 #define CM0_DEPTH_WRITE_DISABLE (1 << 1)
3009 #define CM0_RC_OP_FLUSH_DISABLE (1 << 0)
3010 #define GFX_FLSH_CNTL _MMIO(0x2170) /* 915+ only */
3011 #define GFX_FLSH_CNTL_GEN6 _MMIO(0x101008)
3012 #define GFX_FLSH_CNTL_EN (1 << 0)
3013 #define ECOSKPD _MMIO(0x21d0)
3014 #define ECO_CONSTANT_BUFFER_SR_DISABLE REG_BIT(4)
3015 #define ECO_GATING_CX_ONLY (1 << 3)
3016 #define ECO_FLIP_DONE (1 << 0)
3017
3018 #define CACHE_MODE_0_GEN7 _MMIO(0x7000) /* IVB+ */
3019 #define RC_OP_FLUSH_ENABLE (1 << 0)
3020 #define HIZ_RAW_STALL_OPT_DISABLE (1 << 2)
3021 #define CACHE_MODE_1 _MMIO(0x7004) /* IVB+ */
3022 #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1 << 6)
3023 #define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1 << 6)
3024 #define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1 << 1)
3025
3026 #define GEN6_BLITTER_ECOSKPD _MMIO(0x221d0)
3027 #define GEN6_BLITTER_LOCK_SHIFT 16
3028 #define GEN6_BLITTER_FBC_NOTIFY (1 << 3)
3029
3030 #define GEN6_RC_SLEEP_PSMI_CONTROL _MMIO(0x2050)
3031 #define GEN6_PSMI_SLEEP_MSG_DISABLE (1 << 0)
3032 #define GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)
3033 #define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)
3034 #define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1 << 10)
3035
3036 #define GEN6_RCS_PWR_FSM _MMIO(0x22ac)
3037 #define GEN9_RCS_FE_FSM2 _MMIO(0x22a4)
3038
3039 #define GEN10_CACHE_MODE_SS _MMIO(0xe420)
3040 #define FLOAT_BLEND_OPTIMIZATION_ENABLE (1 << 4)
3041
3042 /* Fuse readout registers for GT */
3043 #define HSW_PAVP_FUSE1 _MMIO(0x911C)
3044 #define HSW_F1_EU_DIS_SHIFT 16
3045 #define HSW_F1_EU_DIS_MASK (0x3 << HSW_F1_EU_DIS_SHIFT)
3046 #define HSW_F1_EU_DIS_10EUS 0
3047 #define HSW_F1_EU_DIS_8EUS 1
3048 #define HSW_F1_EU_DIS_6EUS 2
3049
3050 #define CHV_FUSE_GT _MMIO(VLV_DISPLAY_BASE + 0x2168)
3051 #define CHV_FGT_DISABLE_SS0 (1 << 10)
3052 #define CHV_FGT_DISABLE_SS1 (1 << 11)
3053 #define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16
3054 #define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT)
3055 #define CHV_FGT_EU_DIS_SS0_R1_SHIFT 20
3056 #define CHV_FGT_EU_DIS_SS0_R1_MASK (0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT)
3057 #define CHV_FGT_EU_DIS_SS1_R0_SHIFT 24
3058 #define CHV_FGT_EU_DIS_SS1_R0_MASK (0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT)
3059 #define CHV_FGT_EU_DIS_SS1_R1_SHIFT 28
3060 #define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT)
3061
3062 #define GEN8_FUSE2 _MMIO(0x9120)
3063 #define GEN8_F2_SS_DIS_SHIFT 21
3064 #define GEN8_F2_SS_DIS_MASK (0x7 << GEN8_F2_SS_DIS_SHIFT)
3065 #define GEN8_F2_S_ENA_SHIFT 25
3066 #define GEN8_F2_S_ENA_MASK (0x7 << GEN8_F2_S_ENA_SHIFT)
3067
3068 #define GEN9_F2_SS_DIS_SHIFT 20
3069 #define GEN9_F2_SS_DIS_MASK (0xf << GEN9_F2_SS_DIS_SHIFT)
3070
3071 #define GEN10_F2_S_ENA_SHIFT 22
3072 #define GEN10_F2_S_ENA_MASK (0x3f << GEN10_F2_S_ENA_SHIFT)
3073 #define GEN10_F2_SS_DIS_SHIFT 18
3074 #define GEN10_F2_SS_DIS_MASK (0xf << GEN10_F2_SS_DIS_SHIFT)
3075
3076 #define GEN10_MIRROR_FUSE3 _MMIO(0x9118)
3077 #define GEN10_L3BANK_PAIR_COUNT 4
3078 #define GEN10_L3BANK_MASK 0x0F
3079
3080 #define GEN8_EU_DISABLE0 _MMIO(0x9134)
3081 #define GEN8_EU_DIS0_S0_MASK 0xffffff
3082 #define GEN8_EU_DIS0_S1_SHIFT 24
3083 #define GEN8_EU_DIS0_S1_MASK (0xff << GEN8_EU_DIS0_S1_SHIFT)
3084
3085 #define GEN8_EU_DISABLE1 _MMIO(0x9138)
3086 #define GEN8_EU_DIS1_S1_MASK 0xffff
3087 #define GEN8_EU_DIS1_S2_SHIFT 16
3088 #define GEN8_EU_DIS1_S2_MASK (0xffff << GEN8_EU_DIS1_S2_SHIFT)
3089
3090 #define GEN8_EU_DISABLE2 _MMIO(0x913c)
3091 #define GEN8_EU_DIS2_S2_MASK 0xff
3092
3093 #define GEN9_EU_DISABLE(slice) _MMIO(0x9134 + (slice) * 0x4)
3094
3095 #define GEN10_EU_DISABLE3 _MMIO(0x9140)
3096 #define GEN10_EU_DIS_SS_MASK 0xff
3097
3098 #define GEN11_GT_VEBOX_VDBOX_DISABLE _MMIO(0x9140)
3099 #define GEN11_GT_VDBOX_DISABLE_MASK 0xff
3100 #define GEN11_GT_VEBOX_DISABLE_SHIFT 16
3101 #define GEN11_GT_VEBOX_DISABLE_MASK (0x0f << GEN11_GT_VEBOX_DISABLE_SHIFT)
3102
3103 #define GEN11_EU_DISABLE _MMIO(0x9134)
3104 #define GEN11_EU_DIS_MASK 0xFF
3105
3106 #define GEN11_GT_SLICE_ENABLE _MMIO(0x9138)
3107 #define GEN11_GT_S_ENA_MASK 0xFF
3108
3109 #define GEN11_GT_SUBSLICE_DISABLE _MMIO(0x913C)
3110
3111 #define GEN12_GT_DSS_ENABLE _MMIO(0x913C)
3112
3113 #define GEN6_BSD_SLEEP_PSMI_CONTROL _MMIO(0x12050)
3114 #define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
3115 #define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
3116 #define GEN6_BSD_SLEEP_INDICATOR (1 << 3)
3117 #define GEN6_BSD_GO_INDICATOR (1 << 4)
3118
3119 /* On modern GEN architectures interrupt control consists of two sets
3120 * of registers. The first set pertains to the ring generating the
3121 * interrupt. The second control is for the functional block generating the
3122 * interrupt. These are PM, GT, DE, etc.
3123 *
3124 * Luckily *knocks on wood* all the ring interrupt bits match up with the
3125 * GT interrupt bits, so we don't need to duplicate the defines.
3126 *
3127 * These defines should cover us well from SNB->HSW with minor exceptions
3128 * it can also work on ILK.
3129 */
3130 #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26)
3131 #define GT_BLT_CS_ERROR_INTERRUPT (1 << 25)
3132 #define GT_BLT_USER_INTERRUPT (1 << 22)
3133 #define GT_BSD_CS_ERROR_INTERRUPT (1 << 15)
3134 #define GT_BSD_USER_INTERRUPT (1 << 12)
3135 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */
3136 #define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11) /* bdw+ */
3137 #define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8)
3138 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */
3139 #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4)
3140 #define GT_CS_MASTER_ERROR_INTERRUPT REG_BIT(3)
3141 #define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2)
3142 #define GT_RENDER_DEBUG_INTERRUPT (1 << 1)
3143 #define GT_RENDER_USER_INTERRUPT (1 << 0)
3144
3145 #define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */
3146 #define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */
3147
3148 #define GT_PARITY_ERROR(dev_priv) \
3149 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
3150 (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
3151
3152 /* These are all the "old" interrupts */
3153 #define ILK_BSD_USER_INTERRUPT (1 << 5)
3154
3155 #define I915_PM_INTERRUPT (1 << 31)
3156 #define I915_ISP_INTERRUPT (1 << 22)
3157 #define I915_LPE_PIPE_B_INTERRUPT (1 << 21)
3158 #define I915_LPE_PIPE_A_INTERRUPT (1 << 20)
3159 #define I915_MIPIC_INTERRUPT (1 << 19)
3160 #define I915_MIPIA_INTERRUPT (1 << 18)
3161 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 18)
3162 #define I915_DISPLAY_PORT_INTERRUPT (1 << 17)
3163 #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1 << 16)
3164 #define I915_MASTER_ERROR_INTERRUPT (1 << 15)
3165 #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1 << 14)
3166 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1 << 14) /* p-state */
3167 #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1 << 13)
3168 #define I915_HWB_OOM_INTERRUPT (1 << 13)
3169 #define I915_LPE_PIPE_C_INTERRUPT (1 << 12)
3170 #define I915_SYNC_STATUS_INTERRUPT (1 << 12)
3171 #define I915_MISC_INTERRUPT (1 << 11)
3172 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1 << 11)
3173 #define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1 << 10)
3174 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1 << 10)
3175 #define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1 << 9)
3176 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1 << 9)
3177 #define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1 << 8)
3178 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1 << 8)
3179 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1 << 7)
3180 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1 << 6)
3181 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1 << 5)
3182 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1 << 4)
3183 #define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1 << 3)
3184 #define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1 << 2)
3185 #define I915_DEBUG_INTERRUPT (1 << 2)
3186 #define I915_WINVALID_INTERRUPT (1 << 1)
3187 #define I915_USER_INTERRUPT (1 << 1)
3188 #define I915_ASLE_INTERRUPT (1 << 0)
3189 #define I915_BSD_USER_INTERRUPT (1 << 25)
3190
3191 #define I915_HDMI_LPE_AUDIO_BASE (VLV_DISPLAY_BASE + 0x65000)
3192 #define I915_HDMI_LPE_AUDIO_SIZE 0x1000
3193
3194 /* DisplayPort Audio w/ LPE */
3195 #define VLV_AUD_CHICKEN_BIT_REG _MMIO(VLV_DISPLAY_BASE + 0x62F38)
3196 #define VLV_CHICKEN_BIT_DBG_ENABLE (1 << 0)
3197
3198 #define _VLV_AUD_PORT_EN_B_DBG (VLV_DISPLAY_BASE + 0x62F20)
3199 #define _VLV_AUD_PORT_EN_C_DBG (VLV_DISPLAY_BASE + 0x62F30)
3200 #define _VLV_AUD_PORT_EN_D_DBG (VLV_DISPLAY_BASE + 0x62F34)
3201 #define VLV_AUD_PORT_EN_DBG(port) _MMIO_PORT3((port) - PORT_B, \
3202 _VLV_AUD_PORT_EN_B_DBG, \
3203 _VLV_AUD_PORT_EN_C_DBG, \
3204 _VLV_AUD_PORT_EN_D_DBG)
3205 #define VLV_AMP_MUTE (1 << 1)
3206
3207 #define GEN6_BSD_RNCID _MMIO(0x12198)
3208
3209 #define GEN7_FF_THREAD_MODE _MMIO(0x20a0)
3210 #define GEN7_FF_SCHED_MASK 0x0077070
3211 #define GEN8_FF_DS_REF_CNT_FFME (1 << 19)
3212 #define GEN12_FF_TESSELATION_DOP_GATE_DISABLE BIT(19)
3213 #define GEN7_FF_TS_SCHED_HS1 (0x5 << 16)
3214 #define GEN7_FF_TS_SCHED_HS0 (0x3 << 16)
3215 #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1 << 16)
3216 #define GEN7_FF_TS_SCHED_HW (0x0 << 16) /* Default */
3217 #define GEN7_FF_VS_REF_CNT_FFME (1 << 15)
3218 #define GEN7_FF_VS_SCHED_HS1 (0x5 << 12)
3219 #define GEN7_FF_VS_SCHED_HS0 (0x3 << 12)
3220 #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1 << 12) /* Default */
3221 #define GEN7_FF_VS_SCHED_HW (0x0 << 12)
3222 #define GEN7_FF_DS_SCHED_HS1 (0x5 << 4)
3223 #define GEN7_FF_DS_SCHED_HS0 (0x3 << 4)
3224 #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1 << 4) /* Default */
3225 #define GEN7_FF_DS_SCHED_HW (0x0 << 4)
3226
3227 /*
3228 * Framebuffer compression (915+ only)
3229 */
3230
3231 #define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */
3232 #define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */
3233 #define FBC_CONTROL _MMIO(0x3208)
3234 #define FBC_CTL_EN REG_BIT(31)
3235 #define FBC_CTL_PERIODIC REG_BIT(30)
3236 #define FBC_CTL_INTERVAL_MASK REG_GENMASK(29, 16)
3237 #define FBC_CTL_INTERVAL(x) REG_FIELD_PREP(FBC_CTL_INTERVAL_MASK, (x))
3238 #define FBC_CTL_STOP_ON_MOD REG_BIT(15)
3239 #define FBC_CTL_UNCOMPRESSIBLE REG_BIT(14) /* i915+ */
3240 #define FBC_CTL_C3_IDLE REG_BIT(13) /* i945gm */
3241 #define FBC_CTL_STRIDE_MASK REG_GENMASK(12, 5)
3242 #define FBC_CTL_STRIDE(x) REG_FIELD_PREP(FBC_CTL_STRIDE_MASK, (x))
3243 #define FBC_CTL_FENCENO_MASK REG_GENMASK(3, 0)
3244 #define FBC_CTL_FENCENO(x) REG_FIELD_PREP(FBC_CTL_FENCENO_MASK, (x))
3245 #define FBC_COMMAND _MMIO(0x320c)
3246 #define FBC_CMD_COMPRESS (1 << 0)
3247 #define FBC_STATUS _MMIO(0x3210)
3248 #define FBC_STAT_COMPRESSING (1 << 31)
3249 #define FBC_STAT_COMPRESSED (1 << 30)
3250 #define FBC_STAT_MODIFIED (1 << 29)
3251 #define FBC_STAT_CURRENT_LINE_SHIFT (0)
3252 #define FBC_CONTROL2 _MMIO(0x3214)
3253 #define FBC_CTL_FENCE_DBL (0 << 4)
3254 #define FBC_CTL_IDLE_IMM (0 << 2)
3255 #define FBC_CTL_IDLE_FULL (1 << 2)
3256 #define FBC_CTL_IDLE_LINE (2 << 2)
3257 #define FBC_CTL_IDLE_DEBUG (3 << 2)
3258 #define FBC_CTL_CPU_FENCE (1 << 1)
3259 #define FBC_CTL_PLANE(plane) ((plane) << 0)
3260 #define FBC_FENCE_OFF _MMIO(0x3218) /* BSpec typo has 321Bh */
3261 #define FBC_TAG(i) _MMIO(0x3300 + (i) * 4)
3262
3263 #define FBC_LL_SIZE (1536)
3264
3265 #define FBC_LLC_READ_CTRL _MMIO(0x9044)
3266 #define FBC_LLC_FULLY_OPEN (1 << 30)
3267
3268 /* Framebuffer compression for GM45+ */
3269 #define DPFC_CB_BASE _MMIO(0x3200)
3270 #define DPFC_CONTROL _MMIO(0x3208)
3271 #define DPFC_CTL_EN (1 << 31)
3272 #define DPFC_CTL_PLANE(plane) ((plane) << 30)
3273 #define IVB_DPFC_CTL_PLANE(plane) ((plane) << 29)
3274 #define DPFC_CTL_FENCE_EN (1 << 29)
3275 #define IVB_DPFC_CTL_FENCE_EN (1 << 28)
3276 #define DPFC_CTL_PERSISTENT_MODE (1 << 25)
3277 #define DPFC_SR_EN (1 << 10)
3278 #define DPFC_CTL_LIMIT_1X (0 << 6)
3279 #define DPFC_CTL_LIMIT_2X (1 << 6)
3280 #define DPFC_CTL_LIMIT_4X (2 << 6)
3281 #define DPFC_RECOMP_CTL _MMIO(0x320c)
3282 #define DPFC_RECOMP_STALL_EN (1 << 27)
3283 #define DPFC_RECOMP_STALL_WM_SHIFT (16)
3284 #define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
3285 #define DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
3286 #define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
3287 #define DPFC_STATUS _MMIO(0x3210)
3288 #define DPFC_INVAL_SEG_SHIFT (16)
3289 #define DPFC_INVAL_SEG_MASK (0x07ff0000)
3290 #define DPFC_COMP_SEG_SHIFT (0)
3291 #define DPFC_COMP_SEG_MASK (0x000007ff)
3292 #define DPFC_STATUS2 _MMIO(0x3214)
3293 #define DPFC_FENCE_YOFF _MMIO(0x3218)
3294 #define DPFC_CHICKEN _MMIO(0x3224)
3295 #define DPFC_HT_MODIFY (1 << 31)
3296
3297 /* Framebuffer compression for Ironlake */
3298 #define ILK_DPFC_CB_BASE _MMIO(0x43200)
3299 #define ILK_DPFC_CONTROL _MMIO(0x43208)
3300 #define FBC_CTL_FALSE_COLOR (1 << 10)
3301 /* The bit 28-8 is reserved */
3302 #define DPFC_RESERVED (0x1FFFFF00)
3303 #define ILK_DPFC_RECOMP_CTL _MMIO(0x4320c)
3304 #define ILK_DPFC_STATUS _MMIO(0x43210)
3305 #define ILK_DPFC_COMP_SEG_MASK 0x7ff
3306 #define IVB_FBC_STATUS2 _MMIO(0x43214)
3307 #define IVB_FBC_COMP_SEG_MASK 0x7ff
3308 #define BDW_FBC_COMP_SEG_MASK 0xfff
3309 #define ILK_DPFC_FENCE_YOFF _MMIO(0x43218)
3310 #define ILK_DPFC_CHICKEN _MMIO(0x43224)
3311 #define ILK_DPFC_DISABLE_DUMMY0 (1 << 8)
3312 #define ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL (1 << 14)
3313 #define ILK_DPFC_NUKE_ON_ANY_MODIFICATION (1 << 23)
3314 #define ILK_FBC_RT_BASE _MMIO(0x2128)
3315 #define ILK_FBC_RT_VALID (1 << 0)
3316 #define SNB_FBC_FRONT_BUFFER (1 << 1)
3317
3318 #define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000)
3319 #define ILK_FBCQ_DIS (1 << 22)
3320 #define ILK_PABSTRETCH_DIS (1 << 21)
3321
3322
3323 /*
3324 * Framebuffer compression for Sandybridge
3325 *
3326 * The following two registers are of type GTTMMADR
3327 */
3328 #define SNB_DPFC_CTL_SA _MMIO(0x100100)
3329 #define SNB_CPU_FENCE_ENABLE (1 << 29)
3330 #define DPFC_CPU_FENCE_OFFSET _MMIO(0x100104)
3331
3332 /* Framebuffer compression for Ivybridge */
3333 #define IVB_FBC_RT_BASE _MMIO(0x7020)
3334 #define IVB_FBC_RT_BASE_UPPER _MMIO(0x7024)
3335
3336 #define IPS_CTL _MMIO(0x43408)
3337 #define IPS_ENABLE (1 << 31)
3338
3339 #define MSG_FBC_REND_STATE _MMIO(0x50380)
3340 #define FBC_REND_NUKE (1 << 2)
3341 #define FBC_REND_CACHE_CLEAN (1 << 1)
3342
3343 /*
3344 * GPIO regs
3345 */
3346 #define GPIO(gpio) _MMIO(dev_priv->gpio_mmio_base + 0x5010 + \
3347 4 * (gpio))
3348
3349 # define GPIO_CLOCK_DIR_MASK (1 << 0)
3350 # define GPIO_CLOCK_DIR_IN (0 << 1)
3351 # define GPIO_CLOCK_DIR_OUT (1 << 1)
3352 # define GPIO_CLOCK_VAL_MASK (1 << 2)
3353 # define GPIO_CLOCK_VAL_OUT (1 << 3)
3354 # define GPIO_CLOCK_VAL_IN (1 << 4)
3355 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
3356 # define GPIO_DATA_DIR_MASK (1 << 8)
3357 # define GPIO_DATA_DIR_IN (0 << 9)
3358 # define GPIO_DATA_DIR_OUT (1 << 9)
3359 # define GPIO_DATA_VAL_MASK (1 << 10)
3360 # define GPIO_DATA_VAL_OUT (1 << 11)
3361 # define GPIO_DATA_VAL_IN (1 << 12)
3362 # define GPIO_DATA_PULLUP_DISABLE (1 << 13)
3363
3364 #define GMBUS0 _MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */
3365 #define GMBUS_AKSV_SELECT (1 << 11)
3366 #define GMBUS_RATE_100KHZ (0 << 8)
3367 #define GMBUS_RATE_50KHZ (1 << 8)
3368 #define GMBUS_RATE_400KHZ (2 << 8) /* reserved on Pineview */
3369 #define GMBUS_RATE_1MHZ (3 << 8) /* reserved on Pineview */
3370 #define GMBUS_HOLD_EXT (1 << 7) /* 300ns hold time, rsvd on Pineview */
3371 #define GMBUS_BYTE_CNT_OVERRIDE (1 << 6)
3372
3373 #define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
3374 #define GMBUS_SW_CLR_INT (1 << 31)
3375 #define GMBUS_SW_RDY (1 << 30)
3376 #define GMBUS_ENT (1 << 29) /* enable timeout */
3377 #define GMBUS_CYCLE_NONE (0 << 25)
3378 #define GMBUS_CYCLE_WAIT (1 << 25)
3379 #define GMBUS_CYCLE_INDEX (2 << 25)
3380 #define GMBUS_CYCLE_STOP (4 << 25)
3381 #define GMBUS_BYTE_COUNT_SHIFT 16
3382 #define GMBUS_BYTE_COUNT_MAX 256U
3383 #define GEN9_GMBUS_BYTE_COUNT_MAX 511U
3384 #define GMBUS_SLAVE_INDEX_SHIFT 8
3385 #define GMBUS_SLAVE_ADDR_SHIFT 1
3386 #define GMBUS_SLAVE_READ (1 << 0)
3387 #define GMBUS_SLAVE_WRITE (0 << 0)
3388 #define GMBUS2 _MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */
3389 #define GMBUS_INUSE (1 << 15)
3390 #define GMBUS_HW_WAIT_PHASE (1 << 14)
3391 #define GMBUS_STALL_TIMEOUT (1 << 13)
3392 #define GMBUS_INT (1 << 12)
3393 #define GMBUS_HW_RDY (1 << 11)
3394 #define GMBUS_SATOER (1 << 10)
3395 #define GMBUS_ACTIVE (1 << 9)
3396 #define GMBUS3 _MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */
3397 #define GMBUS4 _MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */
3398 #define GMBUS_SLAVE_TIMEOUT_EN (1 << 4)
3399 #define GMBUS_NAK_EN (1 << 3)
3400 #define GMBUS_IDLE_EN (1 << 2)
3401 #define GMBUS_HW_WAIT_EN (1 << 1)
3402 #define GMBUS_HW_RDY_EN (1 << 0)
3403 #define GMBUS5 _MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */
3404 #define GMBUS_2BYTE_INDEX_EN (1 << 31)
3405
3406 /*
3407 * Clock control & power management
3408 */
3409 #define _DPLL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x6014)
3410 #define _DPLL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x6018)
3411 #define _CHV_DPLL_C (DISPLAY_MMIO_BASE(dev_priv) + 0x6030)
3412 #define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
3413
3414 #define VGA0 _MMIO(0x6000)
3415 #define VGA1 _MMIO(0x6004)
3416 #define VGA_PD _MMIO(0x6010)
3417 #define VGA0_PD_P2_DIV_4 (1 << 7)
3418 #define VGA0_PD_P1_DIV_2 (1 << 5)
3419 #define VGA0_PD_P1_SHIFT 0
3420 #define VGA0_PD_P1_MASK (0x1f << 0)
3421 #define VGA1_PD_P2_DIV_4 (1 << 15)
3422 #define VGA1_PD_P1_DIV_2 (1 << 13)
3423 #define VGA1_PD_P1_SHIFT 8
3424 #define VGA1_PD_P1_MASK (0x1f << 8)
3425 #define DPLL_VCO_ENABLE (1 << 31)
3426 #define DPLL_SDVO_HIGH_SPEED (1 << 30)
3427 #define DPLL_DVO_2X_MODE (1 << 30)
3428 #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30)
3429 #define DPLL_SYNCLOCK_ENABLE (1 << 29)
3430 #define DPLL_REF_CLK_ENABLE_VLV (1 << 29)
3431 #define DPLL_VGA_MODE_DIS (1 << 28)
3432 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
3433 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */
3434 #define DPLL_MODE_MASK (3 << 26)
3435 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
3436 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
3437 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
3438 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
3439 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
3440 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
3441 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
3442 #define DPLL_LOCK_VLV (1 << 15)
3443 #define DPLL_INTEGRATED_CRI_CLK_VLV (1 << 14)
3444 #define DPLL_INTEGRATED_REF_CLK_VLV (1 << 13)
3445 #define DPLL_SSC_REF_CLK_CHV (1 << 13)
3446 #define DPLL_PORTC_READY_MASK (0xf << 4)
3447 #define DPLL_PORTB_READY_MASK (0xf)
3448
3449 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
3450
3451 /* Additional CHV pll/phy registers */
3452 #define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240)
3453 #define DPLL_PORTD_READY_MASK (0xf)
3454 #define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100)
3455 #define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch) (1 << (2 * (phy) + (ch) + 27))
3456 #define PHY_LDO_DELAY_0NS 0x0
3457 #define PHY_LDO_DELAY_200NS 0x1
3458 #define PHY_LDO_DELAY_600NS 0x2
3459 #define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2 * (phy) + 23))
3460 #define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8 * (phy) + 4 * (ch) + 11))
3461 #define PHY_CH_SU_PSR 0x1
3462 #define PHY_CH_DEEP_PSR 0x7
3463 #define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6 * (phy) + 3 * (ch) + 2))
3464 #define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy))
3465 #define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104)
3466 #define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1 << 31) : (1 << 30))
3467 #define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6 - (6 * (phy) + 3 * (ch))))
3468 #define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8 - (6 * (phy) + 3 * (ch) + (spline))))
3469
3470 /*
3471 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
3472 * this field (only one bit may be set).
3473 */
3474 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
3475 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16
3476 #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
3477 /* i830, required in DVO non-gang */
3478 #define PLL_P2_DIVIDE_BY_4 (1 << 23)
3479 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
3480 #define PLL_REF_INPUT_DREFCLK (0 << 13)
3481 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
3482 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
3483 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
3484 #define PLL_REF_INPUT_MASK (3 << 13)
3485 #define PLL_LOAD_PULSE_PHASE_SHIFT 9
3486 /* Ironlake */
3487 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
3488 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
3489 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x) - 1) << 9)
3490 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0
3491 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff
3492
3493 /*
3494 * Parallel to Serial Load Pulse phase selection.
3495 * Selects the phase for the 10X DPLL clock for the PCIe
3496 * digital display port. The range is 4 to 13; 10 or more
3497 * is just a flip delay. The default is 6
3498 */
3499 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
3500 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
3501 /*
3502 * SDVO multiplier for 945G/GM. Not used on 965.
3503 */
3504 #define SDVO_MULTIPLIER_MASK 0x000000ff
3505 #define SDVO_MULTIPLIER_SHIFT_HIRES 4
3506 #define SDVO_MULTIPLIER_SHIFT_VGA 0
3507
3508 #define _DPLL_A_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x601c)
3509 #define _DPLL_B_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x6020)
3510 #define _CHV_DPLL_C_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x603c)
3511 #define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
3512
3513 /*
3514 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
3515 *
3516 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
3517 */
3518 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
3519 #define DPLL_MD_UDI_DIVIDER_SHIFT 24
3520 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
3521 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
3522 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
3523 /*
3524 * SDVO/UDI pixel multiplier.
3525 *
3526 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
3527 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
3528 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
3529 * dummy bytes in the datastream at an increased clock rate, with both sides of
3530 * the link knowing how many bytes are fill.
3531 *
3532 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
3533 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
3534 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
3535 * through an SDVO command.
3536 *
3537 * This register field has values of multiplication factor minus 1, with
3538 * a maximum multiplier of 5 for SDVO.
3539 */
3540 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
3541 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
3542 /*
3543 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
3544 * This best be set to the default value (3) or the CRT won't work. No,
3545 * I don't entirely understand what this does...
3546 */
3547 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
3548 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
3549
3550 #define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024)
3551
3552 #define _FPA0 0x6040
3553 #define _FPA1 0x6044
3554 #define _FPB0 0x6048
3555 #define _FPB1 0x604c
3556 #define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0)
3557 #define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1)
3558 #define FP_N_DIV_MASK 0x003f0000
3559 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
3560 #define FP_N_DIV_SHIFT 16
3561 #define FP_M1_DIV_MASK 0x00003f00
3562 #define FP_M1_DIV_SHIFT 8
3563 #define FP_M2_DIV_MASK 0x0000003f
3564 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
3565 #define FP_M2_DIV_SHIFT 0
3566 #define DPLL_TEST _MMIO(0x606c)
3567 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
3568 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
3569 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
3570 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
3571 #define DPLLB_TEST_N_BYPASS (1 << 19)
3572 #define DPLLB_TEST_M_BYPASS (1 << 18)
3573 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
3574 #define DPLLA_TEST_N_BYPASS (1 << 3)
3575 #define DPLLA_TEST_M_BYPASS (1 << 2)
3576 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
3577 #define D_STATE _MMIO(0x6104)
3578 #define DSTATE_GFX_RESET_I830 (1 << 6)
3579 #define DSTATE_PLL_D3_OFF (1 << 3)
3580 #define DSTATE_GFX_CLOCK_GATING (1 << 1)
3581 #define DSTATE_DOT_CLOCK_GATING (1 << 0)
3582 #define DSPCLK_GATE_D _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x6200)
3583 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
3584 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
3585 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
3586 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
3587 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
3588 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
3589 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
3590 # define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 24) /* pnv */
3591 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
3592 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
3593 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
3594 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
3595 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
3596 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
3597 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
3598 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
3599 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
3600 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
3601 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
3602 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
3603 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
3604 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
3605 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
3606 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
3607 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
3608 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
3609 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
3610 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
3611 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
3612 /*
3613 * This bit must be set on the 830 to prevent hangs when turning off the
3614 * overlay scaler.
3615 */
3616 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
3617 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
3618 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
3619 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
3620 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
3621
3622 #define RENCLK_GATE_D1 _MMIO(0x6204)
3623 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
3624 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
3625 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
3626 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
3627 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
3628 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
3629 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
3630 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
3631 # define MAG_CLOCK_GATE_DISABLE (1 << 5)
3632 /* This bit must be unset on 855,865 */
3633 # define MECI_CLOCK_GATE_DISABLE (1 << 4)
3634 # define DCMP_CLOCK_GATE_DISABLE (1 << 3)
3635 # define MEC_CLOCK_GATE_DISABLE (1 << 2)
3636 # define MECO_CLOCK_GATE_DISABLE (1 << 1)
3637 /* This bit must be set on 855,865. */
3638 # define SV_CLOCK_GATE_DISABLE (1 << 0)
3639 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
3640 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
3641 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
3642 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
3643 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
3644 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
3645 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
3646 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
3647 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
3648 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
3649 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
3650 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
3651 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
3652 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
3653 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
3654 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
3655 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
3656
3657 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
3658 /* This bit must always be set on 965G/965GM */
3659 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
3660 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
3661 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
3662 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
3663 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
3664 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
3665 /* This bit must always be set on 965G */
3666 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
3667 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
3668 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
3669 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
3670 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
3671 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
3672 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
3673 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
3674 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
3675 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
3676 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
3677 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
3678 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
3679 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
3680 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
3681 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
3682 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
3683 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
3684 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
3685
3686 #define RENCLK_GATE_D2 _MMIO(0x6208)
3687 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
3688 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
3689 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
3690
3691 #define VDECCLK_GATE_D _MMIO(0x620C) /* g4x only */
3692 #define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4)
3693
3694 #define RAMCLK_GATE_D _MMIO(0x6210) /* CRL only */
3695 #define DEUC _MMIO(0x6214) /* CRL only */
3696
3697 #define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500)
3698 #define FW_CSPWRDWNEN (1 << 15)
3699
3700 #define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504)
3701
3702 #define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508)
3703 #define CDCLK_FREQ_SHIFT 4
3704 #define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT)
3705 #define CZCLK_FREQ_MASK 0xf
3706
3707 #define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C)
3708 #define PFI_CREDIT_63 (9 << 28) /* chv only */
3709 #define PFI_CREDIT_31 (8 << 28) /* chv only */
3710 #define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */
3711 #define PFI_CREDIT_RESEND (1 << 27)
3712 #define VGA_FAST_MODE_DISABLE (1 << 14)
3713
3714 #define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510)
3715
3716 /*
3717 * Palette regs
3718 */
3719 #define _PALETTE_A 0xa000
3720 #define _PALETTE_B 0xa800
3721 #define _CHV_PALETTE_C 0xc000
3722 #define PALETTE_RED_MASK REG_GENMASK(23, 16)
3723 #define PALETTE_GREEN_MASK REG_GENMASK(15, 8)
3724 #define PALETTE_BLUE_MASK REG_GENMASK(7, 0)
3725 #define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
3726 _PICK((pipe), _PALETTE_A, \
3727 _PALETTE_B, _CHV_PALETTE_C) + \
3728 (i) * 4)
3729
3730 /* MCH MMIO space */
3731
3732 /*
3733 * MCHBAR mirror.
3734 *
3735 * This mirrors the MCHBAR MMIO space whose location is determined by
3736 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
3737 * every way. It is not accessible from the CP register read instructions.
3738 *
3739 * Starting from Haswell, you can't write registers using the MCHBAR mirror,
3740 * just read.
3741 */
3742 #define MCHBAR_MIRROR_BASE 0x10000
3743
3744 #define MCHBAR_MIRROR_BASE_SNB 0x140000
3745
3746 #define CTG_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x34)
3747 #define ELK_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x48)
3748 #define G4X_STOLEN_RESERVED_ADDR1_MASK (0xFFFF << 16)
3749 #define G4X_STOLEN_RESERVED_ADDR2_MASK (0xFFF << 4)
3750 #define G4X_STOLEN_RESERVED_ENABLE (1 << 0)
3751
3752 /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */
3753 #define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04)
3754
3755 /* 915-945 and GM965 MCH register controlling DRAM channel access */
3756 #define DCC _MMIO(MCHBAR_MIRROR_BASE + 0x200)
3757 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
3758 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
3759 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
3760 #define DCC_ADDRESSING_MODE_MASK (3 << 0)
3761 #define DCC_CHANNEL_XOR_DISABLE (1 << 10)
3762 #define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
3763 #define DCC2 _MMIO(MCHBAR_MIRROR_BASE + 0x204)
3764 #define DCC2_MODIFIED_ENHANCED_DISABLE (1 << 20)
3765
3766 /* Pineview MCH register contains DDR3 setting */
3767 #define CSHRDDR3CTL _MMIO(MCHBAR_MIRROR_BASE + 0x1a8)
3768 #define CSHRDDR3CTL_DDR3 (1 << 2)
3769
3770 /* 965 MCH register controlling DRAM channel configuration */
3771 #define C0DRB3 _MMIO(MCHBAR_MIRROR_BASE + 0x206)
3772 #define C1DRB3 _MMIO(MCHBAR_MIRROR_BASE + 0x606)
3773
3774 /* snb MCH registers for reading the DRAM channel configuration */
3775 #define MAD_DIMM_C0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004)
3776 #define MAD_DIMM_C1 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008)
3777 #define MAD_DIMM_C2 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
3778 #define MAD_DIMM_ECC_MASK (0x3 << 24)
3779 #define MAD_DIMM_ECC_OFF (0x0 << 24)
3780 #define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24)
3781 #define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24)
3782 #define MAD_DIMM_ECC_ON (0x3 << 24)
3783 #define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22)
3784 #define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21)
3785 #define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */
3786 #define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */
3787 #define MAD_DIMM_B_DUAL_RANK (0x1 << 18)
3788 #define MAD_DIMM_A_DUAL_RANK (0x1 << 17)
3789 #define MAD_DIMM_A_SELECT (0x1 << 16)
3790 /* DIMM sizes are in multiples of 256mb. */
3791 #define MAD_DIMM_B_SIZE_SHIFT 8
3792 #define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT)
3793 #define MAD_DIMM_A_SIZE_SHIFT 0
3794 #define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT)
3795
3796 /* snb MCH registers for priority tuning */
3797 #define MCH_SSKPD _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10)
3798 #define MCH_SSKPD_WM0_MASK 0x3f
3799 #define MCH_SSKPD_WM0_VAL 0xc
3800
3801 /* Clocking configuration register */
3802 #define CLKCFG _MMIO(MCHBAR_MIRROR_BASE + 0xc00)
3803 #define CLKCFG_FSB_400 (0 << 0) /* hrawclk 100 */
3804 #define CLKCFG_FSB_400_ALT (5 << 0) /* hrawclk 100 */
3805 #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */
3806 #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */
3807 #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */
3808 #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */
3809 #define CLKCFG_FSB_1067_ALT (0 << 0) /* hrawclk 266 */
3810 #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */
3811 #define CLKCFG_FSB_1333_ALT (4 << 0) /* hrawclk 333 */
3812 #define CLKCFG_FSB_1600_ALT (6 << 0) /* hrawclk 400 */
3813 #define CLKCFG_FSB_MASK (7 << 0)
3814 #define CLKCFG_MEM_533 (1 << 4)
3815 #define CLKCFG_MEM_667 (2 << 4)
3816 #define CLKCFG_MEM_800 (3 << 4)
3817 #define CLKCFG_MEM_MASK (7 << 4)
3818
3819 #define HPLLVCO _MMIO(MCHBAR_MIRROR_BASE + 0xc38)
3820 #define HPLLVCO_MOBILE _MMIO(MCHBAR_MIRROR_BASE + 0xc0f)
3821
3822 #define TSC1 _MMIO(0x11001)
3823 #define TSE (1 << 0)
3824 #define TR1 _MMIO(0x11006)
3825 #define TSFS _MMIO(0x11020)
3826 #define TSFS_SLOPE_MASK 0x0000ff00
3827 #define TSFS_SLOPE_SHIFT 8
3828 #define TSFS_INTR_MASK 0x000000ff
3829
3830 #define CRSTANDVID _MMIO(0x11100)
3831 #define PXVFREQ(fstart) _MMIO(0x11110 + (fstart) * 4) /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
3832 #define PXVFREQ_PX_MASK 0x7f000000
3833 #define PXVFREQ_PX_SHIFT 24
3834 #define VIDFREQ_BASE _MMIO(0x11110)
3835 #define VIDFREQ1 _MMIO(0x11110) /* VIDFREQ1-4 (0x1111c) (Cantiga) */
3836 #define VIDFREQ2 _MMIO(0x11114)
3837 #define VIDFREQ3 _MMIO(0x11118)
3838 #define VIDFREQ4 _MMIO(0x1111c)
3839 #define VIDFREQ_P0_MASK 0x1f000000
3840 #define VIDFREQ_P0_SHIFT 24
3841 #define VIDFREQ_P0_CSCLK_MASK 0x00f00000
3842 #define VIDFREQ_P0_CSCLK_SHIFT 20
3843 #define VIDFREQ_P0_CRCLK_MASK 0x000f0000
3844 #define VIDFREQ_P0_CRCLK_SHIFT 16
3845 #define VIDFREQ_P1_MASK 0x00001f00
3846 #define VIDFREQ_P1_SHIFT 8
3847 #define VIDFREQ_P1_CSCLK_MASK 0x000000f0
3848 #define VIDFREQ_P1_CSCLK_SHIFT 4
3849 #define VIDFREQ_P1_CRCLK_MASK 0x0000000f
3850 #define INTTOEXT_BASE_ILK _MMIO(0x11300)
3851 #define INTTOEXT_BASE _MMIO(0x11120) /* INTTOEXT1-8 (0x1113c) */
3852 #define INTTOEXT_MAP3_SHIFT 24
3853 #define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT)
3854 #define INTTOEXT_MAP2_SHIFT 16
3855 #define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT)
3856 #define INTTOEXT_MAP1_SHIFT 8
3857 #define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT)
3858 #define INTTOEXT_MAP0_SHIFT 0
3859 #define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT)
3860 #define MEMSWCTL _MMIO(0x11170) /* Ironlake only */
3861 #define MEMCTL_CMD_MASK 0xe000
3862 #define MEMCTL_CMD_SHIFT 13
3863 #define MEMCTL_CMD_RCLK_OFF 0
3864 #define MEMCTL_CMD_RCLK_ON 1
3865 #define MEMCTL_CMD_CHFREQ 2
3866 #define MEMCTL_CMD_CHVID 3
3867 #define MEMCTL_CMD_VMMOFF 4
3868 #define MEMCTL_CMD_VMMON 5
3869 #define MEMCTL_CMD_STS (1 << 12) /* write 1 triggers command, clears
3870 when command complete */
3871 #define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */
3872 #define MEMCTL_FREQ_SHIFT 8
3873 #define MEMCTL_SFCAVM (1 << 7)
3874 #define MEMCTL_TGT_VID_MASK 0x007f
3875 #define MEMIHYST _MMIO(0x1117c)
3876 #define MEMINTREN _MMIO(0x11180) /* 16 bits */
3877 #define MEMINT_RSEXIT_EN (1 << 8)
3878 #define MEMINT_CX_SUPR_EN (1 << 7)
3879 #define MEMINT_CONT_BUSY_EN (1 << 6)
3880 #define MEMINT_AVG_BUSY_EN (1 << 5)
3881 #define MEMINT_EVAL_CHG_EN (1 << 4)
3882 #define MEMINT_MON_IDLE_EN (1 << 3)
3883 #define MEMINT_UP_EVAL_EN (1 << 2)
3884 #define MEMINT_DOWN_EVAL_EN (1 << 1)
3885 #define MEMINT_SW_CMD_EN (1 << 0)
3886 #define MEMINTRSTR _MMIO(0x11182) /* 16 bits */
3887 #define MEM_RSEXIT_MASK 0xc000
3888 #define MEM_RSEXIT_SHIFT 14
3889 #define MEM_CONT_BUSY_MASK 0x3000
3890 #define MEM_CONT_BUSY_SHIFT 12
3891 #define MEM_AVG_BUSY_MASK 0x0c00
3892 #define MEM_AVG_BUSY_SHIFT 10
3893 #define MEM_EVAL_CHG_MASK 0x0300
3894 #define MEM_EVAL_BUSY_SHIFT 8
3895 #define MEM_MON_IDLE_MASK 0x00c0
3896 #define MEM_MON_IDLE_SHIFT 6
3897 #define MEM_UP_EVAL_MASK 0x0030
3898 #define MEM_UP_EVAL_SHIFT 4
3899 #define MEM_DOWN_EVAL_MASK 0x000c
3900 #define MEM_DOWN_EVAL_SHIFT 2
3901 #define MEM_SW_CMD_MASK 0x0003
3902 #define MEM_INT_STEER_GFX 0
3903 #define MEM_INT_STEER_CMR 1
3904 #define MEM_INT_STEER_SMI 2
3905 #define MEM_INT_STEER_SCI 3
3906 #define MEMINTRSTS _MMIO(0x11184)
3907 #define MEMINT_RSEXIT (1 << 7)
3908 #define MEMINT_CONT_BUSY (1 << 6)
3909 #define MEMINT_AVG_BUSY (1 << 5)
3910 #define MEMINT_EVAL_CHG (1 << 4)
3911 #define MEMINT_MON_IDLE (1 << 3)
3912 #define MEMINT_UP_EVAL (1 << 2)
3913 #define MEMINT_DOWN_EVAL (1 << 1)
3914 #define MEMINT_SW_CMD (1 << 0)
3915 #define MEMMODECTL _MMIO(0x11190)
3916 #define MEMMODE_BOOST_EN (1 << 31)
3917 #define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
3918 #define MEMMODE_BOOST_FREQ_SHIFT 24
3919 #define MEMMODE_IDLE_MODE_MASK 0x00030000
3920 #define MEMMODE_IDLE_MODE_SHIFT 16
3921 #define MEMMODE_IDLE_MODE_EVAL 0
3922 #define MEMMODE_IDLE_MODE_CONT 1
3923 #define MEMMODE_HWIDLE_EN (1 << 15)
3924 #define MEMMODE_SWMODE_EN (1 << 14)
3925 #define MEMMODE_RCLK_GATE (1 << 13)
3926 #define MEMMODE_HW_UPDATE (1 << 12)
3927 #define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */
3928 #define MEMMODE_FSTART_SHIFT 8
3929 #define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */
3930 #define MEMMODE_FMAX_SHIFT 4
3931 #define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */
3932 #define RCBMAXAVG _MMIO(0x1119c)
3933 #define MEMSWCTL2 _MMIO(0x1119e) /* Cantiga only */
3934 #define SWMEMCMD_RENDER_OFF (0 << 13)
3935 #define SWMEMCMD_RENDER_ON (1 << 13)
3936 #define SWMEMCMD_SWFREQ (2 << 13)
3937 #define SWMEMCMD_TARVID (3 << 13)
3938 #define SWMEMCMD_VRM_OFF (4 << 13)
3939 #define SWMEMCMD_VRM_ON (5 << 13)
3940 #define CMDSTS (1 << 12)
3941 #define SFCAVM (1 << 11)
3942 #define SWFREQ_MASK 0x0380 /* P0-7 */
3943 #define SWFREQ_SHIFT 7
3944 #define TARVID_MASK 0x001f
3945 #define MEMSTAT_CTG _MMIO(0x111a0)
3946 #define RCBMINAVG _MMIO(0x111a0)
3947 #define RCUPEI _MMIO(0x111b0)
3948 #define RCDNEI _MMIO(0x111b4)
3949 #define RSTDBYCTL _MMIO(0x111b8)
3950 #define RS1EN (1 << 31)
3951 #define RS2EN (1 << 30)
3952 #define RS3EN (1 << 29)
3953 #define D3RS3EN (1 << 28) /* Display D3 imlies RS3 */
3954 #define SWPROMORSX (1 << 27) /* RSx promotion timers ignored */
3955 #define RCWAKERW (1 << 26) /* Resetwarn from PCH causes wakeup */
3956 #define DPRSLPVREN (1 << 25) /* Fast voltage ramp enable */
3957 #define GFXTGHYST (1 << 24) /* Hysteresis to allow trunk gating */
3958 #define RCX_SW_EXIT (1 << 23) /* Leave RSx and prevent re-entry */
3959 #define RSX_STATUS_MASK (7 << 20)
3960 #define RSX_STATUS_ON (0 << 20)
3961 #define RSX_STATUS_RC1 (1 << 20)
3962 #define RSX_STATUS_RC1E (2 << 20)
3963 #define RSX_STATUS_RS1 (3 << 20)
3964 #define RSX_STATUS_RS2 (4 << 20) /* aka rc6 */
3965 #define RSX_STATUS_RSVD (5 << 20) /* deep rc6 unsupported on ilk */
3966 #define RSX_STATUS_RS3 (6 << 20) /* rs3 unsupported on ilk */
3967 #define RSX_STATUS_RSVD2 (7 << 20)
3968 #define UWRCRSXE (1 << 19) /* wake counter limit prevents rsx */
3969 #define RSCRP (1 << 18) /* rs requests control on rs1/2 reqs */
3970 #define JRSC (1 << 17) /* rsx coupled to cpu c-state */
3971 #define RS2INC0 (1 << 16) /* allow rs2 in cpu c0 */
3972 #define RS1CONTSAV_MASK (3 << 14)
3973 #define RS1CONTSAV_NO_RS1 (0 << 14) /* rs1 doesn't save/restore context */
3974 #define RS1CONTSAV_RSVD (1 << 14)
3975 #define RS1CONTSAV_SAVE_RS1 (2 << 14) /* rs1 saves context */
3976 #define RS1CONTSAV_FULL_RS1 (3 << 14) /* rs1 saves and restores context */
3977 #define NORMSLEXLAT_MASK (3 << 12)
3978 #define SLOW_RS123 (0 << 12)
3979 #define SLOW_RS23 (1 << 12)
3980 #define SLOW_RS3 (2 << 12)
3981 #define NORMAL_RS123 (3 << 12)
3982 #define RCMODE_TIMEOUT (1 << 11) /* 0 is eval interval method */
3983 #define IMPROMOEN (1 << 10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
3984 #define RCENTSYNC (1 << 9) /* rs coupled to cpu c-state (3/6/7) */
3985 #define STATELOCK (1 << 7) /* locked to rs_cstate if 0 */
3986 #define RS_CSTATE_MASK (3 << 4)
3987 #define RS_CSTATE_C367_RS1 (0 << 4)
3988 #define RS_CSTATE_C36_RS1_C7_RS2 (1 << 4)
3989 #define RS_CSTATE_RSVD (2 << 4)
3990 #define RS_CSTATE_C367_RS2 (3 << 4)
3991 #define REDSAVES (1 << 3) /* no context save if was idle during rs0 */
3992 #define REDRESTORES (1 << 2) /* no restore if was idle during rs0 */
3993 #define VIDCTL _MMIO(0x111c0)
3994 #define VIDSTS _MMIO(0x111c8)
3995 #define VIDSTART _MMIO(0x111cc) /* 8 bits */
3996 #define MEMSTAT_ILK _MMIO(0x111f8)
3997 #define MEMSTAT_VID_MASK 0x7f00
3998 #define MEMSTAT_VID_SHIFT 8
3999 #define MEMSTAT_PSTATE_MASK 0x00f8
4000 #define MEMSTAT_PSTATE_SHIFT 3
4001 #define MEMSTAT_MON_ACTV (1 << 2)
4002 #define MEMSTAT_SRC_CTL_MASK 0x0003
4003 #define MEMSTAT_SRC_CTL_CORE 0
4004 #define MEMSTAT_SRC_CTL_TRB 1
4005 #define MEMSTAT_SRC_CTL_THM 2
4006 #define MEMSTAT_SRC_CTL_STDBY 3
4007 #define RCPREVBSYTUPAVG _MMIO(0x113b8)
4008 #define RCPREVBSYTDNAVG _MMIO(0x113bc)
4009 #define PMMISC _MMIO(0x11214)
4010 #define MCPPCE_EN (1 << 0) /* enable PM_MSG from PCH->MPC */
4011 #define SDEW _MMIO(0x1124c)
4012 #define CSIEW0 _MMIO(0x11250)
4013 #define CSIEW1 _MMIO(0x11254)
4014 #define CSIEW2 _MMIO(0x11258)
4015 #define PEW(i) _MMIO(0x1125c + (i) * 4) /* 5 registers */
4016 #define DEW(i) _MMIO(0x11270 + (i) * 4) /* 3 registers */
4017 #define MCHAFE _MMIO(0x112c0)
4018 #define CSIEC _MMIO(0x112e0)
4019 #define DMIEC _MMIO(0x112e4)
4020 #define DDREC _MMIO(0x112e8)
4021 #define PEG0EC _MMIO(0x112ec)
4022 #define PEG1EC _MMIO(0x112f0)
4023 #define GFXEC _MMIO(0x112f4)
4024 #define RPPREVBSYTUPAVG _MMIO(0x113b8)
4025 #define RPPREVBSYTDNAVG _MMIO(0x113bc)
4026 #define ECR _MMIO(0x11600)
4027 #define ECR_GPFE (1 << 31)
4028 #define ECR_IMONE (1 << 30)
4029 #define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */
4030 #define OGW0 _MMIO(0x11608)
4031 #define OGW1 _MMIO(0x1160c)
4032 #define EG0 _MMIO(0x11610)
4033 #define EG1 _MMIO(0x11614)
4034 #define EG2 _MMIO(0x11618)
4035 #define EG3 _MMIO(0x1161c)
4036 #define EG4 _MMIO(0x11620)
4037 #define EG5 _MMIO(0x11624)
4038 #define EG6 _MMIO(0x11628)
4039 #define EG7 _MMIO(0x1162c)
4040 #define PXW(i) _MMIO(0x11664 + (i) * 4) /* 4 registers */
4041 #define PXWL(i) _MMIO(0x11680 + (i) * 8) /* 8 registers */
4042 #define LCFUSE02 _MMIO(0x116c0)
4043 #define LCFUSE_HIV_MASK 0x000000ff
4044 #define CSIPLL0 _MMIO(0x12c10)
4045 #define DDRMPLL1 _MMIO(0X12c20)
4046 #define PEG_BAND_GAP_DATA _MMIO(0x14d68)
4047
4048 #define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c)
4049 #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
4050
4051 #define GEN6_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948)
4052 #define BXT_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070)
4053 #define GEN6_RP_STATE_LIMITS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994)
4054 #define GEN6_RP_STATE_CAP _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998)
4055 #define BXT_RP_STATE_CAP _MMIO(0x138170)
4056 #define GEN9_RP_STATE_LIMITS _MMIO(0x138148)
4057
4058 /*
4059 * Logical Context regs
4060 */
4061 #define CCID(base) _MMIO((base) + 0x180)
4062 #define CCID_EN BIT(0)
4063 #define CCID_EXTENDED_STATE_RESTORE BIT(2)
4064 #define CCID_EXTENDED_STATE_SAVE BIT(3)
4065 /*
4066 * Notes on SNB/IVB/VLV context size:
4067 * - Power context is saved elsewhere (LLC or stolen)
4068 * - Ring/execlist context is saved on SNB, not on IVB
4069 * - Extended context size already includes render context size
4070 * - We always need to follow the extended context size.
4071 * SNB BSpec has comments indicating that we should use the
4072 * render context size instead if execlists are disabled, but
4073 * based on empirical testing that's just nonsense.
4074 * - Pipelined/VF state is saved on SNB/IVB respectively
4075 * - GT1 size just indicates how much of render context
4076 * doesn't need saving on GT1
4077 */
4078 #define CXT_SIZE _MMIO(0x21a0)
4079 #define GEN6_CXT_POWER_SIZE(cxt_reg) (((cxt_reg) >> 24) & 0x3f)
4080 #define GEN6_CXT_RING_SIZE(cxt_reg) (((cxt_reg) >> 18) & 0x3f)
4081 #define GEN6_CXT_RENDER_SIZE(cxt_reg) (((cxt_reg) >> 12) & 0x3f)
4082 #define GEN6_CXT_EXTENDED_SIZE(cxt_reg) (((cxt_reg) >> 6) & 0x3f)
4083 #define GEN6_CXT_PIPELINE_SIZE(cxt_reg) (((cxt_reg) >> 0) & 0x3f)
4084 #define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \
4085 GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
4086 GEN6_CXT_PIPELINE_SIZE(cxt_reg))
4087 #define GEN7_CXT_SIZE _MMIO(0x21a8)
4088 #define GEN7_CXT_POWER_SIZE(ctx_reg) (((ctx_reg) >> 25) & 0x7f)
4089 #define GEN7_CXT_RING_SIZE(ctx_reg) (((ctx_reg) >> 22) & 0x7)
4090 #define GEN7_CXT_RENDER_SIZE(ctx_reg) (((ctx_reg) >> 16) & 0x3f)
4091 #define GEN7_CXT_EXTENDED_SIZE(ctx_reg) (((ctx_reg) >> 9) & 0x7f)
4092 #define GEN7_CXT_GT1_SIZE(ctx_reg) (((ctx_reg) >> 6) & 0x7)
4093 #define GEN7_CXT_VFSTATE_SIZE(ctx_reg) (((ctx_reg) >> 0) & 0x3f)
4094 #define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
4095 GEN7_CXT_VFSTATE_SIZE(ctx_reg))
4096
4097 enum {
4098 INTEL_ADVANCED_CONTEXT = 0,
4099 INTEL_LEGACY_32B_CONTEXT,
4100 INTEL_ADVANCED_AD_CONTEXT,
4101 INTEL_LEGACY_64B_CONTEXT
4102 };
4103
4104 enum {
4105 FAULT_AND_HANG = 0,
4106 FAULT_AND_HALT, /* Debug only */
4107 FAULT_AND_STREAM,
4108 FAULT_AND_CONTINUE /* Unsupported */
4109 };
4110
4111 #define GEN8_CTX_VALID (1 << 0)
4112 #define GEN8_CTX_FORCE_PD_RESTORE (1 << 1)
4113 #define GEN8_CTX_FORCE_RESTORE (1 << 2)
4114 #define GEN8_CTX_L3LLC_COHERENT (1 << 5)
4115 #define GEN8_CTX_PRIVILEGE (1 << 8)
4116 #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
4117
4118 #define GEN8_CTX_ID_SHIFT 32
4119 #define GEN8_CTX_ID_WIDTH 21
4120 #define GEN11_SW_CTX_ID_SHIFT 37
4121 #define GEN11_SW_CTX_ID_WIDTH 11
4122 #define GEN11_ENGINE_CLASS_SHIFT 61
4123 #define GEN11_ENGINE_CLASS_WIDTH 3
4124 #define GEN11_ENGINE_INSTANCE_SHIFT 48
4125 #define GEN11_ENGINE_INSTANCE_WIDTH 6
4126
4127 #define CHV_CLK_CTL1 _MMIO(0x101100)
4128 #define VLV_CLK_CTL2 _MMIO(0x101104)
4129 #define CLK_CTL2_CZCOUNT_30NS_SHIFT 28
4130
4131 /*
4132 * Overlay regs
4133 */
4134
4135 #define OVADD _MMIO(0x30000)
4136 #define DOVSTA _MMIO(0x30008)
4137 #define OC_BUF (0x3 << 20)
4138 #define OGAMC5 _MMIO(0x30010)
4139 #define OGAMC4 _MMIO(0x30014)
4140 #define OGAMC3 _MMIO(0x30018)
4141 #define OGAMC2 _MMIO(0x3001c)
4142 #define OGAMC1 _MMIO(0x30020)
4143 #define OGAMC0 _MMIO(0x30024)
4144
4145 /*
4146 * GEN9 clock gating regs
4147 */
4148 #define GEN9_CLKGATE_DIS_0 _MMIO(0x46530)
4149 #define DARBF_GATING_DIS (1 << 27)
4150 #define PWM2_GATING_DIS (1 << 14)
4151 #define PWM1_GATING_DIS (1 << 13)
4152
4153 #define GEN9_CLKGATE_DIS_3 _MMIO(0x46538)
4154 #define TGL_VRH_GATING_DIS REG_BIT(31)
4155 #define DPT_GATING_DIS REG_BIT(22)
4156
4157 #define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C)
4158 #define BXT_GMBUS_GATING_DIS (1 << 14)
4159
4160 #define _CLKGATE_DIS_PSL_A 0x46520
4161 #define _CLKGATE_DIS_PSL_B 0x46524
4162 #define _CLKGATE_DIS_PSL_C 0x46528
4163 #define DUPS1_GATING_DIS (1 << 15)
4164 #define DUPS2_GATING_DIS (1 << 19)
4165 #define DUPS3_GATING_DIS (1 << 23)
4166 #define DPF_GATING_DIS (1 << 10)
4167 #define DPF_RAM_GATING_DIS (1 << 9)
4168 #define DPFR_GATING_DIS (1 << 8)
4169
4170 #define CLKGATE_DIS_PSL(pipe) \
4171 _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B)
4172
4173 /*
4174 * GEN10 clock gating regs
4175 */
4176 #define SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
4177 #define SARBUNIT_CLKGATE_DIS (1 << 5)
4178 #define RCCUNIT_CLKGATE_DIS (1 << 7)
4179 #define MSCUNIT_CLKGATE_DIS (1 << 10)
4180 #define L3_CLKGATE_DIS REG_BIT(16)
4181 #define L3_CR2X_CLKGATE_DIS REG_BIT(17)
4182
4183 #define SUBSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9524)
4184 #define GWUNIT_CLKGATE_DIS (1 << 16)
4185
4186 #define SUBSLICE_UNIT_LEVEL_CLKGATE2 _MMIO(0x9528)
4187 #define CPSSUNIT_CLKGATE_DIS REG_BIT(9)
4188
4189 #define UNSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9434)
4190 #define VFUNIT_CLKGATE_DIS REG_BIT(20)
4191 #define HSUNIT_CLKGATE_DIS REG_BIT(8)
4192 #define VSUNIT_CLKGATE_DIS REG_BIT(3)
4193
4194 #define UNSLICE_UNIT_LEVEL_CLKGATE2 _MMIO(0x94e4)
4195 #define VSUNIT_CLKGATE_DIS_TGL REG_BIT(19)
4196 #define PSDUNIT_CLKGATE_DIS REG_BIT(5)
4197
4198 #define INF_UNIT_LEVEL_CLKGATE _MMIO(0x9560)
4199 #define CGPSF_CLKGATE_DIS (1 << 3)
4200
4201 /*
4202 * Display engine regs
4203 */
4204
4205 /* Pipe A CRC regs */
4206 #define _PIPE_CRC_CTL_A 0x60050
4207 #define PIPE_CRC_ENABLE (1 << 31)
4208 /* skl+ source selection */
4209 #define PIPE_CRC_SOURCE_PLANE_1_SKL (0 << 28)
4210 #define PIPE_CRC_SOURCE_PLANE_2_SKL (2 << 28)
4211 #define PIPE_CRC_SOURCE_DMUX_SKL (4 << 28)
4212 #define PIPE_CRC_SOURCE_PLANE_3_SKL (6 << 28)
4213 #define PIPE_CRC_SOURCE_PLANE_4_SKL (7 << 28)
4214 #define PIPE_CRC_SOURCE_PLANE_5_SKL (5 << 28)
4215 #define PIPE_CRC_SOURCE_PLANE_6_SKL (3 << 28)
4216 #define PIPE_CRC_SOURCE_PLANE_7_SKL (1 << 28)
4217 /* ivb+ source selection */
4218 #define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29)
4219 #define PIPE_CRC_SOURCE_SPRITE_IVB (1 << 29)
4220 #define PIPE_CRC_SOURCE_PF_IVB (2 << 29)
4221 /* ilk+ source selection */
4222 #define PIPE_CRC_SOURCE_PRIMARY_ILK (0 << 28)
4223 #define PIPE_CRC_SOURCE_SPRITE_ILK (1 << 28)
4224 #define PIPE_CRC_SOURCE_PIPE_ILK (2 << 28)
4225 /* embedded DP port on the north display block, reserved on ivb */
4226 #define PIPE_CRC_SOURCE_PORT_A_ILK (4 << 28)
4227 #define PIPE_CRC_SOURCE_FDI_ILK (5 << 28) /* reserved on ivb */
4228 /* vlv source selection */
4229 #define PIPE_CRC_SOURCE_PIPE_VLV (0 << 27)
4230 #define PIPE_CRC_SOURCE_HDMIB_VLV (1 << 27)
4231 #define PIPE_CRC_SOURCE_HDMIC_VLV (2 << 27)
4232 /* with DP port the pipe source is invalid */
4233 #define PIPE_CRC_SOURCE_DP_D_VLV (3 << 27)
4234 #define PIPE_CRC_SOURCE_DP_B_VLV (6 << 27)
4235 #define PIPE_CRC_SOURCE_DP_C_VLV (7 << 27)
4236 /* gen3+ source selection */
4237 #define PIPE_CRC_SOURCE_PIPE_I9XX (0 << 28)
4238 #define PIPE_CRC_SOURCE_SDVOB_I9XX (1 << 28)
4239 #define PIPE_CRC_SOURCE_SDVOC_I9XX (2 << 28)
4240 /* with DP/TV port the pipe source is invalid */
4241 #define PIPE_CRC_SOURCE_DP_D_G4X (3 << 28)
4242 #define PIPE_CRC_SOURCE_TV_PRE (4 << 28)
4243 #define PIPE_CRC_SOURCE_TV_POST (5 << 28)
4244 #define PIPE_CRC_SOURCE_DP_B_G4X (6 << 28)
4245 #define PIPE_CRC_SOURCE_DP_C_G4X (7 << 28)
4246 /* gen2 doesn't have source selection bits */
4247 #define PIPE_CRC_INCLUDE_BORDER_I8XX (1 << 30)
4248
4249 #define _PIPE_CRC_RES_1_A_IVB 0x60064
4250 #define _PIPE_CRC_RES_2_A_IVB 0x60068
4251 #define _PIPE_CRC_RES_3_A_IVB 0x6006c
4252 #define _PIPE_CRC_RES_4_A_IVB 0x60070
4253 #define _PIPE_CRC_RES_5_A_IVB 0x60074
4254
4255 #define _PIPE_CRC_RES_RED_A 0x60060
4256 #define _PIPE_CRC_RES_GREEN_A 0x60064
4257 #define _PIPE_CRC_RES_BLUE_A 0x60068
4258 #define _PIPE_CRC_RES_RES1_A_I915 0x6006c
4259 #define _PIPE_CRC_RES_RES2_A_G4X 0x60080
4260
4261 /* Pipe B CRC regs */
4262 #define _PIPE_CRC_RES_1_B_IVB 0x61064
4263 #define _PIPE_CRC_RES_2_B_IVB 0x61068
4264 #define _PIPE_CRC_RES_3_B_IVB 0x6106c
4265 #define _PIPE_CRC_RES_4_B_IVB 0x61070
4266 #define _PIPE_CRC_RES_5_B_IVB 0x61074
4267
4268 #define PIPE_CRC_CTL(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_CTL_A)
4269 #define PIPE_CRC_RES_1_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_1_A_IVB)
4270 #define PIPE_CRC_RES_2_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_2_A_IVB)
4271 #define PIPE_CRC_RES_3_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_3_A_IVB)
4272 #define PIPE_CRC_RES_4_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_4_A_IVB)
4273 #define PIPE_CRC_RES_5_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_5_A_IVB)
4274
4275 #define PIPE_CRC_RES_RED(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RED_A)
4276 #define PIPE_CRC_RES_GREEN(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_GREEN_A)
4277 #define PIPE_CRC_RES_BLUE(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_BLUE_A)
4278 #define PIPE_CRC_RES_RES1_I915(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES1_A_I915)
4279 #define PIPE_CRC_RES_RES2_G4X(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES2_A_G4X)
4280
4281 /* Pipe A timing regs */
4282 #define _HTOTAL_A 0x60000
4283 #define _HBLANK_A 0x60004
4284 #define _HSYNC_A 0x60008
4285 #define _VTOTAL_A 0x6000c
4286 #define _VBLANK_A 0x60010
4287 #define _VSYNC_A 0x60014
4288 #define _EXITLINE_A 0x60018
4289 #define _PIPEASRC 0x6001c
4290 #define _BCLRPAT_A 0x60020
4291 #define _VSYNCSHIFT_A 0x60028
4292 #define _PIPE_MULT_A 0x6002c
4293
4294 /* Pipe B timing regs */
4295 #define _HTOTAL_B 0x61000
4296 #define _HBLANK_B 0x61004
4297 #define _HSYNC_B 0x61008
4298 #define _VTOTAL_B 0x6100c
4299 #define _VBLANK_B 0x61010
4300 #define _VSYNC_B 0x61014
4301 #define _PIPEBSRC 0x6101c
4302 #define _BCLRPAT_B 0x61020
4303 #define _VSYNCSHIFT_B 0x61028
4304 #define _PIPE_MULT_B 0x6102c
4305
4306 /* DSI 0 timing regs */
4307 #define _HTOTAL_DSI0 0x6b000
4308 #define _HSYNC_DSI0 0x6b008
4309 #define _VTOTAL_DSI0 0x6b00c
4310 #define _VSYNC_DSI0 0x6b014
4311 #define _VSYNCSHIFT_DSI0 0x6b028
4312
4313 /* DSI 1 timing regs */
4314 #define _HTOTAL_DSI1 0x6b800
4315 #define _HSYNC_DSI1 0x6b808
4316 #define _VTOTAL_DSI1 0x6b80c
4317 #define _VSYNC_DSI1 0x6b814
4318 #define _VSYNCSHIFT_DSI1 0x6b828
4319
4320 #define TRANSCODER_A_OFFSET 0x60000
4321 #define TRANSCODER_B_OFFSET 0x61000
4322 #define TRANSCODER_C_OFFSET 0x62000
4323 #define CHV_TRANSCODER_C_OFFSET 0x63000
4324 #define TRANSCODER_D_OFFSET 0x63000
4325 #define TRANSCODER_EDP_OFFSET 0x6f000
4326 #define TRANSCODER_DSI0_OFFSET 0x6b000
4327 #define TRANSCODER_DSI1_OFFSET 0x6b800
4328
4329 #define HTOTAL(trans) _MMIO_TRANS2(trans, _HTOTAL_A)
4330 #define HBLANK(trans) _MMIO_TRANS2(trans, _HBLANK_A)
4331 #define HSYNC(trans) _MMIO_TRANS2(trans, _HSYNC_A)
4332 #define VTOTAL(trans) _MMIO_TRANS2(trans, _VTOTAL_A)
4333 #define VBLANK(trans) _MMIO_TRANS2(trans, _VBLANK_A)
4334 #define VSYNC(trans) _MMIO_TRANS2(trans, _VSYNC_A)
4335 #define BCLRPAT(trans) _MMIO_TRANS2(trans, _BCLRPAT_A)
4336 #define VSYNCSHIFT(trans) _MMIO_TRANS2(trans, _VSYNCSHIFT_A)
4337 #define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC)
4338 #define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A)
4339
4340 #define EXITLINE(trans) _MMIO_TRANS2(trans, _EXITLINE_A)
4341 #define EXITLINE_ENABLE REG_BIT(31)
4342 #define EXITLINE_MASK REG_GENMASK(12, 0)
4343 #define EXITLINE_SHIFT 0
4344
4345 /* VRR registers */
4346 #define _TRANS_VRR_CTL_A 0x60420
4347 #define _TRANS_VRR_CTL_B 0x61420
4348 #define _TRANS_VRR_CTL_C 0x62420
4349 #define _TRANS_VRR_CTL_D 0x63420
4350 #define TRANS_VRR_CTL(trans) _MMIO_TRANS2(trans, _TRANS_VRR_CTL_A)
4351 #define VRR_CTL_VRR_ENABLE REG_BIT(31)
4352 #define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30)
4353 #define VRR_CTL_FLIP_LINE_EN REG_BIT(29)
4354 #define VRR_CTL_LINE_COUNT_MASK REG_GENMASK(10, 3)
4355 #define VRR_CTL_SW_FULLLINE_COUNT REG_BIT(0)
4356
4357 #define _TRANS_VRR_VMAX_A 0x60424
4358 #define _TRANS_VRR_VMAX_B 0x61424
4359 #define _TRANS_VRR_VMAX_C 0x62424
4360 #define _TRANS_VRR_VMAX_D 0x63424
4361 #define TRANS_VRR_VMAX(trans) _MMIO_TRANS2(trans, _TRANS_VRR_VMAX_A)
4362 #define VRR_VMAX_MASK REG_GENMASK(19, 0)
4363
4364 #define _TRANS_VRR_VMIN_A 0x60434
4365 #define _TRANS_VRR_VMIN_B 0x61434
4366 #define _TRANS_VRR_VMIN_C 0x62434
4367 #define _TRANS_VRR_VMIN_D 0x63434
4368 #define TRANS_VRR_VMIN(trans) _MMIO_TRANS2(trans, _TRANS_VRR_VMIN_A)
4369 #define VRR_VMIN_MASK REG_GENMASK(15, 0)
4370
4371 #define _TRANS_VRR_VMAXSHIFT_A 0x60428
4372 #define _TRANS_VRR_VMAXSHIFT_B 0x61428
4373 #define _TRANS_VRR_VMAXSHIFT_C 0x62428
4374 #define _TRANS_VRR_VMAXSHIFT_D 0x63428
4375 #define TRANS_VRR_VMAXSHIFT(trans) _MMIO_TRANS2(trans, \
4376 _TRANS_VRR_VMAXSHIFT_A)
4377 #define VRR_VMAXSHIFT_DEC_MASK REG_GENMASK(29, 16)
4378 #define VRR_VMAXSHIFT_DEC REG_BIT(16)
4379 #define VRR_VMAXSHIFT_INC_MASK REG_GENMASK(12, 0)
4380
4381 #define _TRANS_VRR_STATUS_A 0x6042C
4382 #define _TRANS_VRR_STATUS_B 0x6142C
4383 #define _TRANS_VRR_STATUS_C 0x6242C
4384 #define _TRANS_VRR_STATUS_D 0x6342C
4385 #define TRANS_VRR_STATUS(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS_A)
4386 #define VRR_STATUS_VMAX_REACHED REG_BIT(31)
4387 #define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30)
4388 #define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29)
4389 #define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28)
4390 #define VRR_STATUS_VRR_EN_LIVE REG_BIT(27)
4391 #define VRR_STATUS_FLIPS_SERVICED REG_BIT(26)
4392 #define VRR_STATUS_VBLANK_MASK REG_GENMASK(22, 20)
4393 #define STATUS_FSM_IDLE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0)
4394 #define STATUS_FSM_WAIT_TILL_FDB REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1)
4395 #define STATUS_FSM_WAIT_TILL_FS REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2)
4396 #define STATUS_FSM_WAIT_TILL_FLIP REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3)
4397 #define STATUS_FSM_PIPELINE_FILL REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4)
4398 #define STATUS_FSM_ACTIVE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5)
4399 #define STATUS_FSM_LEGACY_VBLANK REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6)
4400
4401 #define _TRANS_VRR_VTOTAL_PREV_A 0x60480
4402 #define _TRANS_VRR_VTOTAL_PREV_B 0x61480
4403 #define _TRANS_VRR_VTOTAL_PREV_C 0x62480
4404 #define _TRANS_VRR_VTOTAL_PREV_D 0x63480
4405 #define TRANS_VRR_VTOTAL_PREV(trans) _MMIO_TRANS2(trans, \
4406 _TRANS_VRR_VTOTAL_PREV_A)
4407 #define VRR_VTOTAL_FLIP_BEFR_BNDR REG_BIT(31)
4408 #define VRR_VTOTAL_FLIP_AFTER_BNDR REG_BIT(30)
4409 #define VRR_VTOTAL_FLIP_AFTER_DBLBUF REG_BIT(29)
4410 #define VRR_VTOTAL_PREV_FRAME_MASK REG_GENMASK(19, 0)
4411
4412 #define _TRANS_VRR_FLIPLINE_A 0x60438
4413 #define _TRANS_VRR_FLIPLINE_B 0x61438
4414 #define _TRANS_VRR_FLIPLINE_C 0x62438
4415 #define _TRANS_VRR_FLIPLINE_D 0x63438
4416 #define TRANS_VRR_FLIPLINE(trans) _MMIO_TRANS2(trans, \
4417 _TRANS_VRR_FLIPLINE_A)
4418 #define VRR_FLIPLINE_MASK REG_GENMASK(19, 0)
4419
4420 #define _TRANS_VRR_STATUS2_A 0x6043C
4421 #define _TRANS_VRR_STATUS2_B 0x6143C
4422 #define _TRANS_VRR_STATUS2_C 0x6243C
4423 #define _TRANS_VRR_STATUS2_D 0x6343C
4424 #define TRANS_VRR_STATUS2(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS2_A)
4425 #define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0)
4426
4427 #define _TRANS_PUSH_A 0x60A70
4428 #define _TRANS_PUSH_B 0x61A70
4429 #define _TRANS_PUSH_C 0x62A70
4430 #define _TRANS_PUSH_D 0x63A70
4431 #define TRANS_PUSH(trans) _MMIO_TRANS2(trans, _TRANS_PUSH_A)
4432 #define TRANS_PUSH_EN REG_BIT(31)
4433 #define TRANS_PUSH_SEND REG_BIT(30)
4434
4435 /*
4436 * HSW+ eDP PSR registers
4437 *
4438 * HSW PSR registers are relative to DDIA(_DDI_BUF_CTL_A + 0x800) with just one
4439 * instance of it
4440 */
4441 #define _HSW_EDP_PSR_BASE 0x64800
4442 #define _SRD_CTL_A 0x60800
4443 #define _SRD_CTL_EDP 0x6f800
4444 #define _PSR_ADJ(tran, reg) (_TRANS2(tran, reg) - dev_priv->hsw_psr_mmio_adjust)
4445 #define EDP_PSR_CTL(tran) _MMIO(_PSR_ADJ(tran, _SRD_CTL_A))
4446 #define EDP_PSR_ENABLE (1 << 31)
4447 #define BDW_PSR_SINGLE_FRAME (1 << 30)
4448 #define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK (1 << 29) /* SW can't modify */
4449 #define EDP_PSR_LINK_STANDBY (1 << 27)
4450 #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3 << 25)
4451 #define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0 << 25)
4452 #define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1 << 25)
4453 #define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2 << 25)
4454 #define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3 << 25)
4455 #define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20
4456 #define EDP_PSR_SKIP_AUX_EXIT (1 << 12)
4457 #define EDP_PSR_TP1_TP2_SEL (0 << 11)
4458 #define EDP_PSR_TP1_TP3_SEL (1 << 11)
4459 #define EDP_PSR_CRC_ENABLE (1 << 10) /* BDW+ */
4460 #define EDP_PSR_TP2_TP3_TIME_500us (0 << 8)
4461 #define EDP_PSR_TP2_TP3_TIME_100us (1 << 8)
4462 #define EDP_PSR_TP2_TP3_TIME_2500us (2 << 8)
4463 #define EDP_PSR_TP2_TP3_TIME_0us (3 << 8)
4464 #define EDP_PSR_TP4_TIME_0US (3 << 6) /* ICL+ */
4465 #define EDP_PSR_TP1_TIME_500us (0 << 4)
4466 #define EDP_PSR_TP1_TIME_100us (1 << 4)
4467 #define EDP_PSR_TP1_TIME_2500us (2 << 4)
4468 #define EDP_PSR_TP1_TIME_0us (3 << 4)
4469 #define EDP_PSR_IDLE_FRAME_SHIFT 0
4470
4471 /*
4472 * Until TGL, IMR/IIR are fixed at 0x648xx. On TGL+ those registers are relative
4473 * to transcoder and bits defined for each one as if using no shift (i.e. as if
4474 * it was for TRANSCODER_EDP)
4475 */
4476 #define EDP_PSR_IMR _MMIO(0x64834)
4477 #define EDP_PSR_IIR _MMIO(0x64838)
4478 #define _PSR_IMR_A 0x60814
4479 #define _PSR_IIR_A 0x60818
4480 #define TRANS_PSR_IMR(tran) _MMIO_TRANS2(tran, _PSR_IMR_A)
4481 #define TRANS_PSR_IIR(tran) _MMIO_TRANS2(tran, _PSR_IIR_A)
4482 #define _EDP_PSR_TRANS_SHIFT(trans) ((trans) == TRANSCODER_EDP ? \
4483 0 : ((trans) - TRANSCODER_A + 1) * 8)
4484 #define EDP_PSR_TRANS_MASK(trans) (0x7 << _EDP_PSR_TRANS_SHIFT(trans))
4485 #define EDP_PSR_ERROR(trans) (0x4 << _EDP_PSR_TRANS_SHIFT(trans))
4486 #define EDP_PSR_POST_EXIT(trans) (0x2 << _EDP_PSR_TRANS_SHIFT(trans))
4487 #define EDP_PSR_PRE_ENTRY(trans) (0x1 << _EDP_PSR_TRANS_SHIFT(trans))
4488
4489 #define _SRD_AUX_CTL_A 0x60810
4490 #define _SRD_AUX_CTL_EDP 0x6f810
4491 #define EDP_PSR_AUX_CTL(tran) _MMIO(_PSR_ADJ(tran, _SRD_AUX_CTL_A))
4492 #define EDP_PSR_AUX_CTL_TIME_OUT_MASK (3 << 26)
4493 #define EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
4494 #define EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK (0xf << 16)
4495 #define EDP_PSR_AUX_CTL_ERROR_INTERRUPT (1 << 11)
4496 #define EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK (0x7ff)
4497
4498 #define _SRD_AUX_DATA_A 0x60814
4499 #define _SRD_AUX_DATA_EDP 0x6f814
4500 #define EDP_PSR_AUX_DATA(tran, i) _MMIO(_PSR_ADJ(tran, _SRD_AUX_DATA_A) + (i) + 4) /* 5 registers */
4501
4502 #define _SRD_STATUS_A 0x60840
4503 #define _SRD_STATUS_EDP 0x6f840
4504 #define EDP_PSR_STATUS(tran) _MMIO(_PSR_ADJ(tran, _SRD_STATUS_A))
4505 #define EDP_PSR_STATUS_STATE_MASK (7 << 29)
4506 #define EDP_PSR_STATUS_STATE_SHIFT 29
4507 #define EDP_PSR_STATUS_STATE_IDLE (0 << 29)
4508 #define EDP_PSR_STATUS_STATE_SRDONACK (1 << 29)
4509 #define EDP_PSR_STATUS_STATE_SRDENT (2 << 29)
4510 #define EDP_PSR_STATUS_STATE_BUFOFF (3 << 29)
4511 #define EDP_PSR_STATUS_STATE_BUFON (4 << 29)
4512 #define EDP_PSR_STATUS_STATE_AUXACK (5 << 29)
4513 #define EDP_PSR_STATUS_STATE_SRDOFFACK (6 << 29)
4514 #define EDP_PSR_STATUS_LINK_MASK (3 << 26)
4515 #define EDP_PSR_STATUS_LINK_FULL_OFF (0 << 26)
4516 #define EDP_PSR_STATUS_LINK_FULL_ON (1 << 26)
4517 #define EDP_PSR_STATUS_LINK_STANDBY (2 << 26)
4518 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20
4519 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f
4520 #define EDP_PSR_STATUS_COUNT_SHIFT 16
4521 #define EDP_PSR_STATUS_COUNT_MASK 0xf
4522 #define EDP_PSR_STATUS_AUX_ERROR (1 << 15)
4523 #define EDP_PSR_STATUS_AUX_SENDING (1 << 12)
4524 #define EDP_PSR_STATUS_SENDING_IDLE (1 << 9)
4525 #define EDP_PSR_STATUS_SENDING_TP2_TP3 (1 << 8)
4526 #define EDP_PSR_STATUS_SENDING_TP1 (1 << 4)
4527 #define EDP_PSR_STATUS_IDLE_MASK 0xf
4528
4529 #define _SRD_PERF_CNT_A 0x60844
4530 #define _SRD_PERF_CNT_EDP 0x6f844
4531 #define EDP_PSR_PERF_CNT(tran) _MMIO(_PSR_ADJ(tran, _SRD_PERF_CNT_A))
4532 #define EDP_PSR_PERF_CNT_MASK 0xffffff
4533
4534 /* PSR_MASK on SKL+ */
4535 #define _SRD_DEBUG_A 0x60860
4536 #define _SRD_DEBUG_EDP 0x6f860
4537 #define EDP_PSR_DEBUG(tran) _MMIO(_PSR_ADJ(tran, _SRD_DEBUG_A))
4538 #define EDP_PSR_DEBUG_MASK_MAX_SLEEP (1 << 28)
4539 #define EDP_PSR_DEBUG_MASK_LPSP (1 << 27)
4540 #define EDP_PSR_DEBUG_MASK_MEMUP (1 << 26)
4541 #define EDP_PSR_DEBUG_MASK_HPD (1 << 25)
4542 #define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (1 << 16) /* Reserved in ICL+ */
4543 #define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1 << 15) /* SKL+ */
4544
4545 #define _PSR2_CTL_A 0x60900
4546 #define _PSR2_CTL_EDP 0x6f900
4547 #define EDP_PSR2_CTL(tran) _MMIO_TRANS2(tran, _PSR2_CTL_A)
4548 #define EDP_PSR2_ENABLE (1 << 31)
4549 #define EDP_SU_TRACK_ENABLE (1 << 30)
4550 #define TGL_EDP_PSR2_BLOCK_COUNT_NUM_2 (0 << 28)
4551 #define TGL_EDP_PSR2_BLOCK_COUNT_NUM_3 (1 << 28)
4552 #define EDP_Y_COORDINATE_VALID (1 << 26) /* GLK and CNL+ */
4553 #define EDP_Y_COORDINATE_ENABLE (1 << 25) /* GLK and CNL+ */
4554 #define EDP_MAX_SU_DISABLE_TIME(t) ((t) << 20)
4555 #define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f << 20)
4556 #define EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES 8
4557 #define EDP_PSR2_IO_BUFFER_WAKE(lines) ((EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES - (lines)) << 13)
4558 #define EDP_PSR2_IO_BUFFER_WAKE_MASK (3 << 13)
4559 #define TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES 5
4560 #define TGL_EDP_PSR2_IO_BUFFER_WAKE(lines) (((lines) - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) << 13)
4561 #define TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK (7 << 13)
4562 #define EDP_PSR2_FAST_WAKE_MAX_LINES 8
4563 #define EDP_PSR2_FAST_WAKE(lines) ((EDP_PSR2_FAST_WAKE_MAX_LINES - (lines)) << 11)
4564 #define EDP_PSR2_FAST_WAKE_MASK (3 << 11)
4565 #define TGL_EDP_PSR2_FAST_WAKE_MIN_LINES 5
4566 #define TGL_EDP_PSR2_FAST_WAKE(lines) (((lines) - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES) << 10)
4567 #define TGL_EDP_PSR2_FAST_WAKE_MASK (7 << 10)
4568 #define EDP_PSR2_TP2_TIME_500us (0 << 8)
4569 #define EDP_PSR2_TP2_TIME_100us (1 << 8)
4570 #define EDP_PSR2_TP2_TIME_2500us (2 << 8)
4571 #define EDP_PSR2_TP2_TIME_50us (3 << 8)
4572 #define EDP_PSR2_TP2_TIME_MASK (3 << 8)
4573 #define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
4574 #define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf << 4)
4575 #define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << 4)
4576 #define EDP_PSR2_IDLE_FRAME_MASK 0xf
4577 #define EDP_PSR2_IDLE_FRAME_SHIFT 0
4578
4579 #define _PSR_EVENT_TRANS_A 0x60848
4580 #define _PSR_EVENT_TRANS_B 0x61848
4581 #define _PSR_EVENT_TRANS_C 0x62848
4582 #define _PSR_EVENT_TRANS_D 0x63848
4583 #define _PSR_EVENT_TRANS_EDP 0x6f848
4584 #define PSR_EVENT(tran) _MMIO_TRANS2(tran, _PSR_EVENT_TRANS_A)
4585 #define PSR_EVENT_PSR2_WD_TIMER_EXPIRE (1 << 17)
4586 #define PSR_EVENT_PSR2_DISABLED (1 << 16)
4587 #define PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN (1 << 15)
4588 #define PSR_EVENT_SU_CRC_FIFO_UNDERRUN (1 << 14)
4589 #define PSR_EVENT_GRAPHICS_RESET (1 << 12)
4590 #define PSR_EVENT_PCH_INTERRUPT (1 << 11)
4591 #define PSR_EVENT_MEMORY_UP (1 << 10)
4592 #define PSR_EVENT_FRONT_BUFFER_MODIFY (1 << 9)
4593 #define PSR_EVENT_WD_TIMER_EXPIRE (1 << 8)
4594 #define PSR_EVENT_PIPE_REGISTERS_UPDATE (1 << 6)
4595 #define PSR_EVENT_REGISTER_UPDATE (1 << 5) /* Reserved in ICL+ */
4596 #define PSR_EVENT_HDCP_ENABLE (1 << 4)
4597 #define PSR_EVENT_KVMR_SESSION_ENABLE (1 << 3)
4598 #define PSR_EVENT_VBI_ENABLE (1 << 2)
4599 #define PSR_EVENT_LPSP_MODE_EXIT (1 << 1)
4600 #define PSR_EVENT_PSR_DISABLE (1 << 0)
4601
4602 #define _PSR2_STATUS_A 0x60940
4603 #define _PSR2_STATUS_EDP 0x6f940
4604 #define EDP_PSR2_STATUS(tran) _MMIO_TRANS2(tran, _PSR2_STATUS_A)
4605 #define EDP_PSR2_STATUS_STATE_MASK (0xf << 28)
4606 #define EDP_PSR2_STATUS_STATE_SHIFT 28
4607
4608 #define _PSR2_SU_STATUS_A 0x60914
4609 #define _PSR2_SU_STATUS_EDP 0x6f914
4610 #define _PSR2_SU_STATUS(tran, index) _MMIO(_TRANS2(tran, _PSR2_SU_STATUS_A) + (index) * 4)
4611 #define PSR2_SU_STATUS(tran, frame) (_PSR2_SU_STATUS(tran, (frame) / 3))
4612 #define PSR2_SU_STATUS_SHIFT(frame) (((frame) % 3) * 10)
4613 #define PSR2_SU_STATUS_MASK(frame) (0x3ff << PSR2_SU_STATUS_SHIFT(frame))
4614 #define PSR2_SU_STATUS_FRAMES 8
4615
4616 #define _PSR2_MAN_TRK_CTL_A 0x60910
4617 #define _PSR2_MAN_TRK_CTL_EDP 0x6f910
4618 #define PSR2_MAN_TRK_CTL(tran) _MMIO_TRANS2(tran, _PSR2_MAN_TRK_CTL_A)
4619 #define PSR2_MAN_TRK_CTL_ENABLE REG_BIT(31)
4620 #define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(30, 21)
4621 #define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
4622 #define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(20, 11)
4623 #define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)
4624 #define PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(3)
4625 #define PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(2)
4626 #define PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(1)
4627
4628 /* Icelake DSC Rate Control Range Parameter Registers */
4629 #define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240)
4630 #define DSCA_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6B240 + 4)
4631 #define DSCC_RC_RANGE_PARAMETERS_0 _MMIO(0x6BA40)
4632 #define DSCC_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6BA40 + 4)
4633 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB (0x78208)
4634 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB (0x78208 + 4)
4635 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB (0x78308)
4636 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB (0x78308 + 4)
4637 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC (0x78408)
4638 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC (0x78408 + 4)
4639 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC (0x78508)
4640 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC (0x78508 + 4)
4641 #define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4642 _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \
4643 _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC)
4644 #define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4645 _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \
4646 _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC)
4647 #define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4648 _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \
4649 _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC)
4650 #define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4651 _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \
4652 _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC)
4653 #define RC_BPG_OFFSET_SHIFT 10
4654 #define RC_MAX_QP_SHIFT 5
4655 #define RC_MIN_QP_SHIFT 0
4656
4657 #define DSCA_RC_RANGE_PARAMETERS_1 _MMIO(0x6B248)
4658 #define DSCA_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6B248 + 4)
4659 #define DSCC_RC_RANGE_PARAMETERS_1 _MMIO(0x6BA48)
4660 #define DSCC_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6BA48 + 4)
4661 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB (0x78210)
4662 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB (0x78210 + 4)
4663 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB (0x78310)
4664 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB (0x78310 + 4)
4665 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC (0x78410)
4666 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC (0x78410 + 4)
4667 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC (0x78510)
4668 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC (0x78510 + 4)
4669 #define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4670 _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \
4671 _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC)
4672 #define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4673 _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \
4674 _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC)
4675 #define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4676 _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \
4677 _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC)
4678 #define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4679 _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \
4680 _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC)
4681
4682 #define DSCA_RC_RANGE_PARAMETERS_2 _MMIO(0x6B250)
4683 #define DSCA_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6B250 + 4)
4684 #define DSCC_RC_RANGE_PARAMETERS_2 _MMIO(0x6BA50)
4685 #define DSCC_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6BA50 + 4)
4686 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB (0x78218)
4687 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB (0x78218 + 4)
4688 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB (0x78318)
4689 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB (0x78318 + 4)
4690 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC (0x78418)
4691 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC (0x78418 + 4)
4692 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC (0x78518)
4693 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC (0x78518 + 4)
4694 #define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4695 _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \
4696 _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC)
4697 #define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4698 _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \
4699 _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC)
4700 #define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4701 _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \
4702 _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC)
4703 #define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4704 _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \
4705 _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC)
4706
4707 #define DSCA_RC_RANGE_PARAMETERS_3 _MMIO(0x6B258)
4708 #define DSCA_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6B258 + 4)
4709 #define DSCC_RC_RANGE_PARAMETERS_3 _MMIO(0x6BA58)
4710 #define DSCC_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6BA58 + 4)
4711 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB (0x78220)
4712 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB (0x78220 + 4)
4713 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB (0x78320)
4714 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB (0x78320 + 4)
4715 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC (0x78420)
4716 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC (0x78420 + 4)
4717 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC (0x78520)
4718 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC (0x78520 + 4)
4719 #define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4720 _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \
4721 _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC)
4722 #define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4723 _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \
4724 _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC)
4725 #define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4726 _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \
4727 _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC)
4728 #define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
4729 _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \
4730 _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC)
4731
4732 /* VGA port control */
4733 #define ADPA _MMIO(0x61100)
4734 #define PCH_ADPA _MMIO(0xe1100)
4735 #define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100)
4736
4737 #define ADPA_DAC_ENABLE (1 << 31)
4738 #define ADPA_DAC_DISABLE 0
4739 #define ADPA_PIPE_SEL_SHIFT 30
4740 #define ADPA_PIPE_SEL_MASK (1 << 30)
4741 #define ADPA_PIPE_SEL(pipe) ((pipe) << 30)
4742 #define ADPA_PIPE_SEL_SHIFT_CPT 29
4743 #define ADPA_PIPE_SEL_MASK_CPT (3 << 29)
4744 #define ADPA_PIPE_SEL_CPT(pipe) ((pipe) << 29)
4745 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
4746 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0 << 24)
4747 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3 << 24)
4748 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3 << 24)
4749 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2 << 24)
4750 #define ADPA_CRT_HOTPLUG_ENABLE (1 << 23)
4751 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0 << 22)
4752 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1 << 22)
4753 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0 << 21)
4754 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1 << 21)
4755 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0 << 20)
4756 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1 << 20)
4757 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0 << 18)
4758 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1 << 18)
4759 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2 << 18)
4760 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3 << 18)
4761 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0 << 17)
4762 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1 << 17)
4763 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1 << 16)
4764 #define ADPA_USE_VGA_HVPOLARITY (1 << 15)
4765 #define ADPA_SETS_HVPOLARITY 0
4766 #define ADPA_VSYNC_CNTL_DISABLE (1 << 10)
4767 #define ADPA_VSYNC_CNTL_ENABLE 0
4768 #define ADPA_HSYNC_CNTL_DISABLE (1 << 11)
4769 #define ADPA_HSYNC_CNTL_ENABLE 0
4770 #define ADPA_VSYNC_ACTIVE_HIGH (1 << 4)
4771 #define ADPA_VSYNC_ACTIVE_LOW 0
4772 #define ADPA_HSYNC_ACTIVE_HIGH (1 << 3)
4773 #define ADPA_HSYNC_ACTIVE_LOW 0
4774 #define ADPA_DPMS_MASK (~(3 << 10))
4775 #define ADPA_DPMS_ON (0 << 10)
4776 #define ADPA_DPMS_SUSPEND (1 << 10)
4777 #define ADPA_DPMS_STANDBY (2 << 10)
4778 #define ADPA_DPMS_OFF (3 << 10)
4779
4780
4781 /* Hotplug control (945+ only) */
4782 #define PORT_HOTPLUG_EN _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110)
4783 #define PORTB_HOTPLUG_INT_EN (1 << 29)
4784 #define PORTC_HOTPLUG_INT_EN (1 << 28)
4785 #define PORTD_HOTPLUG_INT_EN (1 << 27)
4786 #define SDVOB_HOTPLUG_INT_EN (1 << 26)
4787 #define SDVOC_HOTPLUG_INT_EN (1 << 25)
4788 #define TV_HOTPLUG_INT_EN (1 << 18)
4789 #define CRT_HOTPLUG_INT_EN (1 << 9)
4790 #define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \
4791 PORTC_HOTPLUG_INT_EN | \
4792 PORTD_HOTPLUG_INT_EN | \
4793 SDVOC_HOTPLUG_INT_EN | \
4794 SDVOB_HOTPLUG_INT_EN | \
4795 CRT_HOTPLUG_INT_EN)
4796 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
4797 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
4798 /* must use period 64 on GM45 according to docs */
4799 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
4800 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
4801 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
4802 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
4803 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
4804 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
4805 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
4806 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
4807 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
4808 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
4809 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
4810 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
4811
4812 #define PORT_HOTPLUG_STAT _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114)
4813 /*
4814 * HDMI/DP bits are g4x+
4815 *
4816 * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused.
4817 * Please check the detailed lore in the commit message for for experimental
4818 * evidence.
4819 */
4820 /* Bspec says GM45 should match G4X/VLV/CHV, but reality disagrees */
4821 #define PORTD_HOTPLUG_LIVE_STATUS_GM45 (1 << 29)
4822 #define PORTC_HOTPLUG_LIVE_STATUS_GM45 (1 << 28)
4823 #define PORTB_HOTPLUG_LIVE_STATUS_GM45 (1 << 27)
4824 /* G4X/VLV/CHV DP/HDMI bits again match Bspec */
4825 #define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 27)
4826 #define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28)
4827 #define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 29)
4828 #define PORTD_HOTPLUG_INT_STATUS (3 << 21)
4829 #define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21)
4830 #define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21)
4831 #define PORTC_HOTPLUG_INT_STATUS (3 << 19)
4832 #define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19)
4833 #define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19)
4834 #define PORTB_HOTPLUG_INT_STATUS (3 << 17)
4835 #define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17)
4836 #define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17)
4837 /* CRT/TV common between gen3+ */
4838 #define CRT_HOTPLUG_INT_STATUS (1 << 11)
4839 #define TV_HOTPLUG_INT_STATUS (1 << 10)
4840 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
4841 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
4842 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
4843 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
4844 #define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6)
4845 #define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5)
4846 #define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4)
4847 #define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4)
4848
4849 /* SDVO is different across gen3/4 */
4850 #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3)
4851 #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2)
4852 /*
4853 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm,
4854 * since reality corrobates that they're the same as on gen3. But keep these
4855 * bits here (and the comment!) to help any other lost wanderers back onto the
4856 * right tracks.
4857 */
4858 #define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4)
4859 #define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2)
4860 #define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7)
4861 #define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6)
4862 #define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \
4863 SDVOB_HOTPLUG_INT_STATUS_G4X | \
4864 SDVOC_HOTPLUG_INT_STATUS_G4X | \
4865 PORTB_HOTPLUG_INT_STATUS | \
4866 PORTC_HOTPLUG_INT_STATUS | \
4867 PORTD_HOTPLUG_INT_STATUS)
4868
4869 #define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \
4870 SDVOB_HOTPLUG_INT_STATUS_I915 | \
4871 SDVOC_HOTPLUG_INT_STATUS_I915 | \
4872 PORTB_HOTPLUG_INT_STATUS | \
4873 PORTC_HOTPLUG_INT_STATUS | \
4874 PORTD_HOTPLUG_INT_STATUS)
4875
4876 /* SDVO and HDMI port control.
4877 * The same register may be used for SDVO or HDMI */
4878 #define _GEN3_SDVOB 0x61140
4879 #define _GEN3_SDVOC 0x61160
4880 #define GEN3_SDVOB _MMIO(_GEN3_SDVOB)
4881 #define GEN3_SDVOC _MMIO(_GEN3_SDVOC)
4882 #define GEN4_HDMIB GEN3_SDVOB
4883 #define GEN4_HDMIC GEN3_SDVOC
4884 #define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140)
4885 #define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160)
4886 #define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C)
4887 #define PCH_SDVOB _MMIO(0xe1140)
4888 #define PCH_HDMIB PCH_SDVOB
4889 #define PCH_HDMIC _MMIO(0xe1150)
4890 #define PCH_HDMID _MMIO(0xe1160)
4891
4892 #define PORT_DFT_I9XX _MMIO(0x61150)
4893 #define DC_BALANCE_RESET (1 << 25)
4894 #define PORT_DFT2_G4X _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154)
4895 #define DC_BALANCE_RESET_VLV (1 << 31)
4896 #define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0))
4897 #define PIPE_C_SCRAMBLE_RESET (1 << 14) /* chv */
4898 #define PIPE_B_SCRAMBLE_RESET (1 << 1)
4899 #define PIPE_A_SCRAMBLE_RESET (1 << 0)
4900
4901 /* Gen 3 SDVO bits: */
4902 #define SDVO_ENABLE (1 << 31)
4903 #define SDVO_PIPE_SEL_SHIFT 30
4904 #define SDVO_PIPE_SEL_MASK (1 << 30)
4905 #define SDVO_PIPE_SEL(pipe) ((pipe) << 30)
4906 #define SDVO_STALL_SELECT (1 << 29)
4907 #define SDVO_INTERRUPT_ENABLE (1 << 26)
4908 /*
4909 * 915G/GM SDVO pixel multiplier.
4910 * Programmed value is multiplier - 1, up to 5x.
4911 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
4912 */
4913 #define SDVO_PORT_MULTIPLY_MASK (7 << 23)
4914 #define SDVO_PORT_MULTIPLY_SHIFT 23
4915 #define SDVO_PHASE_SELECT_MASK (15 << 19)
4916 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
4917 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
4918 #define SDVOC_GANG_MODE (1 << 16) /* Port C only */
4919 #define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */
4920 #define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */
4921 #define SDVO_DETECTED (1 << 2)
4922 /* Bits to be preserved when writing */
4923 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \
4924 SDVO_INTERRUPT_ENABLE)
4925 #define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE)
4926
4927 /* Gen 4 SDVO/HDMI bits: */
4928 #define SDVO_COLOR_FORMAT_8bpc (0 << 26)
4929 #define SDVO_COLOR_FORMAT_MASK (7 << 26)
4930 #define SDVO_ENCODING_SDVO (0 << 10)
4931 #define SDVO_ENCODING_HDMI (2 << 10)
4932 #define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */
4933 #define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */
4934 #define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */
4935 #define HDMI_AUDIO_ENABLE (1 << 6) /* HDMI only */
4936 /* VSYNC/HSYNC bits new with 965, default is to be set */
4937 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
4938 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
4939
4940 /* Gen 5 (IBX) SDVO/HDMI bits: */
4941 #define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */
4942 #define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */
4943
4944 /* Gen 6 (CPT) SDVO/HDMI bits: */
4945 #define SDVO_PIPE_SEL_SHIFT_CPT 29
4946 #define SDVO_PIPE_SEL_MASK_CPT (3 << 29)
4947 #define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29)
4948
4949 /* CHV SDVO/HDMI bits: */
4950 #define SDVO_PIPE_SEL_SHIFT_CHV 24
4951 #define SDVO_PIPE_SEL_MASK_CHV (3 << 24)
4952 #define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24)
4953
4954
4955 /* DVO port control */
4956 #define _DVOA 0x61120
4957 #define DVOA _MMIO(_DVOA)
4958 #define _DVOB 0x61140
4959 #define DVOB _MMIO(_DVOB)
4960 #define _DVOC 0x61160
4961 #define DVOC _MMIO(_DVOC)
4962 #define DVO_ENABLE (1 << 31)
4963 #define DVO_PIPE_SEL_SHIFT 30
4964 #define DVO_PIPE_SEL_MASK (1 << 30)
4965 #define DVO_PIPE_SEL(pipe) ((pipe) << 30)
4966 #define DVO_PIPE_STALL_UNUSED (0 << 28)
4967 #define DVO_PIPE_STALL (1 << 28)
4968 #define DVO_PIPE_STALL_TV (2 << 28)
4969 #define DVO_PIPE_STALL_MASK (3 << 28)
4970 #define DVO_USE_VGA_SYNC (1 << 15)
4971 #define DVO_DATA_ORDER_I740 (0 << 14)
4972 #define DVO_DATA_ORDER_FP (1 << 14)
4973 #define DVO_VSYNC_DISABLE (1 << 11)
4974 #define DVO_HSYNC_DISABLE (1 << 10)
4975 #define DVO_VSYNC_TRISTATE (1 << 9)
4976 #define DVO_HSYNC_TRISTATE (1 << 8)
4977 #define DVO_BORDER_ENABLE (1 << 7)
4978 #define DVO_DATA_ORDER_GBRG (1 << 6)
4979 #define DVO_DATA_ORDER_RGGB (0 << 6)
4980 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
4981 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
4982 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
4983 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
4984 #define DVO_BLANK_ACTIVE_HIGH (1 << 2)
4985 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
4986 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
4987 #define DVO_PRESERVE_MASK (0x7 << 24)
4988 #define DVOA_SRCDIM _MMIO(0x61124)
4989 #define DVOB_SRCDIM _MMIO(0x61144)
4990 #define DVOC_SRCDIM _MMIO(0x61164)
4991 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12
4992 #define DVO_SRCDIM_VERTICAL_SHIFT 0
4993
4994 /* LVDS port control */
4995 #define LVDS _MMIO(0x61180)
4996 /*
4997 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
4998 * the DPLL semantics change when the LVDS is assigned to that pipe.
4999 */
5000 #define LVDS_PORT_EN (1 << 31)
5001 /* Selects pipe B for LVDS data. Must be set on pre-965. */
5002 #define LVDS_PIPE_SEL_SHIFT 30
5003 #define LVDS_PIPE_SEL_MASK (1 << 30)
5004 #define LVDS_PIPE_SEL(pipe) ((pipe) << 30)
5005 #define LVDS_PIPE_SEL_SHIFT_CPT 29
5006 #define LVDS_PIPE_SEL_MASK_CPT (3 << 29)
5007 #define LVDS_PIPE_SEL_CPT(pipe) ((pipe) << 29)
5008 /* LVDS dithering flag on 965/g4x platform */
5009 #define LVDS_ENABLE_DITHER (1 << 25)
5010 /* LVDS sync polarity flags. Set to invert (i.e. negative) */
5011 #define LVDS_VSYNC_POLARITY (1 << 21)
5012 #define LVDS_HSYNC_POLARITY (1 << 20)
5013
5014 /* Enable border for unscaled (or aspect-scaled) display */
5015 #define LVDS_BORDER_ENABLE (1 << 15)
5016 /*
5017 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
5018 * pixel.
5019 */
5020 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
5021 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
5022 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
5023 /*
5024 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
5025 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
5026 * on.
5027 */
5028 #define LVDS_A3_POWER_MASK (3 << 6)
5029 #define LVDS_A3_POWER_DOWN (0 << 6)
5030 #define LVDS_A3_POWER_UP (3 << 6)
5031 /*
5032 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
5033 * is set.
5034 */
5035 #define LVDS_CLKB_POWER_MASK (3 << 4)
5036 #define LVDS_CLKB_POWER_DOWN (0 << 4)
5037 #define LVDS_CLKB_POWER_UP (3 << 4)
5038 /*
5039 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
5040 * setting for whether we are in dual-channel mode. The B3 pair will
5041 * additionally only be powered up when LVDS_A3_POWER_UP is set.
5042 */
5043 #define LVDS_B0B3_POWER_MASK (3 << 2)
5044 #define LVDS_B0B3_POWER_DOWN (0 << 2)
5045 #define LVDS_B0B3_POWER_UP (3 << 2)
5046
5047 /* Video Data Island Packet control */
5048 #define VIDEO_DIP_DATA _MMIO(0x61178)
5049 /* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC
5050 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
5051 * of the infoframe structure specified by CEA-861. */
5052 #define VIDEO_DIP_DATA_SIZE 32
5053 #define VIDEO_DIP_GMP_DATA_SIZE 36
5054 #define VIDEO_DIP_VSC_DATA_SIZE 36
5055 #define VIDEO_DIP_PPS_DATA_SIZE 132
5056 #define VIDEO_DIP_CTL _MMIO(0x61170)
5057 /* Pre HSW: */
5058 #define VIDEO_DIP_ENABLE (1 << 31)
5059 #define VIDEO_DIP_PORT(port) ((port) << 29)
5060 #define VIDEO_DIP_PORT_MASK (3 << 29)
5061 #define VIDEO_DIP_ENABLE_GCP (1 << 25) /* ilk+ */
5062 #define VIDEO_DIP_ENABLE_AVI (1 << 21)
5063 #define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
5064 #define VIDEO_DIP_ENABLE_GAMUT (4 << 21) /* ilk+ */
5065 #define VIDEO_DIP_ENABLE_SPD (8 << 21)
5066 #define VIDEO_DIP_SELECT_AVI (0 << 19)
5067 #define VIDEO_DIP_SELECT_VENDOR (1 << 19)
5068 #define VIDEO_DIP_SELECT_GAMUT (2 << 19)
5069 #define VIDEO_DIP_SELECT_SPD (3 << 19)
5070 #define VIDEO_DIP_SELECT_MASK (3 << 19)
5071 #define VIDEO_DIP_FREQ_ONCE (0 << 16)
5072 #define VIDEO_DIP_FREQ_VSYNC (1 << 16)
5073 #define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
5074 #define VIDEO_DIP_FREQ_MASK (3 << 16)
5075 /* HSW and later: */
5076 #define VIDEO_DIP_ENABLE_DRM_GLK (1 << 28)
5077 #define PSR_VSC_BIT_7_SET (1 << 27)
5078 #define VSC_SELECT_MASK (0x3 << 25)
5079 #define VSC_SELECT_SHIFT 25
5080 #define VSC_DIP_HW_HEA_DATA (0 << 25)
5081 #define VSC_DIP_HW_HEA_SW_DATA (1 << 25)
5082 #define VSC_DIP_HW_DATA_SW_HEA (2 << 25)
5083 #define VSC_DIP_SW_HEA_DATA (3 << 25)
5084 #define VDIP_ENABLE_PPS (1 << 24)
5085 #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20)
5086 #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16)
5087 #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12)
5088 #define VIDEO_DIP_ENABLE_VS_HSW (1 << 8)
5089 #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
5090 #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
5091
5092 /* Panel power sequencing */
5093 #define PPS_BASE 0x61200
5094 #define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE)
5095 #define PCH_PPS_BASE 0xC7200
5096
5097 #define _MMIO_PPS(pps_idx, reg) _MMIO(dev_priv->pps_mmio_base - \
5098 PPS_BASE + (reg) + \
5099 (pps_idx) * 0x100)
5100
5101 #define _PP_STATUS 0x61200
5102 #define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS)
5103 #define PP_ON REG_BIT(31)
5104 /*
5105 * Indicates that all dependencies of the panel are on:
5106 *
5107 * - PLL enabled
5108 * - pipe enabled
5109 * - LVDS/DVOB/DVOC on
5110 */
5111 #define PP_READY REG_BIT(30)
5112 #define PP_SEQUENCE_MASK REG_GENMASK(29, 28)
5113 #define PP_SEQUENCE_NONE REG_FIELD_PREP(PP_SEQUENCE_MASK, 0)
5114 #define PP_SEQUENCE_POWER_UP REG_FIELD_PREP(PP_SEQUENCE_MASK, 1)
5115 #define PP_SEQUENCE_POWER_DOWN REG_FIELD_PREP(PP_SEQUENCE_MASK, 2)
5116 #define PP_CYCLE_DELAY_ACTIVE REG_BIT(27)
5117 #define PP_SEQUENCE_STATE_MASK REG_GENMASK(3, 0)
5118 #define PP_SEQUENCE_STATE_OFF_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x0)
5119 #define PP_SEQUENCE_STATE_OFF_S0_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x1)
5120 #define PP_SEQUENCE_STATE_OFF_S0_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x2)
5121 #define PP_SEQUENCE_STATE_OFF_S0_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x3)
5122 #define PP_SEQUENCE_STATE_ON_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x8)
5123 #define PP_SEQUENCE_STATE_ON_S1_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x9)
5124 #define PP_SEQUENCE_STATE_ON_S1_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xa)
5125 #define PP_SEQUENCE_STATE_ON_S1_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xb)
5126 #define PP_SEQUENCE_STATE_RESET REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xf)
5127
5128 #define _PP_CONTROL 0x61204
5129 #define PP_CONTROL(pps_idx) _MMIO_PPS(pps_idx, _PP_CONTROL)
5130 #define PANEL_UNLOCK_MASK REG_GENMASK(31, 16)
5131 #define PANEL_UNLOCK_REGS REG_FIELD_PREP(PANEL_UNLOCK_MASK, 0xabcd)
5132 #define BXT_POWER_CYCLE_DELAY_MASK REG_GENMASK(8, 4)
5133 #define EDP_FORCE_VDD REG_BIT(3)
5134 #define EDP_BLC_ENABLE REG_BIT(2)
5135 #define PANEL_POWER_RESET REG_BIT(1)
5136 #define PANEL_POWER_ON REG_BIT(0)
5137
5138 #define _PP_ON_DELAYS 0x61208
5139 #define PP_ON_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_ON_DELAYS)
5140 #define PANEL_PORT_SELECT_MASK REG_GENMASK(31, 30)
5141 #define PANEL_PORT_SELECT_LVDS REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 0)
5142 #define PANEL_PORT_SELECT_DPA REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 1)
5143 #define PANEL_PORT_SELECT_DPC REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 2)
5144 #define PANEL_PORT_SELECT_DPD REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 3)
5145 #define PANEL_PORT_SELECT_VLV(port) REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, port)
5146 #define PANEL_POWER_UP_DELAY_MASK REG_GENMASK(28, 16)
5147 #define PANEL_LIGHT_ON_DELAY_MASK REG_GENMASK(12, 0)
5148
5149 #define _PP_OFF_DELAYS 0x6120C
5150 #define PP_OFF_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_OFF_DELAYS)
5151 #define PANEL_POWER_DOWN_DELAY_MASK REG_GENMASK(28, 16)
5152 #define PANEL_LIGHT_OFF_DELAY_MASK REG_GENMASK(12, 0)
5153
5154 #define _PP_DIVISOR 0x61210
5155 #define PP_DIVISOR(pps_idx) _MMIO_PPS(pps_idx, _PP_DIVISOR)
5156 #define PP_REFERENCE_DIVIDER_MASK REG_GENMASK(31, 8)
5157 #define PANEL_POWER_CYCLE_DELAY_MASK REG_GENMASK(4, 0)
5158
5159 /* Panel fitting */
5160 #define PFIT_CONTROL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230)
5161 #define PFIT_ENABLE (1 << 31)
5162 #define PFIT_PIPE_MASK (3 << 29)
5163 #define PFIT_PIPE_SHIFT 29
5164 #define PFIT_PIPE(pipe) ((pipe) << 29)
5165 #define VERT_INTERP_DISABLE (0 << 10)
5166 #define VERT_INTERP_BILINEAR (1 << 10)
5167 #define VERT_INTERP_MASK (3 << 10)
5168 #define VERT_AUTO_SCALE (1 << 9)
5169 #define HORIZ_INTERP_DISABLE (0 << 6)
5170 #define HORIZ_INTERP_BILINEAR (1 << 6)
5171 #define HORIZ_INTERP_MASK (3 << 6)
5172 #define HORIZ_AUTO_SCALE (1 << 5)
5173 #define PANEL_8TO6_DITHER_ENABLE (1 << 3)
5174 #define PFIT_FILTER_FUZZY (0 << 24)
5175 #define PFIT_SCALING_AUTO (0 << 26)
5176 #define PFIT_SCALING_PROGRAMMED (1 << 26)
5177 #define PFIT_SCALING_PILLAR (2 << 26)
5178 #define PFIT_SCALING_LETTER (3 << 26)
5179 #define PFIT_PGM_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234)
5180 /* Pre-965 */
5181 #define PFIT_VERT_SCALE_SHIFT 20
5182 #define PFIT_VERT_SCALE_MASK 0xfff00000
5183 #define PFIT_HORIZ_SCALE_SHIFT 4
5184 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0
5185 /* 965+ */
5186 #define PFIT_VERT_SCALE_SHIFT_965 16
5187 #define PFIT_VERT_SCALE_MASK_965 0x1fff0000
5188 #define PFIT_HORIZ_SCALE_SHIFT_965 0
5189 #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
5190
5191 #define PFIT_AUTO_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238)
5192
5193 #define _VLV_BLC_PWM_CTL2_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61250)
5194 #define _VLV_BLC_PWM_CTL2_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61350)
5195 #define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
5196 _VLV_BLC_PWM_CTL2_B)
5197
5198 #define _VLV_BLC_PWM_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61254)
5199 #define _VLV_BLC_PWM_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61354)
5200 #define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
5201 _VLV_BLC_PWM_CTL_B)
5202
5203 #define _VLV_BLC_HIST_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61260)
5204 #define _VLV_BLC_HIST_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61360)
5205 #define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
5206 _VLV_BLC_HIST_CTL_B)
5207
5208 /* Backlight control */
5209 #define BLC_PWM_CTL2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61250) /* 965+ only */
5210 #define BLM_PWM_ENABLE (1 << 31)
5211 #define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */
5212 #define BLM_PIPE_SELECT (1 << 29)
5213 #define BLM_PIPE_SELECT_IVB (3 << 29)
5214 #define BLM_PIPE_A (0 << 29)
5215 #define BLM_PIPE_B (1 << 29)
5216 #define BLM_PIPE_C (2 << 29) /* ivb + */
5217 #define BLM_TRANSCODER_A BLM_PIPE_A /* hsw */
5218 #define BLM_TRANSCODER_B BLM_PIPE_B
5219 #define BLM_TRANSCODER_C BLM_PIPE_C
5220 #define BLM_TRANSCODER_EDP (3 << 29)
5221 #define BLM_PIPE(pipe) ((pipe) << 29)
5222 #define BLM_POLARITY_I965 (1 << 28) /* gen4 only */
5223 #define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26)
5224 #define BLM_PHASE_IN_ENABLE (1 << 25)
5225 #define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24)
5226 #define BLM_PHASE_IN_TIME_BASE_SHIFT (16)
5227 #define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16)
5228 #define BLM_PHASE_IN_COUNT_SHIFT (8)
5229 #define BLM_PHASE_IN_COUNT_MASK (0xff << 8)
5230 #define BLM_PHASE_IN_INCR_SHIFT (0)
5231 #define BLM_PHASE_IN_INCR_MASK (0xff << 0)
5232 #define BLC_PWM_CTL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61254)
5233 /*
5234 * This is the most significant 15 bits of the number of backlight cycles in a
5235 * complete cycle of the modulated backlight control.
5236 *
5237 * The actual value is this field multiplied by two.
5238 */
5239 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
5240 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
5241 #define BLM_LEGACY_MODE (1 << 16) /* gen2 only */
5242 /*
5243 * This is the number of cycles out of the backlight modulation cycle for which
5244 * the backlight is on.
5245 *
5246 * This field must be no greater than the number of cycles in the complete
5247 * backlight modulation cycle.
5248 */
5249 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
5250 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
5251 #define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe)
5252 #define BLM_POLARITY_PNV (1 << 0) /* pnv only */
5253
5254 #define BLC_HIST_CTL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61260)
5255 #define BLM_HISTOGRAM_ENABLE (1 << 31)
5256
5257 /* New registers for PCH-split platforms. Safe where new bits show up, the
5258 * register layout machtes with gen4 BLC_PWM_CTL[12]. */
5259 #define BLC_PWM_CPU_CTL2 _MMIO(0x48250)
5260 #define BLC_PWM_CPU_CTL _MMIO(0x48254)
5261
5262 #define HSW_BLC_PWM2_CTL _MMIO(0x48350)
5263
5264 /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
5265 * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
5266 #define BLC_PWM_PCH_CTL1 _MMIO(0xc8250)
5267 #define BLM_PCH_PWM_ENABLE (1 << 31)
5268 #define BLM_PCH_OVERRIDE_ENABLE (1 << 30)
5269 #define BLM_PCH_POLARITY (1 << 29)
5270 #define BLC_PWM_PCH_CTL2 _MMIO(0xc8254)
5271
5272 #define UTIL_PIN_CTL _MMIO(0x48400)
5273 #define UTIL_PIN_ENABLE (1 << 31)
5274 #define UTIL_PIN_PIPE_MASK (3 << 29)
5275 #define UTIL_PIN_PIPE(x) ((x) << 29)
5276 #define UTIL_PIN_MODE_MASK (0xf << 24)
5277 #define UTIL_PIN_MODE_DATA (0 << 24)
5278 #define UTIL_PIN_MODE_PWM (1 << 24)
5279 #define UTIL_PIN_MODE_VBLANK (4 << 24)
5280 #define UTIL_PIN_MODE_VSYNC (5 << 24)
5281 #define UTIL_PIN_MODE_EYE_LEVEL (8 << 24)
5282 #define UTIL_PIN_OUTPUT_DATA (1 << 23)
5283 #define UTIL_PIN_POLARITY (1 << 22)
5284 #define UTIL_PIN_DIRECTION_INPUT (1 << 19)
5285 #define UTIL_PIN_INPUT_DATA (1 << 16)
5286
5287 /* BXT backlight register definition. */
5288 #define _BXT_BLC_PWM_CTL1 0xC8250
5289 #define BXT_BLC_PWM_ENABLE (1 << 31)
5290 #define BXT_BLC_PWM_POLARITY (1 << 29)
5291 #define _BXT_BLC_PWM_FREQ1 0xC8254
5292 #define _BXT_BLC_PWM_DUTY1 0xC8258
5293
5294 #define _BXT_BLC_PWM_CTL2 0xC8350
5295 #define _BXT_BLC_PWM_FREQ2 0xC8354
5296 #define _BXT_BLC_PWM_DUTY2 0xC8358
5297
5298 #define BXT_BLC_PWM_CTL(controller) _MMIO_PIPE(controller, \
5299 _BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2)
5300 #define BXT_BLC_PWM_FREQ(controller) _MMIO_PIPE(controller, \
5301 _BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2)
5302 #define BXT_BLC_PWM_DUTY(controller) _MMIO_PIPE(controller, \
5303 _BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2)
5304
5305 #define PCH_GTC_CTL _MMIO(0xe7000)
5306 #define PCH_GTC_ENABLE (1 << 31)
5307
5308 /* TV port control */
5309 #define TV_CTL _MMIO(0x68000)
5310 /* Enables the TV encoder */
5311 # define TV_ENC_ENABLE (1 << 31)
5312 /* Sources the TV encoder input from pipe B instead of A. */
5313 # define TV_ENC_PIPE_SEL_SHIFT 30
5314 # define TV_ENC_PIPE_SEL_MASK (1 << 30)
5315 # define TV_ENC_PIPE_SEL(pipe) ((pipe) << 30)
5316 /* Outputs composite video (DAC A only) */
5317 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
5318 /* Outputs SVideo video (DAC B/C) */
5319 # define TV_ENC_OUTPUT_SVIDEO (1 << 28)
5320 /* Outputs Component video (DAC A/B/C) */
5321 # define TV_ENC_OUTPUT_COMPONENT (2 << 28)
5322 /* Outputs Composite and SVideo (DAC A/B/C) */
5323 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
5324 # define TV_TRILEVEL_SYNC (1 << 21)
5325 /* Enables slow sync generation (945GM only) */
5326 # define TV_SLOW_SYNC (1 << 20)
5327 /* Selects 4x oversampling for 480i and 576p */
5328 # define TV_OVERSAMPLE_4X (0 << 18)
5329 /* Selects 2x oversampling for 720p and 1080i */
5330 # define TV_OVERSAMPLE_2X (1 << 18)
5331 /* Selects no oversampling for 1080p */
5332 # define TV_OVERSAMPLE_NONE (2 << 18)
5333 /* Selects 8x oversampling */
5334 # define TV_OVERSAMPLE_8X (3 << 18)
5335 # define TV_OVERSAMPLE_MASK (3 << 18)
5336 /* Selects progressive mode rather than interlaced */
5337 # define TV_PROGRESSIVE (1 << 17)
5338 /* Sets the colorburst to PAL mode. Required for non-M PAL modes. */
5339 # define TV_PAL_BURST (1 << 16)
5340 /* Field for setting delay of Y compared to C */
5341 # define TV_YC_SKEW_MASK (7 << 12)
5342 /* Enables a fix for 480p/576p standard definition modes on the 915GM only */
5343 # define TV_ENC_SDP_FIX (1 << 11)
5344 /*
5345 * Enables a fix for the 915GM only.
5346 *
5347 * Not sure what it does.
5348 */
5349 # define TV_ENC_C0_FIX (1 << 10)
5350 /* Bits that must be preserved by software */
5351 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
5352 # define TV_FUSE_STATE_MASK (3 << 4)
5353 /* Read-only state that reports all features enabled */
5354 # define TV_FUSE_STATE_ENABLED (0 << 4)
5355 /* Read-only state that reports that Macrovision is disabled in hardware*/
5356 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
5357 /* Read-only state that reports that TV-out is disabled in hardware. */
5358 # define TV_FUSE_STATE_DISABLED (2 << 4)
5359 /* Normal operation */
5360 # define TV_TEST_MODE_NORMAL (0 << 0)
5361 /* Encoder test pattern 1 - combo pattern */
5362 # define TV_TEST_MODE_PATTERN_1 (1 << 0)
5363 /* Encoder test pattern 2 - full screen vertical 75% color bars */
5364 # define TV_TEST_MODE_PATTERN_2 (2 << 0)
5365 /* Encoder test pattern 3 - full screen horizontal 75% color bars */
5366 # define TV_TEST_MODE_PATTERN_3 (3 << 0)
5367 /* Encoder test pattern 4 - random noise */
5368 # define TV_TEST_MODE_PATTERN_4 (4 << 0)
5369 /* Encoder test pattern 5 - linear color ramps */
5370 # define TV_TEST_MODE_PATTERN_5 (5 << 0)
5371 /*
5372 * This test mode forces the DACs to 50% of full output.
5373 *
5374 * This is used for load detection in combination with TVDAC_SENSE_MASK
5375 */
5376 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
5377 # define TV_TEST_MODE_MASK (7 << 0)
5378
5379 #define TV_DAC _MMIO(0x68004)
5380 # define TV_DAC_SAVE 0x00ffff00
5381 /*
5382 * Reports that DAC state change logic has reported change (RO).
5383 *
5384 * This gets cleared when TV_DAC_STATE_EN is cleared
5385 */
5386 # define TVDAC_STATE_CHG (1 << 31)
5387 # define TVDAC_SENSE_MASK (7 << 28)
5388 /* Reports that DAC A voltage is above the detect threshold */
5389 # define TVDAC_A_SENSE (1 << 30)
5390 /* Reports that DAC B voltage is above the detect threshold */
5391 # define TVDAC_B_SENSE (1 << 29)
5392 /* Reports that DAC C voltage is above the detect threshold */
5393 # define TVDAC_C_SENSE (1 << 28)
5394 /*
5395 * Enables DAC state detection logic, for load-based TV detection.
5396 *
5397 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
5398 * to off, for load detection to work.
5399 */
5400 # define TVDAC_STATE_CHG_EN (1 << 27)
5401 /* Sets the DAC A sense value to high */
5402 # define TVDAC_A_SENSE_CTL (1 << 26)
5403 /* Sets the DAC B sense value to high */
5404 # define TVDAC_B_SENSE_CTL (1 << 25)
5405 /* Sets the DAC C sense value to high */
5406 # define TVDAC_C_SENSE_CTL (1 << 24)
5407 /* Overrides the ENC_ENABLE and DAC voltage levels */
5408 # define DAC_CTL_OVERRIDE (1 << 7)
5409 /* Sets the slew rate. Must be preserved in software */
5410 # define ENC_TVDAC_SLEW_FAST (1 << 6)
5411 # define DAC_A_1_3_V (0 << 4)
5412 # define DAC_A_1_1_V (1 << 4)
5413 # define DAC_A_0_7_V (2 << 4)
5414 # define DAC_A_MASK (3 << 4)
5415 # define DAC_B_1_3_V (0 << 2)
5416 # define DAC_B_1_1_V (1 << 2)
5417 # define DAC_B_0_7_V (2 << 2)
5418 # define DAC_B_MASK (3 << 2)
5419 # define DAC_C_1_3_V (0 << 0)
5420 # define DAC_C_1_1_V (1 << 0)
5421 # define DAC_C_0_7_V (2 << 0)
5422 # define DAC_C_MASK (3 << 0)
5423
5424 /*
5425 * CSC coefficients are stored in a floating point format with 9 bits of
5426 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
5427 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
5428 * -1 (0x3) being the only legal negative value.
5429 */
5430 #define TV_CSC_Y _MMIO(0x68010)
5431 # define TV_RY_MASK 0x07ff0000
5432 # define TV_RY_SHIFT 16
5433 # define TV_GY_MASK 0x00000fff
5434 # define TV_GY_SHIFT 0
5435
5436 #define TV_CSC_Y2 _MMIO(0x68014)
5437 # define TV_BY_MASK 0x07ff0000
5438 # define TV_BY_SHIFT 16
5439 /*
5440 * Y attenuation for component video.
5441 *
5442 * Stored in 1.9 fixed point.
5443 */
5444 # define TV_AY_MASK 0x000003ff
5445 # define TV_AY_SHIFT 0
5446
5447 #define TV_CSC_U _MMIO(0x68018)
5448 # define TV_RU_MASK 0x07ff0000
5449 # define TV_RU_SHIFT 16
5450 # define TV_GU_MASK 0x000007ff
5451 # define TV_GU_SHIFT 0
5452
5453 #define TV_CSC_U2 _MMIO(0x6801c)
5454 # define TV_BU_MASK 0x07ff0000
5455 # define TV_BU_SHIFT 16
5456 /*
5457 * U attenuation for component video.
5458 *
5459 * Stored in 1.9 fixed point.
5460 */
5461 # define TV_AU_MASK 0x000003ff
5462 # define TV_AU_SHIFT 0
5463
5464 #define TV_CSC_V _MMIO(0x68020)
5465 # define TV_RV_MASK 0x0fff0000
5466 # define TV_RV_SHIFT 16
5467 # define TV_GV_MASK 0x000007ff
5468 # define TV_GV_SHIFT 0
5469
5470 #define TV_CSC_V2 _MMIO(0x68024)
5471 # define TV_BV_MASK 0x07ff0000
5472 # define TV_BV_SHIFT 16
5473 /*
5474 * V attenuation for component video.
5475 *
5476 * Stored in 1.9 fixed point.
5477 */
5478 # define TV_AV_MASK 0x000007ff
5479 # define TV_AV_SHIFT 0
5480
5481 #define TV_CLR_KNOBS _MMIO(0x68028)
5482 /* 2s-complement brightness adjustment */
5483 # define TV_BRIGHTNESS_MASK 0xff000000
5484 # define TV_BRIGHTNESS_SHIFT 24
5485 /* Contrast adjustment, as a 2.6 unsigned floating point number */
5486 # define TV_CONTRAST_MASK 0x00ff0000
5487 # define TV_CONTRAST_SHIFT 16
5488 /* Saturation adjustment, as a 2.6 unsigned floating point number */
5489 # define TV_SATURATION_MASK 0x0000ff00
5490 # define TV_SATURATION_SHIFT 8
5491 /* Hue adjustment, as an integer phase angle in degrees */
5492 # define TV_HUE_MASK 0x000000ff
5493 # define TV_HUE_SHIFT 0
5494
5495 #define TV_CLR_LEVEL _MMIO(0x6802c)
5496 /* Controls the DAC level for black */
5497 # define TV_BLACK_LEVEL_MASK 0x01ff0000
5498 # define TV_BLACK_LEVEL_SHIFT 16
5499 /* Controls the DAC level for blanking */
5500 # define TV_BLANK_LEVEL_MASK 0x000001ff
5501 # define TV_BLANK_LEVEL_SHIFT 0
5502
5503 #define TV_H_CTL_1 _MMIO(0x68030)
5504 /* Number of pixels in the hsync. */
5505 # define TV_HSYNC_END_MASK 0x1fff0000
5506 # define TV_HSYNC_END_SHIFT 16
5507 /* Total number of pixels minus one in the line (display and blanking). */
5508 # define TV_HTOTAL_MASK 0x00001fff
5509 # define TV_HTOTAL_SHIFT 0
5510
5511 #define TV_H_CTL_2 _MMIO(0x68034)
5512 /* Enables the colorburst (needed for non-component color) */
5513 # define TV_BURST_ENA (1 << 31)
5514 /* Offset of the colorburst from the start of hsync, in pixels minus one. */
5515 # define TV_HBURST_START_SHIFT 16
5516 # define TV_HBURST_START_MASK 0x1fff0000
5517 /* Length of the colorburst */
5518 # define TV_HBURST_LEN_SHIFT 0
5519 # define TV_HBURST_LEN_MASK 0x0001fff
5520
5521 #define TV_H_CTL_3 _MMIO(0x68038)
5522 /* End of hblank, measured in pixels minus one from start of hsync */
5523 # define TV_HBLANK_END_SHIFT 16
5524 # define TV_HBLANK_END_MASK 0x1fff0000
5525 /* Start of hblank, measured in pixels minus one from start of hsync */
5526 # define TV_HBLANK_START_SHIFT 0
5527 # define TV_HBLANK_START_MASK 0x0001fff
5528
5529 #define TV_V_CTL_1 _MMIO(0x6803c)
5530 /* XXX */
5531 # define TV_NBR_END_SHIFT 16
5532 # define TV_NBR_END_MASK 0x07ff0000
5533 /* XXX */
5534 # define TV_VI_END_F1_SHIFT 8
5535 # define TV_VI_END_F1_MASK 0x00003f00
5536 /* XXX */
5537 # define TV_VI_END_F2_SHIFT 0
5538 # define TV_VI_END_F2_MASK 0x0000003f
5539
5540 #define TV_V_CTL_2 _MMIO(0x68040)
5541 /* Length of vsync, in half lines */
5542 # define TV_VSYNC_LEN_MASK 0x07ff0000
5543 # define TV_VSYNC_LEN_SHIFT 16
5544 /* Offset of the start of vsync in field 1, measured in one less than the
5545 * number of half lines.
5546 */
5547 # define TV_VSYNC_START_F1_MASK 0x00007f00
5548 # define TV_VSYNC_START_F1_SHIFT 8
5549 /*
5550 * Offset of the start of vsync in field 2, measured in one less than the
5551 * number of half lines.
5552 */
5553 # define TV_VSYNC_START_F2_MASK 0x0000007f
5554 # define TV_VSYNC_START_F2_SHIFT 0
5555
5556 #define TV_V_CTL_3 _MMIO(0x68044)
5557 /* Enables generation of the equalization signal */
5558 # define TV_EQUAL_ENA (1 << 31)
5559 /* Length of vsync, in half lines */
5560 # define TV_VEQ_LEN_MASK 0x007f0000
5561 # define TV_VEQ_LEN_SHIFT 16
5562 /* Offset of the start of equalization in field 1, measured in one less than
5563 * the number of half lines.
5564 */
5565 # define TV_VEQ_START_F1_MASK 0x0007f00
5566 # define TV_VEQ_START_F1_SHIFT 8
5567 /*
5568 * Offset of the start of equalization in field 2, measured in one less than
5569 * the number of half lines.
5570 */
5571 # define TV_VEQ_START_F2_MASK 0x000007f
5572 # define TV_VEQ_START_F2_SHIFT 0
5573
5574 #define TV_V_CTL_4 _MMIO(0x68048)
5575 /*
5576 * Offset to start of vertical colorburst, measured in one less than the
5577 * number of lines from vertical start.
5578 */
5579 # define TV_VBURST_START_F1_MASK 0x003f0000
5580 # define TV_VBURST_START_F1_SHIFT 16
5581 /*
5582 * Offset to the end of vertical colorburst, measured in one less than the
5583 * number of lines from the start of NBR.
5584 */
5585 # define TV_VBURST_END_F1_MASK 0x000000ff
5586 # define TV_VBURST_END_F1_SHIFT 0
5587
5588 #define TV_V_CTL_5 _MMIO(0x6804c)
5589 /*
5590 * Offset to start of vertical colorburst, measured in one less than the
5591 * number of lines from vertical start.
5592 */
5593 # define TV_VBURST_START_F2_MASK 0x003f0000
5594 # define TV_VBURST_START_F2_SHIFT 16
5595 /*
5596 * Offset to the end of vertical colorburst, measured in one less than the
5597 * number of lines from the start of NBR.
5598 */
5599 # define TV_VBURST_END_F2_MASK 0x000000ff
5600 # define TV_VBURST_END_F2_SHIFT 0
5601
5602 #define TV_V_CTL_6 _MMIO(0x68050)
5603 /*
5604 * Offset to start of vertical colorburst, measured in one less than the
5605 * number of lines from vertical start.
5606 */
5607 # define TV_VBURST_START_F3_MASK 0x003f0000
5608 # define TV_VBURST_START_F3_SHIFT 16
5609 /*
5610 * Offset to the end of vertical colorburst, measured in one less than the
5611 * number of lines from the start of NBR.
5612 */
5613 # define TV_VBURST_END_F3_MASK 0x000000ff
5614 # define TV_VBURST_END_F3_SHIFT 0
5615
5616 #define TV_V_CTL_7 _MMIO(0x68054)
5617 /*
5618 * Offset to start of vertical colorburst, measured in one less than the
5619 * number of lines from vertical start.
5620 */
5621 # define TV_VBURST_START_F4_MASK 0x003f0000
5622 # define TV_VBURST_START_F4_SHIFT 16
5623 /*
5624 * Offset to the end of vertical colorburst, measured in one less than the
5625 * number of lines from the start of NBR.
5626 */
5627 # define TV_VBURST_END_F4_MASK 0x000000ff
5628 # define TV_VBURST_END_F4_SHIFT 0
5629
5630 #define TV_SC_CTL_1 _MMIO(0x68060)
5631 /* Turns on the first subcarrier phase generation DDA */
5632 # define TV_SC_DDA1_EN (1 << 31)
5633 /* Turns on the first subcarrier phase generation DDA */
5634 # define TV_SC_DDA2_EN (1 << 30)
5635 /* Turns on the first subcarrier phase generation DDA */
5636 # define TV_SC_DDA3_EN (1 << 29)
5637 /* Sets the subcarrier DDA to reset frequency every other field */
5638 # define TV_SC_RESET_EVERY_2 (0 << 24)
5639 /* Sets the subcarrier DDA to reset frequency every fourth field */
5640 # define TV_SC_RESET_EVERY_4 (1 << 24)
5641 /* Sets the subcarrier DDA to reset frequency every eighth field */
5642 # define TV_SC_RESET_EVERY_8 (2 << 24)
5643 /* Sets the subcarrier DDA to never reset the frequency */
5644 # define TV_SC_RESET_NEVER (3 << 24)
5645 /* Sets the peak amplitude of the colorburst.*/
5646 # define TV_BURST_LEVEL_MASK 0x00ff0000
5647 # define TV_BURST_LEVEL_SHIFT 16
5648 /* Sets the increment of the first subcarrier phase generation DDA */
5649 # define TV_SCDDA1_INC_MASK 0x00000fff
5650 # define TV_SCDDA1_INC_SHIFT 0
5651
5652 #define TV_SC_CTL_2 _MMIO(0x68064)
5653 /* Sets the rollover for the second subcarrier phase generation DDA */
5654 # define TV_SCDDA2_SIZE_MASK 0x7fff0000
5655 # define TV_SCDDA2_SIZE_SHIFT 16
5656 /* Sets the increent of the second subcarrier phase generation DDA */
5657 # define TV_SCDDA2_INC_MASK 0x00007fff
5658 # define TV_SCDDA2_INC_SHIFT 0
5659
5660 #define TV_SC_CTL_3 _MMIO(0x68068)
5661 /* Sets the rollover for the third subcarrier phase generation DDA */
5662 # define TV_SCDDA3_SIZE_MASK 0x7fff0000
5663 # define TV_SCDDA3_SIZE_SHIFT 16
5664 /* Sets the increent of the third subcarrier phase generation DDA */
5665 # define TV_SCDDA3_INC_MASK 0x00007fff
5666 # define TV_SCDDA3_INC_SHIFT 0
5667
5668 #define TV_WIN_POS _MMIO(0x68070)
5669 /* X coordinate of the display from the start of horizontal active */
5670 # define TV_XPOS_MASK 0x1fff0000
5671 # define TV_XPOS_SHIFT 16
5672 /* Y coordinate of the display from the start of vertical active (NBR) */
5673 # define TV_YPOS_MASK 0x00000fff
5674 # define TV_YPOS_SHIFT 0
5675
5676 #define TV_WIN_SIZE _MMIO(0x68074)
5677 /* Horizontal size of the display window, measured in pixels*/
5678 # define TV_XSIZE_MASK 0x1fff0000
5679 # define TV_XSIZE_SHIFT 16
5680 /*
5681 * Vertical size of the display window, measured in pixels.
5682 *
5683 * Must be even for interlaced modes.
5684 */
5685 # define TV_YSIZE_MASK 0x00000fff
5686 # define TV_YSIZE_SHIFT 0
5687
5688 #define TV_FILTER_CTL_1 _MMIO(0x68080)
5689 /*
5690 * Enables automatic scaling calculation.
5691 *
5692 * If set, the rest of the registers are ignored, and the calculated values can
5693 * be read back from the register.
5694 */
5695 # define TV_AUTO_SCALE (1 << 31)
5696 /*
5697 * Disables the vertical filter.
5698 *
5699 * This is required on modes more than 1024 pixels wide */
5700 # define TV_V_FILTER_BYPASS (1 << 29)
5701 /* Enables adaptive vertical filtering */
5702 # define TV_VADAPT (1 << 28)
5703 # define TV_VADAPT_MODE_MASK (3 << 26)
5704 /* Selects the least adaptive vertical filtering mode */
5705 # define TV_VADAPT_MODE_LEAST (0 << 26)
5706 /* Selects the moderately adaptive vertical filtering mode */
5707 # define TV_VADAPT_MODE_MODERATE (1 << 26)
5708 /* Selects the most adaptive vertical filtering mode */
5709 # define TV_VADAPT_MODE_MOST (3 << 26)
5710 /*
5711 * Sets the horizontal scaling factor.
5712 *
5713 * This should be the fractional part of the horizontal scaling factor divided
5714 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
5715 *
5716 * (src width - 1) / ((oversample * dest width) - 1)
5717 */
5718 # define TV_HSCALE_FRAC_MASK 0x00003fff
5719 # define TV_HSCALE_FRAC_SHIFT 0
5720
5721 #define TV_FILTER_CTL_2 _MMIO(0x68084)
5722 /*
5723 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
5724 *
5725 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
5726 */
5727 # define TV_VSCALE_INT_MASK 0x00038000
5728 # define TV_VSCALE_INT_SHIFT 15
5729 /*
5730 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
5731 *
5732 * \sa TV_VSCALE_INT_MASK
5733 */
5734 # define TV_VSCALE_FRAC_MASK 0x00007fff
5735 # define TV_VSCALE_FRAC_SHIFT 0
5736
5737 #define TV_FILTER_CTL_3 _MMIO(0x68088)
5738 /*
5739 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
5740 *
5741 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
5742 *
5743 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
5744 */
5745 # define TV_VSCALE_IP_INT_MASK 0x00038000
5746 # define TV_VSCALE_IP_INT_SHIFT 15
5747 /*
5748 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
5749 *
5750 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
5751 *
5752 * \sa TV_VSCALE_IP_INT_MASK
5753 */
5754 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff
5755 # define TV_VSCALE_IP_FRAC_SHIFT 0
5756
5757 #define TV_CC_CONTROL _MMIO(0x68090)
5758 # define TV_CC_ENABLE (1 << 31)
5759 /*
5760 * Specifies which field to send the CC data in.
5761 *
5762 * CC data is usually sent in field 0.
5763 */
5764 # define TV_CC_FID_MASK (1 << 27)
5765 # define TV_CC_FID_SHIFT 27
5766 /* Sets the horizontal position of the CC data. Usually 135. */
5767 # define TV_CC_HOFF_MASK 0x03ff0000
5768 # define TV_CC_HOFF_SHIFT 16
5769 /* Sets the vertical position of the CC data. Usually 21 */
5770 # define TV_CC_LINE_MASK 0x0000003f
5771 # define TV_CC_LINE_SHIFT 0
5772
5773 #define TV_CC_DATA _MMIO(0x68094)
5774 # define TV_CC_RDY (1 << 31)
5775 /* Second word of CC data to be transmitted. */
5776 # define TV_CC_DATA_2_MASK 0x007f0000
5777 # define TV_CC_DATA_2_SHIFT 16
5778 /* First word of CC data to be transmitted. */
5779 # define TV_CC_DATA_1_MASK 0x0000007f
5780 # define TV_CC_DATA_1_SHIFT 0
5781
5782 #define TV_H_LUMA(i) _MMIO(0x68100 + (i) * 4) /* 60 registers */
5783 #define TV_H_CHROMA(i) _MMIO(0x68200 + (i) * 4) /* 60 registers */
5784 #define TV_V_LUMA(i) _MMIO(0x68300 + (i) * 4) /* 43 registers */
5785 #define TV_V_CHROMA(i) _MMIO(0x68400 + (i) * 4) /* 43 registers */
5786
5787 /* Display Port */
5788 #define DP_A _MMIO(0x64000) /* eDP */
5789 #define DP_B _MMIO(0x64100)
5790 #define DP_C _MMIO(0x64200)
5791 #define DP_D _MMIO(0x64300)
5792
5793 #define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100)
5794 #define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200)
5795 #define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300)
5796
5797 #define DP_PORT_EN (1 << 31)
5798 #define DP_PIPE_SEL_SHIFT 30
5799 #define DP_PIPE_SEL_MASK (1 << 30)
5800 #define DP_PIPE_SEL(pipe) ((pipe) << 30)
5801 #define DP_PIPE_SEL_SHIFT_IVB 29
5802 #define DP_PIPE_SEL_MASK_IVB (3 << 29)
5803 #define DP_PIPE_SEL_IVB(pipe) ((pipe) << 29)
5804 #define DP_PIPE_SEL_SHIFT_CHV 16
5805 #define DP_PIPE_SEL_MASK_CHV (3 << 16)
5806 #define DP_PIPE_SEL_CHV(pipe) ((pipe) << 16)
5807
5808 /* Link training mode - select a suitable mode for each stage */
5809 #define DP_LINK_TRAIN_PAT_1 (0 << 28)
5810 #define DP_LINK_TRAIN_PAT_2 (1 << 28)
5811 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
5812 #define DP_LINK_TRAIN_OFF (3 << 28)
5813 #define DP_LINK_TRAIN_MASK (3 << 28)
5814 #define DP_LINK_TRAIN_SHIFT 28
5815
5816 /* CPT Link training mode */
5817 #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
5818 #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8)
5819 #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8)
5820 #define DP_LINK_TRAIN_OFF_CPT (3 << 8)
5821 #define DP_LINK_TRAIN_MASK_CPT (7 << 8)
5822 #define DP_LINK_TRAIN_SHIFT_CPT 8
5823
5824 /* Signal voltages. These are mostly controlled by the other end */
5825 #define DP_VOLTAGE_0_4 (0 << 25)
5826 #define DP_VOLTAGE_0_6 (1 << 25)
5827 #define DP_VOLTAGE_0_8 (2 << 25)
5828 #define DP_VOLTAGE_1_2 (3 << 25)
5829 #define DP_VOLTAGE_MASK (7 << 25)
5830 #define DP_VOLTAGE_SHIFT 25
5831
5832 /* Signal pre-emphasis levels, like voltages, the other end tells us what
5833 * they want
5834 */
5835 #define DP_PRE_EMPHASIS_0 (0 << 22)
5836 #define DP_PRE_EMPHASIS_3_5 (1 << 22)
5837 #define DP_PRE_EMPHASIS_6 (2 << 22)
5838 #define DP_PRE_EMPHASIS_9_5 (3 << 22)
5839 #define DP_PRE_EMPHASIS_MASK (7 << 22)
5840 #define DP_PRE_EMPHASIS_SHIFT 22
5841
5842 /* How many wires to use. I guess 3 was too hard */
5843 #define DP_PORT_WIDTH(width) (((width) - 1) << 19)
5844 #define DP_PORT_WIDTH_MASK (7 << 19)
5845 #define DP_PORT_WIDTH_SHIFT 19
5846
5847 /* Mystic DPCD version 1.1 special mode */
5848 #define DP_ENHANCED_FRAMING (1 << 18)
5849
5850 /* eDP */
5851 #define DP_PLL_FREQ_270MHZ (0 << 16)
5852 #define DP_PLL_FREQ_162MHZ (1 << 16)
5853 #define DP_PLL_FREQ_MASK (3 << 16)
5854
5855 /* locked once port is enabled */
5856 #define DP_PORT_REVERSAL (1 << 15)
5857
5858 /* eDP */
5859 #define DP_PLL_ENABLE (1 << 14)
5860
5861 /* sends the clock on lane 15 of the PEG for debug */
5862 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
5863
5864 #define DP_SCRAMBLING_DISABLE (1 << 12)
5865 #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
5866
5867 /* limit RGB values to avoid confusing TVs */
5868 #define DP_COLOR_RANGE_16_235 (1 << 8)
5869
5870 /* Turn on the audio link */
5871 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
5872
5873 /* vs and hs sync polarity */
5874 #define DP_SYNC_VS_HIGH (1 << 4)
5875 #define DP_SYNC_HS_HIGH (1 << 3)
5876
5877 /* A fantasy */
5878 #define DP_DETECTED (1 << 2)
5879
5880 /* The aux channel provides a way to talk to the
5881 * signal sink for DDC etc. Max packet size supported
5882 * is 20 bytes in each direction, hence the 5 fixed
5883 * data registers
5884 */
5885 #define _DPA_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64010)
5886 #define _DPA_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64014)
5887
5888 #define _DPB_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64110)
5889 #define _DPB_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64114)
5890
5891 #define DP_AUX_CH_CTL(aux_ch) _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
5892 #define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
5893
5894 #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
5895 #define DP_AUX_CH_CTL_DONE (1 << 30)
5896 #define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
5897 #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
5898 #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
5899 #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
5900 #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
5901 #define DP_AUX_CH_CTL_TIME_OUT_MAX (3 << 26) /* Varies per platform */
5902 #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
5903 #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
5904 #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
5905 #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
5906 #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
5907 #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
5908 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
5909 #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
5910 #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
5911 #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
5912 #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
5913 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
5914 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
5915 #define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL (1 << 14)
5916 #define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL (1 << 13)
5917 #define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL (1 << 12)
5918 #define DP_AUX_CH_CTL_TBT_IO (1 << 11)
5919 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5)
5920 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
5921 #define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1)
5922
5923 /*
5924 * Computing GMCH M and N values for the Display Port link
5925 *
5926 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
5927 *
5928 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
5929 *
5930 * The GMCH value is used internally
5931 *
5932 * bytes_per_pixel is the number of bytes coming out of the plane,
5933 * which is after the LUTs, so we want the bytes for our color format.
5934 * For our current usage, this is always 3, one byte for R, G and B.
5935 */
5936 #define _PIPEA_DATA_M_G4X 0x70050
5937 #define _PIPEB_DATA_M_G4X 0x71050
5938
5939 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
5940 #define TU_SIZE(x) (((x) - 1) << 25) /* default size 64 */
5941 #define TU_SIZE_SHIFT 25
5942 #define TU_SIZE_MASK (0x3f << 25)
5943
5944 #define DATA_LINK_M_N_MASK (0xffffff)
5945 #define DATA_LINK_N_MAX (0x800000)
5946
5947 #define _PIPEA_DATA_N_G4X 0x70054
5948 #define _PIPEB_DATA_N_G4X 0x71054
5949 #define PIPE_GMCH_DATA_N_MASK (0xffffff)
5950
5951 /*
5952 * Computing Link M and N values for the Display Port link
5953 *
5954 * Link M / N = pixel_clock / ls_clk
5955 *
5956 * (the DP spec calls pixel_clock the 'strm_clk')
5957 *
5958 * The Link value is transmitted in the Main Stream
5959 * Attributes and VB-ID.
5960 */
5961
5962 #define _PIPEA_LINK_M_G4X 0x70060
5963 #define _PIPEB_LINK_M_G4X 0x71060
5964 #define PIPEA_DP_LINK_M_MASK (0xffffff)
5965
5966 #define _PIPEA_LINK_N_G4X 0x70064
5967 #define _PIPEB_LINK_N_G4X 0x71064
5968 #define PIPEA_DP_LINK_N_MASK (0xffffff)
5969
5970 #define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
5971 #define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
5972 #define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
5973 #define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
5974
5975 /* Display & cursor control */
5976
5977 /* Pipe A */
5978 #define _PIPEADSL 0x70000
5979 #define DSL_LINEMASK_GEN2 0x00000fff
5980 #define DSL_LINEMASK_GEN3 0x00001fff
5981 #define _PIPEACONF 0x70008
5982 #define PIPECONF_ENABLE (1 << 31)
5983 #define PIPECONF_DISABLE 0
5984 #define PIPECONF_DOUBLE_WIDE (1 << 30)
5985 #define I965_PIPECONF_ACTIVE (1 << 30)
5986 #define PIPECONF_DSI_PLL_LOCKED (1 << 29) /* vlv & pipe A only */
5987 #define PIPECONF_FRAME_START_DELAY_MASK (3 << 27) /* pre-hsw */
5988 #define PIPECONF_FRAME_START_DELAY(x) ((x) << 27) /* pre-hsw: 0-3 */
5989 #define PIPECONF_SINGLE_WIDE 0
5990 #define PIPECONF_PIPE_UNLOCKED 0
5991 #define PIPECONF_PIPE_LOCKED (1 << 25)
5992 #define PIPECONF_FORCE_BORDER (1 << 25)
5993 #define PIPECONF_GAMMA_MODE_MASK_I9XX (1 << 24) /* gmch */
5994 #define PIPECONF_GAMMA_MODE_MASK_ILK (3 << 24) /* ilk-ivb */
5995 #define PIPECONF_GAMMA_MODE_8BIT (0 << 24) /* gmch,ilk-ivb */
5996 #define PIPECONF_GAMMA_MODE_10BIT (1 << 24) /* gmch,ilk-ivb */
5997 #define PIPECONF_GAMMA_MODE_12BIT (2 << 24) /* ilk-ivb */
5998 #define PIPECONF_GAMMA_MODE_SPLIT (3 << 24) /* ivb */
5999 #define PIPECONF_GAMMA_MODE(x) ((x) << 24) /* pass in GAMMA_MODE_MODE_* */
6000 #define PIPECONF_GAMMA_MODE_SHIFT 24
6001 #define PIPECONF_INTERLACE_MASK (7 << 21)
6002 #define PIPECONF_INTERLACE_MASK_HSW (3 << 21)
6003 /* Note that pre-gen3 does not support interlaced display directly. Panel
6004 * fitting must be disabled on pre-ilk for interlaced. */
6005 #define PIPECONF_PROGRESSIVE (0 << 21)
6006 #define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */
6007 #define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */
6008 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
6009 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */
6010 /* Ironlake and later have a complete new set of values for interlaced. PFIT
6011 * means panel fitter required, PF means progressive fetch, DBL means power
6012 * saving pixel doubling. */
6013 #define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21)
6014 #define PIPECONF_INTERLACED_ILK (3 << 21)
6015 #define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */
6016 #define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */
6017 #define PIPECONF_INTERLACE_MODE_MASK (7 << 21)
6018 #define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20)
6019 #define PIPECONF_CXSR_DOWNCLOCK (1 << 16)
6020 #define PIPECONF_EDP_RR_MODE_SWITCH_VLV (1 << 14)
6021 #define PIPECONF_COLOR_RANGE_SELECT (1 << 13)
6022 #define PIPECONF_OUTPUT_COLORSPACE_MASK (3 << 11) /* ilk-ivb */
6023 #define PIPECONF_OUTPUT_COLORSPACE_RGB (0 << 11) /* ilk-ivb */
6024 #define PIPECONF_OUTPUT_COLORSPACE_YUV601 (1 << 11) /* ilk-ivb */
6025 #define PIPECONF_OUTPUT_COLORSPACE_YUV709 (2 << 11) /* ilk-ivb */
6026 #define PIPECONF_OUTPUT_COLORSPACE_YUV_HSW (1 << 11) /* hsw only */
6027 #define PIPECONF_BPC_MASK (0x7 << 5)
6028 #define PIPECONF_8BPC (0 << 5)
6029 #define PIPECONF_10BPC (1 << 5)
6030 #define PIPECONF_6BPC (2 << 5)
6031 #define PIPECONF_12BPC (3 << 5)
6032 #define PIPECONF_DITHER_EN (1 << 4)
6033 #define PIPECONF_DITHER_TYPE_MASK (0x0000000c)
6034 #define PIPECONF_DITHER_TYPE_SP (0 << 2)
6035 #define PIPECONF_DITHER_TYPE_ST1 (1 << 2)
6036 #define PIPECONF_DITHER_TYPE_ST2 (2 << 2)
6037 #define PIPECONF_DITHER_TYPE_TEMP (3 << 2)
6038 #define _PIPEASTAT 0x70024
6039 #define PIPE_FIFO_UNDERRUN_STATUS (1UL << 31)
6040 #define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL << 30)
6041 #define PIPE_CRC_ERROR_ENABLE (1UL << 29)
6042 #define PIPE_CRC_DONE_ENABLE (1UL << 28)
6043 #define PERF_COUNTER2_INTERRUPT_EN (1UL << 27)
6044 #define PIPE_GMBUS_EVENT_ENABLE (1UL << 27)
6045 #define PLANE_FLIP_DONE_INT_EN_VLV (1UL << 26)
6046 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL << 26)
6047 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL << 25)
6048 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL << 24)
6049 #define PIPE_DPST_EVENT_ENABLE (1UL << 23)
6050 #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL << 22)
6051 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL << 22)
6052 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL << 21)
6053 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL << 20)
6054 #define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL << 19)
6055 #define PERF_COUNTER_INTERRUPT_EN (1UL << 19)
6056 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL << 18) /* pre-965 */
6057 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL << 18) /* 965 or later */
6058 #define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL << 17)
6059 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL << 17)
6060 #define PIPEA_HBLANK_INT_EN_VLV (1UL << 16)
6061 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL << 16)
6062 #define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL << 15)
6063 #define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL << 14)
6064 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL << 13)
6065 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL << 12)
6066 #define PERF_COUNTER2_INTERRUPT_STATUS (1UL << 11)
6067 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL << 11)
6068 #define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL << 10)
6069 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL << 10)
6070 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL << 9)
6071 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL << 8)
6072 #define PIPE_DPST_EVENT_STATUS (1UL << 7)
6073 #define PIPE_A_PSR_STATUS_VLV (1UL << 6)
6074 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL << 6)
6075 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL << 5)
6076 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL << 4)
6077 #define PIPE_B_PSR_STATUS_VLV (1UL << 3)
6078 #define PERF_COUNTER_INTERRUPT_STATUS (1UL << 3)
6079 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL << 2) /* pre-965 */
6080 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL << 2) /* 965 or later */
6081 #define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL << 1)
6082 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL << 1)
6083 #define PIPE_HBLANK_INT_STATUS (1UL << 0)
6084 #define PIPE_OVERLAY_UPDATED_STATUS (1UL << 0)
6085
6086 #define PIPESTAT_INT_ENABLE_MASK 0x7fff0000
6087 #define PIPESTAT_INT_STATUS_MASK 0x0000ffff
6088
6089 #define PIPE_A_OFFSET 0x70000
6090 #define PIPE_B_OFFSET 0x71000
6091 #define PIPE_C_OFFSET 0x72000
6092 #define PIPE_D_OFFSET 0x73000
6093 #define CHV_PIPE_C_OFFSET 0x74000
6094 /*
6095 * There's actually no pipe EDP. Some pipe registers have
6096 * simply shifted from the pipe to the transcoder, while
6097 * keeping their original offset. Thus we need PIPE_EDP_OFFSET
6098 * to access such registers in transcoder EDP.
6099 */
6100 #define PIPE_EDP_OFFSET 0x7f000
6101
6102 /* ICL DSI 0 and 1 */
6103 #define PIPE_DSI0_OFFSET 0x7b000
6104 #define PIPE_DSI1_OFFSET 0x7b800
6105
6106 #define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF)
6107 #define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL)
6108 #define PIPEFRAME(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH)
6109 #define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL)
6110 #define PIPESTAT(pipe) _MMIO_PIPE2(pipe, _PIPEASTAT)
6111
6112 #define _PIPEAGCMAX 0x70010
6113 #define _PIPEBGCMAX 0x71010
6114 #define PIPEGCMAX(pipe, i) _MMIO_PIPE2(pipe, _PIPEAGCMAX + (i) * 4)
6115
6116 #define _PIPE_MISC_A 0x70030
6117 #define _PIPE_MISC_B 0x71030
6118 #define PIPEMISC_YUV420_ENABLE (1 << 27) /* glk+ */
6119 #define PIPEMISC_YUV420_MODE_FULL_BLEND (1 << 26) /* glk+ */
6120 #define PIPEMISC_HDR_MODE_PRECISION (1 << 23) /* icl+ */
6121 #define PIPEMISC_OUTPUT_COLORSPACE_YUV (1 << 11)
6122 #define PIPEMISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */
6123 #define PIPEMISC_DITHER_BPC_MASK (7 << 5)
6124 #define PIPEMISC_DITHER_8_BPC (0 << 5)
6125 #define PIPEMISC_DITHER_10_BPC (1 << 5)
6126 #define PIPEMISC_DITHER_6_BPC (2 << 5)
6127 #define PIPEMISC_DITHER_12_BPC (3 << 5)
6128 #define PIPEMISC_DITHER_ENABLE (1 << 4)
6129 #define PIPEMISC_DITHER_TYPE_MASK (3 << 2)
6130 #define PIPEMISC_DITHER_TYPE_SP (0 << 2)
6131 #define PIPEMISC(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC_A)
6132
6133 /* Skylake+ pipe bottom (background) color */
6134 #define _SKL_BOTTOM_COLOR_A 0x70034
6135 #define SKL_BOTTOM_COLOR_GAMMA_ENABLE (1 << 31)
6136 #define SKL_BOTTOM_COLOR_CSC_ENABLE (1 << 30)
6137 #define SKL_BOTTOM_COLOR(pipe) _MMIO_PIPE2(pipe, _SKL_BOTTOM_COLOR_A)
6138
6139 #define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028)
6140 #define PIPEB_LINE_COMPARE_INT_EN (1 << 29)
6141 #define PIPEB_HLINE_INT_EN (1 << 28)
6142 #define PIPEB_VBLANK_INT_EN (1 << 27)
6143 #define SPRITED_FLIP_DONE_INT_EN (1 << 26)
6144 #define SPRITEC_FLIP_DONE_INT_EN (1 << 25)
6145 #define PLANEB_FLIP_DONE_INT_EN (1 << 24)
6146 #define PIPE_PSR_INT_EN (1 << 22)
6147 #define PIPEA_LINE_COMPARE_INT_EN (1 << 21)
6148 #define PIPEA_HLINE_INT_EN (1 << 20)
6149 #define PIPEA_VBLANK_INT_EN (1 << 19)
6150 #define SPRITEB_FLIP_DONE_INT_EN (1 << 18)
6151 #define SPRITEA_FLIP_DONE_INT_EN (1 << 17)
6152 #define PLANEA_FLIPDONE_INT_EN (1 << 16)
6153 #define PIPEC_LINE_COMPARE_INT_EN (1 << 13)
6154 #define PIPEC_HLINE_INT_EN (1 << 12)
6155 #define PIPEC_VBLANK_INT_EN (1 << 11)
6156 #define SPRITEF_FLIPDONE_INT_EN (1 << 10)
6157 #define SPRITEE_FLIPDONE_INT_EN (1 << 9)
6158 #define PLANEC_FLIPDONE_INT_EN (1 << 8)
6159
6160 #define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
6161 #define SPRITEF_INVALID_GTT_INT_EN (1 << 27)
6162 #define SPRITEE_INVALID_GTT_INT_EN (1 << 26)
6163 #define PLANEC_INVALID_GTT_INT_EN (1 << 25)
6164 #define CURSORC_INVALID_GTT_INT_EN (1 << 24)
6165 #define CURSORB_INVALID_GTT_INT_EN (1 << 23)
6166 #define CURSORA_INVALID_GTT_INT_EN (1 << 22)
6167 #define SPRITED_INVALID_GTT_INT_EN (1 << 21)
6168 #define SPRITEC_INVALID_GTT_INT_EN (1 << 20)
6169 #define PLANEB_INVALID_GTT_INT_EN (1 << 19)
6170 #define SPRITEB_INVALID_GTT_INT_EN (1 << 18)
6171 #define SPRITEA_INVALID_GTT_INT_EN (1 << 17)
6172 #define PLANEA_INVALID_GTT_INT_EN (1 << 16)
6173 #define DPINVGTT_EN_MASK 0xff0000
6174 #define DPINVGTT_EN_MASK_CHV 0xfff0000
6175 #define SPRITEF_INVALID_GTT_STATUS (1 << 11)
6176 #define SPRITEE_INVALID_GTT_STATUS (1 << 10)
6177 #define PLANEC_INVALID_GTT_STATUS (1 << 9)
6178 #define CURSORC_INVALID_GTT_STATUS (1 << 8)
6179 #define CURSORB_INVALID_GTT_STATUS (1 << 7)
6180 #define CURSORA_INVALID_GTT_STATUS (1 << 6)
6181 #define SPRITED_INVALID_GTT_STATUS (1 << 5)
6182 #define SPRITEC_INVALID_GTT_STATUS (1 << 4)
6183 #define PLANEB_INVALID_GTT_STATUS (1 << 3)
6184 #define SPRITEB_INVALID_GTT_STATUS (1 << 2)
6185 #define SPRITEA_INVALID_GTT_STATUS (1 << 1)
6186 #define PLANEA_INVALID_GTT_STATUS (1 << 0)
6187 #define DPINVGTT_STATUS_MASK 0xff
6188 #define DPINVGTT_STATUS_MASK_CHV 0xfff
6189
6190 #define DSPARB _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030)
6191 #define DSPARB_CSTART_MASK (0x7f << 7)
6192 #define DSPARB_CSTART_SHIFT 7
6193 #define DSPARB_BSTART_MASK (0x7f)
6194 #define DSPARB_BSTART_SHIFT 0
6195 #define DSPARB_BEND_SHIFT 9 /* on 855 */
6196 #define DSPARB_AEND_SHIFT 0
6197 #define DSPARB_SPRITEA_SHIFT_VLV 0
6198 #define DSPARB_SPRITEA_MASK_VLV (0xff << 0)
6199 #define DSPARB_SPRITEB_SHIFT_VLV 8
6200 #define DSPARB_SPRITEB_MASK_VLV (0xff << 8)
6201 #define DSPARB_SPRITEC_SHIFT_VLV 16
6202 #define DSPARB_SPRITEC_MASK_VLV (0xff << 16)
6203 #define DSPARB_SPRITED_SHIFT_VLV 24
6204 #define DSPARB_SPRITED_MASK_VLV (0xff << 24)
6205 #define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
6206 #define DSPARB_SPRITEA_HI_SHIFT_VLV 0
6207 #define DSPARB_SPRITEA_HI_MASK_VLV (0x1 << 0)
6208 #define DSPARB_SPRITEB_HI_SHIFT_VLV 4
6209 #define DSPARB_SPRITEB_HI_MASK_VLV (0x1 << 4)
6210 #define DSPARB_SPRITEC_HI_SHIFT_VLV 8
6211 #define DSPARB_SPRITEC_HI_MASK_VLV (0x1 << 8)
6212 #define DSPARB_SPRITED_HI_SHIFT_VLV 12
6213 #define DSPARB_SPRITED_HI_MASK_VLV (0x1 << 12)
6214 #define DSPARB_SPRITEE_HI_SHIFT_VLV 16
6215 #define DSPARB_SPRITEE_HI_MASK_VLV (0x1 << 16)
6216 #define DSPARB_SPRITEF_HI_SHIFT_VLV 20
6217 #define DSPARB_SPRITEF_HI_MASK_VLV (0x1 << 20)
6218 #define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */
6219 #define DSPARB_SPRITEE_SHIFT_VLV 0
6220 #define DSPARB_SPRITEE_MASK_VLV (0xff << 0)
6221 #define DSPARB_SPRITEF_SHIFT_VLV 8
6222 #define DSPARB_SPRITEF_MASK_VLV (0xff << 8)
6223
6224 /* pnv/gen4/g4x/vlv/chv */
6225 #define DSPFW1 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034)
6226 #define DSPFW_SR_SHIFT 23
6227 #define DSPFW_SR_MASK (0x1ff << 23)
6228 #define DSPFW_CURSORB_SHIFT 16
6229 #define DSPFW_CURSORB_MASK (0x3f << 16)
6230 #define DSPFW_PLANEB_SHIFT 8
6231 #define DSPFW_PLANEB_MASK (0x7f << 8)
6232 #define DSPFW_PLANEB_MASK_VLV (0xff << 8) /* vlv/chv */
6233 #define DSPFW_PLANEA_SHIFT 0
6234 #define DSPFW_PLANEA_MASK (0x7f << 0)
6235 #define DSPFW_PLANEA_MASK_VLV (0xff << 0) /* vlv/chv */
6236 #define DSPFW2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038)
6237 #define DSPFW_FBC_SR_EN (1 << 31) /* g4x */
6238 #define DSPFW_FBC_SR_SHIFT 28
6239 #define DSPFW_FBC_SR_MASK (0x7 << 28) /* g4x */
6240 #define DSPFW_FBC_HPLL_SR_SHIFT 24
6241 #define DSPFW_FBC_HPLL_SR_MASK (0xf << 24) /* g4x */
6242 #define DSPFW_SPRITEB_SHIFT (16)
6243 #define DSPFW_SPRITEB_MASK (0x7f << 16) /* g4x */
6244 #define DSPFW_SPRITEB_MASK_VLV (0xff << 16) /* vlv/chv */
6245 #define DSPFW_CURSORA_SHIFT 8
6246 #define DSPFW_CURSORA_MASK (0x3f << 8)
6247 #define DSPFW_PLANEC_OLD_SHIFT 0
6248 #define DSPFW_PLANEC_OLD_MASK (0x7f << 0) /* pre-gen4 sprite C */
6249 #define DSPFW_SPRITEA_SHIFT 0
6250 #define DSPFW_SPRITEA_MASK (0x7f << 0) /* g4x */
6251 #define DSPFW_SPRITEA_MASK_VLV (0xff << 0) /* vlv/chv */
6252 #define DSPFW3 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c)
6253 #define DSPFW_HPLL_SR_EN (1 << 31)
6254 #define PINEVIEW_SELF_REFRESH_EN (1 << 30)
6255 #define DSPFW_CURSOR_SR_SHIFT 24
6256 #define DSPFW_CURSOR_SR_MASK (0x3f << 24)
6257 #define DSPFW_HPLL_CURSOR_SHIFT 16
6258 #define DSPFW_HPLL_CURSOR_MASK (0x3f << 16)
6259 #define DSPFW_HPLL_SR_SHIFT 0
6260 #define DSPFW_HPLL_SR_MASK (0x1ff << 0)
6261
6262 /* vlv/chv */
6263 #define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070)
6264 #define DSPFW_SPRITEB_WM1_SHIFT 16
6265 #define DSPFW_SPRITEB_WM1_MASK (0xff << 16)
6266 #define DSPFW_CURSORA_WM1_SHIFT 8
6267 #define DSPFW_CURSORA_WM1_MASK (0x3f << 8)
6268 #define DSPFW_SPRITEA_WM1_SHIFT 0
6269 #define DSPFW_SPRITEA_WM1_MASK (0xff << 0)
6270 #define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074)
6271 #define DSPFW_PLANEB_WM1_SHIFT 24
6272 #define DSPFW_PLANEB_WM1_MASK (0xff << 24)
6273 #define DSPFW_PLANEA_WM1_SHIFT 16
6274 #define DSPFW_PLANEA_WM1_MASK (0xff << 16)
6275 #define DSPFW_CURSORB_WM1_SHIFT 8
6276 #define DSPFW_CURSORB_WM1_MASK (0x3f << 8)
6277 #define DSPFW_CURSOR_SR_WM1_SHIFT 0
6278 #define DSPFW_CURSOR_SR_WM1_MASK (0x3f << 0)
6279 #define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078)
6280 #define DSPFW_SR_WM1_SHIFT 0
6281 #define DSPFW_SR_WM1_MASK (0x1ff << 0)
6282 #define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c)
6283 #define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
6284 #define DSPFW_SPRITED_WM1_SHIFT 24
6285 #define DSPFW_SPRITED_WM1_MASK (0xff << 24)
6286 #define DSPFW_SPRITED_SHIFT 16
6287 #define DSPFW_SPRITED_MASK_VLV (0xff << 16)
6288 #define DSPFW_SPRITEC_WM1_SHIFT 8
6289 #define DSPFW_SPRITEC_WM1_MASK (0xff << 8)
6290 #define DSPFW_SPRITEC_SHIFT 0
6291 #define DSPFW_SPRITEC_MASK_VLV (0xff << 0)
6292 #define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8)
6293 #define DSPFW_SPRITEF_WM1_SHIFT 24
6294 #define DSPFW_SPRITEF_WM1_MASK (0xff << 24)
6295 #define DSPFW_SPRITEF_SHIFT 16
6296 #define DSPFW_SPRITEF_MASK_VLV (0xff << 16)
6297 #define DSPFW_SPRITEE_WM1_SHIFT 8
6298 #define DSPFW_SPRITEE_WM1_MASK (0xff << 8)
6299 #define DSPFW_SPRITEE_SHIFT 0
6300 #define DSPFW_SPRITEE_MASK_VLV (0xff << 0)
6301 #define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
6302 #define DSPFW_PLANEC_WM1_SHIFT 24
6303 #define DSPFW_PLANEC_WM1_MASK (0xff << 24)
6304 #define DSPFW_PLANEC_SHIFT 16
6305 #define DSPFW_PLANEC_MASK_VLV (0xff << 16)
6306 #define DSPFW_CURSORC_WM1_SHIFT 8
6307 #define DSPFW_CURSORC_WM1_MASK (0x3f << 16)
6308 #define DSPFW_CURSORC_SHIFT 0
6309 #define DSPFW_CURSORC_MASK (0x3f << 0)
6310
6311 /* vlv/chv high order bits */
6312 #define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064)
6313 #define DSPFW_SR_HI_SHIFT 24
6314 #define DSPFW_SR_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */
6315 #define DSPFW_SPRITEF_HI_SHIFT 23
6316 #define DSPFW_SPRITEF_HI_MASK (1 << 23)
6317 #define DSPFW_SPRITEE_HI_SHIFT 22
6318 #define DSPFW_SPRITEE_HI_MASK (1 << 22)
6319 #define DSPFW_PLANEC_HI_SHIFT 21
6320 #define DSPFW_PLANEC_HI_MASK (1 << 21)
6321 #define DSPFW_SPRITED_HI_SHIFT 20
6322 #define DSPFW_SPRITED_HI_MASK (1 << 20)
6323 #define DSPFW_SPRITEC_HI_SHIFT 16
6324 #define DSPFW_SPRITEC_HI_MASK (1 << 16)
6325 #define DSPFW_PLANEB_HI_SHIFT 12
6326 #define DSPFW_PLANEB_HI_MASK (1 << 12)
6327 #define DSPFW_SPRITEB_HI_SHIFT 8
6328 #define DSPFW_SPRITEB_HI_MASK (1 << 8)
6329 #define DSPFW_SPRITEA_HI_SHIFT 4
6330 #define DSPFW_SPRITEA_HI_MASK (1 << 4)
6331 #define DSPFW_PLANEA_HI_SHIFT 0
6332 #define DSPFW_PLANEA_HI_MASK (1 << 0)
6333 #define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068)
6334 #define DSPFW_SR_WM1_HI_SHIFT 24
6335 #define DSPFW_SR_WM1_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */
6336 #define DSPFW_SPRITEF_WM1_HI_SHIFT 23
6337 #define DSPFW_SPRITEF_WM1_HI_MASK (1 << 23)
6338 #define DSPFW_SPRITEE_WM1_HI_SHIFT 22
6339 #define DSPFW_SPRITEE_WM1_HI_MASK (1 << 22)
6340 #define DSPFW_PLANEC_WM1_HI_SHIFT 21
6341 #define DSPFW_PLANEC_WM1_HI_MASK (1 << 21)
6342 #define DSPFW_SPRITED_WM1_HI_SHIFT 20
6343 #define DSPFW_SPRITED_WM1_HI_MASK (1 << 20)
6344 #define DSPFW_SPRITEC_WM1_HI_SHIFT 16
6345 #define DSPFW_SPRITEC_WM1_HI_MASK (1 << 16)
6346 #define DSPFW_PLANEB_WM1_HI_SHIFT 12
6347 #define DSPFW_PLANEB_WM1_HI_MASK (1 << 12)
6348 #define DSPFW_SPRITEB_WM1_HI_SHIFT 8
6349 #define DSPFW_SPRITEB_WM1_HI_MASK (1 << 8)
6350 #define DSPFW_SPRITEA_WM1_HI_SHIFT 4
6351 #define DSPFW_SPRITEA_WM1_HI_MASK (1 << 4)
6352 #define DSPFW_PLANEA_WM1_HI_SHIFT 0
6353 #define DSPFW_PLANEA_WM1_HI_MASK (1 << 0)
6354
6355 /* drain latency register values*/
6356 #define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
6357 #define DDL_CURSOR_SHIFT 24
6358 #define DDL_SPRITE_SHIFT(sprite) (8 + 8 * (sprite))
6359 #define DDL_PLANE_SHIFT 0
6360 #define DDL_PRECISION_HIGH (1 << 7)
6361 #define DDL_PRECISION_LOW (0 << 7)
6362 #define DRAIN_LATENCY_MASK 0x7f
6363
6364 #define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400)
6365 #define CBR_PND_DEADLINE_DISABLE (1 << 31)
6366 #define CBR_PWM_CLOCK_MUX_SELECT (1 << 30)
6367
6368 #define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450)
6369 #define CBR_DPLLBMD_PIPE(pipe) (1 << (7 + (pipe) * 11)) /* pipes B and C */
6370
6371 /* FIFO watermark sizes etc */
6372 #define G4X_FIFO_LINE_SIZE 64
6373 #define I915_FIFO_LINE_SIZE 64
6374 #define I830_FIFO_LINE_SIZE 32
6375
6376 #define VALLEYVIEW_FIFO_SIZE 255
6377 #define G4X_FIFO_SIZE 127
6378 #define I965_FIFO_SIZE 512
6379 #define I945_FIFO_SIZE 127
6380 #define I915_FIFO_SIZE 95
6381 #define I855GM_FIFO_SIZE 127 /* In cachelines */
6382 #define I830_FIFO_SIZE 95
6383
6384 #define VALLEYVIEW_MAX_WM 0xff
6385 #define G4X_MAX_WM 0x3f
6386 #define I915_MAX_WM 0x3f
6387
6388 #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */
6389 #define PINEVIEW_FIFO_LINE_SIZE 64
6390 #define PINEVIEW_MAX_WM 0x1ff
6391 #define PINEVIEW_DFT_WM 0x3f
6392 #define PINEVIEW_DFT_HPLLOFF_WM 0
6393 #define PINEVIEW_GUARD_WM 10
6394 #define PINEVIEW_CURSOR_FIFO 64
6395 #define PINEVIEW_CURSOR_MAX_WM 0x3f
6396 #define PINEVIEW_CURSOR_DFT_WM 0
6397 #define PINEVIEW_CURSOR_GUARD_WM 5
6398
6399 #define VALLEYVIEW_CURSOR_MAX_WM 64
6400 #define I965_CURSOR_FIFO 64
6401 #define I965_CURSOR_MAX_WM 32
6402 #define I965_CURSOR_DFT_WM 8
6403
6404 /* Watermark register definitions for SKL */
6405 #define _CUR_WM_A_0 0x70140
6406 #define _CUR_WM_B_0 0x71140
6407 #define _PLANE_WM_1_A_0 0x70240
6408 #define _PLANE_WM_1_B_0 0x71240
6409 #define _PLANE_WM_2_A_0 0x70340
6410 #define _PLANE_WM_2_B_0 0x71340
6411 #define _PLANE_WM_TRANS_1_A_0 0x70268
6412 #define _PLANE_WM_TRANS_1_B_0 0x71268
6413 #define _PLANE_WM_TRANS_2_A_0 0x70368
6414 #define _PLANE_WM_TRANS_2_B_0 0x71368
6415 #define _CUR_WM_TRANS_A_0 0x70168
6416 #define _CUR_WM_TRANS_B_0 0x71168
6417 #define PLANE_WM_EN (1 << 31)
6418 #define PLANE_WM_IGNORE_LINES (1 << 30)
6419 #define PLANE_WM_LINES_SHIFT 14
6420 #define PLANE_WM_LINES_MASK 0x1f
6421 #define PLANE_WM_BLOCKS_MASK 0x7ff /* skl+: 10 bits, icl+ 11 bits */
6422
6423 #define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
6424 #define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level)))
6425 #define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A_0, _CUR_WM_TRANS_B_0)
6426
6427 #define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0)
6428 #define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
6429 #define _PLANE_WM_BASE(pipe, plane) \
6430 _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
6431 #define PLANE_WM(pipe, plane, level) \
6432 _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
6433 #define _PLANE_WM_TRANS_1(pipe) \
6434 _PIPE(pipe, _PLANE_WM_TRANS_1_A_0, _PLANE_WM_TRANS_1_B_0)
6435 #define _PLANE_WM_TRANS_2(pipe) \
6436 _PIPE(pipe, _PLANE_WM_TRANS_2_A_0, _PLANE_WM_TRANS_2_B_0)
6437 #define PLANE_WM_TRANS(pipe, plane) \
6438 _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
6439
6440 /* define the Watermark register on Ironlake */
6441 #define _WM0_PIPEA_ILK 0x45100
6442 #define _WM0_PIPEB_ILK 0x45104
6443 #define _WM0_PIPEC_IVB 0x45200
6444 #define WM0_PIPE_ILK(pipe) _MMIO_PIPE3((pipe), _WM0_PIPEA_ILK, \
6445 _WM0_PIPEB_ILK, _WM0_PIPEC_IVB)
6446 #define WM0_PIPE_PLANE_MASK (0xffff << 16)
6447 #define WM0_PIPE_PLANE_SHIFT 16
6448 #define WM0_PIPE_SPRITE_MASK (0xff << 8)
6449 #define WM0_PIPE_SPRITE_SHIFT 8
6450 #define WM0_PIPE_CURSOR_MASK (0xff)
6451 #define WM1_LP_ILK _MMIO(0x45108)
6452 #define WM1_LP_SR_EN (1 << 31)
6453 #define WM1_LP_LATENCY_SHIFT 24
6454 #define WM1_LP_LATENCY_MASK (0x7f << 24)
6455 #define WM1_LP_FBC_MASK (0xf << 20)
6456 #define WM1_LP_FBC_SHIFT 20
6457 #define WM1_LP_FBC_SHIFT_BDW 19
6458 #define WM1_LP_SR_MASK (0x7ff << 8)
6459 #define WM1_LP_SR_SHIFT 8
6460 #define WM1_LP_CURSOR_MASK (0xff)
6461 #define WM2_LP_ILK _MMIO(0x4510c)
6462 #define WM2_LP_EN (1 << 31)
6463 #define WM3_LP_ILK _MMIO(0x45110)
6464 #define WM3_LP_EN (1 << 31)
6465 #define WM1S_LP_ILK _MMIO(0x45120)
6466 #define WM2S_LP_IVB _MMIO(0x45124)
6467 #define WM3S_LP_IVB _MMIO(0x45128)
6468 #define WM1S_LP_EN (1 << 31)
6469
6470 #define HSW_WM_LP_VAL(lat, fbc, pri, cur) \
6471 (WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \
6472 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur))
6473
6474 /* Memory latency timer register */
6475 #define MLTR_ILK _MMIO(0x11222)
6476 #define MLTR_WM1_SHIFT 0
6477 #define MLTR_WM2_SHIFT 8
6478 /* the unit of memory self-refresh latency time is 0.5us */
6479 #define ILK_SRLT_MASK 0x3f
6480
6481
6482 /* the address where we get all kinds of latency value */
6483 #define SSKPD _MMIO(0x5d10)
6484 #define SSKPD_WM_MASK 0x3f
6485 #define SSKPD_WM0_SHIFT 0
6486 #define SSKPD_WM1_SHIFT 8
6487 #define SSKPD_WM2_SHIFT 16
6488 #define SSKPD_WM3_SHIFT 24
6489
6490 /*
6491 * The two pipe frame counter registers are not synchronized, so
6492 * reading a stable value is somewhat tricky. The following code
6493 * should work:
6494 *
6495 * do {
6496 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
6497 * PIPE_FRAME_HIGH_SHIFT;
6498 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
6499 * PIPE_FRAME_LOW_SHIFT);
6500 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
6501 * PIPE_FRAME_HIGH_SHIFT);
6502 * } while (high1 != high2);
6503 * frame = (high1 << 8) | low1;
6504 */
6505 #define _PIPEAFRAMEHIGH 0x70040
6506 #define PIPE_FRAME_HIGH_MASK 0x0000ffff
6507 #define PIPE_FRAME_HIGH_SHIFT 0
6508 #define _PIPEAFRAMEPIXEL 0x70044
6509 #define PIPE_FRAME_LOW_MASK 0xff000000
6510 #define PIPE_FRAME_LOW_SHIFT 24
6511 #define PIPE_PIXEL_MASK 0x00ffffff
6512 #define PIPE_PIXEL_SHIFT 0
6513 /* GM45+ just has to be different */
6514 #define _PIPEA_FRMCOUNT_G4X 0x70040
6515 #define _PIPEA_FLIPCOUNT_G4X 0x70044
6516 #define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FRMCOUNT_G4X)
6517 #define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X)
6518
6519 /* Cursor A & B regs */
6520 #define _CURACNTR 0x70080
6521 /* Old style CUR*CNTR flags (desktop 8xx) */
6522 #define CURSOR_ENABLE 0x80000000
6523 #define CURSOR_GAMMA_ENABLE 0x40000000
6524 #define CURSOR_STRIDE_SHIFT 28
6525 #define CURSOR_STRIDE(x) ((ffs(x) - 9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */
6526 #define CURSOR_FORMAT_SHIFT 24
6527 #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
6528 #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
6529 #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
6530 #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
6531 #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
6532 #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
6533 /* New style CUR*CNTR flags */
6534 #define MCURSOR_MODE 0x27
6535 #define MCURSOR_MODE_DISABLE 0x00
6536 #define MCURSOR_MODE_128_32B_AX 0x02
6537 #define MCURSOR_MODE_256_32B_AX 0x03
6538 #define MCURSOR_MODE_64_32B_AX 0x07
6539 #define MCURSOR_MODE_128_ARGB_AX ((1 << 5) | MCURSOR_MODE_128_32B_AX)
6540 #define MCURSOR_MODE_256_ARGB_AX ((1 << 5) | MCURSOR_MODE_256_32B_AX)
6541 #define MCURSOR_MODE_64_ARGB_AX ((1 << 5) | MCURSOR_MODE_64_32B_AX)
6542 #define MCURSOR_PIPE_SELECT_MASK (0x3 << 28)
6543 #define MCURSOR_PIPE_SELECT_SHIFT 28
6544 #define MCURSOR_PIPE_SELECT(pipe) ((pipe) << 28)
6545 #define MCURSOR_GAMMA_ENABLE (1 << 26)
6546 #define MCURSOR_PIPE_CSC_ENABLE (1 << 24) /* ilk+ */
6547 #define MCURSOR_ROTATE_180 (1 << 15)
6548 #define MCURSOR_TRICKLE_FEED_DISABLE (1 << 14)
6549 #define _CURABASE 0x70084
6550 #define _CURAPOS 0x70088
6551 #define CURSOR_POS_MASK 0x007FF
6552 #define CURSOR_POS_SIGN 0x8000
6553 #define CURSOR_X_SHIFT 0
6554 #define CURSOR_Y_SHIFT 16
6555 #define CURSIZE _MMIO(0x700a0) /* 845/865 */
6556 #define _CUR_FBC_CTL_A 0x700a0 /* ivb+ */
6557 #define CUR_FBC_CTL_EN (1 << 31)
6558 #define _CURASURFLIVE 0x700ac /* g4x+ */
6559 #define _CURBCNTR 0x700c0
6560 #define _CURBBASE 0x700c4
6561 #define _CURBPOS 0x700c8
6562
6563 #define _CURBCNTR_IVB 0x71080
6564 #define _CURBBASE_IVB 0x71084
6565 #define _CURBPOS_IVB 0x71088
6566
6567 #define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR)
6568 #define CURBASE(pipe) _CURSOR2(pipe, _CURABASE)
6569 #define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS)
6570 #define CUR_FBC_CTL(pipe) _CURSOR2(pipe, _CUR_FBC_CTL_A)
6571 #define CURSURFLIVE(pipe) _CURSOR2(pipe, _CURASURFLIVE)
6572
6573 #define CURSOR_A_OFFSET 0x70080
6574 #define CURSOR_B_OFFSET 0x700c0
6575 #define CHV_CURSOR_C_OFFSET 0x700e0
6576 #define IVB_CURSOR_B_OFFSET 0x71080
6577 #define IVB_CURSOR_C_OFFSET 0x72080
6578 #define TGL_CURSOR_D_OFFSET 0x73080
6579
6580 /* Display A control */
6581 #define _DSPACNTR 0x70180
6582 #define DISPLAY_PLANE_ENABLE (1 << 31)
6583 #define DISPLAY_PLANE_DISABLE 0
6584 #define DISPPLANE_GAMMA_ENABLE (1 << 30)
6585 #define DISPPLANE_GAMMA_DISABLE 0
6586 #define DISPPLANE_PIXFORMAT_MASK (0xf << 26)
6587 #define DISPPLANE_YUV422 (0x0 << 26)
6588 #define DISPPLANE_8BPP (0x2 << 26)
6589 #define DISPPLANE_BGRA555 (0x3 << 26)
6590 #define DISPPLANE_BGRX555 (0x4 << 26)
6591 #define DISPPLANE_BGRX565 (0x5 << 26)
6592 #define DISPPLANE_BGRX888 (0x6 << 26)
6593 #define DISPPLANE_BGRA888 (0x7 << 26)
6594 #define DISPPLANE_RGBX101010 (0x8 << 26)
6595 #define DISPPLANE_RGBA101010 (0x9 << 26)
6596 #define DISPPLANE_BGRX101010 (0xa << 26)
6597 #define DISPPLANE_BGRA101010 (0xb << 26)
6598 #define DISPPLANE_RGBX161616 (0xc << 26)
6599 #define DISPPLANE_RGBX888 (0xe << 26)
6600 #define DISPPLANE_RGBA888 (0xf << 26)
6601 #define DISPPLANE_STEREO_ENABLE (1 << 25)
6602 #define DISPPLANE_STEREO_DISABLE 0
6603 #define DISPPLANE_PIPE_CSC_ENABLE (1 << 24) /* ilk+ */
6604 #define DISPPLANE_SEL_PIPE_SHIFT 24
6605 #define DISPPLANE_SEL_PIPE_MASK (3 << DISPPLANE_SEL_PIPE_SHIFT)
6606 #define DISPPLANE_SEL_PIPE(pipe) ((pipe) << DISPPLANE_SEL_PIPE_SHIFT)
6607 #define DISPPLANE_SRC_KEY_ENABLE (1 << 22)
6608 #define DISPPLANE_SRC_KEY_DISABLE 0
6609 #define DISPPLANE_LINE_DOUBLE (1 << 20)
6610 #define DISPPLANE_NO_LINE_DOUBLE 0
6611 #define DISPPLANE_STEREO_POLARITY_FIRST 0
6612 #define DISPPLANE_STEREO_POLARITY_SECOND (1 << 18)
6613 #define DISPPLANE_ALPHA_PREMULTIPLY (1 << 16) /* CHV pipe B */
6614 #define DISPPLANE_ROTATE_180 (1 << 15)
6615 #define DISPPLANE_TRICKLE_FEED_DISABLE (1 << 14) /* Ironlake */
6616 #define DISPPLANE_TILED (1 << 10)
6617 #define DISPPLANE_MIRROR (1 << 8) /* CHV pipe B */
6618 #define _DSPAADDR 0x70184
6619 #define _DSPASTRIDE 0x70188
6620 #define _DSPAPOS 0x7018C /* reserved */
6621 #define _DSPASIZE 0x70190
6622 #define _DSPASURF 0x7019C /* 965+ only */
6623 #define _DSPATILEOFF 0x701A4 /* 965+ only */
6624 #define _DSPAOFFSET 0x701A4 /* HSW */
6625 #define _DSPASURFLIVE 0x701AC
6626 #define _DSPAGAMC 0x701E0
6627
6628 #define DSPCNTR(plane) _MMIO_PIPE2(plane, _DSPACNTR)
6629 #define DSPADDR(plane) _MMIO_PIPE2(plane, _DSPAADDR)
6630 #define DSPSTRIDE(plane) _MMIO_PIPE2(plane, _DSPASTRIDE)
6631 #define DSPPOS(plane) _MMIO_PIPE2(plane, _DSPAPOS)
6632 #define DSPSIZE(plane) _MMIO_PIPE2(plane, _DSPASIZE)
6633 #define DSPSURF(plane) _MMIO_PIPE2(plane, _DSPASURF)
6634 #define DSPTILEOFF(plane) _MMIO_PIPE2(plane, _DSPATILEOFF)
6635 #define DSPLINOFF(plane) DSPADDR(plane)
6636 #define DSPOFFSET(plane) _MMIO_PIPE2(plane, _DSPAOFFSET)
6637 #define DSPSURFLIVE(plane) _MMIO_PIPE2(plane, _DSPASURFLIVE)
6638 #define DSPGAMC(plane, i) _MMIO(_PIPE2(plane, _DSPAGAMC) + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */
6639
6640 /* CHV pipe B blender and primary plane */
6641 #define _CHV_BLEND_A 0x60a00
6642 #define CHV_BLEND_LEGACY (0 << 30)
6643 #define CHV_BLEND_ANDROID (1 << 30)
6644 #define CHV_BLEND_MPO (2 << 30)
6645 #define CHV_BLEND_MASK (3 << 30)
6646 #define _CHV_CANVAS_A 0x60a04
6647 #define _PRIMPOS_A 0x60a08
6648 #define _PRIMSIZE_A 0x60a0c
6649 #define _PRIMCNSTALPHA_A 0x60a10
6650 #define PRIM_CONST_ALPHA_ENABLE (1 << 31)
6651
6652 #define CHV_BLEND(pipe) _MMIO_TRANS2(pipe, _CHV_BLEND_A)
6653 #define CHV_CANVAS(pipe) _MMIO_TRANS2(pipe, _CHV_CANVAS_A)
6654 #define PRIMPOS(plane) _MMIO_TRANS2(plane, _PRIMPOS_A)
6655 #define PRIMSIZE(plane) _MMIO_TRANS2(plane, _PRIMSIZE_A)
6656 #define PRIMCNSTALPHA(plane) _MMIO_TRANS2(plane, _PRIMCNSTALPHA_A)
6657
6658 /* Display/Sprite base address macros */
6659 #define DISP_BASEADDR_MASK (0xfffff000)
6660 #define I915_LO_DISPBASE(val) ((val) & ~DISP_BASEADDR_MASK)
6661 #define I915_HI_DISPBASE(val) ((val) & DISP_BASEADDR_MASK)
6662
6663 /*
6664 * VBIOS flags
6665 * gen2:
6666 * [00:06] alm,mgm
6667 * [10:16] all
6668 * [30:32] alm,mgm
6669 * gen3+:
6670 * [00:0f] all
6671 * [10:1f] all
6672 * [30:32] all
6673 */
6674 #define SWF0(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4)
6675 #define SWF1(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4)
6676 #define SWF3(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4)
6677 #define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4)
6678
6679 /* Pipe B */
6680 #define _PIPEBDSL (DISPLAY_MMIO_BASE(dev_priv) + 0x71000)
6681 #define _PIPEBCONF (DISPLAY_MMIO_BASE(dev_priv) + 0x71008)
6682 #define _PIPEBSTAT (DISPLAY_MMIO_BASE(dev_priv) + 0x71024)
6683 #define _PIPEBFRAMEHIGH 0x71040
6684 #define _PIPEBFRAMEPIXEL 0x71044
6685 #define _PIPEB_FRMCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71040)
6686 #define _PIPEB_FLIPCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71044)
6687
6688
6689 /* Display B control */
6690 #define _DSPBCNTR (DISPLAY_MMIO_BASE(dev_priv) + 0x71180)
6691 #define DISPPLANE_ALPHA_TRANS_ENABLE (1 << 15)
6692 #define DISPPLANE_ALPHA_TRANS_DISABLE 0
6693 #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
6694 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
6695 #define _DSPBADDR (DISPLAY_MMIO_BASE(dev_priv) + 0x71184)
6696 #define _DSPBSTRIDE (DISPLAY_MMIO_BASE(dev_priv) + 0x71188)
6697 #define _DSPBPOS (DISPLAY_MMIO_BASE(dev_priv) + 0x7118C)
6698 #define _DSPBSIZE (DISPLAY_MMIO_BASE(dev_priv) + 0x71190)
6699 #define _DSPBSURF (DISPLAY_MMIO_BASE(dev_priv) + 0x7119C)
6700 #define _DSPBTILEOFF (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
6701 #define _DSPBOFFSET (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
6702 #define _DSPBSURFLIVE (DISPLAY_MMIO_BASE(dev_priv) + 0x711AC)
6703
6704 /* ICL DSI 0 and 1 */
6705 #define _PIPEDSI0CONF 0x7b008
6706 #define _PIPEDSI1CONF 0x7b808
6707
6708 /* Sprite A control */
6709 #define _DVSACNTR 0x72180
6710 #define DVS_ENABLE (1 << 31)
6711 #define DVS_GAMMA_ENABLE (1 << 30)
6712 #define DVS_YUV_RANGE_CORRECTION_DISABLE (1 << 27)
6713 #define DVS_PIXFORMAT_MASK (3 << 25)
6714 #define DVS_FORMAT_YUV422 (0 << 25)
6715 #define DVS_FORMAT_RGBX101010 (1 << 25)
6716 #define DVS_FORMAT_RGBX888 (2 << 25)
6717 #define DVS_FORMAT_RGBX161616 (3 << 25)
6718 #define DVS_PIPE_CSC_ENABLE (1 << 24)
6719 #define DVS_SOURCE_KEY (1 << 22)
6720 #define DVS_RGB_ORDER_XBGR (1 << 20)
6721 #define DVS_YUV_FORMAT_BT709 (1 << 18)
6722 #define DVS_YUV_BYTE_ORDER_MASK (3 << 16)
6723 #define DVS_YUV_ORDER_YUYV (0 << 16)
6724 #define DVS_YUV_ORDER_UYVY (1 << 16)
6725 #define DVS_YUV_ORDER_YVYU (2 << 16)
6726 #define DVS_YUV_ORDER_VYUY (3 << 16)
6727 #define DVS_ROTATE_180 (1 << 15)
6728 #define DVS_DEST_KEY (1 << 2)
6729 #define DVS_TRICKLE_FEED_DISABLE (1 << 14)
6730 #define DVS_TILED (1 << 10)
6731 #define _DVSALINOFF 0x72184
6732 #define _DVSASTRIDE 0x72188
6733 #define _DVSAPOS 0x7218c
6734 #define _DVSASIZE 0x72190
6735 #define _DVSAKEYVAL 0x72194
6736 #define _DVSAKEYMSK 0x72198
6737 #define _DVSASURF 0x7219c
6738 #define _DVSAKEYMAXVAL 0x721a0
6739 #define _DVSATILEOFF 0x721a4
6740 #define _DVSASURFLIVE 0x721ac
6741 #define _DVSAGAMC_G4X 0x721e0 /* g4x */
6742 #define _DVSASCALE 0x72204
6743 #define DVS_SCALE_ENABLE (1 << 31)
6744 #define DVS_FILTER_MASK (3 << 29)
6745 #define DVS_FILTER_MEDIUM (0 << 29)
6746 #define DVS_FILTER_ENHANCING (1 << 29)
6747 #define DVS_FILTER_SOFTENING (2 << 29)
6748 #define DVS_VERTICAL_OFFSET_HALF (1 << 28) /* must be enabled below */
6749 #define DVS_VERTICAL_OFFSET_ENABLE (1 << 27)
6750 #define _DVSAGAMC_ILK 0x72300 /* ilk/snb */
6751 #define _DVSAGAMCMAX_ILK 0x72340 /* ilk/snb */
6752
6753 #define _DVSBCNTR 0x73180
6754 #define _DVSBLINOFF 0x73184
6755 #define _DVSBSTRIDE 0x73188
6756 #define _DVSBPOS 0x7318c
6757 #define _DVSBSIZE 0x73190
6758 #define _DVSBKEYVAL 0x73194
6759 #define _DVSBKEYMSK 0x73198
6760 #define _DVSBSURF 0x7319c
6761 #define _DVSBKEYMAXVAL 0x731a0
6762 #define _DVSBTILEOFF 0x731a4
6763 #define _DVSBSURFLIVE 0x731ac
6764 #define _DVSBGAMC_G4X 0x731e0 /* g4x */
6765 #define _DVSBSCALE 0x73204
6766 #define _DVSBGAMC_ILK 0x73300 /* ilk/snb */
6767 #define _DVSBGAMCMAX_ILK 0x73340 /* ilk/snb */
6768
6769 #define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR)
6770 #define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
6771 #define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
6772 #define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS)
6773 #define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF)
6774 #define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
6775 #define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE)
6776 #define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE)
6777 #define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
6778 #define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
6779 #define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
6780 #define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
6781 #define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */
6782 #define DVSGAMC_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_ILK, _DVSBGAMC_ILK) + (i) * 4) /* 16 x u0.10 */
6783 #define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */
6784
6785 #define _SPRA_CTL 0x70280
6786 #define SPRITE_ENABLE (1 << 31)
6787 #define SPRITE_GAMMA_ENABLE (1 << 30)
6788 #define SPRITE_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
6789 #define SPRITE_PIXFORMAT_MASK (7 << 25)
6790 #define SPRITE_FORMAT_YUV422 (0 << 25)
6791 #define SPRITE_FORMAT_RGBX101010 (1 << 25)
6792 #define SPRITE_FORMAT_RGBX888 (2 << 25)
6793 #define SPRITE_FORMAT_RGBX161616 (3 << 25)
6794 #define SPRITE_FORMAT_YUV444 (4 << 25)
6795 #define SPRITE_FORMAT_XR_BGR101010 (5 << 25) /* Extended range */
6796 #define SPRITE_PIPE_CSC_ENABLE (1 << 24)
6797 #define SPRITE_SOURCE_KEY (1 << 22)
6798 #define SPRITE_RGB_ORDER_RGBX (1 << 20) /* only for 888 and 161616 */
6799 #define SPRITE_YUV_TO_RGB_CSC_DISABLE (1 << 19)
6800 #define SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709 (1 << 18) /* 0 is BT601 */
6801 #define SPRITE_YUV_BYTE_ORDER_MASK (3 << 16)
6802 #define SPRITE_YUV_ORDER_YUYV (0 << 16)
6803 #define SPRITE_YUV_ORDER_UYVY (1 << 16)
6804 #define SPRITE_YUV_ORDER_YVYU (2 << 16)
6805 #define SPRITE_YUV_ORDER_VYUY (3 << 16)
6806 #define SPRITE_ROTATE_180 (1 << 15)
6807 #define SPRITE_TRICKLE_FEED_DISABLE (1 << 14)
6808 #define SPRITE_INT_GAMMA_DISABLE (1 << 13)
6809 #define SPRITE_TILED (1 << 10)
6810 #define SPRITE_DEST_KEY (1 << 2)
6811 #define _SPRA_LINOFF 0x70284
6812 #define _SPRA_STRIDE 0x70288
6813 #define _SPRA_POS 0x7028c
6814 #define _SPRA_SIZE 0x70290
6815 #define _SPRA_KEYVAL 0x70294
6816 #define _SPRA_KEYMSK 0x70298
6817 #define _SPRA_SURF 0x7029c
6818 #define _SPRA_KEYMAX 0x702a0
6819 #define _SPRA_TILEOFF 0x702a4
6820 #define _SPRA_OFFSET 0x702a4
6821 #define _SPRA_SURFLIVE 0x702ac
6822 #define _SPRA_SCALE 0x70304
6823 #define SPRITE_SCALE_ENABLE (1 << 31)
6824 #define SPRITE_FILTER_MASK (3 << 29)
6825 #define SPRITE_FILTER_MEDIUM (0 << 29)
6826 #define SPRITE_FILTER_ENHANCING (1 << 29)
6827 #define SPRITE_FILTER_SOFTENING (2 << 29)
6828 #define SPRITE_VERTICAL_OFFSET_HALF (1 << 28) /* must be enabled below */
6829 #define SPRITE_VERTICAL_OFFSET_ENABLE (1 << 27)
6830 #define _SPRA_GAMC 0x70400
6831 #define _SPRA_GAMC16 0x70440
6832 #define _SPRA_GAMC17 0x7044c
6833
6834 #define _SPRB_CTL 0x71280
6835 #define _SPRB_LINOFF 0x71284
6836 #define _SPRB_STRIDE 0x71288
6837 #define _SPRB_POS 0x7128c
6838 #define _SPRB_SIZE 0x71290
6839 #define _SPRB_KEYVAL 0x71294
6840 #define _SPRB_KEYMSK 0x71298
6841 #define _SPRB_SURF 0x7129c
6842 #define _SPRB_KEYMAX 0x712a0
6843 #define _SPRB_TILEOFF 0x712a4
6844 #define _SPRB_OFFSET 0x712a4
6845 #define _SPRB_SURFLIVE 0x712ac
6846 #define _SPRB_SCALE 0x71304
6847 #define _SPRB_GAMC 0x71400
6848 #define _SPRB_GAMC16 0x71440
6849 #define _SPRB_GAMC17 0x7144c
6850
6851 #define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
6852 #define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
6853 #define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
6854 #define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS)
6855 #define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
6856 #define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
6857 #define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
6858 #define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
6859 #define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
6860 #define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
6861 #define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
6862 #define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
6863 #define SPRGAMC(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) + (i) * 4) /* 16 x u0.10 */
6864 #define SPRGAMC16(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC16, _SPRB_GAMC16) + (i) * 4) /* 3 x u1.10 */
6865 #define SPRGAMC17(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + (i) * 4) /* 3 x u2.10 */
6866 #define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
6867
6868 #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
6869 #define SP_ENABLE (1 << 31)
6870 #define SP_GAMMA_ENABLE (1 << 30)
6871 #define SP_PIXFORMAT_MASK (0xf << 26)
6872 #define SP_FORMAT_YUV422 (0x0 << 26)
6873 #define SP_FORMAT_8BPP (0x2 << 26)
6874 #define SP_FORMAT_BGR565 (0x5 << 26)
6875 #define SP_FORMAT_BGRX8888 (0x6 << 26)
6876 #define SP_FORMAT_BGRA8888 (0x7 << 26)
6877 #define SP_FORMAT_RGBX1010102 (0x8 << 26)
6878 #define SP_FORMAT_RGBA1010102 (0x9 << 26)
6879 #define SP_FORMAT_BGRX1010102 (0xa << 26) /* CHV pipe B */
6880 #define SP_FORMAT_BGRA1010102 (0xb << 26) /* CHV pipe B */
6881 #define SP_FORMAT_RGBX8888 (0xe << 26)
6882 #define SP_FORMAT_RGBA8888 (0xf << 26)
6883 #define SP_ALPHA_PREMULTIPLY (1 << 23) /* CHV pipe B */
6884 #define SP_SOURCE_KEY (1 << 22)
6885 #define SP_YUV_FORMAT_BT709 (1 << 18)
6886 #define SP_YUV_BYTE_ORDER_MASK (3 << 16)
6887 #define SP_YUV_ORDER_YUYV (0 << 16)
6888 #define SP_YUV_ORDER_UYVY (1 << 16)
6889 #define SP_YUV_ORDER_YVYU (2 << 16)
6890 #define SP_YUV_ORDER_VYUY (3 << 16)
6891 #define SP_ROTATE_180 (1 << 15)
6892 #define SP_TILED (1 << 10)
6893 #define SP_MIRROR (1 << 8) /* CHV pipe B */
6894 #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
6895 #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
6896 #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c)
6897 #define _SPASIZE (VLV_DISPLAY_BASE + 0x72190)
6898 #define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194)
6899 #define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198)
6900 #define _SPASURF (VLV_DISPLAY_BASE + 0x7219c)
6901 #define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0)
6902 #define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4)
6903 #define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8)
6904 #define SP_CONST_ALPHA_ENABLE (1 << 31)
6905 #define _SPACLRC0 (VLV_DISPLAY_BASE + 0x721d0)
6906 #define SP_CONTRAST(x) ((x) << 18) /* u3.6 */
6907 #define SP_BRIGHTNESS(x) ((x) & 0xff) /* s8 */
6908 #define _SPACLRC1 (VLV_DISPLAY_BASE + 0x721d4)
6909 #define SP_SH_SIN(x) (((x) & 0x7ff) << 16) /* s4.7 */
6910 #define SP_SH_COS(x) (x) /* u3.7 */
6911 #define _SPAGAMC (VLV_DISPLAY_BASE + 0x721e0)
6912
6913 #define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
6914 #define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284)
6915 #define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288)
6916 #define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c)
6917 #define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290)
6918 #define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294)
6919 #define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298)
6920 #define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c)
6921 #define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)
6922 #define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)
6923 #define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
6924 #define _SPBCLRC0 (VLV_DISPLAY_BASE + 0x722d0)
6925 #define _SPBCLRC1 (VLV_DISPLAY_BASE + 0x722d4)
6926 #define _SPBGAMC (VLV_DISPLAY_BASE + 0x722e0)
6927
6928 #define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \
6929 _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
6930 #define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \
6931 _MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b)))
6932
6933 #define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR)
6934 #define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF)
6935 #define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE)
6936 #define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS)
6937 #define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE)
6938 #define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL)
6939 #define SPKEYMSK(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK)
6940 #define SPSURF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF)
6941 #define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
6942 #define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF)
6943 #define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA)
6944 #define SPCLRC0(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0)
6945 #define SPCLRC1(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1)
6946 #define SPGAMC(pipe, plane_id, i) _MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)) * 4) /* 6 x u0.10 */
6947
6948 /*
6949 * CHV pipe B sprite CSC
6950 *
6951 * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff|
6952 * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff|
6953 * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff|
6954 */
6955 #define _MMIO_CHV_SPCSC(plane_id, reg) \
6956 _MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg))
6957
6958 #define SPCSCYGOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d900)
6959 #define SPCSCCBOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d904)
6960 #define SPCSCCROFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d908)
6961 #define SPCSC_OOFF(x) (((x) & 0x7ff) << 16) /* s11 */
6962 #define SPCSC_IOFF(x) (((x) & 0x7ff) << 0) /* s11 */
6963
6964 #define SPCSCC01(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d90c)
6965 #define SPCSCC23(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d910)
6966 #define SPCSCC45(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d914)
6967 #define SPCSCC67(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d918)
6968 #define SPCSCC8(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d91c)
6969 #define SPCSC_C1(x) (((x) & 0x7fff) << 16) /* s3.12 */
6970 #define SPCSC_C0(x) (((x) & 0x7fff) << 0) /* s3.12 */
6971
6972 #define SPCSCYGICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d920)
6973 #define SPCSCCBICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d924)
6974 #define SPCSCCRICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d928)
6975 #define SPCSC_IMAX(x) (((x) & 0x7ff) << 16) /* s11 */
6976 #define SPCSC_IMIN(x) (((x) & 0x7ff) << 0) /* s11 */
6977
6978 #define SPCSCYGOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d92c)
6979 #define SPCSCCBOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d930)
6980 #define SPCSCCROCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d934)
6981 #define SPCSC_OMAX(x) ((x) << 16) /* u10 */
6982 #define SPCSC_OMIN(x) ((x) << 0) /* u10 */
6983
6984 /* Skylake plane registers */
6985
6986 #define _PLANE_CTL_1_A 0x70180
6987 #define _PLANE_CTL_2_A 0x70280
6988 #define _PLANE_CTL_3_A 0x70380
6989 #define PLANE_CTL_ENABLE (1 << 31)
6990 #define PLANE_CTL_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-GLK */
6991 #define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
6992 /*
6993 * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition
6994 * expanded to include bit 23 as well. However, the shift-24 based values
6995 * correctly map to the same formats in ICL, as long as bit 23 is set to 0
6996 */
6997 #define PLANE_CTL_FORMAT_MASK (0xf << 24)
6998 #define PLANE_CTL_FORMAT_YUV422 (0 << 24)
6999 #define PLANE_CTL_FORMAT_NV12 (1 << 24)
7000 #define PLANE_CTL_FORMAT_XRGB_2101010 (2 << 24)
7001 #define PLANE_CTL_FORMAT_P010 (3 << 24)
7002 #define PLANE_CTL_FORMAT_XRGB_8888 (4 << 24)
7003 #define PLANE_CTL_FORMAT_P012 (5 << 24)
7004 #define PLANE_CTL_FORMAT_XRGB_16161616F (6 << 24)
7005 #define PLANE_CTL_FORMAT_P016 (7 << 24)
7006 #define PLANE_CTL_FORMAT_XYUV (8 << 24)
7007 #define PLANE_CTL_FORMAT_INDEXED (12 << 24)
7008 #define PLANE_CTL_FORMAT_RGB_565 (14 << 24)
7009 #define ICL_PLANE_CTL_FORMAT_MASK (0x1f << 23)
7010 #define PLANE_CTL_PIPE_CSC_ENABLE (1 << 23) /* Pre-GLK */
7011 #define PLANE_CTL_FORMAT_Y210 (1 << 23)
7012 #define PLANE_CTL_FORMAT_Y212 (3 << 23)
7013 #define PLANE_CTL_FORMAT_Y216 (5 << 23)
7014 #define PLANE_CTL_FORMAT_Y410 (7 << 23)
7015 #define PLANE_CTL_FORMAT_Y412 (9 << 23)
7016 #define PLANE_CTL_FORMAT_Y416 (0xb << 23)
7017 #define PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21)
7018 #define PLANE_CTL_KEY_ENABLE_SOURCE (1 << 21)
7019 #define PLANE_CTL_KEY_ENABLE_DESTINATION (2 << 21)
7020 #define PLANE_CTL_ORDER_BGRX (0 << 20)
7021 #define PLANE_CTL_ORDER_RGBX (1 << 20)
7022 #define PLANE_CTL_YUV420_Y_PLANE (1 << 19)
7023 #define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 (1 << 18)
7024 #define PLANE_CTL_YUV422_ORDER_MASK (0x3 << 16)
7025 #define PLANE_CTL_YUV422_YUYV (0 << 16)
7026 #define PLANE_CTL_YUV422_UYVY (1 << 16)
7027 #define PLANE_CTL_YUV422_YVYU (2 << 16)
7028 #define PLANE_CTL_YUV422_VYUY (3 << 16)
7029 #define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE (1 << 15)
7030 #define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14)
7031 #define PLANE_CTL_CLEAR_COLOR_DISABLE (1 << 13) /* TGL+ */
7032 #define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13) /* Pre-GLK */
7033 #define PLANE_CTL_TILED_MASK (0x7 << 10)
7034 #define PLANE_CTL_TILED_LINEAR (0 << 10)
7035 #define PLANE_CTL_TILED_X (1 << 10)
7036 #define PLANE_CTL_TILED_Y (4 << 10)
7037 #define PLANE_CTL_TILED_YF (5 << 10)
7038 #define PLANE_CTL_ASYNC_FLIP (1 << 9)
7039 #define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
7040 #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */
7041 #define PLANE_CTL_ALPHA_MASK (0x3 << 4) /* Pre-GLK */
7042 #define PLANE_CTL_ALPHA_DISABLE (0 << 4)
7043 #define PLANE_CTL_ALPHA_SW_PREMULTIPLY (2 << 4)
7044 #define PLANE_CTL_ALPHA_HW_PREMULTIPLY (3 << 4)
7045 #define PLANE_CTL_ROTATE_MASK 0x3
7046 #define PLANE_CTL_ROTATE_0 0x0
7047 #define PLANE_CTL_ROTATE_90 0x1
7048 #define PLANE_CTL_ROTATE_180 0x2
7049 #define PLANE_CTL_ROTATE_270 0x3
7050 #define _PLANE_STRIDE_1_A 0x70188
7051 #define _PLANE_STRIDE_2_A 0x70288
7052 #define _PLANE_STRIDE_3_A 0x70388
7053 #define _PLANE_POS_1_A 0x7018c
7054 #define _PLANE_POS_2_A 0x7028c
7055 #define _PLANE_POS_3_A 0x7038c
7056 #define _PLANE_SIZE_1_A 0x70190
7057 #define _PLANE_SIZE_2_A 0x70290
7058 #define _PLANE_SIZE_3_A 0x70390
7059 #define _PLANE_SURF_1_A 0x7019c
7060 #define _PLANE_SURF_2_A 0x7029c
7061 #define _PLANE_SURF_3_A 0x7039c
7062 #define _PLANE_OFFSET_1_A 0x701a4
7063 #define _PLANE_OFFSET_2_A 0x702a4
7064 #define _PLANE_OFFSET_3_A 0x703a4
7065 #define _PLANE_KEYVAL_1_A 0x70194
7066 #define _PLANE_KEYVAL_2_A 0x70294
7067 #define _PLANE_KEYMSK_1_A 0x70198
7068 #define _PLANE_KEYMSK_2_A 0x70298
7069 #define PLANE_KEYMSK_ALPHA_ENABLE (1 << 31)
7070 #define _PLANE_KEYMAX_1_A 0x701a0
7071 #define _PLANE_KEYMAX_2_A 0x702a0
7072 #define PLANE_KEYMAX_ALPHA(a) ((a) << 24)
7073 #define _PLANE_AUX_DIST_1_A 0x701c0
7074 #define _PLANE_AUX_DIST_2_A 0x702c0
7075 #define _PLANE_AUX_OFFSET_1_A 0x701c4
7076 #define _PLANE_AUX_OFFSET_2_A 0x702c4
7077 #define _PLANE_CUS_CTL_1_A 0x701c8
7078 #define _PLANE_CUS_CTL_2_A 0x702c8
7079 #define PLANE_CUS_ENABLE (1 << 31)
7080 #define PLANE_CUS_PLANE_4_RKL (0 << 30)
7081 #define PLANE_CUS_PLANE_5_RKL (1 << 30)
7082 #define PLANE_CUS_PLANE_6 (0 << 30)
7083 #define PLANE_CUS_PLANE_7 (1 << 30)
7084 #define PLANE_CUS_HPHASE_SIGN_NEGATIVE (1 << 19)
7085 #define PLANE_CUS_HPHASE_0 (0 << 16)
7086 #define PLANE_CUS_HPHASE_0_25 (1 << 16)
7087 #define PLANE_CUS_HPHASE_0_5 (2 << 16)
7088 #define PLANE_CUS_VPHASE_SIGN_NEGATIVE (1 << 15)
7089 #define PLANE_CUS_VPHASE_0 (0 << 12)
7090 #define PLANE_CUS_VPHASE_0_25 (1 << 12)
7091 #define PLANE_CUS_VPHASE_0_5 (2 << 12)
7092 #define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */
7093 #define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */
7094 #define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
7095 #define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-ICL */
7096 #define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
7097 #define PLANE_COLOR_INPUT_CSC_ENABLE (1 << 20) /* ICL+ */
7098 #define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23) /* Pre-ICL */
7099 #define PLANE_COLOR_CSC_MODE_BYPASS (0 << 17)
7100 #define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601 (1 << 17)
7101 #define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 (2 << 17)
7102 #define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 (3 << 17)
7103 #define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 (4 << 17)
7104 #define PLANE_COLOR_PLANE_GAMMA_DISABLE (1 << 13)
7105 #define PLANE_COLOR_ALPHA_MASK (0x3 << 4)
7106 #define PLANE_COLOR_ALPHA_DISABLE (0 << 4)
7107 #define PLANE_COLOR_ALPHA_SW_PREMULTIPLY (2 << 4)
7108 #define PLANE_COLOR_ALPHA_HW_PREMULTIPLY (3 << 4)
7109 #define _PLANE_BUF_CFG_1_A 0x7027c
7110 #define _PLANE_BUF_CFG_2_A 0x7037c
7111 #define _PLANE_NV12_BUF_CFG_1_A 0x70278
7112 #define _PLANE_NV12_BUF_CFG_2_A 0x70378
7113
7114 /* Input CSC Register Definitions */
7115 #define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0
7116 #define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0
7117
7118 #define _PLANE_INPUT_CSC_RY_GY_1_B 0x711E0
7119 #define _PLANE_INPUT_CSC_RY_GY_2_B 0x712E0
7120
7121 #define _PLANE_INPUT_CSC_RY_GY_1(pipe) \
7122 _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, \
7123 _PLANE_INPUT_CSC_RY_GY_1_B)
7124 #define _PLANE_INPUT_CSC_RY_GY_2(pipe) \
7125 _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \
7126 _PLANE_INPUT_CSC_RY_GY_2_B)
7127
7128 #define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \
7129 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \
7130 _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4)
7131
7132 #define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701F8
7133 #define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702F8
7134
7135 #define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711F8
7136 #define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712F8
7137
7138 #define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) \
7139 _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, \
7140 _PLANE_INPUT_CSC_PREOFF_HI_1_B)
7141 #define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) \
7142 _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, \
7143 _PLANE_INPUT_CSC_PREOFF_HI_2_B)
7144 #define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \
7145 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \
7146 _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4)
7147
7148 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_A 0x70204
7149 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_A 0x70304
7150
7151 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_B 0x71204
7152 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_B 0x71304
7153
7154 #define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) \
7155 _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, \
7156 _PLANE_INPUT_CSC_POSTOFF_HI_1_B)
7157 #define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) \
7158 _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, \
7159 _PLANE_INPUT_CSC_POSTOFF_HI_2_B)
7160 #define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) \
7161 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \
7162 _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
7163
7164 #define _PLANE_CTL_1_B 0x71180
7165 #define _PLANE_CTL_2_B 0x71280
7166 #define _PLANE_CTL_3_B 0x71380
7167 #define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)
7168 #define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
7169 #define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B)
7170 #define PLANE_CTL(pipe, plane) \
7171 _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
7172
7173 #define _PLANE_STRIDE_1_B 0x71188
7174 #define _PLANE_STRIDE_2_B 0x71288
7175 #define _PLANE_STRIDE_3_B 0x71388
7176 #define _PLANE_STRIDE_1(pipe) \
7177 _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B)
7178 #define _PLANE_STRIDE_2(pipe) \
7179 _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
7180 #define _PLANE_STRIDE_3(pipe) \
7181 _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
7182 #define PLANE_STRIDE(pipe, plane) \
7183 _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
7184
7185 #define _PLANE_POS_1_B 0x7118c
7186 #define _PLANE_POS_2_B 0x7128c
7187 #define _PLANE_POS_3_B 0x7138c
7188 #define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B)
7189 #define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)
7190 #define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B)
7191 #define PLANE_POS(pipe, plane) \
7192 _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
7193
7194 #define _PLANE_SIZE_1_B 0x71190
7195 #define _PLANE_SIZE_2_B 0x71290
7196 #define _PLANE_SIZE_3_B 0x71390
7197 #define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B)
7198 #define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
7199 #define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B)
7200 #define PLANE_SIZE(pipe, plane) \
7201 _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
7202
7203 #define _PLANE_SURF_1_B 0x7119c
7204 #define _PLANE_SURF_2_B 0x7129c
7205 #define _PLANE_SURF_3_B 0x7139c
7206 #define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B)
7207 #define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)
7208 #define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
7209 #define PLANE_SURF(pipe, plane) \
7210 _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
7211
7212 #define _PLANE_OFFSET_1_B 0x711a4
7213 #define _PLANE_OFFSET_2_B 0x712a4
7214 #define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B)
7215 #define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)
7216 #define PLANE_OFFSET(pipe, plane) \
7217 _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
7218
7219 #define _PLANE_KEYVAL_1_B 0x71194
7220 #define _PLANE_KEYVAL_2_B 0x71294
7221 #define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B)
7222 #define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)
7223 #define PLANE_KEYVAL(pipe, plane) \
7224 _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
7225
7226 #define _PLANE_KEYMSK_1_B 0x71198
7227 #define _PLANE_KEYMSK_2_B 0x71298
7228 #define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B)
7229 #define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)
7230 #define PLANE_KEYMSK(pipe, plane) \
7231 _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
7232
7233 #define _PLANE_KEYMAX_1_B 0x711a0
7234 #define _PLANE_KEYMAX_2_B 0x712a0
7235 #define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B)
7236 #define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)
7237 #define PLANE_KEYMAX(pipe, plane) \
7238 _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
7239
7240 #define _PLANE_BUF_CFG_1_B 0x7127c
7241 #define _PLANE_BUF_CFG_2_B 0x7137c
7242 #define DDB_ENTRY_MASK 0x7FF /* skl+: 10 bits, icl+ 11 bits */
7243 #define DDB_ENTRY_END_SHIFT 16
7244 #define _PLANE_BUF_CFG_1(pipe) \
7245 _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
7246 #define _PLANE_BUF_CFG_2(pipe) \
7247 _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
7248 #define PLANE_BUF_CFG(pipe, plane) \
7249 _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
7250
7251 #define _PLANE_NV12_BUF_CFG_1_B 0x71278
7252 #define _PLANE_NV12_BUF_CFG_2_B 0x71378
7253 #define _PLANE_NV12_BUF_CFG_1(pipe) \
7254 _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B)
7255 #define _PLANE_NV12_BUF_CFG_2(pipe) \
7256 _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
7257 #define PLANE_NV12_BUF_CFG(pipe, plane) \
7258 _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
7259
7260 #define _PLANE_AUX_DIST_1_B 0x711c0
7261 #define _PLANE_AUX_DIST_2_B 0x712c0
7262 #define _PLANE_AUX_DIST_1(pipe) \
7263 _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B)
7264 #define _PLANE_AUX_DIST_2(pipe) \
7265 _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B)
7266 #define PLANE_AUX_DIST(pipe, plane) \
7267 _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))
7268
7269 #define _PLANE_AUX_OFFSET_1_B 0x711c4
7270 #define _PLANE_AUX_OFFSET_2_B 0x712c4
7271 #define _PLANE_AUX_OFFSET_1(pipe) \
7272 _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B)
7273 #define _PLANE_AUX_OFFSET_2(pipe) \
7274 _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B)
7275 #define PLANE_AUX_OFFSET(pipe, plane) \
7276 _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
7277
7278 #define _PLANE_CUS_CTL_1_B 0x711c8
7279 #define _PLANE_CUS_CTL_2_B 0x712c8
7280 #define _PLANE_CUS_CTL_1(pipe) \
7281 _PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B)
7282 #define _PLANE_CUS_CTL_2(pipe) \
7283 _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B)
7284 #define PLANE_CUS_CTL(pipe, plane) \
7285 _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe))
7286
7287 #define _PLANE_COLOR_CTL_1_B 0x711CC
7288 #define _PLANE_COLOR_CTL_2_B 0x712CC
7289 #define _PLANE_COLOR_CTL_3_B 0x713CC
7290 #define _PLANE_COLOR_CTL_1(pipe) \
7291 _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B)
7292 #define _PLANE_COLOR_CTL_2(pipe) \
7293 _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B)
7294 #define PLANE_COLOR_CTL(pipe, plane) \
7295 _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe))
7296
7297 #define _SEL_FETCH_PLANE_BASE_1_A 0x70890
7298 #define _SEL_FETCH_PLANE_BASE_2_A 0x708B0
7299 #define _SEL_FETCH_PLANE_BASE_3_A 0x708D0
7300 #define _SEL_FETCH_PLANE_BASE_4_A 0x708F0
7301 #define _SEL_FETCH_PLANE_BASE_5_A 0x70920
7302 #define _SEL_FETCH_PLANE_BASE_6_A 0x70940
7303 #define _SEL_FETCH_PLANE_BASE_7_A 0x70960
7304 #define _SEL_FETCH_PLANE_BASE_CUR_A 0x70880
7305 #define _SEL_FETCH_PLANE_BASE_1_B 0x70990
7306
7307 #define _SEL_FETCH_PLANE_BASE_A(plane) _PICK(plane, \
7308 _SEL_FETCH_PLANE_BASE_1_A, \
7309 _SEL_FETCH_PLANE_BASE_2_A, \
7310 _SEL_FETCH_PLANE_BASE_3_A, \
7311 _SEL_FETCH_PLANE_BASE_4_A, \
7312 _SEL_FETCH_PLANE_BASE_5_A, \
7313 _SEL_FETCH_PLANE_BASE_6_A, \
7314 _SEL_FETCH_PLANE_BASE_7_A, \
7315 _SEL_FETCH_PLANE_BASE_CUR_A)
7316 #define _SEL_FETCH_PLANE_BASE_1(pipe) _PIPE(pipe, _SEL_FETCH_PLANE_BASE_1_A, _SEL_FETCH_PLANE_BASE_1_B)
7317 #define _SEL_FETCH_PLANE_BASE(pipe, plane) (_SEL_FETCH_PLANE_BASE_1(pipe) - \
7318 _SEL_FETCH_PLANE_BASE_1_A + \
7319 _SEL_FETCH_PLANE_BASE_A(plane))
7320
7321 #define _SEL_FETCH_PLANE_CTL_1_A 0x70890
7322 #define PLANE_SEL_FETCH_CTL(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
7323 _SEL_FETCH_PLANE_CTL_1_A - \
7324 _SEL_FETCH_PLANE_BASE_1_A)
7325 #define PLANE_SEL_FETCH_CTL_ENABLE REG_BIT(31)
7326
7327 #define _SEL_FETCH_PLANE_POS_1_A 0x70894
7328 #define PLANE_SEL_FETCH_POS(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
7329 _SEL_FETCH_PLANE_POS_1_A - \
7330 _SEL_FETCH_PLANE_BASE_1_A)
7331
7332 #define _SEL_FETCH_PLANE_SIZE_1_A 0x70898
7333 #define PLANE_SEL_FETCH_SIZE(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
7334 _SEL_FETCH_PLANE_SIZE_1_A - \
7335 _SEL_FETCH_PLANE_BASE_1_A)
7336
7337 #define _SEL_FETCH_PLANE_OFFSET_1_A 0x7089C
7338 #define PLANE_SEL_FETCH_OFFSET(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
7339 _SEL_FETCH_PLANE_OFFSET_1_A - \
7340 _SEL_FETCH_PLANE_BASE_1_A)
7341
7342 /* SKL new cursor registers */
7343 #define _CUR_BUF_CFG_A 0x7017c
7344 #define _CUR_BUF_CFG_B 0x7117c
7345 #define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
7346
7347 /* VBIOS regs */
7348 #define VGACNTRL _MMIO(0x71400)
7349 # define VGA_DISP_DISABLE (1 << 31)
7350 # define VGA_2X_MODE (1 << 30)
7351 # define VGA_PIPE_B_SELECT (1 << 29)
7352
7353 #define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400)
7354
7355 /* Ironlake */
7356
7357 #define CPU_VGACNTRL _MMIO(0x41000)
7358
7359 #define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030)
7360 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
7361 #define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */
7362 #define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */
7363 #define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2) /* pre-HSW */
7364 #define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2) /* pre-HSW */
7365 #define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2) /* pre-HSW */
7366 #define DIGITAL_PORTA_HOTPLUG_STATUS_MASK (3 << 0)
7367 #define DIGITAL_PORTA_HOTPLUG_NO_DETECT (0 << 0)
7368 #define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT (1 << 0)
7369 #define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0)
7370
7371 /* refresh rate hardware control */
7372 #define RR_HW_CTL _MMIO(0x45300)
7373 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff
7374 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
7375
7376 #define FDI_PLL_BIOS_0 _MMIO(0x46000)
7377 #define FDI_PLL_FB_CLOCK_MASK 0xff
7378 #define FDI_PLL_BIOS_1 _MMIO(0x46004)
7379 #define FDI_PLL_BIOS_2 _MMIO(0x46008)
7380 #define DISPLAY_PORT_PLL_BIOS_0 _MMIO(0x4600c)
7381 #define DISPLAY_PORT_PLL_BIOS_1 _MMIO(0x46010)
7382 #define DISPLAY_PORT_PLL_BIOS_2 _MMIO(0x46014)
7383
7384 #define PCH_3DCGDIS0 _MMIO(0x46020)
7385 # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
7386 # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
7387
7388 #define PCH_3DCGDIS1 _MMIO(0x46024)
7389 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
7390
7391 #define FDI_PLL_FREQ_CTL _MMIO(0x46030)
7392 #define FDI_PLL_FREQ_CHANGE_REQUEST (1 << 24)
7393 #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
7394 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
7395
7396
7397 #define _PIPEA_DATA_M1 0x60030
7398 #define PIPE_DATA_M1_OFFSET 0
7399 #define _PIPEA_DATA_N1 0x60034
7400 #define PIPE_DATA_N1_OFFSET 0
7401
7402 #define _PIPEA_DATA_M2 0x60038
7403 #define PIPE_DATA_M2_OFFSET 0
7404 #define _PIPEA_DATA_N2 0x6003c
7405 #define PIPE_DATA_N2_OFFSET 0
7406
7407 #define _PIPEA_LINK_M1 0x60040
7408 #define PIPE_LINK_M1_OFFSET 0
7409 #define _PIPEA_LINK_N1 0x60044
7410 #define PIPE_LINK_N1_OFFSET 0
7411
7412 #define _PIPEA_LINK_M2 0x60048
7413 #define PIPE_LINK_M2_OFFSET 0
7414 #define _PIPEA_LINK_N2 0x6004c
7415 #define PIPE_LINK_N2_OFFSET 0
7416
7417 /* PIPEB timing regs are same start from 0x61000 */
7418
7419 #define _PIPEB_DATA_M1 0x61030
7420 #define _PIPEB_DATA_N1 0x61034
7421 #define _PIPEB_DATA_M2 0x61038
7422 #define _PIPEB_DATA_N2 0x6103c
7423 #define _PIPEB_LINK_M1 0x61040
7424 #define _PIPEB_LINK_N1 0x61044
7425 #define _PIPEB_LINK_M2 0x61048
7426 #define _PIPEB_LINK_N2 0x6104c
7427
7428 #define PIPE_DATA_M1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M1)
7429 #define PIPE_DATA_N1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N1)
7430 #define PIPE_DATA_M2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M2)
7431 #define PIPE_DATA_N2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N2)
7432 #define PIPE_LINK_M1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M1)
7433 #define PIPE_LINK_N1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N1)
7434 #define PIPE_LINK_M2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M2)
7435 #define PIPE_LINK_N2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N2)
7436
7437 /* CPU panel fitter */
7438 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
7439 #define _PFA_CTL_1 0x68080
7440 #define _PFB_CTL_1 0x68880
7441 #define PF_ENABLE (1 << 31)
7442 #define PF_PIPE_SEL_MASK_IVB (3 << 29)
7443 #define PF_PIPE_SEL_IVB(pipe) ((pipe) << 29)
7444 #define PF_FILTER_MASK (3 << 23)
7445 #define PF_FILTER_PROGRAMMED (0 << 23)
7446 #define PF_FILTER_MED_3x3 (1 << 23)
7447 #define PF_FILTER_EDGE_ENHANCE (2 << 23)
7448 #define PF_FILTER_EDGE_SOFTEN (3 << 23)
7449 #define _PFA_WIN_SZ 0x68074
7450 #define _PFB_WIN_SZ 0x68874
7451 #define _PFA_WIN_POS 0x68070
7452 #define _PFB_WIN_POS 0x68870
7453 #define _PFA_VSCALE 0x68084
7454 #define _PFB_VSCALE 0x68884
7455 #define _PFA_HSCALE 0x68090
7456 #define _PFB_HSCALE 0x68890
7457
7458 #define PF_CTL(pipe) _MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
7459 #define PF_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
7460 #define PF_WIN_POS(pipe) _MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
7461 #define PF_VSCALE(pipe) _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
7462 #define PF_HSCALE(pipe) _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
7463
7464 #define _PSA_CTL 0x68180
7465 #define _PSB_CTL 0x68980
7466 #define PS_ENABLE (1 << 31)
7467 #define _PSA_WIN_SZ 0x68174
7468 #define _PSB_WIN_SZ 0x68974
7469 #define _PSA_WIN_POS 0x68170
7470 #define _PSB_WIN_POS 0x68970
7471
7472 #define PS_CTL(pipe) _MMIO_PIPE(pipe, _PSA_CTL, _PSB_CTL)
7473 #define PS_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ)
7474 #define PS_WIN_POS(pipe) _MMIO_PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS)
7475
7476 /*
7477 * Skylake scalers
7478 */
7479 #define _PS_1A_CTRL 0x68180
7480 #define _PS_2A_CTRL 0x68280
7481 #define _PS_1B_CTRL 0x68980
7482 #define _PS_2B_CTRL 0x68A80
7483 #define _PS_1C_CTRL 0x69180
7484 #define PS_SCALER_EN (1 << 31)
7485 #define SKL_PS_SCALER_MODE_MASK (3 << 28)
7486 #define SKL_PS_SCALER_MODE_DYN (0 << 28)
7487 #define SKL_PS_SCALER_MODE_HQ (1 << 28)
7488 #define SKL_PS_SCALER_MODE_NV12 (2 << 28)
7489 #define PS_SCALER_MODE_PLANAR (1 << 29)
7490 #define PS_SCALER_MODE_NORMAL (0 << 29)
7491 #define PS_PLANE_SEL_MASK (7 << 25)
7492 #define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
7493 #define PS_FILTER_MASK (3 << 23)
7494 #define PS_FILTER_MEDIUM (0 << 23)
7495 #define PS_FILTER_PROGRAMMED (1 << 23)
7496 #define PS_FILTER_EDGE_ENHANCE (2 << 23)
7497 #define PS_FILTER_BILINEAR (3 << 23)
7498 #define PS_VERT3TAP (1 << 21)
7499 #define PS_VERT_INT_INVERT_FIELD1 (0 << 20)
7500 #define PS_VERT_INT_INVERT_FIELD0 (1 << 20)
7501 #define PS_PWRUP_PROGRESS (1 << 17)
7502 #define PS_V_FILTER_BYPASS (1 << 8)
7503 #define PS_VADAPT_EN (1 << 7)
7504 #define PS_VADAPT_MODE_MASK (3 << 5)
7505 #define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5)
7506 #define PS_VADAPT_MODE_MOD_ADAPT (1 << 5)
7507 #define PS_VADAPT_MODE_MOST_ADAPT (3 << 5)
7508 #define PS_PLANE_Y_SEL_MASK (7 << 5)
7509 #define PS_PLANE_Y_SEL(plane) (((plane) + 1) << 5)
7510 #define PS_Y_VERT_FILTER_SELECT(set) ((set) << 4)
7511 #define PS_Y_HORZ_FILTER_SELECT(set) ((set) << 3)
7512 #define PS_UV_VERT_FILTER_SELECT(set) ((set) << 2)
7513 #define PS_UV_HORZ_FILTER_SELECT(set) ((set) << 1)
7514
7515 #define _PS_PWR_GATE_1A 0x68160
7516 #define _PS_PWR_GATE_2A 0x68260
7517 #define _PS_PWR_GATE_1B 0x68960
7518 #define _PS_PWR_GATE_2B 0x68A60
7519 #define _PS_PWR_GATE_1C 0x69160
7520 #define PS_PWR_GATE_DIS_OVERRIDE (1 << 31)
7521 #define PS_PWR_GATE_SETTLING_TIME_32 (0 << 3)
7522 #define PS_PWR_GATE_SETTLING_TIME_64 (1 << 3)
7523 #define PS_PWR_GATE_SETTLING_TIME_96 (2 << 3)
7524 #define PS_PWR_GATE_SETTLING_TIME_128 (3 << 3)
7525 #define PS_PWR_GATE_SLPEN_8 0
7526 #define PS_PWR_GATE_SLPEN_16 1
7527 #define PS_PWR_GATE_SLPEN_24 2
7528 #define PS_PWR_GATE_SLPEN_32 3
7529
7530 #define _PS_WIN_POS_1A 0x68170
7531 #define _PS_WIN_POS_2A 0x68270
7532 #define _PS_WIN_POS_1B 0x68970
7533 #define _PS_WIN_POS_2B 0x68A70
7534 #define _PS_WIN_POS_1C 0x69170
7535
7536 #define _PS_WIN_SZ_1A 0x68174
7537 #define _PS_WIN_SZ_2A 0x68274
7538 #define _PS_WIN_SZ_1B 0x68974
7539 #define _PS_WIN_SZ_2B 0x68A74
7540 #define _PS_WIN_SZ_1C 0x69174
7541
7542 #define _PS_VSCALE_1A 0x68184
7543 #define _PS_VSCALE_2A 0x68284
7544 #define _PS_VSCALE_1B 0x68984
7545 #define _PS_VSCALE_2B 0x68A84
7546 #define _PS_VSCALE_1C 0x69184
7547
7548 #define _PS_HSCALE_1A 0x68190
7549 #define _PS_HSCALE_2A 0x68290
7550 #define _PS_HSCALE_1B 0x68990
7551 #define _PS_HSCALE_2B 0x68A90
7552 #define _PS_HSCALE_1C 0x69190
7553
7554 #define _PS_VPHASE_1A 0x68188
7555 #define _PS_VPHASE_2A 0x68288
7556 #define _PS_VPHASE_1B 0x68988
7557 #define _PS_VPHASE_2B 0x68A88
7558 #define _PS_VPHASE_1C 0x69188
7559 #define PS_Y_PHASE(x) ((x) << 16)
7560 #define PS_UV_RGB_PHASE(x) ((x) << 0)
7561 #define PS_PHASE_MASK (0x7fff << 1) /* u2.13 */
7562 #define PS_PHASE_TRIP (1 << 0)
7563
7564 #define _PS_HPHASE_1A 0x68194
7565 #define _PS_HPHASE_2A 0x68294
7566 #define _PS_HPHASE_1B 0x68994
7567 #define _PS_HPHASE_2B 0x68A94
7568 #define _PS_HPHASE_1C 0x69194
7569
7570 #define _PS_ECC_STAT_1A 0x681D0
7571 #define _PS_ECC_STAT_2A 0x682D0
7572 #define _PS_ECC_STAT_1B 0x689D0
7573 #define _PS_ECC_STAT_2B 0x68AD0
7574 #define _PS_ECC_STAT_1C 0x691D0
7575
7576 #define _PS_COEF_SET0_INDEX_1A 0x68198
7577 #define _PS_COEF_SET0_INDEX_2A 0x68298
7578 #define _PS_COEF_SET0_INDEX_1B 0x68998
7579 #define _PS_COEF_SET0_INDEX_2B 0x68A98
7580 #define PS_COEE_INDEX_AUTO_INC (1 << 10)
7581
7582 #define _PS_COEF_SET0_DATA_1A 0x6819C
7583 #define _PS_COEF_SET0_DATA_2A 0x6829C
7584 #define _PS_COEF_SET0_DATA_1B 0x6899C
7585 #define _PS_COEF_SET0_DATA_2B 0x68A9C
7586
7587 #define _ID(id, a, b) _PICK_EVEN(id, a, b)
7588 #define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \
7589 _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \
7590 _ID(id, _PS_1B_CTRL, _PS_2B_CTRL))
7591 #define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe, \
7592 _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \
7593 _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B))
7594 #define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe, \
7595 _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \
7596 _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B))
7597 #define SKL_PS_WIN_SZ(pipe, id) _MMIO_PIPE(pipe, \
7598 _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \
7599 _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B))
7600 #define SKL_PS_VSCALE(pipe, id) _MMIO_PIPE(pipe, \
7601 _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \
7602 _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B))
7603 #define SKL_PS_HSCALE(pipe, id) _MMIO_PIPE(pipe, \
7604 _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \
7605 _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B))
7606 #define SKL_PS_VPHASE(pipe, id) _MMIO_PIPE(pipe, \
7607 _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \
7608 _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B))
7609 #define SKL_PS_HPHASE(pipe, id) _MMIO_PIPE(pipe, \
7610 _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \
7611 _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B))
7612 #define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \
7613 _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \
7614 _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
7615 #define CNL_PS_COEF_INDEX_SET(pipe, id, set) _MMIO_PIPE(pipe, \
7616 _ID(id, _PS_COEF_SET0_INDEX_1A, _PS_COEF_SET0_INDEX_2A) + (set) * 8, \
7617 _ID(id, _PS_COEF_SET0_INDEX_1B, _PS_COEF_SET0_INDEX_2B) + (set) * 8)
7618
7619 #define CNL_PS_COEF_DATA_SET(pipe, id, set) _MMIO_PIPE(pipe, \
7620 _ID(id, _PS_COEF_SET0_DATA_1A, _PS_COEF_SET0_DATA_2A) + (set) * 8, \
7621 _ID(id, _PS_COEF_SET0_DATA_1B, _PS_COEF_SET0_DATA_2B) + (set) * 8)
7622 /* legacy palette */
7623 #define _LGC_PALETTE_A 0x4a000
7624 #define _LGC_PALETTE_B 0x4a800
7625 #define LGC_PALETTE_RED_MASK REG_GENMASK(23, 16)
7626 #define LGC_PALETTE_GREEN_MASK REG_GENMASK(15, 8)
7627 #define LGC_PALETTE_BLUE_MASK REG_GENMASK(7, 0)
7628 #define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4)
7629
7630 /* ilk/snb precision palette */
7631 #define _PREC_PALETTE_A 0x4b000
7632 #define _PREC_PALETTE_B 0x4c000
7633 #define PREC_PALETTE_RED_MASK REG_GENMASK(29, 20)
7634 #define PREC_PALETTE_GREEN_MASK REG_GENMASK(19, 10)
7635 #define PREC_PALETTE_BLUE_MASK REG_GENMASK(9, 0)
7636 #define PREC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _PREC_PALETTE_A, _PREC_PALETTE_B) + (i) * 4)
7637
7638 #define _PREC_PIPEAGCMAX 0x4d000
7639 #define _PREC_PIPEBGCMAX 0x4d010
7640 #define PREC_PIPEGCMAX(pipe, i) _MMIO(_PIPE(pipe, _PIPEAGCMAX, _PIPEBGCMAX) + (i) * 4)
7641
7642 #define _GAMMA_MODE_A 0x4a480
7643 #define _GAMMA_MODE_B 0x4ac80
7644 #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
7645 #define PRE_CSC_GAMMA_ENABLE (1 << 31)
7646 #define POST_CSC_GAMMA_ENABLE (1 << 30)
7647 #define GAMMA_MODE_MODE_MASK (3 << 0)
7648 #define GAMMA_MODE_MODE_8BIT (0 << 0)
7649 #define GAMMA_MODE_MODE_10BIT (1 << 0)
7650 #define GAMMA_MODE_MODE_12BIT (2 << 0)
7651 #define GAMMA_MODE_MODE_SPLIT (3 << 0) /* ivb-bdw */
7652 #define GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED (3 << 0) /* icl + */
7653
7654 /* DMC/CSR */
7655 #define CSR_PROGRAM(i) _MMIO(0x80000 + (i) * 4)
7656 #define CSR_SSP_BASE_ADDR_GEN9 0x00002FC0
7657 #define CSR_HTP_ADDR_SKL 0x00500034
7658 #define CSR_SSP_BASE _MMIO(0x8F074)
7659 #define CSR_HTP_SKL _MMIO(0x8F004)
7660 #define CSR_LAST_WRITE _MMIO(0x8F034)
7661 #define CSR_LAST_WRITE_VALUE 0xc003b400
7662 /* MMIO address range for CSR program (0x80000 - 0x82FFF) */
7663 #define CSR_MMIO_START_RANGE 0x80000
7664 #define CSR_MMIO_END_RANGE 0x8FFFF
7665 #define SKL_CSR_DC3_DC5_COUNT _MMIO(0x80030)
7666 #define SKL_CSR_DC5_DC6_COUNT _MMIO(0x8002C)
7667 #define BXT_CSR_DC3_DC5_COUNT _MMIO(0x80038)
7668 #define TGL_DMC_DEBUG_DC5_COUNT _MMIO(0x101084)
7669 #define TGL_DMC_DEBUG_DC6_COUNT _MMIO(0x101088)
7670 #define DG1_DMC_DEBUG_DC5_COUNT _MMIO(0x134154)
7671
7672 #define DMC_DEBUG3 _MMIO(0x101090)
7673
7674 /* Display Internal Timeout Register */
7675 #define RM_TIMEOUT _MMIO(0x42060)
7676 #define MMIO_TIMEOUT_US(us) ((us) << 0)
7677
7678 /* interrupts */
7679 #define DE_MASTER_IRQ_CONTROL (1 << 31)
7680 #define DE_SPRITEB_FLIP_DONE (1 << 29)
7681 #define DE_SPRITEA_FLIP_DONE (1 << 28)
7682 #define DE_PLANEB_FLIP_DONE (1 << 27)
7683 #define DE_PLANEA_FLIP_DONE (1 << 26)
7684 #define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
7685 #define DE_PCU_EVENT (1 << 25)
7686 #define DE_GTT_FAULT (1 << 24)
7687 #define DE_POISON (1 << 23)
7688 #define DE_PERFORM_COUNTER (1 << 22)
7689 #define DE_PCH_EVENT (1 << 21)
7690 #define DE_AUX_CHANNEL_A (1 << 20)
7691 #define DE_DP_A_HOTPLUG (1 << 19)
7692 #define DE_GSE (1 << 18)
7693 #define DE_PIPEB_VBLANK (1 << 15)
7694 #define DE_PIPEB_EVEN_FIELD (1 << 14)
7695 #define DE_PIPEB_ODD_FIELD (1 << 13)
7696 #define DE_PIPEB_LINE_COMPARE (1 << 12)
7697 #define DE_PIPEB_VSYNC (1 << 11)
7698 #define DE_PIPEB_CRC_DONE (1 << 10)
7699 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
7700 #define DE_PIPEA_VBLANK (1 << 7)
7701 #define DE_PIPE_VBLANK(pipe) (1 << (7 + 8 * (pipe)))
7702 #define DE_PIPEA_EVEN_FIELD (1 << 6)
7703 #define DE_PIPEA_ODD_FIELD (1 << 5)
7704 #define DE_PIPEA_LINE_COMPARE (1 << 4)
7705 #define DE_PIPEA_VSYNC (1 << 3)
7706 #define DE_PIPEA_CRC_DONE (1 << 2)
7707 #define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8 * (pipe)))
7708 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
7709 #define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8 * (pipe)))
7710
7711 /* More Ivybridge lolz */
7712 #define DE_ERR_INT_IVB (1 << 30)
7713 #define DE_GSE_IVB (1 << 29)
7714 #define DE_PCH_EVENT_IVB (1 << 28)
7715 #define DE_DP_A_HOTPLUG_IVB (1 << 27)
7716 #define DE_AUX_CHANNEL_A_IVB (1 << 26)
7717 #define DE_EDP_PSR_INT_HSW (1 << 19)
7718 #define DE_SPRITEC_FLIP_DONE_IVB (1 << 14)
7719 #define DE_PLANEC_FLIP_DONE_IVB (1 << 13)
7720 #define DE_PIPEC_VBLANK_IVB (1 << 10)
7721 #define DE_SPRITEB_FLIP_DONE_IVB (1 << 9)
7722 #define DE_PLANEB_FLIP_DONE_IVB (1 << 8)
7723 #define DE_PIPEB_VBLANK_IVB (1 << 5)
7724 #define DE_SPRITEA_FLIP_DONE_IVB (1 << 4)
7725 #define DE_PLANEA_FLIP_DONE_IVB (1 << 3)
7726 #define DE_PLANE_FLIP_DONE_IVB(plane) (1 << (3 + 5 * (plane)))
7727 #define DE_PIPEA_VBLANK_IVB (1 << 0)
7728 #define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5))
7729
7730 #define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */
7731 #define MASTER_INTERRUPT_ENABLE (1 << 31)
7732
7733 #define DEISR _MMIO(0x44000)
7734 #define DEIMR _MMIO(0x44004)
7735 #define DEIIR _MMIO(0x44008)
7736 #define DEIER _MMIO(0x4400c)
7737
7738 #define GTISR _MMIO(0x44010)
7739 #define GTIMR _MMIO(0x44014)
7740 #define GTIIR _MMIO(0x44018)
7741 #define GTIER _MMIO(0x4401c)
7742
7743 #define GEN8_MASTER_IRQ _MMIO(0x44200)
7744 #define GEN8_MASTER_IRQ_CONTROL (1 << 31)
7745 #define GEN8_PCU_IRQ (1 << 30)
7746 #define GEN8_DE_PCH_IRQ (1 << 23)
7747 #define GEN8_DE_MISC_IRQ (1 << 22)
7748 #define GEN8_DE_PORT_IRQ (1 << 20)
7749 #define GEN8_DE_PIPE_C_IRQ (1 << 18)
7750 #define GEN8_DE_PIPE_B_IRQ (1 << 17)
7751 #define GEN8_DE_PIPE_A_IRQ (1 << 16)
7752 #define GEN8_DE_PIPE_IRQ(pipe) (1 << (16 + (pipe)))
7753 #define GEN8_GT_VECS_IRQ (1 << 6)
7754 #define GEN8_GT_GUC_IRQ (1 << 5)
7755 #define GEN8_GT_PM_IRQ (1 << 4)
7756 #define GEN8_GT_VCS1_IRQ (1 << 3) /* NB: VCS2 in bspec! */
7757 #define GEN8_GT_VCS0_IRQ (1 << 2) /* NB: VCS1 in bpsec! */
7758 #define GEN8_GT_BCS_IRQ (1 << 1)
7759 #define GEN8_GT_RCS_IRQ (1 << 0)
7760
7761 #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which)))
7762 #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which)))
7763 #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
7764 #define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which)))
7765
7766 #define GEN8_RCS_IRQ_SHIFT 0
7767 #define GEN8_BCS_IRQ_SHIFT 16
7768 #define GEN8_VCS0_IRQ_SHIFT 0 /* NB: VCS1 in bspec! */
7769 #define GEN8_VCS1_IRQ_SHIFT 16 /* NB: VCS2 in bpsec! */
7770 #define GEN8_VECS_IRQ_SHIFT 0
7771 #define GEN8_WD_IRQ_SHIFT 16
7772
7773 #define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe)))
7774 #define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe)))
7775 #define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe)))
7776 #define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe)))
7777 #define GEN8_PIPE_FIFO_UNDERRUN (1 << 31)
7778 #define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29)
7779 #define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28)
7780 #define GEN8_PIPE_CURSOR_FAULT (1 << 10)
7781 #define GEN8_PIPE_SPRITE_FAULT (1 << 9)
7782 #define GEN8_PIPE_PRIMARY_FAULT (1 << 8)
7783 #define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5)
7784 #define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4)
7785 #define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2)
7786 #define GEN8_PIPE_VSYNC (1 << 1)
7787 #define GEN8_PIPE_VBLANK (1 << 0)
7788 #define GEN9_PIPE_CURSOR_FAULT (1 << 11)
7789 #define GEN11_PIPE_PLANE7_FAULT (1 << 22)
7790 #define GEN11_PIPE_PLANE6_FAULT (1 << 21)
7791 #define GEN11_PIPE_PLANE5_FAULT (1 << 20)
7792 #define GEN9_PIPE_PLANE4_FAULT (1 << 10)
7793 #define GEN9_PIPE_PLANE3_FAULT (1 << 9)
7794 #define GEN9_PIPE_PLANE2_FAULT (1 << 8)
7795 #define GEN9_PIPE_PLANE1_FAULT (1 << 7)
7796 #define GEN9_PIPE_PLANE4_FLIP_DONE (1 << 6)
7797 #define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5)
7798 #define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4)
7799 #define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3)
7800 #define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + (p)))
7801 #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \
7802 (GEN8_PIPE_CURSOR_FAULT | \
7803 GEN8_PIPE_SPRITE_FAULT | \
7804 GEN8_PIPE_PRIMARY_FAULT)
7805 #define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \
7806 (GEN9_PIPE_CURSOR_FAULT | \
7807 GEN9_PIPE_PLANE4_FAULT | \
7808 GEN9_PIPE_PLANE3_FAULT | \
7809 GEN9_PIPE_PLANE2_FAULT | \
7810 GEN9_PIPE_PLANE1_FAULT)
7811 #define GEN11_DE_PIPE_IRQ_FAULT_ERRORS \
7812 (GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \
7813 GEN11_PIPE_PLANE7_FAULT | \
7814 GEN11_PIPE_PLANE6_FAULT | \
7815 GEN11_PIPE_PLANE5_FAULT)
7816 #define RKL_DE_PIPE_IRQ_FAULT_ERRORS \
7817 (GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \
7818 GEN11_PIPE_PLANE5_FAULT)
7819
7820 #define _HPD_PIN_DDI(hpd_pin) ((hpd_pin) - HPD_PORT_A)
7821 #define _HPD_PIN_TC(hpd_pin) ((hpd_pin) - HPD_PORT_TC1)
7822
7823 #define GEN8_DE_PORT_ISR _MMIO(0x44440)
7824 #define GEN8_DE_PORT_IMR _MMIO(0x44444)
7825 #define GEN8_DE_PORT_IIR _MMIO(0x44448)
7826 #define GEN8_DE_PORT_IER _MMIO(0x4444c)
7827 #define DSI1_NON_TE (1 << 31)
7828 #define DSI0_NON_TE (1 << 30)
7829 #define ICL_AUX_CHANNEL_E (1 << 29)
7830 #define CNL_AUX_CHANNEL_F (1 << 28)
7831 #define GEN9_AUX_CHANNEL_D (1 << 27)
7832 #define GEN9_AUX_CHANNEL_C (1 << 26)
7833 #define GEN9_AUX_CHANNEL_B (1 << 25)
7834 #define DSI1_TE (1 << 24)
7835 #define DSI0_TE (1 << 23)
7836 #define GEN8_DE_PORT_HOTPLUG(hpd_pin) REG_BIT(3 + _HPD_PIN_DDI(hpd_pin))
7837 #define BXT_DE_PORT_HOTPLUG_MASK (GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | \
7838 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | \
7839 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C))
7840 #define BDW_DE_PORT_HOTPLUG_MASK GEN8_DE_PORT_HOTPLUG(HPD_PORT_A)
7841 #define BXT_DE_PORT_GMBUS (1 << 1)
7842 #define GEN8_AUX_CHANNEL_A (1 << 0)
7843 #define TGL_DE_PORT_AUX_USBC6 (1 << 13)
7844 #define TGL_DE_PORT_AUX_USBC5 (1 << 12)
7845 #define TGL_DE_PORT_AUX_USBC4 (1 << 11)
7846 #define TGL_DE_PORT_AUX_USBC3 (1 << 10)
7847 #define TGL_DE_PORT_AUX_USBC2 (1 << 9)
7848 #define TGL_DE_PORT_AUX_USBC1 (1 << 8)
7849 #define TGL_DE_PORT_AUX_DDIC (1 << 2)
7850 #define TGL_DE_PORT_AUX_DDIB (1 << 1)
7851 #define TGL_DE_PORT_AUX_DDIA (1 << 0)
7852
7853 #define GEN8_DE_MISC_ISR _MMIO(0x44460)
7854 #define GEN8_DE_MISC_IMR _MMIO(0x44464)
7855 #define GEN8_DE_MISC_IIR _MMIO(0x44468)
7856 #define GEN8_DE_MISC_IER _MMIO(0x4446c)
7857 #define GEN8_DE_MISC_GSE (1 << 27)
7858 #define GEN8_DE_EDP_PSR (1 << 19)
7859
7860 #define GEN8_PCU_ISR _MMIO(0x444e0)
7861 #define GEN8_PCU_IMR _MMIO(0x444e4)
7862 #define GEN8_PCU_IIR _MMIO(0x444e8)
7863 #define GEN8_PCU_IER _MMIO(0x444ec)
7864
7865 #define GEN11_GU_MISC_ISR _MMIO(0x444f0)
7866 #define GEN11_GU_MISC_IMR _MMIO(0x444f4)
7867 #define GEN11_GU_MISC_IIR _MMIO(0x444f8)
7868 #define GEN11_GU_MISC_IER _MMIO(0x444fc)
7869 #define GEN11_GU_MISC_GSE (1 << 27)
7870
7871 #define GEN11_GFX_MSTR_IRQ _MMIO(0x190010)
7872 #define GEN11_MASTER_IRQ (1 << 31)
7873 #define GEN11_PCU_IRQ (1 << 30)
7874 #define GEN11_GU_MISC_IRQ (1 << 29)
7875 #define GEN11_DISPLAY_IRQ (1 << 16)
7876 #define GEN11_GT_DW_IRQ(x) (1 << (x))
7877 #define GEN11_GT_DW1_IRQ (1 << 1)
7878 #define GEN11_GT_DW0_IRQ (1 << 0)
7879
7880 #define DG1_MSTR_UNIT_INTR _MMIO(0x190008)
7881 #define DG1_MSTR_IRQ REG_BIT(31)
7882 #define DG1_MSTR_UNIT(u) REG_BIT(u)
7883
7884 #define GEN11_DISPLAY_INT_CTL _MMIO(0x44200)
7885 #define GEN11_DISPLAY_IRQ_ENABLE (1 << 31)
7886 #define GEN11_AUDIO_CODEC_IRQ (1 << 24)
7887 #define GEN11_DE_PCH_IRQ (1 << 23)
7888 #define GEN11_DE_MISC_IRQ (1 << 22)
7889 #define GEN11_DE_HPD_IRQ (1 << 21)
7890 #define GEN11_DE_PORT_IRQ (1 << 20)
7891 #define GEN11_DE_PIPE_C (1 << 18)
7892 #define GEN11_DE_PIPE_B (1 << 17)
7893 #define GEN11_DE_PIPE_A (1 << 16)
7894
7895 #define GEN11_DE_HPD_ISR _MMIO(0x44470)
7896 #define GEN11_DE_HPD_IMR _MMIO(0x44474)
7897 #define GEN11_DE_HPD_IIR _MMIO(0x44478)
7898 #define GEN11_DE_HPD_IER _MMIO(0x4447c)
7899 #define GEN11_TC_HOTPLUG(hpd_pin) REG_BIT(16 + _HPD_PIN_TC(hpd_pin))
7900 #define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC_HOTPLUG(HPD_PORT_TC6) | \
7901 GEN11_TC_HOTPLUG(HPD_PORT_TC5) | \
7902 GEN11_TC_HOTPLUG(HPD_PORT_TC4) | \
7903 GEN11_TC_HOTPLUG(HPD_PORT_TC3) | \
7904 GEN11_TC_HOTPLUG(HPD_PORT_TC2) | \
7905 GEN11_TC_HOTPLUG(HPD_PORT_TC1))
7906 #define GEN11_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin))
7907 #define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT_HOTPLUG(HPD_PORT_TC6) | \
7908 GEN11_TBT_HOTPLUG(HPD_PORT_TC5) | \
7909 GEN11_TBT_HOTPLUG(HPD_PORT_TC4) | \
7910 GEN11_TBT_HOTPLUG(HPD_PORT_TC3) | \
7911 GEN11_TBT_HOTPLUG(HPD_PORT_TC2) | \
7912 GEN11_TBT_HOTPLUG(HPD_PORT_TC1))
7913
7914 #define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030)
7915 #define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038)
7916 #define GEN11_HOTPLUG_CTL_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4))
7917 #define GEN11_HOTPLUG_CTL_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4))
7918 #define GEN11_HOTPLUG_CTL_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4))
7919 #define GEN11_HOTPLUG_CTL_NO_DETECT(hpd_pin) (0 << (_HPD_PIN_TC(hpd_pin) * 4))
7920
7921 #define GEN11_GT_INTR_DW0 _MMIO(0x190018)
7922 #define GEN11_CSME (31)
7923 #define GEN11_GUNIT (28)
7924 #define GEN11_GUC (25)
7925 #define GEN11_WDPERF (20)
7926 #define GEN11_KCR (19)
7927 #define GEN11_GTPM (16)
7928 #define GEN11_BCS (15)
7929 #define GEN11_RCS0 (0)
7930
7931 #define GEN11_GT_INTR_DW1 _MMIO(0x19001c)
7932 #define GEN11_VECS(x) (31 - (x))
7933 #define GEN11_VCS(x) (x)
7934
7935 #define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4))
7936
7937 #define GEN11_INTR_IDENTITY_REG0 _MMIO(0x190060)
7938 #define GEN11_INTR_IDENTITY_REG1 _MMIO(0x190064)
7939 #define GEN11_INTR_DATA_VALID (1 << 31)
7940 #define GEN11_INTR_ENGINE_CLASS(x) (((x) & GENMASK(18, 16)) >> 16)
7941 #define GEN11_INTR_ENGINE_INSTANCE(x) (((x) & GENMASK(25, 20)) >> 20)
7942 #define GEN11_INTR_ENGINE_INTR(x) ((x) & 0xffff)
7943 /* irq instances for OTHER_CLASS */
7944 #define OTHER_GUC_INSTANCE 0
7945 #define OTHER_GTPM_INSTANCE 1
7946
7947 #define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4))
7948
7949 #define GEN11_IIR_REG0_SELECTOR _MMIO(0x190070)
7950 #define GEN11_IIR_REG1_SELECTOR _MMIO(0x190074)
7951
7952 #define GEN11_IIR_REG_SELECTOR(x) _MMIO(0x190070 + ((x) * 4))
7953
7954 #define GEN11_RENDER_COPY_INTR_ENABLE _MMIO(0x190030)
7955 #define GEN11_VCS_VECS_INTR_ENABLE _MMIO(0x190034)
7956 #define GEN11_GUC_SG_INTR_ENABLE _MMIO(0x190038)
7957 #define GEN11_GPM_WGBOXPERF_INTR_ENABLE _MMIO(0x19003c)
7958 #define GEN11_CRYPTO_RSVD_INTR_ENABLE _MMIO(0x190040)
7959 #define GEN11_GUNIT_CSME_INTR_ENABLE _MMIO(0x190044)
7960
7961 #define GEN11_RCS0_RSVD_INTR_MASK _MMIO(0x190090)
7962 #define GEN11_BCS_RSVD_INTR_MASK _MMIO(0x1900a0)
7963 #define GEN11_VCS0_VCS1_INTR_MASK _MMIO(0x1900a8)
7964 #define GEN11_VCS2_VCS3_INTR_MASK _MMIO(0x1900ac)
7965 #define GEN11_VECS0_VECS1_INTR_MASK _MMIO(0x1900d0)
7966 #define GEN11_GUC_SG_INTR_MASK _MMIO(0x1900e8)
7967 #define GEN11_GPM_WGBOXPERF_INTR_MASK _MMIO(0x1900ec)
7968 #define GEN11_CRYPTO_RSVD_INTR_MASK _MMIO(0x1900f0)
7969 #define GEN11_GUNIT_CSME_INTR_MASK _MMIO(0x1900f4)
7970
7971 #define ENGINE1_MASK REG_GENMASK(31, 16)
7972 #define ENGINE0_MASK REG_GENMASK(15, 0)
7973
7974 #define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004)
7975 /* Required on all Ironlake and Sandybridge according to the B-Spec. */
7976 #define ILK_ELPIN_409_SELECT (1 << 25)
7977 #define ILK_DPARB_GATE (1 << 22)
7978 #define ILK_VSDPFD_FULL (1 << 21)
7979 #define FUSE_STRAP _MMIO(0x42014)
7980 #define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31)
7981 #define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30)
7982 #define ILK_DISPLAY_DEBUG_DISABLE (1 << 29)
7983 #define IVB_PIPE_C_DISABLE (1 << 28)
7984 #define ILK_HDCP_DISABLE (1 << 25)
7985 #define ILK_eDP_A_DISABLE (1 << 24)
7986 #define HSW_CDCLK_LIMIT (1 << 24)
7987 #define ILK_DESKTOP (1 << 23)
7988 #define HSW_CPU_SSC_ENABLE (1 << 21)
7989
7990 #define FUSE_STRAP3 _MMIO(0x42020)
7991 #define HSW_REF_CLK_SELECT (1 << 1)
7992
7993 #define ILK_DSPCLK_GATE_D _MMIO(0x42020)
7994 #define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28)
7995 #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9)
7996 #define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8)
7997 #define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7)
7998 #define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5)
7999
8000 #define IVB_CHICKEN3 _MMIO(0x4200c)
8001 # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5)
8002 # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2)
8003
8004 #define CHICKEN_PAR1_1 _MMIO(0x42080)
8005 #define KBL_ARB_FILL_SPARE_22 REG_BIT(22)
8006 #define DIS_RAM_BYPASS_PSR2_MAN_TRACK (1 << 16)
8007 #define SKL_DE_COMPRESSED_HASH_MODE (1 << 15)
8008 #define DPA_MASK_VBLANK_SRD (1 << 15)
8009 #define FORCE_ARB_IDLE_PLANES (1 << 14)
8010 #define SKL_EDP_PSR_FIX_RDWRAP (1 << 3)
8011 #define IGNORE_PSR2_HW_TRACKING (1 << 1)
8012
8013 #define CHICKEN_PAR2_1 _MMIO(0x42090)
8014 #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT (1 << 14)
8015
8016 #define CHICKEN_MISC_2 _MMIO(0x42084)
8017 #define CNL_COMP_PWR_DOWN (1 << 23)
8018 #define KBL_ARB_FILL_SPARE_14 REG_BIT(14)
8019 #define KBL_ARB_FILL_SPARE_13 REG_BIT(13)
8020 #define GLK_CL2_PWR_DOWN (1 << 12)
8021 #define GLK_CL1_PWR_DOWN (1 << 11)
8022 #define GLK_CL0_PWR_DOWN (1 << 10)
8023
8024 #define CHICKEN_MISC_4 _MMIO(0x4208c)
8025 #define FBC_STRIDE_OVERRIDE (1 << 13)
8026 #define FBC_STRIDE_MASK 0x1FFF
8027
8028 #define _CHICKEN_PIPESL_1_A 0x420b0
8029 #define _CHICKEN_PIPESL_1_B 0x420b4
8030 #define HSW_FBCQ_DIS (1 << 22)
8031 #define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
8032 #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
8033
8034 #define _CHICKEN_TRANS_A 0x420c0
8035 #define _CHICKEN_TRANS_B 0x420c4
8036 #define _CHICKEN_TRANS_C 0x420c8
8037 #define _CHICKEN_TRANS_EDP 0x420cc
8038 #define _CHICKEN_TRANS_D 0x420d8
8039 #define CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \
8040 [TRANSCODER_EDP] = _CHICKEN_TRANS_EDP, \
8041 [TRANSCODER_A] = _CHICKEN_TRANS_A, \
8042 [TRANSCODER_B] = _CHICKEN_TRANS_B, \
8043 [TRANSCODER_C] = _CHICKEN_TRANS_C, \
8044 [TRANSCODER_D] = _CHICKEN_TRANS_D))
8045 #define HSW_FRAME_START_DELAY_MASK (3 << 27)
8046 #define HSW_FRAME_START_DELAY(x) ((x) << 27) /* 0-3 */
8047 #define VSC_DATA_SEL_SOFTWARE_CONTROL (1 << 25) /* GLK and CNL+ */
8048 #define DDI_TRAINING_OVERRIDE_ENABLE (1 << 19)
8049 #define DDI_TRAINING_OVERRIDE_VALUE (1 << 18)
8050 #define DDIE_TRAINING_OVERRIDE_ENABLE (1 << 17) /* CHICKEN_TRANS_A only */
8051 #define DDIE_TRAINING_OVERRIDE_VALUE (1 << 16) /* CHICKEN_TRANS_A only */
8052 #define PSR2_ADD_VERTICAL_LINE_COUNT (1 << 15)
8053 #define PSR2_VSC_ENABLE_PROG_HEADER (1 << 12)
8054
8055 #define DISP_ARB_CTL _MMIO(0x45000)
8056 #define DISP_FBC_MEMORY_WAKE (1 << 31)
8057 #define DISP_TILE_SURFACE_SWIZZLING (1 << 13)
8058 #define DISP_FBC_WM_DIS (1 << 15)
8059 #define DISP_ARB_CTL2 _MMIO(0x45004)
8060 #define DISP_DATA_PARTITION_5_6 (1 << 6)
8061 #define DISP_IPC_ENABLE (1 << 3)
8062
8063 #define _DBUF_CTL_S1 0x45008
8064 #define _DBUF_CTL_S2 0x44FE8
8065 #define DBUF_CTL_S(slice) _MMIO(_PICK_EVEN(slice, _DBUF_CTL_S1, _DBUF_CTL_S2))
8066 #define DBUF_POWER_REQUEST REG_BIT(31)
8067 #define DBUF_POWER_STATE REG_BIT(30)
8068 #define DBUF_TRACKER_STATE_SERVICE_MASK REG_GENMASK(23, 19)
8069 #define DBUF_TRACKER_STATE_SERVICE(x) REG_FIELD_PREP(DBUF_TRACKER_STATE_SERVICE_MASK, x)
8070
8071 #define GEN7_MSG_CTL _MMIO(0x45010)
8072 #define WAIT_FOR_PCH_RESET_ACK (1 << 1)
8073 #define WAIT_FOR_PCH_FLR_ACK (1 << 0)
8074
8075 #define _BW_BUDDY0_CTL 0x45130
8076 #define _BW_BUDDY1_CTL 0x45140
8077 #define BW_BUDDY_CTL(x) _MMIO(_PICK_EVEN(x, \
8078 _BW_BUDDY0_CTL, \
8079 _BW_BUDDY1_CTL))
8080 #define BW_BUDDY_DISABLE REG_BIT(31)
8081 #define BW_BUDDY_TLB_REQ_TIMER_MASK REG_GENMASK(21, 16)
8082 #define BW_BUDDY_TLB_REQ_TIMER(x) REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, x)
8083
8084 #define _BW_BUDDY0_PAGE_MASK 0x45134
8085 #define _BW_BUDDY1_PAGE_MASK 0x45144
8086 #define BW_BUDDY_PAGE_MASK(x) _MMIO(_PICK_EVEN(x, \
8087 _BW_BUDDY0_PAGE_MASK, \
8088 _BW_BUDDY1_PAGE_MASK))
8089
8090 #define HSW_NDE_RSTWRN_OPT _MMIO(0x46408)
8091 #define RESET_PCH_HANDSHAKE_ENABLE (1 << 4)
8092
8093 #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
8094 #define SKL_SELECT_ALTERNATE_DC_EXIT (1 << 30)
8095 #define CNL_DELAY_PMRSP (1 << 22)
8096 #define MASK_WAKEMEM (1 << 13)
8097 #define CNL_DDI_CLOCK_REG_ACCESS_ON (1 << 7)
8098
8099 #define GEN11_CHICKEN_DCPR_2 _MMIO(0x46434)
8100 #define DCPR_MASK_MAXLATENCY_MEMUP_CLR REG_BIT(27)
8101 #define DCPR_MASK_LPMODE REG_BIT(26)
8102 #define DCPR_SEND_RESP_IMM REG_BIT(25)
8103 #define DCPR_CLEAR_MEMSTAT_DIS REG_BIT(24)
8104
8105 #define SKL_DFSM _MMIO(0x51000)
8106 #define SKL_DFSM_DISPLAY_PM_DISABLE (1 << 27)
8107 #define SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25)
8108 #define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23)
8109 #define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23)
8110 #define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
8111 #define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23)
8112 #define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23)
8113 #define ICL_DFSM_DMC_DISABLE (1 << 23)
8114 #define SKL_DFSM_PIPE_A_DISABLE (1 << 30)
8115 #define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
8116 #define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
8117 #define TGL_DFSM_PIPE_D_DISABLE (1 << 22)
8118 #define CNL_DFSM_DISPLAY_DSC_DISABLE (1 << 7)
8119
8120 #define SKL_DSSM _MMIO(0x51004)
8121 #define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz (1 << 31)
8122 #define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29)
8123 #define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29)
8124 #define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29)
8125 #define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29)
8126
8127 #define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0)
8128 #define GEN9_FFSC_PERCTX_PREEMPT_CTRL (1 << 14)
8129
8130 #define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4)
8131 #define GEN9_TSG_BARRIER_ACK_DISABLE (1 << 8)
8132 #define GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE (1 << 10)
8133
8134 #define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec)
8135 #define FF_DOP_CLOCK_GATE_DISABLE REG_BIT(1)
8136 #define GEN9_CTX_PREEMPT_REG _MMIO(0x2248)
8137 #define GEN12_DISABLE_POSH_BUSY_FF_DOP_CG REG_BIT(11)
8138
8139 #define GEN8_CS_CHICKEN1 _MMIO(0x2580)
8140 #define GEN9_PREEMPT_3D_OBJECT_LEVEL (1 << 0)
8141 #define GEN9_PREEMPT_GPGPU_LEVEL(hi, lo) (((hi) << 2) | ((lo) << 1))
8142 #define GEN9_PREEMPT_GPGPU_MID_THREAD_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 0)
8143 #define GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 1)
8144 #define GEN9_PREEMPT_GPGPU_COMMAND_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(1, 0)
8145 #define GEN9_PREEMPT_GPGPU_LEVEL_MASK GEN9_PREEMPT_GPGPU_LEVEL(1, 1)
8146
8147 /* GEN7 chicken */
8148 #define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010)
8149 #define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC (1 << 10)
8150 #define GEN9_RHWO_OPTIMIZATION_DISABLE (1 << 14)
8151
8152 #define COMMON_SLICE_CHICKEN2 _MMIO(0x7014)
8153 #define GEN9_PBE_COMPRESSED_HASH_SELECTION (1 << 13)
8154 #define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE (1 << 12)
8155 #define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1 << 8)
8156 #define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1 << 0)
8157
8158 #define GEN8_L3CNTLREG _MMIO(0x7034)
8159 #define GEN8_ERRDETBCTRL (1 << 9)
8160
8161 #define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304)
8162 #define DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN REG_BIT(12)
8163 #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC REG_BIT(11)
8164 #define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE REG_BIT(9)
8165
8166 #define HIZ_CHICKEN _MMIO(0x7018)
8167 # define CHV_HZ_8X8_MODE_IN_1X REG_BIT(15)
8168 # define DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE REG_BIT(14)
8169 # define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE REG_BIT(3)
8170
8171 #define GEN9_SLICE_COMMON_ECO_CHICKEN0 _MMIO(0x7308)
8172 #define DISABLE_PIXEL_MASK_CAMMING (1 << 14)
8173
8174 #define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
8175 #define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11)
8176
8177 #define GEN7_SARCHKMD _MMIO(0xB000)
8178 #define GEN7_DISABLE_DEMAND_PREFETCH (1 << 31)
8179 #define GEN7_DISABLE_SAMPLER_PREFETCH (1 << 30)
8180
8181 #define GEN7_L3SQCREG1 _MMIO(0xB010)
8182 #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
8183
8184 #define GEN8_L3SQCREG1 _MMIO(0xB100)
8185 /*
8186 * Note that on CHV the following has an off-by-one error wrt. to BSpec.
8187 * Using the formula in BSpec leads to a hang, while the formula here works
8188 * fine and matches the formulas for all other platforms. A BSpec change
8189 * request has been filed to clarify this.
8190 */
8191 #define L3_GENERAL_PRIO_CREDITS(x) (((x) >> 1) << 19)
8192 #define L3_HIGH_PRIO_CREDITS(x) (((x) >> 1) << 14)
8193 #define L3_PRIO_CREDITS_MASK ((0x1f << 19) | (0x1f << 14))
8194
8195 #define GEN7_L3CNTLREG1 _MMIO(0xB01C)
8196 #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C
8197 #define GEN7_L3AGDIS (1 << 19)
8198 #define GEN7_L3CNTLREG2 _MMIO(0xB020)
8199 #define GEN7_L3CNTLREG3 _MMIO(0xB024)
8200
8201 #define GEN7_L3_CHICKEN_MODE_REGISTER _MMIO(0xB030)
8202 #define GEN7_WA_L3_CHICKEN_MODE 0x20000000
8203 #define GEN10_L3_CHICKEN_MODE_REGISTER _MMIO(0xB114)
8204 #define GEN11_I2M_WRITE_DISABLE (1 << 28)
8205
8206 #define GEN7_L3SQCREG4 _MMIO(0xb034)
8207 #define L3SQ_URB_READ_CAM_MATCH_DISABLE (1 << 27)
8208
8209 #define GEN11_SCRATCH2 _MMIO(0xb140)
8210 #define GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE (1 << 19)
8211
8212 #define GEN8_L3SQCREG4 _MMIO(0xb118)
8213 #define GEN11_LQSC_CLEAN_EVICT_DISABLE (1 << 6)
8214 #define GEN8_LQSC_RO_PERF_DIS (1 << 27)
8215 #define GEN8_LQSC_FLUSH_COHERENT_LINES (1 << 21)
8216
8217 /* GEN8 chicken */
8218 #define HDC_CHICKEN0 _MMIO(0x7300)
8219 #define CNL_HDC_CHICKEN0 _MMIO(0xE5F0)
8220 #define ICL_HDC_MODE _MMIO(0xE5F4)
8221 #define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1 << 15)
8222 #define HDC_FENCE_DEST_SLM_DISABLE (1 << 14)
8223 #define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1 << 11)
8224 #define HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT (1 << 5)
8225 #define HDC_FORCE_NON_COHERENT (1 << 4)
8226 #define HDC_BARRIER_PERFORMANCE_DISABLE (1 << 10)
8227
8228 #define GEN8_HDC_CHICKEN1 _MMIO(0x7304)
8229
8230 /* GEN9 chicken */
8231 #define SLICE_ECO_CHICKEN0 _MMIO(0x7308)
8232 #define PIXEL_MASK_CAMMING_DISABLE (1 << 14)
8233
8234 #define GEN9_WM_CHICKEN3 _MMIO(0x5588)
8235 #define GEN9_FACTOR_IN_CLR_VAL_HIZ (1 << 9)
8236
8237 /* WaCatErrorRejectionIssue */
8238 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG _MMIO(0x9030)
8239 #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1 << 11)
8240
8241 #define HSW_SCRATCH1 _MMIO(0xb038)
8242 #define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1 << 27)
8243
8244 #define BDW_SCRATCH1 _MMIO(0xb11c)
8245 #define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE (1 << 2)
8246
8247 /*GEN11 chicken */
8248 #define _PIPEA_CHICKEN 0x70038
8249 #define _PIPEB_CHICKEN 0x71038
8250 #define _PIPEC_CHICKEN 0x72038
8251 #define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\
8252 _PIPEB_CHICKEN)
8253 #define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU (1 << 15)
8254 #define PER_PIXEL_ALPHA_BYPASS_EN (1 << 7)
8255
8256 #define FF_MODE2 _MMIO(0x6604)
8257 #define FF_MODE2_GS_TIMER_MASK REG_GENMASK(31, 24)
8258 #define FF_MODE2_GS_TIMER_224 REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224)
8259 #define FF_MODE2_TDS_TIMER_MASK REG_GENMASK(23, 16)
8260 #define FF_MODE2_TDS_TIMER_128 REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4)
8261
8262 /* PCH */
8263
8264 #define PCH_DISPLAY_BASE 0xc0000u
8265
8266 /* south display engine interrupt: IBX */
8267 #define SDE_AUDIO_POWER_D (1 << 27)
8268 #define SDE_AUDIO_POWER_C (1 << 26)
8269 #define SDE_AUDIO_POWER_B (1 << 25)
8270 #define SDE_AUDIO_POWER_SHIFT (25)
8271 #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT)
8272 #define SDE_GMBUS (1 << 24)
8273 #define SDE_AUDIO_HDCP_TRANSB (1 << 23)
8274 #define SDE_AUDIO_HDCP_TRANSA (1 << 22)
8275 #define SDE_AUDIO_HDCP_MASK (3 << 22)
8276 #define SDE_AUDIO_TRANSB (1 << 21)
8277 #define SDE_AUDIO_TRANSA (1 << 20)
8278 #define SDE_AUDIO_TRANS_MASK (3 << 20)
8279 #define SDE_POISON (1 << 19)
8280 /* 18 reserved */
8281 #define SDE_FDI_RXB (1 << 17)
8282 #define SDE_FDI_RXA (1 << 16)
8283 #define SDE_FDI_MASK (3 << 16)
8284 #define SDE_AUXD (1 << 15)
8285 #define SDE_AUXC (1 << 14)
8286 #define SDE_AUXB (1 << 13)
8287 #define SDE_AUX_MASK (7 << 13)
8288 /* 12 reserved */
8289 #define SDE_CRT_HOTPLUG (1 << 11)
8290 #define SDE_PORTD_HOTPLUG (1 << 10)
8291 #define SDE_PORTC_HOTPLUG (1 << 9)
8292 #define SDE_PORTB_HOTPLUG (1 << 8)
8293 #define SDE_SDVOB_HOTPLUG (1 << 6)
8294 #define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \
8295 SDE_SDVOB_HOTPLUG | \
8296 SDE_PORTB_HOTPLUG | \
8297 SDE_PORTC_HOTPLUG | \
8298 SDE_PORTD_HOTPLUG)
8299 #define SDE_TRANSB_CRC_DONE (1 << 5)
8300 #define SDE_TRANSB_CRC_ERR (1 << 4)
8301 #define SDE_TRANSB_FIFO_UNDER (1 << 3)
8302 #define SDE_TRANSA_CRC_DONE (1 << 2)
8303 #define SDE_TRANSA_CRC_ERR (1 << 1)
8304 #define SDE_TRANSA_FIFO_UNDER (1 << 0)
8305 #define SDE_TRANS_MASK (0x3f)
8306
8307 /* south display engine interrupt: CPT - CNP */
8308 #define SDE_AUDIO_POWER_D_CPT (1 << 31)
8309 #define SDE_AUDIO_POWER_C_CPT (1 << 30)
8310 #define SDE_AUDIO_POWER_B_CPT (1 << 29)
8311 #define SDE_AUDIO_POWER_SHIFT_CPT 29
8312 #define SDE_AUDIO_POWER_MASK_CPT (7 << 29)
8313 #define SDE_AUXD_CPT (1 << 27)
8314 #define SDE_AUXC_CPT (1 << 26)
8315 #define SDE_AUXB_CPT (1 << 25)
8316 #define SDE_AUX_MASK_CPT (7 << 25)
8317 #define SDE_PORTE_HOTPLUG_SPT (1 << 25)
8318 #define SDE_PORTA_HOTPLUG_SPT (1 << 24)
8319 #define SDE_PORTD_HOTPLUG_CPT (1 << 23)
8320 #define SDE_PORTC_HOTPLUG_CPT (1 << 22)
8321 #define SDE_PORTB_HOTPLUG_CPT (1 << 21)
8322 #define SDE_CRT_HOTPLUG_CPT (1 << 19)
8323 #define SDE_SDVOB_HOTPLUG_CPT (1 << 18)
8324 #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
8325 SDE_SDVOB_HOTPLUG_CPT | \
8326 SDE_PORTD_HOTPLUG_CPT | \
8327 SDE_PORTC_HOTPLUG_CPT | \
8328 SDE_PORTB_HOTPLUG_CPT)
8329 #define SDE_HOTPLUG_MASK_SPT (SDE_PORTE_HOTPLUG_SPT | \
8330 SDE_PORTD_HOTPLUG_CPT | \
8331 SDE_PORTC_HOTPLUG_CPT | \
8332 SDE_PORTB_HOTPLUG_CPT | \
8333 SDE_PORTA_HOTPLUG_SPT)
8334 #define SDE_GMBUS_CPT (1 << 17)
8335 #define SDE_ERROR_CPT (1 << 16)
8336 #define SDE_AUDIO_CP_REQ_C_CPT (1 << 10)
8337 #define SDE_AUDIO_CP_CHG_C_CPT (1 << 9)
8338 #define SDE_FDI_RXC_CPT (1 << 8)
8339 #define SDE_AUDIO_CP_REQ_B_CPT (1 << 6)
8340 #define SDE_AUDIO_CP_CHG_B_CPT (1 << 5)
8341 #define SDE_FDI_RXB_CPT (1 << 4)
8342 #define SDE_AUDIO_CP_REQ_A_CPT (1 << 2)
8343 #define SDE_AUDIO_CP_CHG_A_CPT (1 << 1)
8344 #define SDE_FDI_RXA_CPT (1 << 0)
8345 #define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \
8346 SDE_AUDIO_CP_REQ_B_CPT | \
8347 SDE_AUDIO_CP_REQ_A_CPT)
8348 #define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \
8349 SDE_AUDIO_CP_CHG_B_CPT | \
8350 SDE_AUDIO_CP_CHG_A_CPT)
8351 #define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \
8352 SDE_FDI_RXB_CPT | \
8353 SDE_FDI_RXA_CPT)
8354
8355 /* south display engine interrupt: ICP/TGP */
8356 #define SDE_GMBUS_ICP (1 << 23)
8357 #define SDE_TC_HOTPLUG_ICP(hpd_pin) REG_BIT(24 + _HPD_PIN_TC(hpd_pin))
8358 #define SDE_DDI_HOTPLUG_ICP(hpd_pin) REG_BIT(16 + _HPD_PIN_DDI(hpd_pin))
8359 #define SDE_DDI_HOTPLUG_MASK_ICP (SDE_DDI_HOTPLUG_ICP(HPD_PORT_D) | \
8360 SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
8361 SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
8362 SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))
8363 #define SDE_TC_HOTPLUG_MASK_ICP (SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \
8364 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5) | \
8365 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \
8366 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \
8367 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \
8368 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1))
8369
8370 #define SDEISR _MMIO(0xc4000)
8371 #define SDEIMR _MMIO(0xc4004)
8372 #define SDEIIR _MMIO(0xc4008)
8373 #define SDEIER _MMIO(0xc400c)
8374
8375 #define SERR_INT _MMIO(0xc4040)
8376 #define SERR_INT_POISON (1 << 31)
8377 #define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3))
8378
8379 /* digital port hotplug */
8380 #define PCH_PORT_HOTPLUG _MMIO(0xc4030) /* SHOTPLUG_CTL */
8381 #define PORTA_HOTPLUG_ENABLE (1 << 28) /* LPT:LP+ & BXT */
8382 #define BXT_DDIA_HPD_INVERT (1 << 27)
8383 #define PORTA_HOTPLUG_STATUS_MASK (3 << 24) /* SPT+ & BXT */
8384 #define PORTA_HOTPLUG_NO_DETECT (0 << 24) /* SPT+ & BXT */
8385 #define PORTA_HOTPLUG_SHORT_DETECT (1 << 24) /* SPT+ & BXT */
8386 #define PORTA_HOTPLUG_LONG_DETECT (2 << 24) /* SPT+ & BXT */
8387 #define PORTD_HOTPLUG_ENABLE (1 << 20)
8388 #define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */
8389 #define PORTD_PULSE_DURATION_4_5ms (1 << 18) /* pre-LPT */
8390 #define PORTD_PULSE_DURATION_6ms (2 << 18) /* pre-LPT */
8391 #define PORTD_PULSE_DURATION_100ms (3 << 18) /* pre-LPT */
8392 #define PORTD_PULSE_DURATION_MASK (3 << 18) /* pre-LPT */
8393 #define PORTD_HOTPLUG_STATUS_MASK (3 << 16)
8394 #define PORTD_HOTPLUG_NO_DETECT (0 << 16)
8395 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
8396 #define PORTD_HOTPLUG_LONG_DETECT (2 << 16)
8397 #define PORTC_HOTPLUG_ENABLE (1 << 12)
8398 #define BXT_DDIC_HPD_INVERT (1 << 11)
8399 #define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */
8400 #define PORTC_PULSE_DURATION_4_5ms (1 << 10) /* pre-LPT */
8401 #define PORTC_PULSE_DURATION_6ms (2 << 10) /* pre-LPT */
8402 #define PORTC_PULSE_DURATION_100ms (3 << 10) /* pre-LPT */
8403 #define PORTC_PULSE_DURATION_MASK (3 << 10) /* pre-LPT */
8404 #define PORTC_HOTPLUG_STATUS_MASK (3 << 8)
8405 #define PORTC_HOTPLUG_NO_DETECT (0 << 8)
8406 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
8407 #define PORTC_HOTPLUG_LONG_DETECT (2 << 8)
8408 #define PORTB_HOTPLUG_ENABLE (1 << 4)
8409 #define BXT_DDIB_HPD_INVERT (1 << 3)
8410 #define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */
8411 #define PORTB_PULSE_DURATION_4_5ms (1 << 2) /* pre-LPT */
8412 #define PORTB_PULSE_DURATION_6ms (2 << 2) /* pre-LPT */
8413 #define PORTB_PULSE_DURATION_100ms (3 << 2) /* pre-LPT */
8414 #define PORTB_PULSE_DURATION_MASK (3 << 2) /* pre-LPT */
8415 #define PORTB_HOTPLUG_STATUS_MASK (3 << 0)
8416 #define PORTB_HOTPLUG_NO_DETECT (0 << 0)
8417 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
8418 #define PORTB_HOTPLUG_LONG_DETECT (2 << 0)
8419 #define BXT_DDI_HPD_INVERT_MASK (BXT_DDIA_HPD_INVERT | \
8420 BXT_DDIB_HPD_INVERT | \
8421 BXT_DDIC_HPD_INVERT)
8422
8423 #define PCH_PORT_HOTPLUG2 _MMIO(0xc403C) /* SHOTPLUG_CTL2 SPT+ */
8424 #define PORTE_HOTPLUG_ENABLE (1 << 4)
8425 #define PORTE_HOTPLUG_STATUS_MASK (3 << 0)
8426 #define PORTE_HOTPLUG_NO_DETECT (0 << 0)
8427 #define PORTE_HOTPLUG_SHORT_DETECT (1 << 0)
8428 #define PORTE_HOTPLUG_LONG_DETECT (2 << 0)
8429
8430 /* This register is a reuse of PCH_PORT_HOTPLUG register. The
8431 * functionality covered in PCH_PORT_HOTPLUG is split into
8432 * SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC.
8433 */
8434
8435 #define SHOTPLUG_CTL_DDI _MMIO(0xc4030)
8436 #define SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin) (0x8 << (_HPD_PIN_DDI(hpd_pin) * 4))
8437 #define SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4))
8438 #define SHOTPLUG_CTL_DDI_HPD_NO_DETECT(hpd_pin) (0x0 << (_HPD_PIN_DDI(hpd_pin) * 4))
8439 #define SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(hpd_pin) (0x1 << (_HPD_PIN_DDI(hpd_pin) * 4))
8440 #define SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(hpd_pin) (0x2 << (_HPD_PIN_DDI(hpd_pin) * 4))
8441 #define SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4))
8442
8443 #define SHOTPLUG_CTL_TC _MMIO(0xc4034)
8444 #define ICP_TC_HPD_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4))
8445 #define ICP_TC_HPD_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4))
8446 #define ICP_TC_HPD_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4))
8447
8448 #define SHPD_FILTER_CNT _MMIO(0xc4038)
8449 #define SHPD_FILTER_CNT_500_ADJ 0x001D9
8450
8451 #define _PCH_DPLL_A 0xc6014
8452 #define _PCH_DPLL_B 0xc6018
8453 #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
8454
8455 #define _PCH_FPA0 0xc6040
8456 #define FP_CB_TUNE (0x3 << 22)
8457 #define _PCH_FPA1 0xc6044
8458 #define _PCH_FPB0 0xc6048
8459 #define _PCH_FPB1 0xc604c
8460 #define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0)
8461 #define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1)
8462
8463 #define PCH_DPLL_TEST _MMIO(0xc606c)
8464
8465 #define PCH_DREF_CONTROL _MMIO(0xC6200)
8466 #define DREF_CONTROL_MASK 0x7fc3
8467 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0 << 13)
8468 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2 << 13)
8469 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3 << 13)
8470 #define DREF_CPU_SOURCE_OUTPUT_MASK (3 << 13)
8471 #define DREF_SSC_SOURCE_DISABLE (0 << 11)
8472 #define DREF_SSC_SOURCE_ENABLE (2 << 11)
8473 #define DREF_SSC_SOURCE_MASK (3 << 11)
8474 #define DREF_NONSPREAD_SOURCE_DISABLE (0 << 9)
8475 #define DREF_NONSPREAD_CK505_ENABLE (1 << 9)
8476 #define DREF_NONSPREAD_SOURCE_ENABLE (2 << 9)
8477 #define DREF_NONSPREAD_SOURCE_MASK (3 << 9)
8478 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0 << 7)
8479 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2 << 7)
8480 #define DREF_SUPERSPREAD_SOURCE_MASK (3 << 7)
8481 #define DREF_SSC4_DOWNSPREAD (0 << 6)
8482 #define DREF_SSC4_CENTERSPREAD (1 << 6)
8483 #define DREF_SSC1_DISABLE (0 << 1)
8484 #define DREF_SSC1_ENABLE (1 << 1)
8485 #define DREF_SSC4_DISABLE (0)
8486 #define DREF_SSC4_ENABLE (1)
8487
8488 #define PCH_RAWCLK_FREQ _MMIO(0xc6204)
8489 #define FDL_TP1_TIMER_SHIFT 12
8490 #define FDL_TP1_TIMER_MASK (3 << 12)
8491 #define FDL_TP2_TIMER_SHIFT 10
8492 #define FDL_TP2_TIMER_MASK (3 << 10)
8493 #define RAWCLK_FREQ_MASK 0x3ff
8494 #define CNP_RAWCLK_DIV_MASK (0x3ff << 16)
8495 #define CNP_RAWCLK_DIV(div) ((div) << 16)
8496 #define CNP_RAWCLK_FRAC_MASK (0xf << 26)
8497 #define CNP_RAWCLK_DEN(den) ((den) << 26)
8498 #define ICP_RAWCLK_NUM(num) ((num) << 11)
8499
8500 #define PCH_DPLL_TMR_CFG _MMIO(0xc6208)
8501
8502 #define PCH_SSC4_PARMS _MMIO(0xc6210)
8503 #define PCH_SSC4_AUX_PARMS _MMIO(0xc6214)
8504
8505 #define PCH_DPLL_SEL _MMIO(0xc7000)
8506 #define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4))
8507 #define TRANS_DPLLA_SEL(pipe) 0
8508 #define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3))
8509
8510 /* transcoder */
8511
8512 #define _PCH_TRANS_HTOTAL_A 0xe0000
8513 #define TRANS_HTOTAL_SHIFT 16
8514 #define TRANS_HACTIVE_SHIFT 0
8515 #define _PCH_TRANS_HBLANK_A 0xe0004
8516 #define TRANS_HBLANK_END_SHIFT 16
8517 #define TRANS_HBLANK_START_SHIFT 0
8518 #define _PCH_TRANS_HSYNC_A 0xe0008
8519 #define TRANS_HSYNC_END_SHIFT 16
8520 #define TRANS_HSYNC_START_SHIFT 0
8521 #define _PCH_TRANS_VTOTAL_A 0xe000c
8522 #define TRANS_VTOTAL_SHIFT 16
8523 #define TRANS_VACTIVE_SHIFT 0
8524 #define _PCH_TRANS_VBLANK_A 0xe0010
8525 #define TRANS_VBLANK_END_SHIFT 16
8526 #define TRANS_VBLANK_START_SHIFT 0
8527 #define _PCH_TRANS_VSYNC_A 0xe0014
8528 #define TRANS_VSYNC_END_SHIFT 16
8529 #define TRANS_VSYNC_START_SHIFT 0
8530 #define _PCH_TRANS_VSYNCSHIFT_A 0xe0028
8531
8532 #define _PCH_TRANSA_DATA_M1 0xe0030
8533 #define _PCH_TRANSA_DATA_N1 0xe0034
8534 #define _PCH_TRANSA_DATA_M2 0xe0038
8535 #define _PCH_TRANSA_DATA_N2 0xe003c
8536 #define _PCH_TRANSA_LINK_M1 0xe0040
8537 #define _PCH_TRANSA_LINK_N1 0xe0044
8538 #define _PCH_TRANSA_LINK_M2 0xe0048
8539 #define _PCH_TRANSA_LINK_N2 0xe004c
8540
8541 /* Per-transcoder DIP controls (PCH) */
8542 #define _VIDEO_DIP_CTL_A 0xe0200
8543 #define _VIDEO_DIP_DATA_A 0xe0208
8544 #define _VIDEO_DIP_GCP_A 0xe0210
8545 #define GCP_COLOR_INDICATION (1 << 2)
8546 #define GCP_DEFAULT_PHASE_ENABLE (1 << 1)
8547 #define GCP_AV_MUTE (1 << 0)
8548
8549 #define _VIDEO_DIP_CTL_B 0xe1200
8550 #define _VIDEO_DIP_DATA_B 0xe1208
8551 #define _VIDEO_DIP_GCP_B 0xe1210
8552
8553 #define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
8554 #define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
8555 #define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
8556
8557 /* Per-transcoder DIP controls (VLV) */
8558 #define _VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200)
8559 #define _VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208)
8560 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210)
8561
8562 #define _VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170)
8563 #define _VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174)
8564 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178)
8565
8566 #define _CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0)
8567 #define _CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4)
8568 #define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8)
8569
8570 #define VLV_TVIDEO_DIP_CTL(pipe) \
8571 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_CTL_A, \
8572 _VLV_VIDEO_DIP_CTL_B, _CHV_VIDEO_DIP_CTL_C)
8573 #define VLV_TVIDEO_DIP_DATA(pipe) \
8574 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_DATA_A, \
8575 _VLV_VIDEO_DIP_DATA_B, _CHV_VIDEO_DIP_DATA_C)
8576 #define VLV_TVIDEO_DIP_GCP(pipe) \
8577 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \
8578 _VLV_VIDEO_DIP_GDCP_PAYLOAD_B, _CHV_VIDEO_DIP_GDCP_PAYLOAD_C)
8579
8580 /* Haswell DIP controls */
8581
8582 #define _HSW_VIDEO_DIP_CTL_A 0x60200
8583 #define _HSW_VIDEO_DIP_AVI_DATA_A 0x60220
8584 #define _HSW_VIDEO_DIP_VS_DATA_A 0x60260
8585 #define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
8586 #define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
8587 #define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320
8588 #define _GLK_VIDEO_DIP_DRM_DATA_A 0x60440
8589 #define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240
8590 #define _HSW_VIDEO_DIP_VS_ECC_A 0x60280
8591 #define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0
8592 #define _HSW_VIDEO_DIP_GMP_ECC_A 0x60300
8593 #define _HSW_VIDEO_DIP_VSC_ECC_A 0x60344
8594 #define _HSW_VIDEO_DIP_GCP_A 0x60210
8595
8596 #define _HSW_VIDEO_DIP_CTL_B 0x61200
8597 #define _HSW_VIDEO_DIP_AVI_DATA_B 0x61220
8598 #define _HSW_VIDEO_DIP_VS_DATA_B 0x61260
8599 #define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
8600 #define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
8601 #define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320
8602 #define _GLK_VIDEO_DIP_DRM_DATA_B 0x61440
8603 #define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240
8604 #define _HSW_VIDEO_DIP_VS_ECC_B 0x61280
8605 #define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0
8606 #define _HSW_VIDEO_DIP_GMP_ECC_B 0x61300
8607 #define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344
8608 #define _HSW_VIDEO_DIP_GCP_B 0x61210
8609
8610 /* Icelake PPS_DATA and _ECC DIP Registers.
8611 * These are available for transcoders B,C and eDP.
8612 * Adding the _A so as to reuse the _MMIO_TRANS2
8613 * definition, with which it offsets to the right location.
8614 */
8615
8616 #define _ICL_VIDEO_DIP_PPS_DATA_A 0x60350
8617 #define _ICL_VIDEO_DIP_PPS_DATA_B 0x61350
8618 #define _ICL_VIDEO_DIP_PPS_ECC_A 0x603D4
8619 #define _ICL_VIDEO_DIP_PPS_ECC_B 0x613D4
8620
8621 #define HSW_TVIDEO_DIP_CTL(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_CTL_A)
8622 #define HSW_TVIDEO_DIP_GCP(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A)
8623 #define HSW_TVIDEO_DIP_AVI_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4)
8624 #define HSW_TVIDEO_DIP_VS_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4)
8625 #define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)
8626 #define HSW_TVIDEO_DIP_GMP_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4)
8627 #define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4)
8628 #define GLK_TVIDEO_DIP_DRM_DATA(trans, i) _MMIO_TRANS2(trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4)
8629 #define ICL_VIDEO_DIP_PPS_DATA(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4)
8630 #define ICL_VIDEO_DIP_PPS_ECC(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4)
8631
8632 #define _HSW_STEREO_3D_CTL_A 0x70020
8633 #define S3D_ENABLE (1 << 31)
8634 #define _HSW_STEREO_3D_CTL_B 0x71020
8635
8636 #define HSW_STEREO_3D_CTL(trans) _MMIO_PIPE2(trans, _HSW_STEREO_3D_CTL_A)
8637
8638 #define _PCH_TRANS_HTOTAL_B 0xe1000
8639 #define _PCH_TRANS_HBLANK_B 0xe1004
8640 #define _PCH_TRANS_HSYNC_B 0xe1008
8641 #define _PCH_TRANS_VTOTAL_B 0xe100c
8642 #define _PCH_TRANS_VBLANK_B 0xe1010
8643 #define _PCH_TRANS_VSYNC_B 0xe1014
8644 #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
8645
8646 #define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
8647 #define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
8648 #define PCH_TRANS_HSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
8649 #define PCH_TRANS_VTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
8650 #define PCH_TRANS_VBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
8651 #define PCH_TRANS_VSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
8652 #define PCH_TRANS_VSYNCSHIFT(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B)
8653
8654 #define _PCH_TRANSB_DATA_M1 0xe1030
8655 #define _PCH_TRANSB_DATA_N1 0xe1034
8656 #define _PCH_TRANSB_DATA_M2 0xe1038
8657 #define _PCH_TRANSB_DATA_N2 0xe103c
8658 #define _PCH_TRANSB_LINK_M1 0xe1040
8659 #define _PCH_TRANSB_LINK_N1 0xe1044
8660 #define _PCH_TRANSB_LINK_M2 0xe1048
8661 #define _PCH_TRANSB_LINK_N2 0xe104c
8662
8663 #define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
8664 #define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
8665 #define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
8666 #define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
8667 #define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
8668 #define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
8669 #define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
8670 #define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
8671
8672 #define _PCH_TRANSACONF 0xf0008
8673 #define _PCH_TRANSBCONF 0xf1008
8674 #define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
8675 #define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */
8676 #define TRANS_DISABLE (0 << 31)
8677 #define TRANS_ENABLE (1 << 31)
8678 #define TRANS_STATE_MASK (1 << 30)
8679 #define TRANS_STATE_DISABLE (0 << 30)
8680 #define TRANS_STATE_ENABLE (1 << 30)
8681 #define TRANS_FRAME_START_DELAY_MASK (3 << 27) /* ibx */
8682 #define TRANS_FRAME_START_DELAY(x) ((x) << 27) /* ibx: 0-3 */
8683 #define TRANS_INTERLACE_MASK (7 << 21)
8684 #define TRANS_PROGRESSIVE (0 << 21)
8685 #define TRANS_INTERLACED (3 << 21)
8686 #define TRANS_LEGACY_INTERLACED_ILK (2 << 21)
8687 #define TRANS_8BPC (0 << 5)
8688 #define TRANS_10BPC (1 << 5)
8689 #define TRANS_6BPC (2 << 5)
8690 #define TRANS_12BPC (3 << 5)
8691
8692 #define _TRANSA_CHICKEN1 0xf0060
8693 #define _TRANSB_CHICKEN1 0xf1060
8694 #define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
8695 #define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE (1 << 10)
8696 #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1 << 4)
8697 #define _TRANSA_CHICKEN2 0xf0064
8698 #define _TRANSB_CHICKEN2 0xf1064
8699 #define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
8700 #define TRANS_CHICKEN2_TIMING_OVERRIDE (1 << 31)
8701 #define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1 << 29)
8702 #define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3 << 27)
8703 #define TRANS_CHICKEN2_FRAME_START_DELAY(x) ((x) << 27) /* 0-3 */
8704 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1 << 26)
8705 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1 << 25)
8706
8707 #define SOUTH_CHICKEN1 _MMIO(0xc2000)
8708 #define FDIA_PHASE_SYNC_SHIFT_OVR 19
8709 #define FDIA_PHASE_SYNC_SHIFT_EN 18
8710 #define INVERT_DDID_HPD (1 << 18)
8711 #define INVERT_DDIC_HPD (1 << 17)
8712 #define INVERT_DDIB_HPD (1 << 16)
8713 #define INVERT_DDIA_HPD (1 << 15)
8714 #define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
8715 #define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
8716 #define FDI_BC_BIFURCATION_SELECT (1 << 12)
8717 #define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8)
8718 #define CHASSIS_CLK_REQ_DURATION(x) ((x) << 8)
8719 #define SBCLK_RUN_REFCLK_DIS (1 << 7)
8720 #define SPT_PWM_GRANULARITY (1 << 0)
8721 #define SOUTH_CHICKEN2 _MMIO(0xc2004)
8722 #define FDI_MPHY_IOSFSB_RESET_STATUS (1 << 13)
8723 #define FDI_MPHY_IOSFSB_RESET_CTL (1 << 12)
8724 #define LPT_PWM_GRANULARITY (1 << 5)
8725 #define DPLS_EDP_PPS_FIX_DIS (1 << 0)
8726
8727 #define _FDI_RXA_CHICKEN 0xc200c
8728 #define _FDI_RXB_CHICKEN 0xc2010
8729 #define FDI_RX_PHASE_SYNC_POINTER_OVR (1 << 1)
8730 #define FDI_RX_PHASE_SYNC_POINTER_EN (1 << 0)
8731 #define FDI_RX_CHICKEN(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
8732
8733 #define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020)
8734 #define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31)
8735 #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30)
8736 #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29)
8737 #define PCH_DPMGUNIT_CLOCK_GATE_DISABLE (1 << 15)
8738 #define PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14)
8739 #define CNP_PWM_CGE_GATING_DISABLE (1 << 13)
8740 #define PCH_LP_PARTITION_LEVEL_DISABLE (1 << 12)
8741
8742 /* CPU: FDI_TX */
8743 #define _FDI_TXA_CTL 0x60100
8744 #define _FDI_TXB_CTL 0x61100
8745 #define FDI_TX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
8746 #define FDI_TX_DISABLE (0 << 31)
8747 #define FDI_TX_ENABLE (1 << 31)
8748 #define FDI_LINK_TRAIN_PATTERN_1 (0 << 28)
8749 #define FDI_LINK_TRAIN_PATTERN_2 (1 << 28)
8750 #define FDI_LINK_TRAIN_PATTERN_IDLE (2 << 28)
8751 #define FDI_LINK_TRAIN_NONE (3 << 28)
8752 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0 << 25)
8753 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1 << 25)
8754 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2 << 25)
8755 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3 << 25)
8756 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0 << 22)
8757 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1 << 22)
8758 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2 << 22)
8759 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3 << 22)
8760 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
8761 SNB has different settings. */
8762 /* SNB A-stepping */
8763 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22)
8764 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22)
8765 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22)
8766 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22)
8767 /* SNB B-stepping */
8768 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0 << 22)
8769 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a << 22)
8770 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39 << 22)
8771 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38 << 22)
8772 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f << 22)
8773 #define FDI_DP_PORT_WIDTH_SHIFT 19
8774 #define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT)
8775 #define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT)
8776 #define FDI_TX_ENHANCE_FRAME_ENABLE (1 << 18)
8777 /* Ironlake: hardwired to 1 */
8778 #define FDI_TX_PLL_ENABLE (1 << 14)
8779
8780 /* Ivybridge has different bits for lolz */
8781 #define FDI_LINK_TRAIN_PATTERN_1_IVB (0 << 8)
8782 #define FDI_LINK_TRAIN_PATTERN_2_IVB (1 << 8)
8783 #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2 << 8)
8784 #define FDI_LINK_TRAIN_NONE_IVB (3 << 8)
8785
8786 /* both Tx and Rx */
8787 #define FDI_COMPOSITE_SYNC (1 << 11)
8788 #define FDI_LINK_TRAIN_AUTO (1 << 10)
8789 #define FDI_SCRAMBLING_ENABLE (0 << 7)
8790 #define FDI_SCRAMBLING_DISABLE (1 << 7)
8791
8792 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
8793 #define _FDI_RXA_CTL 0xf000c
8794 #define _FDI_RXB_CTL 0xf100c
8795 #define FDI_RX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
8796 #define FDI_RX_ENABLE (1 << 31)
8797 /* train, dp width same as FDI_TX */
8798 #define FDI_FS_ERRC_ENABLE (1 << 27)
8799 #define FDI_FE_ERRC_ENABLE (1 << 26)
8800 #define FDI_RX_POLARITY_REVERSED_LPT (1 << 16)
8801 #define FDI_8BPC (0 << 16)
8802 #define FDI_10BPC (1 << 16)
8803 #define FDI_6BPC (2 << 16)
8804 #define FDI_12BPC (3 << 16)
8805 #define FDI_RX_LINK_REVERSAL_OVERRIDE (1 << 15)
8806 #define FDI_DMI_LINK_REVERSE_MASK (1 << 14)
8807 #define FDI_RX_PLL_ENABLE (1 << 13)
8808 #define FDI_FS_ERR_CORRECT_ENABLE (1 << 11)
8809 #define FDI_FE_ERR_CORRECT_ENABLE (1 << 10)
8810 #define FDI_FS_ERR_REPORT_ENABLE (1 << 9)
8811 #define FDI_FE_ERR_REPORT_ENABLE (1 << 8)
8812 #define FDI_RX_ENHANCE_FRAME_ENABLE (1 << 6)
8813 #define FDI_PCDCLK (1 << 4)
8814 /* CPT */
8815 #define FDI_AUTO_TRAINING (1 << 10)
8816 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0 << 8)
8817 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1 << 8)
8818 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2 << 8)
8819 #define FDI_LINK_TRAIN_NORMAL_CPT (3 << 8)
8820 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3 << 8)
8821
8822 #define _FDI_RXA_MISC 0xf0010
8823 #define _FDI_RXB_MISC 0xf1010
8824 #define FDI_RX_PWRDN_LANE1_MASK (3 << 26)
8825 #define FDI_RX_PWRDN_LANE1_VAL(x) ((x) << 26)
8826 #define FDI_RX_PWRDN_LANE0_MASK (3 << 24)
8827 #define FDI_RX_PWRDN_LANE0_VAL(x) ((x) << 24)
8828 #define FDI_RX_TP1_TO_TP2_48 (2 << 20)
8829 #define FDI_RX_TP1_TO_TP2_64 (3 << 20)
8830 #define FDI_RX_FDI_DELAY_90 (0x90 << 0)
8831 #define FDI_RX_MISC(pipe) _MMIO_PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
8832
8833 #define _FDI_RXA_TUSIZE1 0xf0030
8834 #define _FDI_RXA_TUSIZE2 0xf0038
8835 #define _FDI_RXB_TUSIZE1 0xf1030
8836 #define _FDI_RXB_TUSIZE2 0xf1038
8837 #define FDI_RX_TUSIZE1(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
8838 #define FDI_RX_TUSIZE2(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
8839
8840 /* FDI_RX interrupt register format */
8841 #define FDI_RX_INTER_LANE_ALIGN (1 << 10)
8842 #define FDI_RX_SYMBOL_LOCK (1 << 9) /* train 2 */
8843 #define FDI_RX_BIT_LOCK (1 << 8) /* train 1 */
8844 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1 << 7)
8845 #define FDI_RX_FS_CODE_ERR (1 << 6)
8846 #define FDI_RX_FE_CODE_ERR (1 << 5)
8847 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1 << 4)
8848 #define FDI_RX_HDCP_LINK_FAIL (1 << 3)
8849 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1 << 2)
8850 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1 << 1)
8851 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1 << 0)
8852
8853 #define _FDI_RXA_IIR 0xf0014
8854 #define _FDI_RXA_IMR 0xf0018
8855 #define _FDI_RXB_IIR 0xf1014
8856 #define _FDI_RXB_IMR 0xf1018
8857 #define FDI_RX_IIR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
8858 #define FDI_RX_IMR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
8859
8860 #define FDI_PLL_CTL_1 _MMIO(0xfe000)
8861 #define FDI_PLL_CTL_2 _MMIO(0xfe004)
8862
8863 #define PCH_LVDS _MMIO(0xe1180)
8864 #define LVDS_DETECTED (1 << 1)
8865
8866 #define _PCH_DP_B 0xe4100
8867 #define PCH_DP_B _MMIO(_PCH_DP_B)
8868 #define _PCH_DPB_AUX_CH_CTL 0xe4110
8869 #define _PCH_DPB_AUX_CH_DATA1 0xe4114
8870 #define _PCH_DPB_AUX_CH_DATA2 0xe4118
8871 #define _PCH_DPB_AUX_CH_DATA3 0xe411c
8872 #define _PCH_DPB_AUX_CH_DATA4 0xe4120
8873 #define _PCH_DPB_AUX_CH_DATA5 0xe4124
8874
8875 #define _PCH_DP_C 0xe4200
8876 #define PCH_DP_C _MMIO(_PCH_DP_C)
8877 #define _PCH_DPC_AUX_CH_CTL 0xe4210
8878 #define _PCH_DPC_AUX_CH_DATA1 0xe4214
8879 #define _PCH_DPC_AUX_CH_DATA2 0xe4218
8880 #define _PCH_DPC_AUX_CH_DATA3 0xe421c
8881 #define _PCH_DPC_AUX_CH_DATA4 0xe4220
8882 #define _PCH_DPC_AUX_CH_DATA5 0xe4224
8883
8884 #define _PCH_DP_D 0xe4300
8885 #define PCH_DP_D _MMIO(_PCH_DP_D)
8886 #define _PCH_DPD_AUX_CH_CTL 0xe4310
8887 #define _PCH_DPD_AUX_CH_DATA1 0xe4314
8888 #define _PCH_DPD_AUX_CH_DATA2 0xe4318
8889 #define _PCH_DPD_AUX_CH_DATA3 0xe431c
8890 #define _PCH_DPD_AUX_CH_DATA4 0xe4320
8891 #define _PCH_DPD_AUX_CH_DATA5 0xe4324
8892
8893 #define PCH_DP_AUX_CH_CTL(aux_ch) _MMIO_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL)
8894 #define PCH_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
8895
8896 /* CPT */
8897 #define _TRANS_DP_CTL_A 0xe0300
8898 #define _TRANS_DP_CTL_B 0xe1300
8899 #define _TRANS_DP_CTL_C 0xe2300
8900 #define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B)
8901 #define TRANS_DP_OUTPUT_ENABLE (1 << 31)
8902 #define TRANS_DP_PORT_SEL_MASK (3 << 29)
8903 #define TRANS_DP_PORT_SEL_NONE (3 << 29)
8904 #define TRANS_DP_PORT_SEL(port) (((port) - PORT_B) << 29)
8905 #define TRANS_DP_AUDIO_ONLY (1 << 26)
8906 #define TRANS_DP_ENH_FRAMING (1 << 18)
8907 #define TRANS_DP_8BPC (0 << 9)
8908 #define TRANS_DP_10BPC (1 << 9)
8909 #define TRANS_DP_6BPC (2 << 9)
8910 #define TRANS_DP_12BPC (3 << 9)
8911 #define TRANS_DP_BPC_MASK (3 << 9)
8912 #define TRANS_DP_VSYNC_ACTIVE_HIGH (1 << 4)
8913 #define TRANS_DP_VSYNC_ACTIVE_LOW 0
8914 #define TRANS_DP_HSYNC_ACTIVE_HIGH (1 << 3)
8915 #define TRANS_DP_HSYNC_ACTIVE_LOW 0
8916 #define TRANS_DP_SYNC_MASK (3 << 3)
8917
8918 /* SNB eDP training params */
8919 /* SNB A-stepping */
8920 #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22)
8921 #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22)
8922 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22)
8923 #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22)
8924 /* SNB B-stepping */
8925 #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0 << 22)
8926 #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1 << 22)
8927 #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a << 22)
8928 #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39 << 22)
8929 #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38 << 22)
8930 #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f << 22)
8931
8932 /* IVB */
8933 #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 << 22)
8934 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a << 22)
8935 #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f << 22)
8936 #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 << 22)
8937 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 << 22)
8938 #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 << 22)
8939 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e << 22)
8940
8941 /* legacy values */
8942 #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 << 22)
8943 #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 << 22)
8944 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 << 22)
8945 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 << 22)
8946 #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 << 22)
8947
8948 #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f << 22)
8949
8950 #define VLV_PMWGICZ _MMIO(0x1300a4)
8951
8952 #define RC6_LOCATION _MMIO(0xD40)
8953 #define RC6_CTX_IN_DRAM (1 << 0)
8954 #define RC6_CTX_BASE _MMIO(0xD48)
8955 #define RC6_CTX_BASE_MASK 0xFFFFFFF0
8956 #define PWRCTX_MAXCNT_RCSUNIT _MMIO(0x2054)
8957 #define PWRCTX_MAXCNT_VCSUNIT0 _MMIO(0x12054)
8958 #define PWRCTX_MAXCNT_BCSUNIT _MMIO(0x22054)
8959 #define PWRCTX_MAXCNT_VECSUNIT _MMIO(0x1A054)
8960 #define PWRCTX_MAXCNT_VCSUNIT1 _MMIO(0x1C054)
8961 #define IDLE_TIME_MASK 0xFFFFF
8962 #define FORCEWAKE _MMIO(0xA18C)
8963 #define FORCEWAKE_VLV _MMIO(0x1300b0)
8964 #define FORCEWAKE_ACK_VLV _MMIO(0x1300b4)
8965 #define FORCEWAKE_MEDIA_VLV _MMIO(0x1300b8)
8966 #define FORCEWAKE_ACK_MEDIA_VLV _MMIO(0x1300bc)
8967 #define FORCEWAKE_ACK_HSW _MMIO(0x130044)
8968 #define FORCEWAKE_ACK _MMIO(0x130090)
8969 #define VLV_GTLC_WAKE_CTRL _MMIO(0x130090)
8970 #define VLV_GTLC_RENDER_CTX_EXISTS (1 << 25)
8971 #define VLV_GTLC_MEDIA_CTX_EXISTS (1 << 24)
8972 #define VLV_GTLC_ALLOWWAKEREQ (1 << 0)
8973
8974 #define VLV_GTLC_PW_STATUS _MMIO(0x130094)
8975 #define VLV_GTLC_ALLOWWAKEACK (1 << 0)
8976 #define VLV_GTLC_ALLOWWAKEERR (1 << 1)
8977 #define VLV_GTLC_PW_MEDIA_STATUS_MASK (1 << 5)
8978 #define VLV_GTLC_PW_RENDER_STATUS_MASK (1 << 7)
8979 #define FORCEWAKE_MT _MMIO(0xa188) /* multi-threaded */
8980 #define FORCEWAKE_MEDIA_GEN9 _MMIO(0xa270)
8981 #define FORCEWAKE_MEDIA_VDBOX_GEN11(n) _MMIO(0xa540 + (n) * 4)
8982 #define FORCEWAKE_MEDIA_VEBOX_GEN11(n) _MMIO(0xa560 + (n) * 4)
8983 #define FORCEWAKE_RENDER_GEN9 _MMIO(0xa278)
8984 #define FORCEWAKE_GT_GEN9 _MMIO(0xa188)
8985 #define FORCEWAKE_ACK_MEDIA_GEN9 _MMIO(0x0D88)
8986 #define FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(n) _MMIO(0x0D50 + (n) * 4)
8987 #define FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(n) _MMIO(0x0D70 + (n) * 4)
8988 #define FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0x0D84)
8989 #define FORCEWAKE_ACK_GT_GEN9 _MMIO(0x130044)
8990 #define FORCEWAKE_KERNEL BIT(0)
8991 #define FORCEWAKE_USER BIT(1)
8992 #define FORCEWAKE_KERNEL_FALLBACK BIT(15)
8993 #define FORCEWAKE_MT_ACK _MMIO(0x130040)
8994 #define ECOBUS _MMIO(0xa180)
8995 #define FORCEWAKE_MT_ENABLE (1 << 5)
8996 #define VLV_SPAREG2H _MMIO(0xA194)
8997 #define GEN9_PWRGT_DOMAIN_STATUS _MMIO(0xA2A0)
8998 #define GEN9_PWRGT_MEDIA_STATUS_MASK (1 << 0)
8999 #define GEN9_PWRGT_RENDER_STATUS_MASK (1 << 1)
9000
9001 #define GTFIFODBG _MMIO(0x120000)
9002 #define GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV (0x1f << 20)
9003 #define GT_FIFO_FREE_ENTRIES_CHV (0x7f << 13)
9004 #define GT_FIFO_SBDROPERR (1 << 6)
9005 #define GT_FIFO_BLOBDROPERR (1 << 5)
9006 #define GT_FIFO_SB_READ_ABORTERR (1 << 4)
9007 #define GT_FIFO_DROPERR (1 << 3)
9008 #define GT_FIFO_OVFERR (1 << 2)
9009 #define GT_FIFO_IAWRERR (1 << 1)
9010 #define GT_FIFO_IARDERR (1 << 0)
9011
9012 #define GTFIFOCTL _MMIO(0x120008)
9013 #define GT_FIFO_FREE_ENTRIES_MASK 0x7f
9014 #define GT_FIFO_NUM_RESERVED_ENTRIES 20
9015 #define GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL (1 << 12)
9016 #define GT_FIFO_CTL_RC6_POLICY_STALL (1 << 11)
9017
9018 #define HSW_IDICR _MMIO(0x9008)
9019 #define IDIHASHMSK(x) (((x) & 0x3f) << 16)
9020 #define HSW_EDRAM_CAP _MMIO(0x120010)
9021 #define EDRAM_ENABLED 0x1
9022 #define EDRAM_NUM_BANKS(cap) (((cap) >> 1) & 0xf)
9023 #define EDRAM_WAYS_IDX(cap) (((cap) >> 5) & 0x7)
9024 #define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3)
9025
9026 #define GEN6_UCGCTL1 _MMIO(0x9400)
9027 # define GEN6_GAMUNIT_CLOCK_GATE_DISABLE (1 << 22)
9028 # define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16)
9029 # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5)
9030 # define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7)
9031
9032 #define GEN6_UCGCTL2 _MMIO(0x9404)
9033 # define GEN6_VFUNIT_CLOCK_GATE_DISABLE (1 << 31)
9034 # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30)
9035 # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22)
9036 # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13)
9037 # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12)
9038 # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11)
9039
9040 #define GEN6_UCGCTL3 _MMIO(0x9408)
9041 # define GEN6_OACSUNIT_CLOCK_GATE_DISABLE (1 << 20)
9042
9043 #define GEN7_UCGCTL4 _MMIO(0x940c)
9044 #define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1 << 25)
9045 #define GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE (1 << 14)
9046
9047 #define GEN6_RCGCTL1 _MMIO(0x9410)
9048 #define GEN6_RCGCTL2 _MMIO(0x9414)
9049 #define GEN6_RSTCTL _MMIO(0x9420)
9050
9051 #define GEN8_UCGCTL6 _MMIO(0x9430)
9052 #define GEN8_GAPSUNIT_CLOCK_GATE_DISABLE (1 << 24)
9053 #define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1 << 14)
9054 #define GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1 << 28)
9055
9056 #define GEN6_GFXPAUSE _MMIO(0xA000)
9057 #define GEN6_RPNSWREQ _MMIO(0xA008)
9058 #define GEN6_TURBO_DISABLE (1 << 31)
9059 #define GEN6_FREQUENCY(x) ((x) << 25)
9060 #define HSW_FREQUENCY(x) ((x) << 24)
9061 #define GEN9_FREQUENCY(x) ((x) << 23)
9062 #define GEN6_OFFSET(x) ((x) << 19)
9063 #define GEN6_AGGRESSIVE_TURBO (0 << 15)
9064 #define GEN6_RC_VIDEO_FREQ _MMIO(0xA00C)
9065 #define GEN6_RC_CONTROL _MMIO(0xA090)
9066 #define GEN6_RC_CTL_RC6pp_ENABLE (1 << 16)
9067 #define GEN6_RC_CTL_RC6p_ENABLE (1 << 17)
9068 #define GEN6_RC_CTL_RC6_ENABLE (1 << 18)
9069 #define GEN6_RC_CTL_RC1e_ENABLE (1 << 20)
9070 #define GEN6_RC_CTL_RC7_ENABLE (1 << 22)
9071 #define VLV_RC_CTL_CTX_RST_PARALLEL (1 << 24)
9072 #define GEN7_RC_CTL_TO_MODE (1 << 28)
9073 #define GEN6_RC_CTL_EI_MODE(x) ((x) << 27)
9074 #define GEN6_RC_CTL_HW_ENABLE (1 << 31)
9075 #define GEN6_RP_DOWN_TIMEOUT _MMIO(0xA010)
9076 #define GEN6_RP_INTERRUPT_LIMITS _MMIO(0xA014)
9077 #define GEN6_RPSTAT1 _MMIO(0xA01C)
9078 #define GEN6_CAGF_SHIFT 8
9079 #define HSW_CAGF_SHIFT 7
9080 #define GEN9_CAGF_SHIFT 23
9081 #define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT)
9082 #define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT)
9083 #define GEN9_CAGF_MASK (0x1ff << GEN9_CAGF_SHIFT)
9084 #define GEN6_RP_CONTROL _MMIO(0xA024)
9085 #define GEN6_RP_MEDIA_TURBO (1 << 11)
9086 #define GEN6_RP_MEDIA_MODE_MASK (3 << 9)
9087 #define GEN6_RP_MEDIA_HW_TURBO_MODE (3 << 9)
9088 #define GEN6_RP_MEDIA_HW_NORMAL_MODE (2 << 9)
9089 #define GEN6_RP_MEDIA_HW_MODE (1 << 9)
9090 #define GEN6_RP_MEDIA_SW_MODE (0 << 9)
9091 #define GEN6_RP_MEDIA_IS_GFX (1 << 8)
9092 #define GEN6_RP_ENABLE (1 << 7)
9093 #define GEN6_RP_UP_IDLE_MIN (0x1 << 3)
9094 #define GEN6_RP_UP_BUSY_AVG (0x2 << 3)
9095 #define GEN6_RP_UP_BUSY_CONT (0x4 << 3)
9096 #define GEN6_RP_DOWN_IDLE_AVG (0x2 << 0)
9097 #define GEN6_RP_DOWN_IDLE_CONT (0x1 << 0)
9098 #define GEN6_RP_UP_THRESHOLD _MMIO(0xA02C)
9099 #define GEN6_RP_DOWN_THRESHOLD _MMIO(0xA030)
9100 #define GEN6_RP_CUR_UP_EI _MMIO(0xA050)
9101 #define GEN6_RP_EI_MASK 0xffffff
9102 #define GEN6_CURICONT_MASK GEN6_RP_EI_MASK
9103 #define GEN6_RP_CUR_UP _MMIO(0xA054)
9104 #define GEN6_CURBSYTAVG_MASK GEN6_RP_EI_MASK
9105 #define GEN6_RP_PREV_UP _MMIO(0xA058)
9106 #define GEN6_RP_CUR_DOWN_EI _MMIO(0xA05C)
9107 #define GEN6_CURIAVG_MASK GEN6_RP_EI_MASK
9108 #define GEN6_RP_CUR_DOWN _MMIO(0xA060)
9109 #define GEN6_RP_PREV_DOWN _MMIO(0xA064)
9110 #define GEN6_RP_UP_EI _MMIO(0xA068)
9111 #define GEN6_RP_DOWN_EI _MMIO(0xA06C)
9112 #define GEN6_RP_IDLE_HYSTERSIS _MMIO(0xA070)
9113 #define GEN6_RPDEUHWTC _MMIO(0xA080)
9114 #define GEN6_RPDEUC _MMIO(0xA084)
9115 #define GEN6_RPDEUCSW _MMIO(0xA088)
9116 #define GEN6_RC_STATE _MMIO(0xA094)
9117 #define RC_SW_TARGET_STATE_SHIFT 16
9118 #define RC_SW_TARGET_STATE_MASK (7 << RC_SW_TARGET_STATE_SHIFT)
9119 #define GEN6_RC1_WAKE_RATE_LIMIT _MMIO(0xA098)
9120 #define GEN6_RC6_WAKE_RATE_LIMIT _MMIO(0xA09C)
9121 #define GEN6_RC6pp_WAKE_RATE_LIMIT _MMIO(0xA0A0)
9122 #define GEN10_MEDIA_WAKE_RATE_LIMIT _MMIO(0xA0A0)
9123 #define GEN6_RC_EVALUATION_INTERVAL _MMIO(0xA0A8)
9124 #define GEN6_RC_IDLE_HYSTERSIS _MMIO(0xA0AC)
9125 #define GEN6_RC_SLEEP _MMIO(0xA0B0)
9126 #define GEN6_RCUBMABDTMR _MMIO(0xA0B0)
9127 #define GEN6_RC1e_THRESHOLD _MMIO(0xA0B4)
9128 #define GEN6_RC6_THRESHOLD _MMIO(0xA0B8)
9129 #define GEN6_RC6p_THRESHOLD _MMIO(0xA0BC)
9130 #define VLV_RCEDATA _MMIO(0xA0BC)
9131 #define GEN6_RC6pp_THRESHOLD _MMIO(0xA0C0)
9132 #define GEN6_PMINTRMSK _MMIO(0xA168)
9133 #define GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC (1 << 31)
9134 #define ARAT_EXPIRED_INTRMSK (1 << 9)
9135 #define GEN8_MISC_CTRL0 _MMIO(0xA180)
9136 #define VLV_PWRDWNUPCTL _MMIO(0xA294)
9137 #define GEN9_MEDIA_PG_IDLE_HYSTERESIS _MMIO(0xA0C4)
9138 #define GEN9_RENDER_PG_IDLE_HYSTERESIS _MMIO(0xA0C8)
9139 #define GEN9_PG_ENABLE _MMIO(0xA210)
9140 #define GEN9_RENDER_PG_ENABLE REG_BIT(0)
9141 #define GEN9_MEDIA_PG_ENABLE REG_BIT(1)
9142 #define GEN11_MEDIA_SAMPLER_PG_ENABLE REG_BIT(2)
9143 #define VDN_HCP_POWERGATE_ENABLE(n) REG_BIT(3 + 2 * (n))
9144 #define VDN_MFX_POWERGATE_ENABLE(n) REG_BIT(4 + 2 * (n))
9145 #define GEN8_PUSHBUS_CONTROL _MMIO(0xA248)
9146 #define GEN8_PUSHBUS_ENABLE _MMIO(0xA250)
9147 #define GEN8_PUSHBUS_SHIFT _MMIO(0xA25C)
9148
9149 #define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C)
9150 #define PIXEL_OVERLAP_CNT_MASK (3 << 30)
9151 #define PIXEL_OVERLAP_CNT_SHIFT 30
9152
9153 #define GEN6_PMISR _MMIO(0x44020)
9154 #define GEN6_PMIMR _MMIO(0x44024) /* rps_lock */
9155 #define GEN6_PMIIR _MMIO(0x44028)
9156 #define GEN6_PMIER _MMIO(0x4402C)
9157 #define GEN6_PM_MBOX_EVENT (1 << 25)
9158 #define GEN6_PM_THERMAL_EVENT (1 << 24)
9159
9160 /*
9161 * For Gen11 these are in the upper word of the GPM_WGBOXPERF
9162 * registers. Shifting is handled on accessing the imr and ier.
9163 */
9164 #define GEN6_PM_RP_DOWN_TIMEOUT (1 << 6)
9165 #define GEN6_PM_RP_UP_THRESHOLD (1 << 5)
9166 #define GEN6_PM_RP_DOWN_THRESHOLD (1 << 4)
9167 #define GEN6_PM_RP_UP_EI_EXPIRED (1 << 2)
9168 #define GEN6_PM_RP_DOWN_EI_EXPIRED (1 << 1)
9169 #define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_EI_EXPIRED | \
9170 GEN6_PM_RP_UP_THRESHOLD | \
9171 GEN6_PM_RP_DOWN_EI_EXPIRED | \
9172 GEN6_PM_RP_DOWN_THRESHOLD | \
9173 GEN6_PM_RP_DOWN_TIMEOUT)
9174
9175 #define GEN7_GT_SCRATCH(i) _MMIO(0x4F100 + (i) * 4)
9176 #define GEN7_GT_SCRATCH_REG_NUM 8
9177
9178 #define VLV_GTLC_SURVIVABILITY_REG _MMIO(0x130098)
9179 #define VLV_GFX_CLK_STATUS_BIT (1 << 3)
9180 #define VLV_GFX_CLK_FORCE_ON_BIT (1 << 2)
9181
9182 #define GEN6_GT_GFX_RC6_LOCKED _MMIO(0x138104)
9183 #define VLV_COUNTER_CONTROL _MMIO(0x138104)
9184 #define VLV_COUNT_RANGE_HIGH (1 << 15)
9185 #define VLV_MEDIA_RC0_COUNT_EN (1 << 5)
9186 #define VLV_RENDER_RC0_COUNT_EN (1 << 4)
9187 #define VLV_MEDIA_RC6_COUNT_EN (1 << 1)
9188 #define VLV_RENDER_RC6_COUNT_EN (1 << 0)
9189 #define GEN6_GT_GFX_RC6 _MMIO(0x138108)
9190 #define VLV_GT_RENDER_RC6 _MMIO(0x138108)
9191 #define VLV_GT_MEDIA_RC6 _MMIO(0x13810C)
9192
9193 #define GEN6_GT_GFX_RC6p _MMIO(0x13810C)
9194 #define GEN6_GT_GFX_RC6pp _MMIO(0x138110)
9195 #define VLV_RENDER_C0_COUNT _MMIO(0x138118)
9196 #define VLV_MEDIA_C0_COUNT _MMIO(0x13811C)
9197
9198 #define GEN6_PCODE_MAILBOX _MMIO(0x138124)
9199 #define GEN6_PCODE_READY (1 << 31)
9200 #define GEN6_PCODE_ERROR_MASK 0xFF
9201 #define GEN6_PCODE_SUCCESS 0x0
9202 #define GEN6_PCODE_ILLEGAL_CMD 0x1
9203 #define GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2
9204 #define GEN6_PCODE_TIMEOUT 0x3
9205 #define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF
9206 #define GEN7_PCODE_TIMEOUT 0x2
9207 #define GEN7_PCODE_ILLEGAL_DATA 0x3
9208 #define GEN11_PCODE_ILLEGAL_SUBCOMMAND 0x4
9209 #define GEN11_PCODE_LOCKED 0x6
9210 #define GEN11_PCODE_REJECTED 0x11
9211 #define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
9212 #define GEN6_PCODE_WRITE_RC6VIDS 0x4
9213 #define GEN6_PCODE_READ_RC6VIDS 0x5
9214 #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
9215 #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
9216 #define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18
9217 #define GEN9_PCODE_READ_MEM_LATENCY 0x6
9218 #define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF
9219 #define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8
9220 #define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16
9221 #define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24
9222 #define SKL_PCODE_LOAD_HDCP_KEYS 0x5
9223 #define SKL_PCODE_CDCLK_CONTROL 0x7
9224 #define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3
9225 #define SKL_CDCLK_READY_FOR_CHANGE 0x1
9226 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
9227 #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
9228 #define GEN6_READ_OC_PARAMS 0xc
9229 #define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd
9230 #define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8)
9231 #define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8))
9232 #define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe
9233 #define ICL_PCODE_POINTS_RESTRICTED 0x0
9234 #define ICL_PCODE_POINTS_RESTRICTED_MASK 0x1
9235 #define GEN6_PCODE_READ_D_COMP 0x10
9236 #define GEN6_PCODE_WRITE_D_COMP 0x11
9237 #define ICL_PCODE_EXIT_TCCOLD 0x12
9238 #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
9239 #define DISPLAY_IPS_CONTROL 0x19
9240 #define TGL_PCODE_TCCOLD 0x26
9241 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED REG_BIT(0)
9242 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ 0
9243 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ REG_BIT(0)
9244 /* See also IPS_CTL */
9245 #define IPS_PCODE_CONTROL (1 << 30)
9246 #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
9247 #define GEN9_PCODE_SAGV_CONTROL 0x21
9248 #define GEN9_SAGV_DISABLE 0x0
9249 #define GEN9_SAGV_IS_DISABLED 0x1
9250 #define GEN9_SAGV_ENABLE 0x3
9251 #define DG1_PCODE_STATUS 0x7E
9252 #define DG1_UNCORE_GET_INIT_STATUS 0x0
9253 #define DG1_UNCORE_INIT_STATUS_COMPLETE 0x1
9254 #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
9255 #define GEN6_PCODE_DATA _MMIO(0x138128)
9256 #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
9257 #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
9258 #define GEN6_PCODE_DATA1 _MMIO(0x13812C)
9259
9260 #define GEN6_GT_CORE_STATUS _MMIO(0x138060)
9261 #define GEN6_CORE_CPD_STATE_MASK (7 << 4)
9262 #define GEN6_RCn_MASK 7
9263 #define GEN6_RC0 0
9264 #define GEN6_RC3 2
9265 #define GEN6_RC6 3
9266 #define GEN6_RC7 4
9267
9268 #define GEN8_GT_SLICE_INFO _MMIO(0x138064)
9269 #define GEN8_LSLICESTAT_MASK 0x7
9270
9271 #define CHV_POWER_SS0_SIG1 _MMIO(0xa720)
9272 #define CHV_POWER_SS1_SIG1 _MMIO(0xa728)
9273 #define CHV_SS_PG_ENABLE (1 << 1)
9274 #define CHV_EU08_PG_ENABLE (1 << 9)
9275 #define CHV_EU19_PG_ENABLE (1 << 17)
9276 #define CHV_EU210_PG_ENABLE (1 << 25)
9277
9278 #define CHV_POWER_SS0_SIG2 _MMIO(0xa724)
9279 #define CHV_POWER_SS1_SIG2 _MMIO(0xa72c)
9280 #define CHV_EU311_PG_ENABLE (1 << 1)
9281
9282 #define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice) * 0x4)
9283 #define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \
9284 ((slice) % 3) * 0x4)
9285 #define GEN9_PGCTL_SLICE_ACK (1 << 0)
9286 #define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice) * 2))
9287 #define GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F)
9288
9289 #define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice) * 0x8)
9290 #define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \
9291 ((slice) % 3) * 0x8)
9292 #define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice) * 0x8)
9293 #define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \
9294 ((slice) % 3) * 0x8)
9295 #define GEN9_PGCTL_SSA_EU08_ACK (1 << 0)
9296 #define GEN9_PGCTL_SSA_EU19_ACK (1 << 2)
9297 #define GEN9_PGCTL_SSA_EU210_ACK (1 << 4)
9298 #define GEN9_PGCTL_SSA_EU311_ACK (1 << 6)
9299 #define GEN9_PGCTL_SSB_EU08_ACK (1 << 8)
9300 #define GEN9_PGCTL_SSB_EU19_ACK (1 << 10)
9301 #define GEN9_PGCTL_SSB_EU210_ACK (1 << 12)
9302 #define GEN9_PGCTL_SSB_EU311_ACK (1 << 14)
9303
9304 #define GEN7_MISCCPCTL _MMIO(0x9424)
9305 #define GEN7_DOP_CLOCK_GATE_ENABLE (1 << 0)
9306 #define GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE (1 << 2)
9307 #define GEN8_DOP_CLOCK_GATE_GUC_ENABLE (1 << 4)
9308 #define GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE (1 << 6)
9309
9310 #define GEN8_GARBCNTL _MMIO(0xB004)
9311 #define GEN9_GAPS_TSV_CREDIT_DISABLE (1 << 7)
9312 #define GEN11_ARBITRATION_PRIO_ORDER_MASK (0x3f << 22)
9313 #define GEN11_HASH_CTRL_EXCL_MASK (0x7f << 0)
9314 #define GEN11_HASH_CTRL_EXCL_BIT0 (1 << 0)
9315
9316 #define GEN11_GLBLINVL _MMIO(0xB404)
9317 #define GEN11_BANK_HASH_ADDR_EXCL_MASK (0x7f << 5)
9318 #define GEN11_BANK_HASH_ADDR_EXCL_BIT0 (1 << 5)
9319
9320 #define GEN10_DFR_RATIO_EN_AND_CHICKEN _MMIO(0x9550)
9321 #define DFR_DISABLE (1 << 9)
9322
9323 #define GEN11_GACB_PERF_CTRL _MMIO(0x4B80)
9324 #define GEN11_HASH_CTRL_MASK (0x3 << 12 | 0xf << 0)
9325 #define GEN11_HASH_CTRL_BIT0 (1 << 0)
9326 #define GEN11_HASH_CTRL_BIT4 (1 << 12)
9327
9328 #define GEN11_LSN_UNSLCVC _MMIO(0xB43C)
9329 #define GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC (1 << 9)
9330 #define GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC (1 << 7)
9331
9332 #define GEN10_SAMPLER_MODE _MMIO(0xE18C)
9333 #define ENABLE_SMALLPL REG_BIT(15)
9334 #define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5)
9335
9336 /* IVYBRIDGE DPF */
9337 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
9338 #define GEN7_L3CDERRST1_ROW_MASK (0x7ff << 14)
9339 #define GEN7_PARITY_ERROR_VALID (1 << 13)
9340 #define GEN7_L3CDERRST1_BANK_MASK (3 << 11)
9341 #define GEN7_L3CDERRST1_SUBBANK_MASK (7 << 8)
9342 #define GEN7_PARITY_ERROR_ROW(reg) \
9343 (((reg) & GEN7_L3CDERRST1_ROW_MASK) >> 14)
9344 #define GEN7_PARITY_ERROR_BANK(reg) \
9345 (((reg) & GEN7_L3CDERRST1_BANK_MASK) >> 11)
9346 #define GEN7_PARITY_ERROR_SUBBANK(reg) \
9347 (((reg) & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
9348 #define GEN7_L3CDERRST1_ENABLE (1 << 7)
9349
9350 #define GEN7_L3LOG(slice, i) _MMIO(0xB070 + (slice) * 0x200 + (i) * 4)
9351 #define GEN7_L3LOG_SIZE 0x80
9352
9353 #define GEN7_HALF_SLICE_CHICKEN1 _MMIO(0xe100) /* IVB GT1 + VLV */
9354 #define GEN7_HALF_SLICE_CHICKEN1_GT2 _MMIO(0xf100)
9355 #define GEN7_MAX_PS_THREAD_DEP (8 << 12)
9356 #define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1 << 10)
9357 #define GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE (1 << 4)
9358 #define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1 << 3)
9359
9360 #define GEN9_HALF_SLICE_CHICKEN5 _MMIO(0xe188)
9361 #define GEN9_DG_MIRROR_FIX_ENABLE (1 << 5)
9362 #define GEN9_CCS_TLB_PREFETCH_ENABLE (1 << 3)
9363
9364 #define GEN8_ROW_CHICKEN _MMIO(0xe4f0)
9365 #define FLOW_CONTROL_ENABLE (1 << 15)
9366 #define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1 << 8)
9367 #define STALL_DOP_GATING_DISABLE (1 << 5)
9368 #define THROTTLE_12_5 (7 << 2)
9369 #define DISABLE_EARLY_EOT (1 << 1)
9370
9371 #define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4)
9372 #define GEN12_DISABLE_EARLY_READ REG_BIT(14)
9373 #define GEN12_PUSH_CONST_DEREF_HOLD_DIS REG_BIT(8)
9374
9375 #define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4)
9376 #define DOP_CLOCK_GATING_DISABLE (1 << 0)
9377 #define PUSH_CONSTANT_DEREF_DISABLE (1 << 8)
9378 #define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1)
9379
9380 #define GEN9_ROW_CHICKEN4 _MMIO(0xe48c)
9381 #define GEN12_DISABLE_TDL_PUSH REG_BIT(9)
9382 #define GEN11_DIS_PICK_2ND_EU REG_BIT(7)
9383
9384 #define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
9385 #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
9386
9387 #define HALF_SLICE_CHICKEN2 _MMIO(0xe180)
9388 #define GEN8_ST_PO_DISABLE (1 << 13)
9389
9390 #define HALF_SLICE_CHICKEN3 _MMIO(0xe184)
9391 #define HSW_SAMPLE_C_PERFORMANCE (1 << 9)
9392 #define GEN8_CENTROID_PIXEL_OPT_DIS (1 << 8)
9393 #define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1 << 5)
9394 #define CNL_FAST_ANISO_L1_BANKING_FIX (1 << 4)
9395 #define GEN8_SAMPLER_POWER_BYPASS_DIS (1 << 1)
9396
9397 #define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194)
9398 #define GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR (1 << 8)
9399 #define GEN9_ENABLE_YV12_BUGFIX (1 << 4)
9400 #define GEN9_ENABLE_GPGPU_PREEMPTION (1 << 2)
9401
9402 /* Audio */
9403 #define G4X_AUD_VID_DID _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x62020)
9404 #define INTEL_AUDIO_DEVCL 0x808629FB
9405 #define INTEL_AUDIO_DEVBLC 0x80862801
9406 #define INTEL_AUDIO_DEVCTG 0x80862802
9407
9408 #define G4X_AUD_CNTL_ST _MMIO(0x620B4)
9409 #define G4X_ELDV_DEVCL_DEVBLC (1 << 13)
9410 #define G4X_ELDV_DEVCTG (1 << 14)
9411 #define G4X_ELD_ADDR_MASK (0xf << 5)
9412 #define G4X_ELD_ACK (1 << 4)
9413 #define G4X_HDMIW_HDMIEDID _MMIO(0x6210C)
9414
9415 #define _IBX_HDMIW_HDMIEDID_A 0xE2050
9416 #define _IBX_HDMIW_HDMIEDID_B 0xE2150
9417 #define IBX_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \
9418 _IBX_HDMIW_HDMIEDID_B)
9419 #define _IBX_AUD_CNTL_ST_A 0xE20B4
9420 #define _IBX_AUD_CNTL_ST_B 0xE21B4
9421 #define IBX_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \
9422 _IBX_AUD_CNTL_ST_B)
9423 #define IBX_ELD_BUFFER_SIZE_MASK (0x1f << 10)
9424 #define IBX_ELD_ADDRESS_MASK (0x1f << 5)
9425 #define IBX_ELD_ACK (1 << 4)
9426 #define IBX_AUD_CNTL_ST2 _MMIO(0xE20C0)
9427 #define IBX_CP_READY(port) ((1 << 1) << (((port) - 1) * 4))
9428 #define IBX_ELD_VALID(port) ((1 << 0) << (((port) - 1) * 4))
9429
9430 #define _CPT_HDMIW_HDMIEDID_A 0xE5050
9431 #define _CPT_HDMIW_HDMIEDID_B 0xE5150
9432 #define CPT_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B)
9433 #define _CPT_AUD_CNTL_ST_A 0xE50B4
9434 #define _CPT_AUD_CNTL_ST_B 0xE51B4
9435 #define CPT_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B)
9436 #define CPT_AUD_CNTRL_ST2 _MMIO(0xE50C0)
9437
9438 #define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050)
9439 #define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150)
9440 #define VLV_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B)
9441 #define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4)
9442 #define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4)
9443 #define VLV_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B)
9444 #define VLV_AUD_CNTL_ST2 _MMIO(VLV_DISPLAY_BASE + 0x620C0)
9445
9446 /* These are the 4 32-bit write offset registers for each stream
9447 * output buffer. It determines the offset from the
9448 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
9449 */
9450 #define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4)
9451
9452 #define _IBX_AUD_CONFIG_A 0xe2000
9453 #define _IBX_AUD_CONFIG_B 0xe2100
9454 #define IBX_AUD_CFG(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B)
9455 #define _CPT_AUD_CONFIG_A 0xe5000
9456 #define _CPT_AUD_CONFIG_B 0xe5100
9457 #define CPT_AUD_CFG(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B)
9458 #define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000)
9459 #define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100)
9460 #define VLV_AUD_CFG(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B)
9461
9462 #define AUD_CONFIG_N_VALUE_INDEX (1 << 29)
9463 #define AUD_CONFIG_N_PROG_ENABLE (1 << 28)
9464 #define AUD_CONFIG_UPPER_N_SHIFT 20
9465 #define AUD_CONFIG_UPPER_N_MASK (0xff << 20)
9466 #define AUD_CONFIG_LOWER_N_SHIFT 4
9467 #define AUD_CONFIG_LOWER_N_MASK (0xfff << 4)
9468 #define AUD_CONFIG_N_MASK (AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK)
9469 #define AUD_CONFIG_N(n) \
9470 (((((n) >> 12) & 0xff) << AUD_CONFIG_UPPER_N_SHIFT) | \
9471 (((n) & 0xfff) << AUD_CONFIG_LOWER_N_SHIFT))
9472 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16
9473 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16)
9474 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16)
9475 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16)
9476 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16)
9477 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16)
9478 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16)
9479 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16)
9480 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16)
9481 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16)
9482 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16)
9483 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16)
9484 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_296703 (10 << 16)
9485 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_297000 (11 << 16)
9486 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_593407 (12 << 16)
9487 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_594000 (13 << 16)
9488 #define AUD_CONFIG_DISABLE_NCTS (1 << 3)
9489
9490 /* HSW Audio */
9491 #define _HSW_AUD_CONFIG_A 0x65000
9492 #define _HSW_AUD_CONFIG_B 0x65100
9493 #define HSW_AUD_CFG(trans) _MMIO_TRANS(trans, _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B)
9494
9495 #define _HSW_AUD_MISC_CTRL_A 0x65010
9496 #define _HSW_AUD_MISC_CTRL_B 0x65110
9497 #define HSW_AUD_MISC_CTRL(trans) _MMIO_TRANS(trans, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
9498
9499 #define _HSW_AUD_M_CTS_ENABLE_A 0x65028
9500 #define _HSW_AUD_M_CTS_ENABLE_B 0x65128
9501 #define HSW_AUD_M_CTS_ENABLE(trans) _MMIO_TRANS(trans, _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
9502 #define AUD_M_CTS_M_VALUE_INDEX (1 << 21)
9503 #define AUD_M_CTS_M_PROG_ENABLE (1 << 20)
9504 #define AUD_CONFIG_M_MASK 0xfffff
9505
9506 #define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4
9507 #define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4
9508 #define HSW_AUD_DIP_ELD_CTRL(trans) _MMIO_TRANS(trans, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B)
9509
9510 /* Audio Digital Converter */
9511 #define _HSW_AUD_DIG_CNVT_1 0x65080
9512 #define _HSW_AUD_DIG_CNVT_2 0x65180
9513 #define AUD_DIG_CNVT(trans) _MMIO_TRANS(trans, _HSW_AUD_DIG_CNVT_1, _HSW_AUD_DIG_CNVT_2)
9514 #define DIP_PORT_SEL_MASK 0x3
9515
9516 #define _HSW_AUD_EDID_DATA_A 0x65050
9517 #define _HSW_AUD_EDID_DATA_B 0x65150
9518 #define HSW_AUD_EDID_DATA(trans) _MMIO_TRANS(trans, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B)
9519
9520 #define HSW_AUD_PIPE_CONV_CFG _MMIO(0x6507c)
9521 #define HSW_AUD_PIN_ELD_CP_VLD _MMIO(0x650c0)
9522 #define AUDIO_INACTIVE(trans) ((1 << 3) << ((trans) * 4))
9523 #define AUDIO_OUTPUT_ENABLE(trans) ((1 << 2) << ((trans) * 4))
9524 #define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4))
9525 #define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4))
9526
9527 #define HSW_AUD_CHICKENBIT _MMIO(0x65f10)
9528 #define SKL_AUD_CODEC_WAKE_SIGNAL (1 << 15)
9529
9530 #define AUD_FREQ_CNTRL _MMIO(0x65900)
9531 #define AUD_PIN_BUF_CTL _MMIO(0x48414)
9532 #define AUD_PIN_BUF_ENABLE REG_BIT(31)
9533
9534 /* Display Audio Config Reg */
9535 #define AUD_CONFIG_BE _MMIO(0x65ef0)
9536 #define HBLANK_EARLY_ENABLE_ICL(pipe) (0x1 << (20 - (pipe)))
9537 #define HBLANK_EARLY_ENABLE_TGL(pipe) (0x1 << (24 + (pipe)))
9538 #define HBLANK_START_COUNT_MASK(pipe) (0x7 << (3 + ((pipe) * 6)))
9539 #define HBLANK_START_COUNT(pipe, val) (((val) & 0x7) << (3 + ((pipe)) * 6))
9540 #define NUMBER_SAMPLES_PER_LINE_MASK(pipe) (0x3 << ((pipe) * 6))
9541 #define NUMBER_SAMPLES_PER_LINE(pipe, val) (((val) & 0x3) << ((pipe) * 6))
9542
9543 #define HBLANK_START_COUNT_8 0
9544 #define HBLANK_START_COUNT_16 1
9545 #define HBLANK_START_COUNT_32 2
9546 #define HBLANK_START_COUNT_64 3
9547 #define HBLANK_START_COUNT_96 4
9548 #define HBLANK_START_COUNT_128 5
9549
9550 /*
9551 * HSW - ICL power wells
9552 *
9553 * Platforms have up to 3 power well control register sets, each set
9554 * controlling up to 16 power wells via a request/status HW flag tuple:
9555 * - main (HSW_PWR_WELL_CTL[1-4])
9556 * - AUX (ICL_PWR_WELL_CTL_AUX[1-4])
9557 * - DDI (ICL_PWR_WELL_CTL_DDI[1-4])
9558 * Each control register set consists of up to 4 registers used by different
9559 * sources that can request a power well to be enabled:
9560 * - BIOS (HSW_PWR_WELL_CTL1/ICL_PWR_WELL_CTL_AUX1/ICL_PWR_WELL_CTL_DDI1)
9561 * - DRIVER (HSW_PWR_WELL_CTL2/ICL_PWR_WELL_CTL_AUX2/ICL_PWR_WELL_CTL_DDI2)
9562 * - KVMR (HSW_PWR_WELL_CTL3) (only in the main register set)
9563 * - DEBUG (HSW_PWR_WELL_CTL4/ICL_PWR_WELL_CTL_AUX4/ICL_PWR_WELL_CTL_DDI4)
9564 */
9565 #define HSW_PWR_WELL_CTL1 _MMIO(0x45400)
9566 #define HSW_PWR_WELL_CTL2 _MMIO(0x45404)
9567 #define HSW_PWR_WELL_CTL3 _MMIO(0x45408)
9568 #define HSW_PWR_WELL_CTL4 _MMIO(0x4540C)
9569 #define HSW_PWR_WELL_CTL_REQ(pw_idx) (0x2 << ((pw_idx) * 2))
9570 #define HSW_PWR_WELL_CTL_STATE(pw_idx) (0x1 << ((pw_idx) * 2))
9571
9572 /* HSW/BDW power well */
9573 #define HSW_PW_CTL_IDX_GLOBAL 15
9574
9575 /* SKL/BXT/GLK/CNL power wells */
9576 #define SKL_PW_CTL_IDX_PW_2 15
9577 #define SKL_PW_CTL_IDX_PW_1 14
9578 #define CNL_PW_CTL_IDX_AUX_F 12
9579 #define CNL_PW_CTL_IDX_AUX_D 11
9580 #define GLK_PW_CTL_IDX_AUX_C 10
9581 #define GLK_PW_CTL_IDX_AUX_B 9
9582 #define GLK_PW_CTL_IDX_AUX_A 8
9583 #define CNL_PW_CTL_IDX_DDI_F 6
9584 #define SKL_PW_CTL_IDX_DDI_D 4
9585 #define SKL_PW_CTL_IDX_DDI_C 3
9586 #define SKL_PW_CTL_IDX_DDI_B 2
9587 #define SKL_PW_CTL_IDX_DDI_A_E 1
9588 #define GLK_PW_CTL_IDX_DDI_A 1
9589 #define SKL_PW_CTL_IDX_MISC_IO 0
9590
9591 /* ICL/TGL - power wells */
9592 #define TGL_PW_CTL_IDX_PW_5 4
9593 #define ICL_PW_CTL_IDX_PW_4 3
9594 #define ICL_PW_CTL_IDX_PW_3 2
9595 #define ICL_PW_CTL_IDX_PW_2 1
9596 #define ICL_PW_CTL_IDX_PW_1 0
9597
9598 #define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440)
9599 #define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444)
9600 #define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C)
9601 #define TGL_PW_CTL_IDX_AUX_TBT6 14
9602 #define TGL_PW_CTL_IDX_AUX_TBT5 13
9603 #define TGL_PW_CTL_IDX_AUX_TBT4 12
9604 #define ICL_PW_CTL_IDX_AUX_TBT4 11
9605 #define TGL_PW_CTL_IDX_AUX_TBT3 11
9606 #define ICL_PW_CTL_IDX_AUX_TBT3 10
9607 #define TGL_PW_CTL_IDX_AUX_TBT2 10
9608 #define ICL_PW_CTL_IDX_AUX_TBT2 9
9609 #define TGL_PW_CTL_IDX_AUX_TBT1 9
9610 #define ICL_PW_CTL_IDX_AUX_TBT1 8
9611 #define TGL_PW_CTL_IDX_AUX_TC6 8
9612 #define TGL_PW_CTL_IDX_AUX_TC5 7
9613 #define TGL_PW_CTL_IDX_AUX_TC4 6
9614 #define ICL_PW_CTL_IDX_AUX_F 5
9615 #define TGL_PW_CTL_IDX_AUX_TC3 5
9616 #define ICL_PW_CTL_IDX_AUX_E 4
9617 #define TGL_PW_CTL_IDX_AUX_TC2 4
9618 #define ICL_PW_CTL_IDX_AUX_D 3
9619 #define TGL_PW_CTL_IDX_AUX_TC1 3
9620 #define ICL_PW_CTL_IDX_AUX_C 2
9621 #define ICL_PW_CTL_IDX_AUX_B 1
9622 #define ICL_PW_CTL_IDX_AUX_A 0
9623
9624 #define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450)
9625 #define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454)
9626 #define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C)
9627 #define TGL_PW_CTL_IDX_DDI_TC6 8
9628 #define TGL_PW_CTL_IDX_DDI_TC5 7
9629 #define TGL_PW_CTL_IDX_DDI_TC4 6
9630 #define ICL_PW_CTL_IDX_DDI_F 5
9631 #define TGL_PW_CTL_IDX_DDI_TC3 5
9632 #define ICL_PW_CTL_IDX_DDI_E 4
9633 #define TGL_PW_CTL_IDX_DDI_TC2 4
9634 #define ICL_PW_CTL_IDX_DDI_D 3
9635 #define TGL_PW_CTL_IDX_DDI_TC1 3
9636 #define ICL_PW_CTL_IDX_DDI_C 2
9637 #define ICL_PW_CTL_IDX_DDI_B 1
9638 #define ICL_PW_CTL_IDX_DDI_A 0
9639
9640 /* HSW - power well misc debug registers */
9641 #define HSW_PWR_WELL_CTL5 _MMIO(0x45410)
9642 #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1 << 31)
9643 #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1 << 20)
9644 #define HSW_PWR_WELL_FORCE_ON (1 << 19)
9645 #define HSW_PWR_WELL_CTL6 _MMIO(0x45414)
9646
9647 /* SKL Fuse Status */
9648 enum skl_power_gate {
9649 SKL_PG0,
9650 SKL_PG1,
9651 SKL_PG2,
9652 ICL_PG3,
9653 ICL_PG4,
9654 };
9655
9656 #define SKL_FUSE_STATUS _MMIO(0x42000)
9657 #define SKL_FUSE_DOWNLOAD_STATUS (1 << 31)
9658 /*
9659 * PG0 is HW controlled, so doesn't have a corresponding power well control knob
9660 * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2
9661 */
9662 #define SKL_PW_CTL_IDX_TO_PG(pw_idx) \
9663 ((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1)
9664 /*
9665 * PG0 is HW controlled, so doesn't have a corresponding power well control knob
9666 * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4
9667 */
9668 #define ICL_PW_CTL_IDX_TO_PG(pw_idx) \
9669 ((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1)
9670 #define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg)))
9671
9672 #define _CNL_AUX_REG_IDX(pw_idx) ((pw_idx) - GLK_PW_CTL_IDX_AUX_B)
9673 #define _CNL_AUX_ANAOVRD1_B 0x162250
9674 #define _CNL_AUX_ANAOVRD1_C 0x162210
9675 #define _CNL_AUX_ANAOVRD1_D 0x1622D0
9676 #define _CNL_AUX_ANAOVRD1_F 0x162A90
9677 #define CNL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_CNL_AUX_REG_IDX(pw_idx), \
9678 _CNL_AUX_ANAOVRD1_B, \
9679 _CNL_AUX_ANAOVRD1_C, \
9680 _CNL_AUX_ANAOVRD1_D, \
9681 _CNL_AUX_ANAOVRD1_F))
9682 #define CNL_AUX_ANAOVRD1_ENABLE (1 << 16)
9683 #define CNL_AUX_ANAOVRD1_LDO_BYPASS (1 << 23)
9684
9685 #define _ICL_AUX_REG_IDX(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
9686 #define _ICL_AUX_ANAOVRD1_A 0x162398
9687 #define _ICL_AUX_ANAOVRD1_B 0x6C398
9688 #define ICL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_ICL_AUX_REG_IDX(pw_idx), \
9689 _ICL_AUX_ANAOVRD1_A, \
9690 _ICL_AUX_ANAOVRD1_B))
9691 #define ICL_AUX_ANAOVRD1_LDO_BYPASS (1 << 7)
9692 #define ICL_AUX_ANAOVRD1_ENABLE (1 << 0)
9693
9694 /* HDCP Key Registers */
9695 #define HDCP_KEY_CONF _MMIO(0x66c00)
9696 #define HDCP_AKSV_SEND_TRIGGER BIT(31)
9697 #define HDCP_CLEAR_KEYS_TRIGGER BIT(30)
9698 #define HDCP_KEY_LOAD_TRIGGER BIT(8)
9699 #define HDCP_KEY_STATUS _MMIO(0x66c04)
9700 #define HDCP_FUSE_IN_PROGRESS BIT(7)
9701 #define HDCP_FUSE_ERROR BIT(6)
9702 #define HDCP_FUSE_DONE BIT(5)
9703 #define HDCP_KEY_LOAD_STATUS BIT(1)
9704 #define HDCP_KEY_LOAD_DONE BIT(0)
9705 #define HDCP_AKSV_LO _MMIO(0x66c10)
9706 #define HDCP_AKSV_HI _MMIO(0x66c14)
9707
9708 /* HDCP Repeater Registers */
9709 #define HDCP_REP_CTL _MMIO(0x66d00)
9710 #define HDCP_TRANSA_REP_PRESENT BIT(31)
9711 #define HDCP_TRANSB_REP_PRESENT BIT(30)
9712 #define HDCP_TRANSC_REP_PRESENT BIT(29)
9713 #define HDCP_TRANSD_REP_PRESENT BIT(28)
9714 #define HDCP_DDIB_REP_PRESENT BIT(30)
9715 #define HDCP_DDIA_REP_PRESENT BIT(29)
9716 #define HDCP_DDIC_REP_PRESENT BIT(28)
9717 #define HDCP_DDID_REP_PRESENT BIT(27)
9718 #define HDCP_DDIF_REP_PRESENT BIT(26)
9719 #define HDCP_DDIE_REP_PRESENT BIT(25)
9720 #define HDCP_TRANSA_SHA1_M0 (1 << 20)
9721 #define HDCP_TRANSB_SHA1_M0 (2 << 20)
9722 #define HDCP_TRANSC_SHA1_M0 (3 << 20)
9723 #define HDCP_TRANSD_SHA1_M0 (4 << 20)
9724 #define HDCP_DDIB_SHA1_M0 (1 << 20)
9725 #define HDCP_DDIA_SHA1_M0 (2 << 20)
9726 #define HDCP_DDIC_SHA1_M0 (3 << 20)
9727 #define HDCP_DDID_SHA1_M0 (4 << 20)
9728 #define HDCP_DDIF_SHA1_M0 (5 << 20)
9729 #define HDCP_DDIE_SHA1_M0 (6 << 20) /* Bspec says 5? */
9730 #define HDCP_SHA1_BUSY BIT(16)
9731 #define HDCP_SHA1_READY BIT(17)
9732 #define HDCP_SHA1_COMPLETE BIT(18)
9733 #define HDCP_SHA1_V_MATCH BIT(19)
9734 #define HDCP_SHA1_TEXT_32 (1 << 1)
9735 #define HDCP_SHA1_COMPLETE_HASH (2 << 1)
9736 #define HDCP_SHA1_TEXT_24 (4 << 1)
9737 #define HDCP_SHA1_TEXT_16 (5 << 1)
9738 #define HDCP_SHA1_TEXT_8 (6 << 1)
9739 #define HDCP_SHA1_TEXT_0 (7 << 1)
9740 #define HDCP_SHA_V_PRIME_H0 _MMIO(0x66d04)
9741 #define HDCP_SHA_V_PRIME_H1 _MMIO(0x66d08)
9742 #define HDCP_SHA_V_PRIME_H2 _MMIO(0x66d0C)
9743 #define HDCP_SHA_V_PRIME_H3 _MMIO(0x66d10)
9744 #define HDCP_SHA_V_PRIME_H4 _MMIO(0x66d14)
9745 #define HDCP_SHA_V_PRIME(h) _MMIO((0x66d04 + (h) * 4))
9746 #define HDCP_SHA_TEXT _MMIO(0x66d18)
9747
9748 /* HDCP Auth Registers */
9749 #define _PORTA_HDCP_AUTHENC 0x66800
9750 #define _PORTB_HDCP_AUTHENC 0x66500
9751 #define _PORTC_HDCP_AUTHENC 0x66600
9752 #define _PORTD_HDCP_AUTHENC 0x66700
9753 #define _PORTE_HDCP_AUTHENC 0x66A00
9754 #define _PORTF_HDCP_AUTHENC 0x66900
9755 #define _PORT_HDCP_AUTHENC(port, x) _MMIO(_PICK(port, \
9756 _PORTA_HDCP_AUTHENC, \
9757 _PORTB_HDCP_AUTHENC, \
9758 _PORTC_HDCP_AUTHENC, \
9759 _PORTD_HDCP_AUTHENC, \
9760 _PORTE_HDCP_AUTHENC, \
9761 _PORTF_HDCP_AUTHENC) + (x))
9762 #define PORT_HDCP_CONF(port) _PORT_HDCP_AUTHENC(port, 0x0)
9763 #define _TRANSA_HDCP_CONF 0x66400
9764 #define _TRANSB_HDCP_CONF 0x66500
9765 #define TRANS_HDCP_CONF(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_CONF, \
9766 _TRANSB_HDCP_CONF)
9767 #define HDCP_CONF(dev_priv, trans, port) \
9768 (INTEL_GEN(dev_priv) >= 12 ? \
9769 TRANS_HDCP_CONF(trans) : \
9770 PORT_HDCP_CONF(port))
9771
9772 #define HDCP_CONF_CAPTURE_AN BIT(0)
9773 #define HDCP_CONF_AUTH_AND_ENC (BIT(1) | BIT(0))
9774 #define PORT_HDCP_ANINIT(port) _PORT_HDCP_AUTHENC(port, 0x4)
9775 #define _TRANSA_HDCP_ANINIT 0x66404
9776 #define _TRANSB_HDCP_ANINIT 0x66504
9777 #define TRANS_HDCP_ANINIT(trans) _MMIO_TRANS(trans, \
9778 _TRANSA_HDCP_ANINIT, \
9779 _TRANSB_HDCP_ANINIT)
9780 #define HDCP_ANINIT(dev_priv, trans, port) \
9781 (INTEL_GEN(dev_priv) >= 12 ? \
9782 TRANS_HDCP_ANINIT(trans) : \
9783 PORT_HDCP_ANINIT(port))
9784
9785 #define PORT_HDCP_ANLO(port) _PORT_HDCP_AUTHENC(port, 0x8)
9786 #define _TRANSA_HDCP_ANLO 0x66408
9787 #define _TRANSB_HDCP_ANLO 0x66508
9788 #define TRANS_HDCP_ANLO(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_ANLO, \
9789 _TRANSB_HDCP_ANLO)
9790 #define HDCP_ANLO(dev_priv, trans, port) \
9791 (INTEL_GEN(dev_priv) >= 12 ? \
9792 TRANS_HDCP_ANLO(trans) : \
9793 PORT_HDCP_ANLO(port))
9794
9795 #define PORT_HDCP_ANHI(port) _PORT_HDCP_AUTHENC(port, 0xC)
9796 #define _TRANSA_HDCP_ANHI 0x6640C
9797 #define _TRANSB_HDCP_ANHI 0x6650C
9798 #define TRANS_HDCP_ANHI(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_ANHI, \
9799 _TRANSB_HDCP_ANHI)
9800 #define HDCP_ANHI(dev_priv, trans, port) \
9801 (INTEL_GEN(dev_priv) >= 12 ? \
9802 TRANS_HDCP_ANHI(trans) : \
9803 PORT_HDCP_ANHI(port))
9804
9805 #define PORT_HDCP_BKSVLO(port) _PORT_HDCP_AUTHENC(port, 0x10)
9806 #define _TRANSA_HDCP_BKSVLO 0x66410
9807 #define _TRANSB_HDCP_BKSVLO 0x66510
9808 #define TRANS_HDCP_BKSVLO(trans) _MMIO_TRANS(trans, \
9809 _TRANSA_HDCP_BKSVLO, \
9810 _TRANSB_HDCP_BKSVLO)
9811 #define HDCP_BKSVLO(dev_priv, trans, port) \
9812 (INTEL_GEN(dev_priv) >= 12 ? \
9813 TRANS_HDCP_BKSVLO(trans) : \
9814 PORT_HDCP_BKSVLO(port))
9815
9816 #define PORT_HDCP_BKSVHI(port) _PORT_HDCP_AUTHENC(port, 0x14)
9817 #define _TRANSA_HDCP_BKSVHI 0x66414
9818 #define _TRANSB_HDCP_BKSVHI 0x66514
9819 #define TRANS_HDCP_BKSVHI(trans) _MMIO_TRANS(trans, \
9820 _TRANSA_HDCP_BKSVHI, \
9821 _TRANSB_HDCP_BKSVHI)
9822 #define HDCP_BKSVHI(dev_priv, trans, port) \
9823 (INTEL_GEN(dev_priv) >= 12 ? \
9824 TRANS_HDCP_BKSVHI(trans) : \
9825 PORT_HDCP_BKSVHI(port))
9826
9827 #define PORT_HDCP_RPRIME(port) _PORT_HDCP_AUTHENC(port, 0x18)
9828 #define _TRANSA_HDCP_RPRIME 0x66418
9829 #define _TRANSB_HDCP_RPRIME 0x66518
9830 #define TRANS_HDCP_RPRIME(trans) _MMIO_TRANS(trans, \
9831 _TRANSA_HDCP_RPRIME, \
9832 _TRANSB_HDCP_RPRIME)
9833 #define HDCP_RPRIME(dev_priv, trans, port) \
9834 (INTEL_GEN(dev_priv) >= 12 ? \
9835 TRANS_HDCP_RPRIME(trans) : \
9836 PORT_HDCP_RPRIME(port))
9837
9838 #define PORT_HDCP_STATUS(port) _PORT_HDCP_AUTHENC(port, 0x1C)
9839 #define _TRANSA_HDCP_STATUS 0x6641C
9840 #define _TRANSB_HDCP_STATUS 0x6651C
9841 #define TRANS_HDCP_STATUS(trans) _MMIO_TRANS(trans, \
9842 _TRANSA_HDCP_STATUS, \
9843 _TRANSB_HDCP_STATUS)
9844 #define HDCP_STATUS(dev_priv, trans, port) \
9845 (INTEL_GEN(dev_priv) >= 12 ? \
9846 TRANS_HDCP_STATUS(trans) : \
9847 PORT_HDCP_STATUS(port))
9848
9849 #define HDCP_STATUS_STREAM_A_ENC BIT(31)
9850 #define HDCP_STATUS_STREAM_B_ENC BIT(30)
9851 #define HDCP_STATUS_STREAM_C_ENC BIT(29)
9852 #define HDCP_STATUS_STREAM_D_ENC BIT(28)
9853 #define HDCP_STATUS_AUTH BIT(21)
9854 #define HDCP_STATUS_ENC BIT(20)
9855 #define HDCP_STATUS_RI_MATCH BIT(19)
9856 #define HDCP_STATUS_R0_READY BIT(18)
9857 #define HDCP_STATUS_AN_READY BIT(17)
9858 #define HDCP_STATUS_CIPHER BIT(16)
9859 #define HDCP_STATUS_FRAME_CNT(x) (((x) >> 8) & 0xff)
9860
9861 /* HDCP2.2 Registers */
9862 #define _PORTA_HDCP2_BASE 0x66800
9863 #define _PORTB_HDCP2_BASE 0x66500
9864 #define _PORTC_HDCP2_BASE 0x66600
9865 #define _PORTD_HDCP2_BASE 0x66700
9866 #define _PORTE_HDCP2_BASE 0x66A00
9867 #define _PORTF_HDCP2_BASE 0x66900
9868 #define _PORT_HDCP2_BASE(port, x) _MMIO(_PICK((port), \
9869 _PORTA_HDCP2_BASE, \
9870 _PORTB_HDCP2_BASE, \
9871 _PORTC_HDCP2_BASE, \
9872 _PORTD_HDCP2_BASE, \
9873 _PORTE_HDCP2_BASE, \
9874 _PORTF_HDCP2_BASE) + (x))
9875 #define PORT_HDCP2_AUTH(port) _PORT_HDCP2_BASE(port, 0x98)
9876 #define _TRANSA_HDCP2_AUTH 0x66498
9877 #define _TRANSB_HDCP2_AUTH 0x66598
9878 #define TRANS_HDCP2_AUTH(trans) _MMIO_TRANS(trans, _TRANSA_HDCP2_AUTH, \
9879 _TRANSB_HDCP2_AUTH)
9880 #define AUTH_LINK_AUTHENTICATED BIT(31)
9881 #define AUTH_LINK_TYPE BIT(30)
9882 #define AUTH_FORCE_CLR_INPUTCTR BIT(19)
9883 #define AUTH_CLR_KEYS BIT(18)
9884 #define HDCP2_AUTH(dev_priv, trans, port) \
9885 (INTEL_GEN(dev_priv) >= 12 ? \
9886 TRANS_HDCP2_AUTH(trans) : \
9887 PORT_HDCP2_AUTH(port))
9888
9889 #define PORT_HDCP2_CTL(port) _PORT_HDCP2_BASE(port, 0xB0)
9890 #define _TRANSA_HDCP2_CTL 0x664B0
9891 #define _TRANSB_HDCP2_CTL 0x665B0
9892 #define TRANS_HDCP2_CTL(trans) _MMIO_TRANS(trans, _TRANSA_HDCP2_CTL, \
9893 _TRANSB_HDCP2_CTL)
9894 #define CTL_LINK_ENCRYPTION_REQ BIT(31)
9895 #define HDCP2_CTL(dev_priv, trans, port) \
9896 (INTEL_GEN(dev_priv) >= 12 ? \
9897 TRANS_HDCP2_CTL(trans) : \
9898 PORT_HDCP2_CTL(port))
9899
9900 #define PORT_HDCP2_STATUS(port) _PORT_HDCP2_BASE(port, 0xB4)
9901 #define _TRANSA_HDCP2_STATUS 0x664B4
9902 #define _TRANSB_HDCP2_STATUS 0x665B4
9903 #define TRANS_HDCP2_STATUS(trans) _MMIO_TRANS(trans, \
9904 _TRANSA_HDCP2_STATUS, \
9905 _TRANSB_HDCP2_STATUS)
9906 #define LINK_TYPE_STATUS BIT(22)
9907 #define LINK_AUTH_STATUS BIT(21)
9908 #define LINK_ENCRYPTION_STATUS BIT(20)
9909 #define HDCP2_STATUS(dev_priv, trans, port) \
9910 (INTEL_GEN(dev_priv) >= 12 ? \
9911 TRANS_HDCP2_STATUS(trans) : \
9912 PORT_HDCP2_STATUS(port))
9913
9914 /* Per-pipe DDI Function Control */
9915 #define _TRANS_DDI_FUNC_CTL_A 0x60400
9916 #define _TRANS_DDI_FUNC_CTL_B 0x61400
9917 #define _TRANS_DDI_FUNC_CTL_C 0x62400
9918 #define _TRANS_DDI_FUNC_CTL_D 0x63400
9919 #define _TRANS_DDI_FUNC_CTL_EDP 0x6F400
9920 #define _TRANS_DDI_FUNC_CTL_DSI0 0x6b400
9921 #define _TRANS_DDI_FUNC_CTL_DSI1 0x6bc00
9922 #define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A)
9923
9924 #define TRANS_DDI_FUNC_ENABLE (1 << 31)
9925 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */
9926 #define TRANS_DDI_PORT_SHIFT 28
9927 #define TGL_TRANS_DDI_PORT_SHIFT 27
9928 #define TRANS_DDI_PORT_MASK (7 << TRANS_DDI_PORT_SHIFT)
9929 #define TGL_TRANS_DDI_PORT_MASK (0xf << TGL_TRANS_DDI_PORT_SHIFT)
9930 #define TRANS_DDI_SELECT_PORT(x) ((x) << TRANS_DDI_PORT_SHIFT)
9931 #define TGL_TRANS_DDI_SELECT_PORT(x) (((x) + 1) << TGL_TRANS_DDI_PORT_SHIFT)
9932 #define TRANS_DDI_FUNC_CTL_VAL_TO_PORT(val) (((val) & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT)
9933 #define TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(val) ((((val) & TGL_TRANS_DDI_PORT_MASK) >> TGL_TRANS_DDI_PORT_SHIFT) - 1)
9934 #define TRANS_DDI_MODE_SELECT_MASK (7 << 24)
9935 #define TRANS_DDI_MODE_SELECT_HDMI (0 << 24)
9936 #define TRANS_DDI_MODE_SELECT_DVI (1 << 24)
9937 #define TRANS_DDI_MODE_SELECT_DP_SST (2 << 24)
9938 #define TRANS_DDI_MODE_SELECT_DP_MST (3 << 24)
9939 #define TRANS_DDI_MODE_SELECT_FDI (4 << 24)
9940 #define TRANS_DDI_BPC_MASK (7 << 20)
9941 #define TRANS_DDI_BPC_8 (0 << 20)
9942 #define TRANS_DDI_BPC_10 (1 << 20)
9943 #define TRANS_DDI_BPC_6 (2 << 20)
9944 #define TRANS_DDI_BPC_12 (3 << 20)
9945 #define TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK REG_GENMASK(19, 18) /* bdw-cnl */
9946 #define TRANS_DDI_PORT_SYNC_MASTER_SELECT(x) REG_FIELD_PREP(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, (x))
9947 #define TRANS_DDI_PVSYNC (1 << 17)
9948 #define TRANS_DDI_PHSYNC (1 << 16)
9949 #define TRANS_DDI_PORT_SYNC_ENABLE REG_BIT(15) /* bdw-cnl */
9950 #define TRANS_DDI_EDP_INPUT_MASK (7 << 12)
9951 #define TRANS_DDI_EDP_INPUT_A_ON (0 << 12)
9952 #define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12)
9953 #define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12)
9954 #define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12)
9955 #define TRANS_DDI_EDP_INPUT_D_ONOFF (7 << 12)
9956 #define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(11, 10)
9957 #define TRANS_DDI_MST_TRANSPORT_SELECT(trans) \
9958 REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans)
9959 #define TRANS_DDI_HDCP_SIGNALLING (1 << 9)
9960 #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8)
9961 #define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7)
9962 #define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6)
9963 #define TRANS_DDI_BFI_ENABLE (1 << 4)
9964 #define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1 << 4)
9965 #define TRANS_DDI_HDMI_SCRAMBLING (1 << 0)
9966 #define TRANS_DDI_HDMI_SCRAMBLING_MASK (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE \
9967 | TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \
9968 | TRANS_DDI_HDMI_SCRAMBLING)
9969
9970 #define _TRANS_DDI_FUNC_CTL2_A 0x60404
9971 #define _TRANS_DDI_FUNC_CTL2_B 0x61404
9972 #define _TRANS_DDI_FUNC_CTL2_C 0x62404
9973 #define _TRANS_DDI_FUNC_CTL2_EDP 0x6f404
9974 #define _TRANS_DDI_FUNC_CTL2_DSI0 0x6b404
9975 #define _TRANS_DDI_FUNC_CTL2_DSI1 0x6bc04
9976 #define TRANS_DDI_FUNC_CTL2(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL2_A)
9977 #define PORT_SYNC_MODE_ENABLE REG_BIT(4)
9978 #define PORT_SYNC_MODE_MASTER_SELECT_MASK REG_GENMASK(2, 0)
9979 #define PORT_SYNC_MODE_MASTER_SELECT(x) REG_FIELD_PREP(PORT_SYNC_MODE_MASTER_SELECT_MASK, (x))
9980
9981 /* DisplayPort Transport Control */
9982 #define _DP_TP_CTL_A 0x64040
9983 #define _DP_TP_CTL_B 0x64140
9984 #define _TGL_DP_TP_CTL_A 0x60540
9985 #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
9986 #define TGL_DP_TP_CTL(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_CTL_A)
9987 #define DP_TP_CTL_ENABLE (1 << 31)
9988 #define DP_TP_CTL_FEC_ENABLE (1 << 30)
9989 #define DP_TP_CTL_MODE_SST (0 << 27)
9990 #define DP_TP_CTL_MODE_MST (1 << 27)
9991 #define DP_TP_CTL_FORCE_ACT (1 << 25)
9992 #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18)
9993 #define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15)
9994 #define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8)
9995 #define DP_TP_CTL_LINK_TRAIN_PAT1 (0 << 8)
9996 #define DP_TP_CTL_LINK_TRAIN_PAT2 (1 << 8)
9997 #define DP_TP_CTL_LINK_TRAIN_PAT3 (4 << 8)
9998 #define DP_TP_CTL_LINK_TRAIN_PAT4 (5 << 8)
9999 #define DP_TP_CTL_LINK_TRAIN_IDLE (2 << 8)
10000 #define DP_TP_CTL_LINK_TRAIN_NORMAL (3 << 8)
10001 #define DP_TP_CTL_SCRAMBLE_DISABLE (1 << 7)
10002
10003 /* DisplayPort Transport Status */
10004 #define _DP_TP_STATUS_A 0x64044
10005 #define _DP_TP_STATUS_B 0x64144
10006 #define _TGL_DP_TP_STATUS_A 0x60544
10007 #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
10008 #define TGL_DP_TP_STATUS(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_STATUS_A)
10009 #define DP_TP_STATUS_FEC_ENABLE_LIVE (1 << 28)
10010 #define DP_TP_STATUS_IDLE_DONE (1 << 25)
10011 #define DP_TP_STATUS_ACT_SENT (1 << 24)
10012 #define DP_TP_STATUS_MODE_STATUS_MST (1 << 23)
10013 #define DP_TP_STATUS_AUTOTRAIN_DONE (1 << 12)
10014 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8)
10015 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4)
10016 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0)
10017
10018 /* DDI Buffer Control */
10019 #define _DDI_BUF_CTL_A 0x64000
10020 #define _DDI_BUF_CTL_B 0x64100
10021 #define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B)
10022 #define DDI_BUF_CTL_ENABLE (1 << 31)
10023 #define DDI_BUF_TRANS_SELECT(n) ((n) << 24)
10024 #define DDI_BUF_EMP_MASK (0xf << 24)
10025 #define DDI_BUF_PORT_REVERSAL (1 << 16)
10026 #define DDI_BUF_IS_IDLE (1 << 7)
10027 #define DDI_A_4_LANES (1 << 4)
10028 #define DDI_PORT_WIDTH(width) (((width) - 1) << 1)
10029 #define DDI_PORT_WIDTH_MASK (7 << 1)
10030 #define DDI_PORT_WIDTH_SHIFT 1
10031 #define DDI_INIT_DISPLAY_DETECTED (1 << 0)
10032
10033 /* DDI Buffer Translations */
10034 #define _DDI_BUF_TRANS_A 0x64E00
10035 #define _DDI_BUF_TRANS_B 0x64E60
10036 #define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8)
10037 #define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31)
10038 #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
10039
10040 /* DDI DP Compliance Control */
10041 #define _DDI_DP_COMP_CTL_A 0x605F0
10042 #define _DDI_DP_COMP_CTL_B 0x615F0
10043 #define DDI_DP_COMP_CTL(pipe) _MMIO_PIPE(pipe, _DDI_DP_COMP_CTL_A, _DDI_DP_COMP_CTL_B)
10044 #define DDI_DP_COMP_CTL_ENABLE (1 << 31)
10045 #define DDI_DP_COMP_CTL_D10_2 (0 << 28)
10046 #define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28)
10047 #define DDI_DP_COMP_CTL_PRBS7 (2 << 28)
10048 #define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28)
10049 #define DDI_DP_COMP_CTL_HBR2 (4 << 28)
10050 #define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28)
10051 #define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0)
10052
10053 /* DDI DP Compliance Pattern */
10054 #define _DDI_DP_COMP_PAT_A 0x605F4
10055 #define _DDI_DP_COMP_PAT_B 0x615F4
10056 #define DDI_DP_COMP_PAT(pipe, i) _MMIO(_PIPE(pipe, _DDI_DP_COMP_PAT_A, _DDI_DP_COMP_PAT_B) + (i) * 4)
10057
10058 /* Sideband Interface (SBI) is programmed indirectly, via
10059 * SBI_ADDR, which contains the register offset; and SBI_DATA,
10060 * which contains the payload */
10061 #define SBI_ADDR _MMIO(0xC6000)
10062 #define SBI_DATA _MMIO(0xC6004)
10063 #define SBI_CTL_STAT _MMIO(0xC6008)
10064 #define SBI_CTL_DEST_ICLK (0x0 << 16)
10065 #define SBI_CTL_DEST_MPHY (0x1 << 16)
10066 #define SBI_CTL_OP_IORD (0x2 << 8)
10067 #define SBI_CTL_OP_IOWR (0x3 << 8)
10068 #define SBI_CTL_OP_CRRD (0x6 << 8)
10069 #define SBI_CTL_OP_CRWR (0x7 << 8)
10070 #define SBI_RESPONSE_FAIL (0x1 << 1)
10071 #define SBI_RESPONSE_SUCCESS (0x0 << 1)
10072 #define SBI_BUSY (0x1 << 0)
10073 #define SBI_READY (0x0 << 0)
10074
10075 /* SBI offsets */
10076 #define SBI_SSCDIVINTPHASE 0x0200
10077 #define SBI_SSCDIVINTPHASE6 0x0600
10078 #define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1
10079 #define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f << 1)
10080 #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x) << 1)
10081 #define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8
10082 #define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f << 8)
10083 #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x) << 8)
10084 #define SBI_SSCDIVINTPHASE_DIR(x) ((x) << 15)
10085 #define SBI_SSCDIVINTPHASE_PROPAGATE (1 << 0)
10086 #define SBI_SSCDITHPHASE 0x0204
10087 #define SBI_SSCCTL 0x020c
10088 #define SBI_SSCCTL6 0x060C
10089 #define SBI_SSCCTL_PATHALT (1 << 3)
10090 #define SBI_SSCCTL_DISABLE (1 << 0)
10091 #define SBI_SSCAUXDIV6 0x0610
10092 #define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4
10093 #define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1 << 4)
10094 #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x) << 4)
10095 #define SBI_DBUFF0 0x2a00
10096 #define SBI_GEN0 0x1f00
10097 #define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1 << 0)
10098
10099 /* LPT PIXCLK_GATE */
10100 #define PIXCLK_GATE _MMIO(0xC6020)
10101 #define PIXCLK_GATE_UNGATE (1 << 0)
10102 #define PIXCLK_GATE_GATE (0 << 0)
10103
10104 /* SPLL */
10105 #define SPLL_CTL _MMIO(0x46020)
10106 #define SPLL_PLL_ENABLE (1 << 31)
10107 #define SPLL_REF_BCLK (0 << 28)
10108 #define SPLL_REF_MUXED_SSC (1 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */
10109 #define SPLL_REF_NON_SSC_HSW (2 << 28)
10110 #define SPLL_REF_PCH_SSC_BDW (2 << 28)
10111 #define SPLL_REF_LCPLL (3 << 28)
10112 #define SPLL_REF_MASK (3 << 28)
10113 #define SPLL_FREQ_810MHz (0 << 26)
10114 #define SPLL_FREQ_1350MHz (1 << 26)
10115 #define SPLL_FREQ_2700MHz (2 << 26)
10116 #define SPLL_FREQ_MASK (3 << 26)
10117
10118 /* WRPLL */
10119 #define _WRPLL_CTL1 0x46040
10120 #define _WRPLL_CTL2 0x46060
10121 #define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2)
10122 #define WRPLL_PLL_ENABLE (1 << 31)
10123 #define WRPLL_REF_BCLK (0 << 28)
10124 #define WRPLL_REF_PCH_SSC (1 << 28)
10125 #define WRPLL_REF_MUXED_SSC_BDW (2 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */
10126 #define WRPLL_REF_SPECIAL_HSW (2 << 28) /* muxed SSC (ULT), non-SSC (non-ULT) */
10127 #define WRPLL_REF_LCPLL (3 << 28)
10128 #define WRPLL_REF_MASK (3 << 28)
10129 /* WRPLL divider programming */
10130 #define WRPLL_DIVIDER_REFERENCE(x) ((x) << 0)
10131 #define WRPLL_DIVIDER_REF_MASK (0xff)
10132 #define WRPLL_DIVIDER_POST(x) ((x) << 8)
10133 #define WRPLL_DIVIDER_POST_MASK (0x3f << 8)
10134 #define WRPLL_DIVIDER_POST_SHIFT 8
10135 #define WRPLL_DIVIDER_FEEDBACK(x) ((x) << 16)
10136 #define WRPLL_DIVIDER_FB_SHIFT 16
10137 #define WRPLL_DIVIDER_FB_MASK (0xff << 16)
10138
10139 /* Port clock selection */
10140 #define _PORT_CLK_SEL_A 0x46100
10141 #define _PORT_CLK_SEL_B 0x46104
10142 #define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B)
10143 #define PORT_CLK_SEL_LCPLL_2700 (0 << 29)
10144 #define PORT_CLK_SEL_LCPLL_1350 (1 << 29)
10145 #define PORT_CLK_SEL_LCPLL_810 (2 << 29)
10146 #define PORT_CLK_SEL_SPLL (3 << 29)
10147 #define PORT_CLK_SEL_WRPLL(pll) (((pll) + 4) << 29)
10148 #define PORT_CLK_SEL_WRPLL1 (4 << 29)
10149 #define PORT_CLK_SEL_WRPLL2 (5 << 29)
10150 #define PORT_CLK_SEL_NONE (7 << 29)
10151 #define PORT_CLK_SEL_MASK (7 << 29)
10152
10153 /* On ICL+ this is the same as PORT_CLK_SEL, but all bits change. */
10154 #define DDI_CLK_SEL(port) PORT_CLK_SEL(port)
10155 #define DDI_CLK_SEL_NONE (0x0 << 28)
10156 #define DDI_CLK_SEL_MG (0x8 << 28)
10157 #define DDI_CLK_SEL_TBT_162 (0xC << 28)
10158 #define DDI_CLK_SEL_TBT_270 (0xD << 28)
10159 #define DDI_CLK_SEL_TBT_540 (0xE << 28)
10160 #define DDI_CLK_SEL_TBT_810 (0xF << 28)
10161 #define DDI_CLK_SEL_MASK (0xF << 28)
10162
10163 /* Transcoder clock selection */
10164 #define _TRANS_CLK_SEL_A 0x46140
10165 #define _TRANS_CLK_SEL_B 0x46144
10166 #define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B)
10167 /* For each transcoder, we need to select the corresponding port clock */
10168 #define TRANS_CLK_SEL_DISABLED (0x0 << 29)
10169 #define TRANS_CLK_SEL_PORT(x) (((x) + 1) << 29)
10170 #define TGL_TRANS_CLK_SEL_DISABLED (0x0 << 28)
10171 #define TGL_TRANS_CLK_SEL_PORT(x) (((x) + 1) << 28)
10172
10173
10174 #define CDCLK_FREQ _MMIO(0x46200)
10175
10176 #define _TRANSA_MSA_MISC 0x60410
10177 #define _TRANSB_MSA_MISC 0x61410
10178 #define _TRANSC_MSA_MISC 0x62410
10179 #define _TRANS_EDP_MSA_MISC 0x6f410
10180 #define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC)
10181 /* See DP_MSA_MISC_* for the bit definitions */
10182
10183 /* LCPLL Control */
10184 #define LCPLL_CTL _MMIO(0x130040)
10185 #define LCPLL_PLL_DISABLE (1 << 31)
10186 #define LCPLL_PLL_LOCK (1 << 30)
10187 #define LCPLL_REF_NON_SSC (0 << 28)
10188 #define LCPLL_REF_BCLK (2 << 28)
10189 #define LCPLL_REF_PCH_SSC (3 << 28)
10190 #define LCPLL_REF_MASK (3 << 28)
10191 #define LCPLL_CLK_FREQ_MASK (3 << 26)
10192 #define LCPLL_CLK_FREQ_450 (0 << 26)
10193 #define LCPLL_CLK_FREQ_54O_BDW (1 << 26)
10194 #define LCPLL_CLK_FREQ_337_5_BDW (2 << 26)
10195 #define LCPLL_CLK_FREQ_675_BDW (3 << 26)
10196 #define LCPLL_CD_CLOCK_DISABLE (1 << 25)
10197 #define LCPLL_ROOT_CD_CLOCK_DISABLE (1 << 24)
10198 #define LCPLL_CD2X_CLOCK_DISABLE (1 << 23)
10199 #define LCPLL_POWER_DOWN_ALLOW (1 << 22)
10200 #define LCPLL_CD_SOURCE_FCLK (1 << 21)
10201 #define LCPLL_CD_SOURCE_FCLK_DONE (1 << 19)
10202
10203 /*
10204 * SKL Clocks
10205 */
10206
10207 /* CDCLK_CTL */
10208 #define CDCLK_CTL _MMIO(0x46000)
10209 #define CDCLK_FREQ_SEL_MASK (3 << 26)
10210 #define CDCLK_FREQ_450_432 (0 << 26)
10211 #define CDCLK_FREQ_540 (1 << 26)
10212 #define CDCLK_FREQ_337_308 (2 << 26)
10213 #define CDCLK_FREQ_675_617 (3 << 26)
10214 #define BXT_CDCLK_CD2X_DIV_SEL_MASK (3 << 22)
10215 #define BXT_CDCLK_CD2X_DIV_SEL_1 (0 << 22)
10216 #define BXT_CDCLK_CD2X_DIV_SEL_1_5 (1 << 22)
10217 #define BXT_CDCLK_CD2X_DIV_SEL_2 (2 << 22)
10218 #define BXT_CDCLK_CD2X_DIV_SEL_4 (3 << 22)
10219 #define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe) << 20)
10220 #define CDCLK_DIVMUX_CD_OVERRIDE (1 << 19)
10221 #define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3)
10222 #define ICL_CDCLK_CD2X_PIPE(pipe) (_PICK(pipe, 0, 2, 6) << 19)
10223 #define ICL_CDCLK_CD2X_PIPE_NONE (7 << 19)
10224 #define TGL_CDCLK_CD2X_PIPE(pipe) BXT_CDCLK_CD2X_PIPE(pipe)
10225 #define TGL_CDCLK_CD2X_PIPE_NONE ICL_CDCLK_CD2X_PIPE_NONE
10226 #define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1 << 16)
10227 #define CDCLK_FREQ_DECIMAL_MASK (0x7ff)
10228
10229 /* LCPLL_CTL */
10230 #define LCPLL1_CTL _MMIO(0x46010)
10231 #define LCPLL2_CTL _MMIO(0x46014)
10232 #define LCPLL_PLL_ENABLE (1 << 31)
10233
10234 /* DPLL control1 */
10235 #define DPLL_CTRL1 _MMIO(0x6C058)
10236 #define DPLL_CTRL1_HDMI_MODE(id) (1 << ((id) * 6 + 5))
10237 #define DPLL_CTRL1_SSC(id) (1 << ((id) * 6 + 4))
10238 #define DPLL_CTRL1_LINK_RATE_MASK(id) (7 << ((id) * 6 + 1))
10239 #define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id) * 6 + 1)
10240 #define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate) << ((id) * 6 + 1))
10241 #define DPLL_CTRL1_OVERRIDE(id) (1 << ((id) * 6))
10242 #define DPLL_CTRL1_LINK_RATE_2700 0
10243 #define DPLL_CTRL1_LINK_RATE_1350 1
10244 #define DPLL_CTRL1_LINK_RATE_810 2
10245 #define DPLL_CTRL1_LINK_RATE_1620 3
10246 #define DPLL_CTRL1_LINK_RATE_1080 4
10247 #define DPLL_CTRL1_LINK_RATE_2160 5
10248
10249 /* DPLL control2 */
10250 #define DPLL_CTRL2 _MMIO(0x6C05C)
10251 #define DPLL_CTRL2_DDI_CLK_OFF(port) (1 << ((port) + 15))
10252 #define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3 << ((port) * 3 + 1))
10253 #define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port) * 3 + 1)
10254 #define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk) << ((port) * 3 + 1))
10255 #define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1 << ((port) * 3))
10256
10257 /* DPLL Status */
10258 #define DPLL_STATUS _MMIO(0x6C060)
10259 #define DPLL_LOCK(id) (1 << ((id) * 8))
10260
10261 /* DPLL cfg */
10262 #define _DPLL1_CFGCR1 0x6C040
10263 #define _DPLL2_CFGCR1 0x6C048
10264 #define _DPLL3_CFGCR1 0x6C050
10265 #define DPLL_CFGCR1_FREQ_ENABLE (1 << 31)
10266 #define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff << 9)
10267 #define DPLL_CFGCR1_DCO_FRACTION(x) ((x) << 9)
10268 #define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff)
10269
10270 #define _DPLL1_CFGCR2 0x6C044
10271 #define _DPLL2_CFGCR2 0x6C04C
10272 #define _DPLL3_CFGCR2 0x6C054
10273 #define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff << 8)
10274 #define DPLL_CFGCR2_QDIV_RATIO(x) ((x) << 8)
10275 #define DPLL_CFGCR2_QDIV_MODE(x) ((x) << 7)
10276 #define DPLL_CFGCR2_KDIV_MASK (3 << 5)
10277 #define DPLL_CFGCR2_KDIV(x) ((x) << 5)
10278 #define DPLL_CFGCR2_KDIV_5 (0 << 5)
10279 #define DPLL_CFGCR2_KDIV_2 (1 << 5)
10280 #define DPLL_CFGCR2_KDIV_3 (2 << 5)
10281 #define DPLL_CFGCR2_KDIV_1 (3 << 5)
10282 #define DPLL_CFGCR2_PDIV_MASK (7 << 2)
10283 #define DPLL_CFGCR2_PDIV(x) ((x) << 2)
10284 #define DPLL_CFGCR2_PDIV_1 (0 << 2)
10285 #define DPLL_CFGCR2_PDIV_2 (1 << 2)
10286 #define DPLL_CFGCR2_PDIV_3 (2 << 2)
10287 #define DPLL_CFGCR2_PDIV_7 (4 << 2)
10288 #define DPLL_CFGCR2_PDIV_7_INVALID (5 << 2)
10289 #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3)
10290
10291 #define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1)
10292 #define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2)
10293
10294 /*
10295 * CNL Clocks
10296 */
10297 #define DPCLKA_CFGCR0 _MMIO(0x6C200)
10298 #define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) == PORT_F ? 23 : \
10299 (port) + 10))
10300 #define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port) == PORT_F ? 21 : \
10301 (port) * 2)
10302 #define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
10303 #define DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port) ((pll) << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
10304
10305 /* ICL Clocks */
10306 #define ICL_DPCLKA_CFGCR0 _MMIO(0x164280)
10307 #define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24))
10308 #define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10)
10309 #define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < TC_PORT_4 ? \
10310 (tc_port) + 12 : \
10311 (tc_port) - TC_PORT_4 + 21))
10312 #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2)
10313 #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
10314 #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
10315 #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) _PICK(phy, 0, 2, 4, 27)
10316 #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) \
10317 (3 << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
10318 #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) \
10319 ((pll) << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
10320
10321 /*
10322 * DG1 Clocks
10323 * First registers controls the first A and B, while the second register
10324 * controls the phy C and D. The bits on these registers are the
10325 * same, but refer to different phys
10326 */
10327 #define _DG1_DPCLKA_CFGCR0 0x164280
10328 #define _DG1_DPCLKA1_CFGCR0 0x16C280
10329 #define _DG1_DPCLKA_PHY_IDX(phy) ((phy) % 2)
10330 #define _DG1_DPCLKA_PLL_IDX(pll) ((pll) % 2)
10331 #define _DG1_PHY_DPLL_MAP(phy) ((phy) >= PHY_C ? DPLL_ID_DG1_DPLL2 : DPLL_ID_DG1_DPLL0)
10332 #define DG1_DPCLKA_CFGCR0(phy) _MMIO_PHY((phy) / 2, \
10333 _DG1_DPCLKA_CFGCR0, \
10334 _DG1_DPCLKA1_CFGCR0)
10335 #define DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT(_DG1_DPCLKA_PHY_IDX(phy) + 10)
10336 #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) (_DG1_DPCLKA_PHY_IDX(phy) * 2)
10337 #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) (_DG1_DPCLKA_PLL_IDX(pll) << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
10338 #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (0x3 << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
10339 #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_DPLL_MAP(clk_sel, phy) \
10340 (((clk_sel) >> DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) + _DG1_PHY_DPLL_MAP(phy))
10341
10342 /* CNL PLL */
10343 #define DPLL0_ENABLE 0x46010
10344 #define DPLL1_ENABLE 0x46014
10345 #define PLL_ENABLE (1 << 31)
10346 #define PLL_LOCK (1 << 30)
10347 #define PLL_POWER_ENABLE (1 << 27)
10348 #define PLL_POWER_STATE (1 << 26)
10349 #define CNL_DPLL_ENABLE(pll) _MMIO_PLL(pll, DPLL0_ENABLE, DPLL1_ENABLE)
10350
10351 #define TBT_PLL_ENABLE _MMIO(0x46020)
10352
10353 #define _MG_PLL1_ENABLE 0x46030
10354 #define _MG_PLL2_ENABLE 0x46034
10355 #define _MG_PLL3_ENABLE 0x46038
10356 #define _MG_PLL4_ENABLE 0x4603C
10357 /* Bits are the same as DPLL0_ENABLE */
10358 #define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \
10359 _MG_PLL2_ENABLE)
10360
10361 /* DG1 PLL */
10362 #define DG1_DPLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
10363 _MG_PLL1_ENABLE, _MG_PLL2_ENABLE)
10364
10365 #define _MG_REFCLKIN_CTL_PORT1 0x16892C
10366 #define _MG_REFCLKIN_CTL_PORT2 0x16992C
10367 #define _MG_REFCLKIN_CTL_PORT3 0x16A92C
10368 #define _MG_REFCLKIN_CTL_PORT4 0x16B92C
10369 #define MG_REFCLKIN_CTL_OD_2_MUX(x) ((x) << 8)
10370 #define MG_REFCLKIN_CTL_OD_2_MUX_MASK (0x7 << 8)
10371 #define MG_REFCLKIN_CTL(tc_port) _MMIO_PORT((tc_port), \
10372 _MG_REFCLKIN_CTL_PORT1, \
10373 _MG_REFCLKIN_CTL_PORT2)
10374
10375 #define _MG_CLKTOP2_CORECLKCTL1_PORT1 0x1688D8
10376 #define _MG_CLKTOP2_CORECLKCTL1_PORT2 0x1698D8
10377 #define _MG_CLKTOP2_CORECLKCTL1_PORT3 0x16A8D8
10378 #define _MG_CLKTOP2_CORECLKCTL1_PORT4 0x16B8D8
10379 #define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO(x) ((x) << 16)
10380 #define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO_MASK (0xff << 16)
10381 #define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(x) ((x) << 8)
10382 #define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK (0xff << 8)
10383 #define MG_CLKTOP2_CORECLKCTL1(tc_port) _MMIO_PORT((tc_port), \
10384 _MG_CLKTOP2_CORECLKCTL1_PORT1, \
10385 _MG_CLKTOP2_CORECLKCTL1_PORT2)
10386
10387 #define _MG_CLKTOP2_HSCLKCTL_PORT1 0x1688D4
10388 #define _MG_CLKTOP2_HSCLKCTL_PORT2 0x1698D4
10389 #define _MG_CLKTOP2_HSCLKCTL_PORT3 0x16A8D4
10390 #define _MG_CLKTOP2_HSCLKCTL_PORT4 0x16B8D4
10391 #define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(x) ((x) << 16)
10392 #define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK (0x1 << 16)
10393 #define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(x) ((x) << 14)
10394 #define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK (0x3 << 14)
10395 #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK (0x3 << 12)
10396 #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2 (0 << 12)
10397 #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3 (1 << 12)
10398 #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5 (2 << 12)
10399 #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7 (3 << 12)
10400 #define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x) ((x) << 8)
10401 #define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT 8
10402 #define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK (0xf << 8)
10403 #define MG_CLKTOP2_HSCLKCTL(tc_port) _MMIO_PORT((tc_port), \
10404 _MG_CLKTOP2_HSCLKCTL_PORT1, \
10405 _MG_CLKTOP2_HSCLKCTL_PORT2)
10406
10407 #define _MG_PLL_DIV0_PORT1 0x168A00
10408 #define _MG_PLL_DIV0_PORT2 0x169A00
10409 #define _MG_PLL_DIV0_PORT3 0x16AA00
10410 #define _MG_PLL_DIV0_PORT4 0x16BA00
10411 #define MG_PLL_DIV0_FRACNEN_H (1 << 30)
10412 #define MG_PLL_DIV0_FBDIV_FRAC_MASK (0x3fffff << 8)
10413 #define MG_PLL_DIV0_FBDIV_FRAC_SHIFT 8
10414 #define MG_PLL_DIV0_FBDIV_FRAC(x) ((x) << 8)
10415 #define MG_PLL_DIV0_FBDIV_INT_MASK (0xff << 0)
10416 #define MG_PLL_DIV0_FBDIV_INT(x) ((x) << 0)
10417 #define MG_PLL_DIV0(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV0_PORT1, \
10418 _MG_PLL_DIV0_PORT2)
10419
10420 #define _MG_PLL_DIV1_PORT1 0x168A04
10421 #define _MG_PLL_DIV1_PORT2 0x169A04
10422 #define _MG_PLL_DIV1_PORT3 0x16AA04
10423 #define _MG_PLL_DIV1_PORT4 0x16BA04
10424 #define MG_PLL_DIV1_IREF_NDIVRATIO(x) ((x) << 16)
10425 #define MG_PLL_DIV1_DITHER_DIV_1 (0 << 12)
10426 #define MG_PLL_DIV1_DITHER_DIV_2 (1 << 12)
10427 #define MG_PLL_DIV1_DITHER_DIV_4 (2 << 12)
10428 #define MG_PLL_DIV1_DITHER_DIV_8 (3 << 12)
10429 #define MG_PLL_DIV1_NDIVRATIO(x) ((x) << 4)
10430 #define MG_PLL_DIV1_FBPREDIV_MASK (0xf << 0)
10431 #define MG_PLL_DIV1_FBPREDIV(x) ((x) << 0)
10432 #define MG_PLL_DIV1(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV1_PORT1, \
10433 _MG_PLL_DIV1_PORT2)
10434
10435 #define _MG_PLL_LF_PORT1 0x168A08
10436 #define _MG_PLL_LF_PORT2 0x169A08
10437 #define _MG_PLL_LF_PORT3 0x16AA08
10438 #define _MG_PLL_LF_PORT4 0x16BA08
10439 #define MG_PLL_LF_TDCTARGETCNT(x) ((x) << 24)
10440 #define MG_PLL_LF_AFCCNTSEL_256 (0 << 20)
10441 #define MG_PLL_LF_AFCCNTSEL_512 (1 << 20)
10442 #define MG_PLL_LF_GAINCTRL(x) ((x) << 16)
10443 #define MG_PLL_LF_INT_COEFF(x) ((x) << 8)
10444 #define MG_PLL_LF_PROP_COEFF(x) ((x) << 0)
10445 #define MG_PLL_LF(tc_port) _MMIO_PORT((tc_port), _MG_PLL_LF_PORT1, \
10446 _MG_PLL_LF_PORT2)
10447
10448 #define _MG_PLL_FRAC_LOCK_PORT1 0x168A0C
10449 #define _MG_PLL_FRAC_LOCK_PORT2 0x169A0C
10450 #define _MG_PLL_FRAC_LOCK_PORT3 0x16AA0C
10451 #define _MG_PLL_FRAC_LOCK_PORT4 0x16BA0C
10452 #define MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32 (1 << 18)
10453 #define MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32 (1 << 16)
10454 #define MG_PLL_FRAC_LOCK_LOCKTHRESH(x) ((x) << 11)
10455 #define MG_PLL_FRAC_LOCK_DCODITHEREN (1 << 10)
10456 #define MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN (1 << 8)
10457 #define MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(x) ((x) << 0)
10458 #define MG_PLL_FRAC_LOCK(tc_port) _MMIO_PORT((tc_port), \
10459 _MG_PLL_FRAC_LOCK_PORT1, \
10460 _MG_PLL_FRAC_LOCK_PORT2)
10461
10462 #define _MG_PLL_SSC_PORT1 0x168A10
10463 #define _MG_PLL_SSC_PORT2 0x169A10
10464 #define _MG_PLL_SSC_PORT3 0x16AA10
10465 #define _MG_PLL_SSC_PORT4 0x16BA10
10466 #define MG_PLL_SSC_EN (1 << 28)
10467 #define MG_PLL_SSC_TYPE(x) ((x) << 26)
10468 #define MG_PLL_SSC_STEPLENGTH(x) ((x) << 16)
10469 #define MG_PLL_SSC_STEPNUM(x) ((x) << 10)
10470 #define MG_PLL_SSC_FLLEN (1 << 9)
10471 #define MG_PLL_SSC_STEPSIZE(x) ((x) << 0)
10472 #define MG_PLL_SSC(tc_port) _MMIO_PORT((tc_port), _MG_PLL_SSC_PORT1, \
10473 _MG_PLL_SSC_PORT2)
10474
10475 #define _MG_PLL_BIAS_PORT1 0x168A14
10476 #define _MG_PLL_BIAS_PORT2 0x169A14
10477 #define _MG_PLL_BIAS_PORT3 0x16AA14
10478 #define _MG_PLL_BIAS_PORT4 0x16BA14
10479 #define MG_PLL_BIAS_BIAS_GB_SEL(x) ((x) << 30)
10480 #define MG_PLL_BIAS_BIAS_GB_SEL_MASK (0x3 << 30)
10481 #define MG_PLL_BIAS_INIT_DCOAMP(x) ((x) << 24)
10482 #define MG_PLL_BIAS_INIT_DCOAMP_MASK (0x3f << 24)
10483 #define MG_PLL_BIAS_BIAS_BONUS(x) ((x) << 16)
10484 #define MG_PLL_BIAS_BIAS_BONUS_MASK (0xff << 16)
10485 #define MG_PLL_BIAS_BIASCAL_EN (1 << 15)
10486 #define MG_PLL_BIAS_CTRIM(x) ((x) << 8)
10487 #define MG_PLL_BIAS_CTRIM_MASK (0x1f << 8)
10488 #define MG_PLL_BIAS_VREF_RDAC(x) ((x) << 5)
10489 #define MG_PLL_BIAS_VREF_RDAC_MASK (0x7 << 5)
10490 #define MG_PLL_BIAS_IREFTRIM(x) ((x) << 0)
10491 #define MG_PLL_BIAS_IREFTRIM_MASK (0x1f << 0)
10492 #define MG_PLL_BIAS(tc_port) _MMIO_PORT((tc_port), _MG_PLL_BIAS_PORT1, \
10493 _MG_PLL_BIAS_PORT2)
10494
10495 #define _MG_PLL_TDC_COLDST_BIAS_PORT1 0x168A18
10496 #define _MG_PLL_TDC_COLDST_BIAS_PORT2 0x169A18
10497 #define _MG_PLL_TDC_COLDST_BIAS_PORT3 0x16AA18
10498 #define _MG_PLL_TDC_COLDST_BIAS_PORT4 0x16BA18
10499 #define MG_PLL_TDC_COLDST_IREFINT_EN (1 << 27)
10500 #define MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(x) ((x) << 17)
10501 #define MG_PLL_TDC_COLDST_COLDSTART (1 << 16)
10502 #define MG_PLL_TDC_TDCOVCCORR_EN (1 << 2)
10503 #define MG_PLL_TDC_TDCSEL(x) ((x) << 0)
10504 #define MG_PLL_TDC_COLDST_BIAS(tc_port) _MMIO_PORT((tc_port), \
10505 _MG_PLL_TDC_COLDST_BIAS_PORT1, \
10506 _MG_PLL_TDC_COLDST_BIAS_PORT2)
10507
10508 #define _CNL_DPLL0_CFGCR0 0x6C000
10509 #define _CNL_DPLL1_CFGCR0 0x6C080
10510 #define DPLL_CFGCR0_HDMI_MODE (1 << 30)
10511 #define DPLL_CFGCR0_SSC_ENABLE (1 << 29)
10512 #define DPLL_CFGCR0_SSC_ENABLE_ICL (1 << 25)
10513 #define DPLL_CFGCR0_LINK_RATE_MASK (0xf << 25)
10514 #define DPLL_CFGCR0_LINK_RATE_2700 (0 << 25)
10515 #define DPLL_CFGCR0_LINK_RATE_1350 (1 << 25)
10516 #define DPLL_CFGCR0_LINK_RATE_810 (2 << 25)
10517 #define DPLL_CFGCR0_LINK_RATE_1620 (3 << 25)
10518 #define DPLL_CFGCR0_LINK_RATE_1080 (4 << 25)
10519 #define DPLL_CFGCR0_LINK_RATE_2160 (5 << 25)
10520 #define DPLL_CFGCR0_LINK_RATE_3240 (6 << 25)
10521 #define DPLL_CFGCR0_LINK_RATE_4050 (7 << 25)
10522 #define DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10)
10523 #define DPLL_CFGCR0_DCO_FRACTION_SHIFT (10)
10524 #define DPLL_CFGCR0_DCO_FRACTION(x) ((x) << 10)
10525 #define DPLL_CFGCR0_DCO_INTEGER_MASK (0x3ff)
10526 #define CNL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _CNL_DPLL0_CFGCR0, _CNL_DPLL1_CFGCR0)
10527
10528 #define _CNL_DPLL0_CFGCR1 0x6C004
10529 #define _CNL_DPLL1_CFGCR1 0x6C084
10530 #define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10)
10531 #define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10)
10532 #define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10)
10533 #define DPLL_CFGCR1_QDIV_MODE_SHIFT (9)
10534 #define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9)
10535 #define DPLL_CFGCR1_KDIV_MASK (7 << 6)
10536 #define DPLL_CFGCR1_KDIV_SHIFT (6)
10537 #define DPLL_CFGCR1_KDIV(x) ((x) << 6)
10538 #define DPLL_CFGCR1_KDIV_1 (1 << 6)
10539 #define DPLL_CFGCR1_KDIV_2 (2 << 6)
10540 #define DPLL_CFGCR1_KDIV_3 (4 << 6)
10541 #define DPLL_CFGCR1_PDIV_MASK (0xf << 2)
10542 #define DPLL_CFGCR1_PDIV_SHIFT (2)
10543 #define DPLL_CFGCR1_PDIV(x) ((x) << 2)
10544 #define DPLL_CFGCR1_PDIV_2 (1 << 2)
10545 #define DPLL_CFGCR1_PDIV_3 (2 << 2)
10546 #define DPLL_CFGCR1_PDIV_5 (4 << 2)
10547 #define DPLL_CFGCR1_PDIV_7 (8 << 2)
10548 #define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0)
10549 #define DPLL_CFGCR1_CENTRAL_FREQ_8400 (3 << 0)
10550 #define TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL (0 << 0)
10551 #define CNL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _CNL_DPLL0_CFGCR1, _CNL_DPLL1_CFGCR1)
10552
10553 #define _ICL_DPLL0_CFGCR0 0x164000
10554 #define _ICL_DPLL1_CFGCR0 0x164080
10555 #define ICL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \
10556 _ICL_DPLL1_CFGCR0)
10557
10558 #define _ICL_DPLL0_CFGCR1 0x164004
10559 #define _ICL_DPLL1_CFGCR1 0x164084
10560 #define ICL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \
10561 _ICL_DPLL1_CFGCR1)
10562
10563 #define _TGL_DPLL0_CFGCR0 0x164284
10564 #define _TGL_DPLL1_CFGCR0 0x16428C
10565 #define _TGL_TBTPLL_CFGCR0 0x16429C
10566 #define TGL_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
10567 _TGL_DPLL1_CFGCR0, \
10568 _TGL_TBTPLL_CFGCR0)
10569 #define RKL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR0, \
10570 _TGL_DPLL1_CFGCR0)
10571
10572 #define _TGL_DPLL0_CFGCR1 0x164288
10573 #define _TGL_DPLL1_CFGCR1 0x164290
10574 #define _TGL_TBTPLL_CFGCR1 0x1642A0
10575 #define TGL_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
10576 _TGL_DPLL1_CFGCR1, \
10577 _TGL_TBTPLL_CFGCR1)
10578 #define RKL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \
10579 _TGL_DPLL1_CFGCR1)
10580
10581 #define _DG1_DPLL2_CFGCR0 0x16C284
10582 #define _DG1_DPLL3_CFGCR0 0x16C28C
10583 #define DG1_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
10584 _TGL_DPLL1_CFGCR0, \
10585 _DG1_DPLL2_CFGCR0, \
10586 _DG1_DPLL3_CFGCR0)
10587
10588 #define _DG1_DPLL2_CFGCR1 0x16C288
10589 #define _DG1_DPLL3_CFGCR1 0x16C290
10590 #define DG1_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
10591 _TGL_DPLL1_CFGCR1, \
10592 _DG1_DPLL2_CFGCR1, \
10593 _DG1_DPLL3_CFGCR1)
10594
10595 #define _DKL_PHY1_BASE 0x168000
10596 #define _DKL_PHY2_BASE 0x169000
10597 #define _DKL_PHY3_BASE 0x16A000
10598 #define _DKL_PHY4_BASE 0x16B000
10599 #define _DKL_PHY5_BASE 0x16C000
10600 #define _DKL_PHY6_BASE 0x16D000
10601
10602 /* DEKEL PHY MMIO Address = Phy base + (internal address & ~index_mask) */
10603 #define _DKL_PLL_DIV0 0x200
10604 #define DKL_PLL_DIV0_INTEG_COEFF(x) ((x) << 16)
10605 #define DKL_PLL_DIV0_INTEG_COEFF_MASK (0x1F << 16)
10606 #define DKL_PLL_DIV0_PROP_COEFF(x) ((x) << 12)
10607 #define DKL_PLL_DIV0_PROP_COEFF_MASK (0xF << 12)
10608 #define DKL_PLL_DIV0_FBPREDIV_SHIFT (8)
10609 #define DKL_PLL_DIV0_FBPREDIV(x) ((x) << DKL_PLL_DIV0_FBPREDIV_SHIFT)
10610 #define DKL_PLL_DIV0_FBPREDIV_MASK (0xF << DKL_PLL_DIV0_FBPREDIV_SHIFT)
10611 #define DKL_PLL_DIV0_FBDIV_INT(x) ((x) << 0)
10612 #define DKL_PLL_DIV0_FBDIV_INT_MASK (0xFF << 0)
10613 #define DKL_PLL_DIV0(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
10614 _DKL_PHY2_BASE) + \
10615 _DKL_PLL_DIV0)
10616
10617 #define _DKL_PLL_DIV1 0x204
10618 #define DKL_PLL_DIV1_IREF_TRIM(x) ((x) << 16)
10619 #define DKL_PLL_DIV1_IREF_TRIM_MASK (0x1F << 16)
10620 #define DKL_PLL_DIV1_TDC_TARGET_CNT(x) ((x) << 0)
10621 #define DKL_PLL_DIV1_TDC_TARGET_CNT_MASK (0xFF << 0)
10622 #define DKL_PLL_DIV1(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
10623 _DKL_PHY2_BASE) + \
10624 _DKL_PLL_DIV1)
10625
10626 #define _DKL_PLL_SSC 0x210
10627 #define DKL_PLL_SSC_IREF_NDIV_RATIO(x) ((x) << 29)
10628 #define DKL_PLL_SSC_IREF_NDIV_RATIO_MASK (0x7 << 29)
10629 #define DKL_PLL_SSC_STEP_LEN(x) ((x) << 16)
10630 #define DKL_PLL_SSC_STEP_LEN_MASK (0xFF << 16)
10631 #define DKL_PLL_SSC_STEP_NUM(x) ((x) << 11)
10632 #define DKL_PLL_SSC_STEP_NUM_MASK (0x7 << 11)
10633 #define DKL_PLL_SSC_EN (1 << 9)
10634 #define DKL_PLL_SSC(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
10635 _DKL_PHY2_BASE) + \
10636 _DKL_PLL_SSC)
10637
10638 #define _DKL_PLL_BIAS 0x214
10639 #define DKL_PLL_BIAS_FRAC_EN_H (1 << 30)
10640 #define DKL_PLL_BIAS_FBDIV_SHIFT (8)
10641 #define DKL_PLL_BIAS_FBDIV_FRAC(x) ((x) << DKL_PLL_BIAS_FBDIV_SHIFT)
10642 #define DKL_PLL_BIAS_FBDIV_FRAC_MASK (0x3FFFFF << DKL_PLL_BIAS_FBDIV_SHIFT)
10643 #define DKL_PLL_BIAS(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
10644 _DKL_PHY2_BASE) + \
10645 _DKL_PLL_BIAS)
10646
10647 #define _DKL_PLL_TDC_COLDST_BIAS 0x218
10648 #define DKL_PLL_TDC_SSC_STEP_SIZE(x) ((x) << 8)
10649 #define DKL_PLL_TDC_SSC_STEP_SIZE_MASK (0xFF << 8)
10650 #define DKL_PLL_TDC_FEED_FWD_GAIN(x) ((x) << 0)
10651 #define DKL_PLL_TDC_FEED_FWD_GAIN_MASK (0xFF << 0)
10652 #define DKL_PLL_TDC_COLDST_BIAS(tc_port) _MMIO(_PORT(tc_port, \
10653 _DKL_PHY1_BASE, \
10654 _DKL_PHY2_BASE) + \
10655 _DKL_PLL_TDC_COLDST_BIAS)
10656
10657 #define _DKL_REFCLKIN_CTL 0x12C
10658 /* Bits are the same as MG_REFCLKIN_CTL */
10659 #define DKL_REFCLKIN_CTL(tc_port) _MMIO(_PORT(tc_port, \
10660 _DKL_PHY1_BASE, \
10661 _DKL_PHY2_BASE) + \
10662 _DKL_REFCLKIN_CTL)
10663
10664 #define _DKL_CLKTOP2_HSCLKCTL 0xD4
10665 /* Bits are the same as MG_CLKTOP2_HSCLKCTL */
10666 #define DKL_CLKTOP2_HSCLKCTL(tc_port) _MMIO(_PORT(tc_port, \
10667 _DKL_PHY1_BASE, \
10668 _DKL_PHY2_BASE) + \
10669 _DKL_CLKTOP2_HSCLKCTL)
10670
10671 #define _DKL_CLKTOP2_CORECLKCTL1 0xD8
10672 /* Bits are the same as MG_CLKTOP2_CORECLKCTL1 */
10673 #define DKL_CLKTOP2_CORECLKCTL1(tc_port) _MMIO(_PORT(tc_port, \
10674 _DKL_PHY1_BASE, \
10675 _DKL_PHY2_BASE) + \
10676 _DKL_CLKTOP2_CORECLKCTL1)
10677
10678 #define _DKL_TX_DPCNTL0 0x2C0
10679 #define DKL_TX_PRESHOOT_COEFF(x) ((x) << 13)
10680 #define DKL_TX_PRESHOOT_COEFF_MASK (0x1f << 13)
10681 #define DKL_TX_DE_EMPHASIS_COEFF(x) ((x) << 8)
10682 #define DKL_TX_DE_EMPAHSIS_COEFF_MASK (0x1f << 8)
10683 #define DKL_TX_VSWING_CONTROL(x) ((x) << 0)
10684 #define DKL_TX_VSWING_CONTROL_MASK (0x7 << 0)
10685 #define DKL_TX_DPCNTL0(tc_port) _MMIO(_PORT(tc_port, \
10686 _DKL_PHY1_BASE, \
10687 _DKL_PHY2_BASE) + \
10688 _DKL_TX_DPCNTL0)
10689
10690 #define _DKL_TX_DPCNTL1 0x2C4
10691 /* Bits are the same as DKL_TX_DPCNTRL0 */
10692 #define DKL_TX_DPCNTL1(tc_port) _MMIO(_PORT(tc_port, \
10693 _DKL_PHY1_BASE, \
10694 _DKL_PHY2_BASE) + \
10695 _DKL_TX_DPCNTL1)
10696
10697 #define _DKL_TX_DPCNTL2 0x2C8
10698 #define DKL_TX_DP20BITMODE (1 << 2)
10699 #define DKL_TX_DPCNTL2(tc_port) _MMIO(_PORT(tc_port, \
10700 _DKL_PHY1_BASE, \
10701 _DKL_PHY2_BASE) + \
10702 _DKL_TX_DPCNTL2)
10703
10704 #define _DKL_TX_FW_CALIB 0x2F8
10705 #define DKL_TX_CFG_DISABLE_WAIT_INIT (1 << 7)
10706 #define DKL_TX_FW_CALIB(tc_port) _MMIO(_PORT(tc_port, \
10707 _DKL_PHY1_BASE, \
10708 _DKL_PHY2_BASE) + \
10709 _DKL_TX_FW_CALIB)
10710
10711 #define _DKL_TX_PMD_LANE_SUS 0xD00
10712 #define DKL_TX_PMD_LANE_SUS(tc_port) _MMIO(_PORT(tc_port, \
10713 _DKL_PHY1_BASE, \
10714 _DKL_PHY2_BASE) + \
10715 _DKL_TX_PMD_LANE_SUS)
10716
10717 #define _DKL_TX_DW17 0xDC4
10718 #define DKL_TX_DW17(tc_port) _MMIO(_PORT(tc_port, \
10719 _DKL_PHY1_BASE, \
10720 _DKL_PHY2_BASE) + \
10721 _DKL_TX_DW17)
10722
10723 #define _DKL_TX_DW18 0xDC8
10724 #define DKL_TX_DW18(tc_port) _MMIO(_PORT(tc_port, \
10725 _DKL_PHY1_BASE, \
10726 _DKL_PHY2_BASE) + \
10727 _DKL_TX_DW18)
10728
10729 #define _DKL_DP_MODE 0xA0
10730 #define DKL_DP_MODE(tc_port) _MMIO(_PORT(tc_port, \
10731 _DKL_PHY1_BASE, \
10732 _DKL_PHY2_BASE) + \
10733 _DKL_DP_MODE)
10734
10735 #define _DKL_CMN_UC_DW27 0x36C
10736 #define DKL_CMN_UC_DW27_UC_HEALTH (0x1 << 15)
10737 #define DKL_CMN_UC_DW_27(tc_port) _MMIO(_PORT(tc_port, \
10738 _DKL_PHY1_BASE, \
10739 _DKL_PHY2_BASE) + \
10740 _DKL_CMN_UC_DW27)
10741
10742 /*
10743 * Each Dekel PHY is addressed through a 4KB aperture. Each PHY has more than
10744 * 4KB of register space, so a separate index is programmed in HIP_INDEX_REG0
10745 * or HIP_INDEX_REG1, based on the port number, to set the upper 2 address
10746 * bits that point the 4KB window into the full PHY register space.
10747 */
10748 #define _HIP_INDEX_REG0 0x1010A0
10749 #define _HIP_INDEX_REG1 0x1010A4
10750 #define HIP_INDEX_REG(tc_port) _MMIO((tc_port) < 4 ? _HIP_INDEX_REG0 \
10751 : _HIP_INDEX_REG1)
10752 #define _HIP_INDEX_SHIFT(tc_port) (8 * ((tc_port) % 4))
10753 #define HIP_INDEX_VAL(tc_port, val) ((val) << _HIP_INDEX_SHIFT(tc_port))
10754
10755 /* BXT display engine PLL */
10756 #define BXT_DE_PLL_CTL _MMIO(0x6d000)
10757 #define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */
10758 #define BXT_DE_PLL_RATIO_MASK 0xff
10759
10760 #define BXT_DE_PLL_ENABLE _MMIO(0x46070)
10761 #define BXT_DE_PLL_PLL_ENABLE (1 << 31)
10762 #define BXT_DE_PLL_LOCK (1 << 30)
10763 #define CNL_CDCLK_PLL_RATIO(x) (x)
10764 #define CNL_CDCLK_PLL_RATIO_MASK 0xff
10765
10766 /* GEN9 DC */
10767 #define DC_STATE_EN _MMIO(0x45504)
10768 #define DC_STATE_DISABLE 0
10769 #define DC_STATE_EN_DC3CO REG_BIT(30)
10770 #define DC_STATE_DC3CO_STATUS REG_BIT(29)
10771 #define DC_STATE_EN_UPTO_DC5 (1 << 0)
10772 #define DC_STATE_EN_DC9 (1 << 3)
10773 #define DC_STATE_EN_UPTO_DC6 (2 << 0)
10774 #define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3
10775
10776 #define DC_STATE_DEBUG _MMIO(0x45520)
10777 #define DC_STATE_DEBUG_MASK_CORES (1 << 0)
10778 #define DC_STATE_DEBUG_MASK_MEMORY_UP (1 << 1)
10779
10780 #define BXT_P_CR_MC_BIOS_REQ_0_0_0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7114)
10781 #define BXT_REQ_DATA_MASK 0x3F
10782 #define BXT_DRAM_CHANNEL_ACTIVE_SHIFT 12
10783 #define BXT_DRAM_CHANNEL_ACTIVE_MASK (0xF << 12)
10784 #define BXT_MEMORY_FREQ_MULTIPLIER_HZ 133333333
10785
10786 #define BXT_D_CR_DRP0_DUNIT8 0x1000
10787 #define BXT_D_CR_DRP0_DUNIT9 0x1200
10788 #define BXT_D_CR_DRP0_DUNIT_START 8
10789 #define BXT_D_CR_DRP0_DUNIT_END 11
10790 #define BXT_D_CR_DRP0_DUNIT(x) _MMIO(MCHBAR_MIRROR_BASE_SNB + \
10791 _PICK_EVEN((x) - 8, BXT_D_CR_DRP0_DUNIT8,\
10792 BXT_D_CR_DRP0_DUNIT9))
10793 #define BXT_DRAM_RANK_MASK 0x3
10794 #define BXT_DRAM_RANK_SINGLE 0x1
10795 #define BXT_DRAM_RANK_DUAL 0x3
10796 #define BXT_DRAM_WIDTH_MASK (0x3 << 4)
10797 #define BXT_DRAM_WIDTH_SHIFT 4
10798 #define BXT_DRAM_WIDTH_X8 (0x0 << 4)
10799 #define BXT_DRAM_WIDTH_X16 (0x1 << 4)
10800 #define BXT_DRAM_WIDTH_X32 (0x2 << 4)
10801 #define BXT_DRAM_WIDTH_X64 (0x3 << 4)
10802 #define BXT_DRAM_SIZE_MASK (0x7 << 6)
10803 #define BXT_DRAM_SIZE_SHIFT 6
10804 #define BXT_DRAM_SIZE_4GBIT (0x0 << 6)
10805 #define BXT_DRAM_SIZE_6GBIT (0x1 << 6)
10806 #define BXT_DRAM_SIZE_8GBIT (0x2 << 6)
10807 #define BXT_DRAM_SIZE_12GBIT (0x3 << 6)
10808 #define BXT_DRAM_SIZE_16GBIT (0x4 << 6)
10809 #define BXT_DRAM_TYPE_MASK (0x7 << 22)
10810 #define BXT_DRAM_TYPE_SHIFT 22
10811 #define BXT_DRAM_TYPE_DDR3 (0x0 << 22)
10812 #define BXT_DRAM_TYPE_LPDDR3 (0x1 << 22)
10813 #define BXT_DRAM_TYPE_LPDDR4 (0x2 << 22)
10814 #define BXT_DRAM_TYPE_DDR4 (0x4 << 22)
10815
10816 #define SKL_MEMORY_FREQ_MULTIPLIER_HZ 266666666
10817 #define SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5E04)
10818 #define SKL_REQ_DATA_MASK (0xF << 0)
10819
10820 #define SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5000)
10821 #define SKL_DRAM_DDR_TYPE_MASK (0x3 << 0)
10822 #define SKL_DRAM_DDR_TYPE_DDR4 (0 << 0)
10823 #define SKL_DRAM_DDR_TYPE_DDR3 (1 << 0)
10824 #define SKL_DRAM_DDR_TYPE_LPDDR3 (2 << 0)
10825 #define SKL_DRAM_DDR_TYPE_LPDDR4 (3 << 0)
10826
10827 #define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
10828 #define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010)
10829 #define SKL_DRAM_S_SHIFT 16
10830 #define SKL_DRAM_SIZE_MASK 0x3F
10831 #define SKL_DRAM_WIDTH_MASK (0x3 << 8)
10832 #define SKL_DRAM_WIDTH_SHIFT 8
10833 #define SKL_DRAM_WIDTH_X8 (0x0 << 8)
10834 #define SKL_DRAM_WIDTH_X16 (0x1 << 8)
10835 #define SKL_DRAM_WIDTH_X32 (0x2 << 8)
10836 #define SKL_DRAM_RANK_MASK (0x1 << 10)
10837 #define SKL_DRAM_RANK_SHIFT 10
10838 #define SKL_DRAM_RANK_1 (0x0 << 10)
10839 #define SKL_DRAM_RANK_2 (0x1 << 10)
10840 #define SKL_DRAM_RANK_MASK (0x1 << 10)
10841 #define CNL_DRAM_SIZE_MASK 0x7F
10842 #define CNL_DRAM_WIDTH_MASK (0x3 << 7)
10843 #define CNL_DRAM_WIDTH_SHIFT 7
10844 #define CNL_DRAM_WIDTH_X8 (0x0 << 7)
10845 #define CNL_DRAM_WIDTH_X16 (0x1 << 7)
10846 #define CNL_DRAM_WIDTH_X32 (0x2 << 7)
10847 #define CNL_DRAM_RANK_MASK (0x3 << 9)
10848 #define CNL_DRAM_RANK_SHIFT 9
10849 #define CNL_DRAM_RANK_1 (0x0 << 9)
10850 #define CNL_DRAM_RANK_2 (0x1 << 9)
10851 #define CNL_DRAM_RANK_3 (0x2 << 9)
10852 #define CNL_DRAM_RANK_4 (0x3 << 9)
10853
10854 /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
10855 * since on HSW we can't write to it using I915_WRITE. */
10856 #define D_COMP_HSW _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
10857 #define D_COMP_BDW _MMIO(0x138144)
10858 #define D_COMP_RCOMP_IN_PROGRESS (1 << 9)
10859 #define D_COMP_COMP_FORCE (1 << 8)
10860 #define D_COMP_COMP_DISABLE (1 << 0)
10861
10862 /* Pipe WM_LINETIME - watermark line time */
10863 #define _WM_LINETIME_A 0x45270
10864 #define _WM_LINETIME_B 0x45274
10865 #define WM_LINETIME(pipe) _MMIO_PIPE(pipe, _WM_LINETIME_A, _WM_LINETIME_B)
10866 #define HSW_LINETIME_MASK REG_GENMASK(8, 0)
10867 #define HSW_LINETIME(x) REG_FIELD_PREP(HSW_LINETIME_MASK, (x))
10868 #define HSW_IPS_LINETIME_MASK REG_GENMASK(24, 16)
10869 #define HSW_IPS_LINETIME(x) REG_FIELD_PREP(HSW_IPS_LINETIME_MASK, (x))
10870
10871 /* SFUSE_STRAP */
10872 #define SFUSE_STRAP _MMIO(0xc2014)
10873 #define SFUSE_STRAP_FUSE_LOCK (1 << 13)
10874 #define SFUSE_STRAP_RAW_FREQUENCY (1 << 8)
10875 #define SFUSE_STRAP_DISPLAY_DISABLED (1 << 7)
10876 #define SFUSE_STRAP_CRT_DISABLED (1 << 6)
10877 #define SFUSE_STRAP_DDIF_DETECTED (1 << 3)
10878 #define SFUSE_STRAP_DDIB_DETECTED (1 << 2)
10879 #define SFUSE_STRAP_DDIC_DETECTED (1 << 1)
10880 #define SFUSE_STRAP_DDID_DETECTED (1 << 0)
10881
10882 #define WM_MISC _MMIO(0x45260)
10883 #define WM_MISC_DATA_PARTITION_5_6 (1 << 0)
10884
10885 #define WM_DBG _MMIO(0x45280)
10886 #define WM_DBG_DISALLOW_MULTIPLE_LP (1 << 0)
10887 #define WM_DBG_DISALLOW_MAXFIFO (1 << 1)
10888 #define WM_DBG_DISALLOW_SPRITE (1 << 2)
10889
10890 /* pipe CSC */
10891 #define _PIPE_A_CSC_COEFF_RY_GY 0x49010
10892 #define _PIPE_A_CSC_COEFF_BY 0x49014
10893 #define _PIPE_A_CSC_COEFF_RU_GU 0x49018
10894 #define _PIPE_A_CSC_COEFF_BU 0x4901c
10895 #define _PIPE_A_CSC_COEFF_RV_GV 0x49020
10896 #define _PIPE_A_CSC_COEFF_BV 0x49024
10897
10898 #define _PIPE_A_CSC_MODE 0x49028
10899 #define ICL_CSC_ENABLE (1 << 31) /* icl+ */
10900 #define ICL_OUTPUT_CSC_ENABLE (1 << 30) /* icl+ */
10901 #define CSC_BLACK_SCREEN_OFFSET (1 << 2) /* ilk/snb */
10902 #define CSC_POSITION_BEFORE_GAMMA (1 << 1) /* pre-glk */
10903 #define CSC_MODE_YUV_TO_RGB (1 << 0) /* ilk/snb */
10904
10905 #define _PIPE_A_CSC_PREOFF_HI 0x49030
10906 #define _PIPE_A_CSC_PREOFF_ME 0x49034
10907 #define _PIPE_A_CSC_PREOFF_LO 0x49038
10908 #define _PIPE_A_CSC_POSTOFF_HI 0x49040
10909 #define _PIPE_A_CSC_POSTOFF_ME 0x49044
10910 #define _PIPE_A_CSC_POSTOFF_LO 0x49048
10911
10912 #define _PIPE_B_CSC_COEFF_RY_GY 0x49110
10913 #define _PIPE_B_CSC_COEFF_BY 0x49114
10914 #define _PIPE_B_CSC_COEFF_RU_GU 0x49118
10915 #define _PIPE_B_CSC_COEFF_BU 0x4911c
10916 #define _PIPE_B_CSC_COEFF_RV_GV 0x49120
10917 #define _PIPE_B_CSC_COEFF_BV 0x49124
10918 #define _PIPE_B_CSC_MODE 0x49128
10919 #define _PIPE_B_CSC_PREOFF_HI 0x49130
10920 #define _PIPE_B_CSC_PREOFF_ME 0x49134
10921 #define _PIPE_B_CSC_PREOFF_LO 0x49138
10922 #define _PIPE_B_CSC_POSTOFF_HI 0x49140
10923 #define _PIPE_B_CSC_POSTOFF_ME 0x49144
10924 #define _PIPE_B_CSC_POSTOFF_LO 0x49148
10925
10926 #define PIPE_CSC_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
10927 #define PIPE_CSC_COEFF_BY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
10928 #define PIPE_CSC_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)
10929 #define PIPE_CSC_COEFF_BU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)
10930 #define PIPE_CSC_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)
10931 #define PIPE_CSC_COEFF_BV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)
10932 #define PIPE_CSC_MODE(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)
10933 #define PIPE_CSC_PREOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)
10934 #define PIPE_CSC_PREOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)
10935 #define PIPE_CSC_PREOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)
10936 #define PIPE_CSC_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)
10937 #define PIPE_CSC_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
10938 #define PIPE_CSC_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
10939
10940 /* Pipe Output CSC */
10941 #define _PIPE_A_OUTPUT_CSC_COEFF_RY_GY 0x49050
10942 #define _PIPE_A_OUTPUT_CSC_COEFF_BY 0x49054
10943 #define _PIPE_A_OUTPUT_CSC_COEFF_RU_GU 0x49058
10944 #define _PIPE_A_OUTPUT_CSC_COEFF_BU 0x4905c
10945 #define _PIPE_A_OUTPUT_CSC_COEFF_RV_GV 0x49060
10946 #define _PIPE_A_OUTPUT_CSC_COEFF_BV 0x49064
10947 #define _PIPE_A_OUTPUT_CSC_PREOFF_HI 0x49068
10948 #define _PIPE_A_OUTPUT_CSC_PREOFF_ME 0x4906c
10949 #define _PIPE_A_OUTPUT_CSC_PREOFF_LO 0x49070
10950 #define _PIPE_A_OUTPUT_CSC_POSTOFF_HI 0x49074
10951 #define _PIPE_A_OUTPUT_CSC_POSTOFF_ME 0x49078
10952 #define _PIPE_A_OUTPUT_CSC_POSTOFF_LO 0x4907c
10953
10954 #define _PIPE_B_OUTPUT_CSC_COEFF_RY_GY 0x49150
10955 #define _PIPE_B_OUTPUT_CSC_COEFF_BY 0x49154
10956 #define _PIPE_B_OUTPUT_CSC_COEFF_RU_GU 0x49158
10957 #define _PIPE_B_OUTPUT_CSC_COEFF_BU 0x4915c
10958 #define _PIPE_B_OUTPUT_CSC_COEFF_RV_GV 0x49160
10959 #define _PIPE_B_OUTPUT_CSC_COEFF_BV 0x49164
10960 #define _PIPE_B_OUTPUT_CSC_PREOFF_HI 0x49168
10961 #define _PIPE_B_OUTPUT_CSC_PREOFF_ME 0x4916c
10962 #define _PIPE_B_OUTPUT_CSC_PREOFF_LO 0x49170
10963 #define _PIPE_B_OUTPUT_CSC_POSTOFF_HI 0x49174
10964 #define _PIPE_B_OUTPUT_CSC_POSTOFF_ME 0x49178
10965 #define _PIPE_B_OUTPUT_CSC_POSTOFF_LO 0x4917c
10966
10967 #define PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe,\
10968 _PIPE_A_OUTPUT_CSC_COEFF_RY_GY,\
10969 _PIPE_B_OUTPUT_CSC_COEFF_RY_GY)
10970 #define PIPE_CSC_OUTPUT_COEFF_BY(pipe) _MMIO_PIPE(pipe, \
10971 _PIPE_A_OUTPUT_CSC_COEFF_BY, \
10972 _PIPE_B_OUTPUT_CSC_COEFF_BY)
10973 #define PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, \
10974 _PIPE_A_OUTPUT_CSC_COEFF_RU_GU, \
10975 _PIPE_B_OUTPUT_CSC_COEFF_RU_GU)
10976 #define PIPE_CSC_OUTPUT_COEFF_BU(pipe) _MMIO_PIPE(pipe, \
10977 _PIPE_A_OUTPUT_CSC_COEFF_BU, \
10978 _PIPE_B_OUTPUT_CSC_COEFF_BU)
10979 #define PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, \
10980 _PIPE_A_OUTPUT_CSC_COEFF_RV_GV, \
10981 _PIPE_B_OUTPUT_CSC_COEFF_RV_GV)
10982 #define PIPE_CSC_OUTPUT_COEFF_BV(pipe) _MMIO_PIPE(pipe, \
10983 _PIPE_A_OUTPUT_CSC_COEFF_BV, \
10984 _PIPE_B_OUTPUT_CSC_COEFF_BV)
10985 #define PIPE_CSC_OUTPUT_PREOFF_HI(pipe) _MMIO_PIPE(pipe, \
10986 _PIPE_A_OUTPUT_CSC_PREOFF_HI, \
10987 _PIPE_B_OUTPUT_CSC_PREOFF_HI)
10988 #define PIPE_CSC_OUTPUT_PREOFF_ME(pipe) _MMIO_PIPE(pipe, \
10989 _PIPE_A_OUTPUT_CSC_PREOFF_ME, \
10990 _PIPE_B_OUTPUT_CSC_PREOFF_ME)
10991 #define PIPE_CSC_OUTPUT_PREOFF_LO(pipe) _MMIO_PIPE(pipe, \
10992 _PIPE_A_OUTPUT_CSC_PREOFF_LO, \
10993 _PIPE_B_OUTPUT_CSC_PREOFF_LO)
10994 #define PIPE_CSC_OUTPUT_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, \
10995 _PIPE_A_OUTPUT_CSC_POSTOFF_HI, \
10996 _PIPE_B_OUTPUT_CSC_POSTOFF_HI)
10997 #define PIPE_CSC_OUTPUT_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, \
10998 _PIPE_A_OUTPUT_CSC_POSTOFF_ME, \
10999 _PIPE_B_OUTPUT_CSC_POSTOFF_ME)
11000 #define PIPE_CSC_OUTPUT_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, \
11001 _PIPE_A_OUTPUT_CSC_POSTOFF_LO, \
11002 _PIPE_B_OUTPUT_CSC_POSTOFF_LO)
11003
11004 /* pipe degamma/gamma LUTs on IVB+ */
11005 #define _PAL_PREC_INDEX_A 0x4A400
11006 #define _PAL_PREC_INDEX_B 0x4AC00
11007 #define _PAL_PREC_INDEX_C 0x4B400
11008 #define PAL_PREC_10_12_BIT (0 << 31)
11009 #define PAL_PREC_SPLIT_MODE (1 << 31)
11010 #define PAL_PREC_AUTO_INCREMENT (1 << 15)
11011 #define PAL_PREC_INDEX_VALUE_MASK (0x3ff << 0)
11012 #define PAL_PREC_INDEX_VALUE(x) ((x) << 0)
11013 #define _PAL_PREC_DATA_A 0x4A404
11014 #define _PAL_PREC_DATA_B 0x4AC04
11015 #define _PAL_PREC_DATA_C 0x4B404
11016 #define _PAL_PREC_GC_MAX_A 0x4A410
11017 #define _PAL_PREC_GC_MAX_B 0x4AC10
11018 #define _PAL_PREC_GC_MAX_C 0x4B410
11019 #define PREC_PAL_DATA_RED_MASK REG_GENMASK(29, 20)
11020 #define PREC_PAL_DATA_GREEN_MASK REG_GENMASK(19, 10)
11021 #define PREC_PAL_DATA_BLUE_MASK REG_GENMASK(9, 0)
11022 #define _PAL_PREC_EXT_GC_MAX_A 0x4A420
11023 #define _PAL_PREC_EXT_GC_MAX_B 0x4AC20
11024 #define _PAL_PREC_EXT_GC_MAX_C 0x4B420
11025 #define _PAL_PREC_EXT2_GC_MAX_A 0x4A430
11026 #define _PAL_PREC_EXT2_GC_MAX_B 0x4AC30
11027 #define _PAL_PREC_EXT2_GC_MAX_C 0x4B430
11028
11029 #define PREC_PAL_INDEX(pipe) _MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B)
11030 #define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B)
11031 #define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4)
11032 #define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4)
11033 #define PREC_PAL_EXT2_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4)
11034
11035 #define _PRE_CSC_GAMC_INDEX_A 0x4A484
11036 #define _PRE_CSC_GAMC_INDEX_B 0x4AC84
11037 #define _PRE_CSC_GAMC_INDEX_C 0x4B484
11038 #define PRE_CSC_GAMC_AUTO_INCREMENT (1 << 10)
11039 #define _PRE_CSC_GAMC_DATA_A 0x4A488
11040 #define _PRE_CSC_GAMC_DATA_B 0x4AC88
11041 #define _PRE_CSC_GAMC_DATA_C 0x4B488
11042
11043 #define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A, _PRE_CSC_GAMC_INDEX_B)
11044 #define PRE_CSC_GAMC_DATA(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B)
11045
11046 /* ICL Multi segmented gamma */
11047 #define _PAL_PREC_MULTI_SEG_INDEX_A 0x4A408
11048 #define _PAL_PREC_MULTI_SEG_INDEX_B 0x4AC08
11049 #define PAL_PREC_MULTI_SEGMENT_AUTO_INCREMENT REG_BIT(15)
11050 #define PAL_PREC_MULTI_SEGMENT_INDEX_VALUE_MASK REG_GENMASK(4, 0)
11051
11052 #define _PAL_PREC_MULTI_SEG_DATA_A 0x4A40C
11053 #define _PAL_PREC_MULTI_SEG_DATA_B 0x4AC0C
11054 #define PAL_PREC_MULTI_SEG_RED_LDW_MASK REG_GENMASK(29, 24)
11055 #define PAL_PREC_MULTI_SEG_RED_UDW_MASK REG_GENMASK(29, 20)
11056 #define PAL_PREC_MULTI_SEG_GREEN_LDW_MASK REG_GENMASK(19, 14)
11057 #define PAL_PREC_MULTI_SEG_GREEN_UDW_MASK REG_GENMASK(19, 10)
11058 #define PAL_PREC_MULTI_SEG_BLUE_LDW_MASK REG_GENMASK(9, 4)
11059 #define PAL_PREC_MULTI_SEG_BLUE_UDW_MASK REG_GENMASK(9, 0)
11060
11061 #define PREC_PAL_MULTI_SEG_INDEX(pipe) _MMIO_PIPE(pipe, \
11062 _PAL_PREC_MULTI_SEG_INDEX_A, \
11063 _PAL_PREC_MULTI_SEG_INDEX_B)
11064 #define PREC_PAL_MULTI_SEG_DATA(pipe) _MMIO_PIPE(pipe, \
11065 _PAL_PREC_MULTI_SEG_DATA_A, \
11066 _PAL_PREC_MULTI_SEG_DATA_B)
11067
11068 /* pipe CSC & degamma/gamma LUTs on CHV */
11069 #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900)
11070 #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904)
11071 #define _CGM_PIPE_A_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x67908)
11072 #define _CGM_PIPE_A_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6790C)
11073 #define _CGM_PIPE_A_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x67910)
11074 #define _CGM_PIPE_A_DEGAMMA (VLV_DISPLAY_BASE + 0x66000)
11075 #define CGM_PIPE_DEGAMMA_RED_MASK REG_GENMASK(13, 0)
11076 #define CGM_PIPE_DEGAMMA_GREEN_MASK REG_GENMASK(29, 16)
11077 #define CGM_PIPE_DEGAMMA_BLUE_MASK REG_GENMASK(13, 0)
11078 #define _CGM_PIPE_A_GAMMA (VLV_DISPLAY_BASE + 0x67000)
11079 #define CGM_PIPE_GAMMA_RED_MASK REG_GENMASK(9, 0)
11080 #define CGM_PIPE_GAMMA_GREEN_MASK REG_GENMASK(25, 16)
11081 #define CGM_PIPE_GAMMA_BLUE_MASK REG_GENMASK(9, 0)
11082 #define _CGM_PIPE_A_MODE (VLV_DISPLAY_BASE + 0x67A00)
11083 #define CGM_PIPE_MODE_GAMMA (1 << 2)
11084 #define CGM_PIPE_MODE_CSC (1 << 1)
11085 #define CGM_PIPE_MODE_DEGAMMA (1 << 0)
11086
11087 #define _CGM_PIPE_B_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x69900)
11088 #define _CGM_PIPE_B_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x69904)
11089 #define _CGM_PIPE_B_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x69908)
11090 #define _CGM_PIPE_B_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6990C)
11091 #define _CGM_PIPE_B_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x69910)
11092 #define _CGM_PIPE_B_DEGAMMA (VLV_DISPLAY_BASE + 0x68000)
11093 #define _CGM_PIPE_B_GAMMA (VLV_DISPLAY_BASE + 0x69000)
11094 #define _CGM_PIPE_B_MODE (VLV_DISPLAY_BASE + 0x69A00)
11095
11096 #define CGM_PIPE_CSC_COEFF01(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF01, _CGM_PIPE_B_CSC_COEFF01)
11097 #define CGM_PIPE_CSC_COEFF23(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF23, _CGM_PIPE_B_CSC_COEFF23)
11098 #define CGM_PIPE_CSC_COEFF45(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF45, _CGM_PIPE_B_CSC_COEFF45)
11099 #define CGM_PIPE_CSC_COEFF67(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF67, _CGM_PIPE_B_CSC_COEFF67)
11100 #define CGM_PIPE_CSC_COEFF8(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF8, _CGM_PIPE_B_CSC_COEFF8)
11101 #define CGM_PIPE_DEGAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_DEGAMMA, _CGM_PIPE_B_DEGAMMA) + (i) * 8 + (w) * 4)
11102 #define CGM_PIPE_GAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA, _CGM_PIPE_B_GAMMA) + (i) * 8 + (w) * 4)
11103 #define CGM_PIPE_MODE(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_MODE, _CGM_PIPE_B_MODE)
11104
11105 /* MIPI DSI registers */
11106
11107 #define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c) /* ports A and C only */
11108 #define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c))
11109
11110 /* Gen11 DSI */
11111 #define _MMIO_DSI(tc, dsi0, dsi1) _MMIO_TRANS((tc) - TRANSCODER_DSI_0, \
11112 dsi0, dsi1)
11113
11114 #define MIPIO_TXESC_CLK_DIV1 _MMIO(0x160004)
11115 #define GLK_TX_ESC_CLK_DIV1_MASK 0x3FF
11116 #define MIPIO_TXESC_CLK_DIV2 _MMIO(0x160008)
11117 #define GLK_TX_ESC_CLK_DIV2_MASK 0x3FF
11118
11119 #define _ICL_DSI_ESC_CLK_DIV0 0x6b090
11120 #define _ICL_DSI_ESC_CLK_DIV1 0x6b890
11121 #define ICL_DSI_ESC_CLK_DIV(port) _MMIO_PORT((port), \
11122 _ICL_DSI_ESC_CLK_DIV0, \
11123 _ICL_DSI_ESC_CLK_DIV1)
11124 #define _ICL_DPHY_ESC_CLK_DIV0 0x162190
11125 #define _ICL_DPHY_ESC_CLK_DIV1 0x6C190
11126 #define ICL_DPHY_ESC_CLK_DIV(port) _MMIO_PORT((port), \
11127 _ICL_DPHY_ESC_CLK_DIV0, \
11128 _ICL_DPHY_ESC_CLK_DIV1)
11129 #define ICL_BYTE_CLK_PER_ESC_CLK_MASK (0x1f << 16)
11130 #define ICL_BYTE_CLK_PER_ESC_CLK_SHIFT 16
11131 #define ICL_ESC_CLK_DIV_MASK 0x1ff
11132 #define ICL_ESC_CLK_DIV_SHIFT 0
11133 #define DSI_MAX_ESC_CLK 20000 /* in KHz */
11134
11135 #define _DSI_CMD_FRMCTL_0 0x6b034
11136 #define _DSI_CMD_FRMCTL_1 0x6b834
11137 #define DSI_CMD_FRMCTL(port) _MMIO_PORT(port, \
11138 _DSI_CMD_FRMCTL_0,\
11139 _DSI_CMD_FRMCTL_1)
11140 #define DSI_FRAME_UPDATE_REQUEST (1 << 31)
11141 #define DSI_PERIODIC_FRAME_UPDATE_ENABLE (1 << 29)
11142 #define DSI_NULL_PACKET_ENABLE (1 << 28)
11143 #define DSI_FRAME_IN_PROGRESS (1 << 0)
11144
11145 #define _DSI_INTR_MASK_REG_0 0x6b070
11146 #define _DSI_INTR_MASK_REG_1 0x6b870
11147 #define DSI_INTR_MASK_REG(port) _MMIO_PORT(port, \
11148 _DSI_INTR_MASK_REG_0,\
11149 _DSI_INTR_MASK_REG_1)
11150
11151 #define _DSI_INTR_IDENT_REG_0 0x6b074
11152 #define _DSI_INTR_IDENT_REG_1 0x6b874
11153 #define DSI_INTR_IDENT_REG(port) _MMIO_PORT(port, \
11154 _DSI_INTR_IDENT_REG_0,\
11155 _DSI_INTR_IDENT_REG_1)
11156 #define DSI_TE_EVENT (1 << 31)
11157 #define DSI_RX_DATA_OR_BTA_TERMINATED (1 << 30)
11158 #define DSI_TX_DATA (1 << 29)
11159 #define DSI_ULPS_ENTRY_DONE (1 << 28)
11160 #define DSI_NON_TE_TRIGGER_RECEIVED (1 << 27)
11161 #define DSI_HOST_CHKSUM_ERROR (1 << 26)
11162 #define DSI_HOST_MULTI_ECC_ERROR (1 << 25)
11163 #define DSI_HOST_SINGL_ECC_ERROR (1 << 24)
11164 #define DSI_HOST_CONTENTION_DETECTED (1 << 23)
11165 #define DSI_HOST_FALSE_CONTROL_ERROR (1 << 22)
11166 #define DSI_HOST_TIMEOUT_ERROR (1 << 21)
11167 #define DSI_HOST_LOW_POWER_TX_SYNC_ERROR (1 << 20)
11168 #define DSI_HOST_ESCAPE_MODE_ENTRY_ERROR (1 << 19)
11169 #define DSI_FRAME_UPDATE_DONE (1 << 16)
11170 #define DSI_PROTOCOL_VIOLATION_REPORTED (1 << 15)
11171 #define DSI_INVALID_TX_LENGTH (1 << 13)
11172 #define DSI_INVALID_VC (1 << 12)
11173 #define DSI_INVALID_DATA_TYPE (1 << 11)
11174 #define DSI_PERIPHERAL_CHKSUM_ERROR (1 << 10)
11175 #define DSI_PERIPHERAL_MULTI_ECC_ERROR (1 << 9)
11176 #define DSI_PERIPHERAL_SINGLE_ECC_ERROR (1 << 8)
11177 #define DSI_PERIPHERAL_CONTENTION_DETECTED (1 << 7)
11178 #define DSI_PERIPHERAL_FALSE_CTRL_ERROR (1 << 6)
11179 #define DSI_PERIPHERAL_TIMEOUT_ERROR (1 << 5)
11180 #define DSI_PERIPHERAL_LP_TX_SYNC_ERROR (1 << 4)
11181 #define DSI_PERIPHERAL_ESC_MODE_ENTRY_CMD_ERR (1 << 3)
11182 #define DSI_EOT_SYNC_ERROR (1 << 2)
11183 #define DSI_SOT_SYNC_ERROR (1 << 1)
11184 #define DSI_SOT_ERROR (1 << 0)
11185
11186 /* Gen4+ Timestamp and Pipe Frame time stamp registers */
11187 #define GEN4_TIMESTAMP _MMIO(0x2358)
11188 #define ILK_TIMESTAMP_HI _MMIO(0x70070)
11189 #define IVB_TIMESTAMP_CTR _MMIO(0x44070)
11190
11191 #define GEN9_TIMESTAMP_OVERRIDE _MMIO(0x44074)
11192 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT 0
11193 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK 0x3ff
11194 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT 12
11195 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf << 12)
11196
11197 #define _PIPE_FRMTMSTMP_A 0x70048
11198 #define PIPE_FRMTMSTMP(pipe) \
11199 _MMIO_PIPE2(pipe, _PIPE_FRMTMSTMP_A)
11200
11201 /* BXT MIPI clock controls */
11202 #define BXT_MAX_VAR_OUTPUT_KHZ 39500
11203
11204 #define BXT_MIPI_CLOCK_CTL _MMIO(0x46090)
11205 #define BXT_MIPI1_DIV_SHIFT 26
11206 #define BXT_MIPI2_DIV_SHIFT 10
11207 #define BXT_MIPI_DIV_SHIFT(port) \
11208 _MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \
11209 BXT_MIPI2_DIV_SHIFT)
11210
11211 /* TX control divider to select actual TX clock output from (8x/var) */
11212 #define BXT_MIPI1_TX_ESCLK_SHIFT 26
11213 #define BXT_MIPI2_TX_ESCLK_SHIFT 10
11214 #define BXT_MIPI_TX_ESCLK_SHIFT(port) \
11215 _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \
11216 BXT_MIPI2_TX_ESCLK_SHIFT)
11217 #define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK (0x3F << 26)
11218 #define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK (0x3F << 10)
11219 #define BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port) \
11220 _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \
11221 BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
11222 #define BXT_MIPI_TX_ESCLK_DIVIDER(port, val) \
11223 (((val) & 0x3F) << BXT_MIPI_TX_ESCLK_SHIFT(port))
11224 /* RX upper control divider to select actual RX clock output from 8x */
11225 #define BXT_MIPI1_RX_ESCLK_UPPER_SHIFT 21
11226 #define BXT_MIPI2_RX_ESCLK_UPPER_SHIFT 5
11227 #define BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port) \
11228 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_SHIFT, \
11229 BXT_MIPI2_RX_ESCLK_UPPER_SHIFT)
11230 #define BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 21)
11231 #define BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 5)
11232 #define BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port) \
11233 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK, \
11234 BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK)
11235 #define BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, val) \
11236 (((val) & 3) << BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port))
11237 /* 8/3X divider to select the actual 8/3X clock output from 8x */
11238 #define BXT_MIPI1_8X_BY3_SHIFT 19
11239 #define BXT_MIPI2_8X_BY3_SHIFT 3
11240 #define BXT_MIPI_8X_BY3_SHIFT(port) \
11241 _MIPI_PORT(port, BXT_MIPI1_8X_BY3_SHIFT, \
11242 BXT_MIPI2_8X_BY3_SHIFT)
11243 #define BXT_MIPI1_8X_BY3_DIVIDER_MASK (3 << 19)
11244 #define BXT_MIPI2_8X_BY3_DIVIDER_MASK (3 << 3)
11245 #define BXT_MIPI_8X_BY3_DIVIDER_MASK(port) \
11246 _MIPI_PORT(port, BXT_MIPI1_8X_BY3_DIVIDER_MASK, \
11247 BXT_MIPI2_8X_BY3_DIVIDER_MASK)
11248 #define BXT_MIPI_8X_BY3_DIVIDER(port, val) \
11249 (((val) & 3) << BXT_MIPI_8X_BY3_SHIFT(port))
11250 /* RX lower control divider to select actual RX clock output from 8x */
11251 #define BXT_MIPI1_RX_ESCLK_LOWER_SHIFT 16
11252 #define BXT_MIPI2_RX_ESCLK_LOWER_SHIFT 0
11253 #define BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port) \
11254 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_SHIFT, \
11255 BXT_MIPI2_RX_ESCLK_LOWER_SHIFT)
11256 #define BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 16)
11257 #define BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 0)
11258 #define BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port) \
11259 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK, \
11260 BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK)
11261 #define BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, val) \
11262 (((val) & 3) << BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port))
11263
11264 #define RX_DIVIDER_BIT_1_2 0x3
11265 #define RX_DIVIDER_BIT_3_4 0xC
11266
11267 /* BXT MIPI mode configure */
11268 #define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8
11269 #define _BXT_MIPIC_TRANS_HACTIVE 0x6B8F8
11270 #define BXT_MIPI_TRANS_HACTIVE(tc) _MMIO_MIPI(tc, \
11271 _BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE)
11272
11273 #define _BXT_MIPIA_TRANS_VACTIVE 0x6B0FC
11274 #define _BXT_MIPIC_TRANS_VACTIVE 0x6B8FC
11275 #define BXT_MIPI_TRANS_VACTIVE(tc) _MMIO_MIPI(tc, \
11276 _BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE)
11277
11278 #define _BXT_MIPIA_TRANS_VTOTAL 0x6B100
11279 #define _BXT_MIPIC_TRANS_VTOTAL 0x6B900
11280 #define BXT_MIPI_TRANS_VTOTAL(tc) _MMIO_MIPI(tc, \
11281 _BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL)
11282
11283 #define BXT_DSI_PLL_CTL _MMIO(0x161000)
11284 #define BXT_DSI_PLL_PVD_RATIO_SHIFT 16
11285 #define BXT_DSI_PLL_PVD_RATIO_MASK (3 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
11286 #define BXT_DSI_PLL_PVD_RATIO_1 (1 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
11287 #define BXT_DSIC_16X_BY1 (0 << 10)
11288 #define BXT_DSIC_16X_BY2 (1 << 10)
11289 #define BXT_DSIC_16X_BY3 (2 << 10)
11290 #define BXT_DSIC_16X_BY4 (3 << 10)
11291 #define BXT_DSIC_16X_MASK (3 << 10)
11292 #define BXT_DSIA_16X_BY1 (0 << 8)
11293 #define BXT_DSIA_16X_BY2 (1 << 8)
11294 #define BXT_DSIA_16X_BY3 (2 << 8)
11295 #define BXT_DSIA_16X_BY4 (3 << 8)
11296 #define BXT_DSIA_16X_MASK (3 << 8)
11297 #define BXT_DSI_FREQ_SEL_SHIFT 8
11298 #define BXT_DSI_FREQ_SEL_MASK (0xF << BXT_DSI_FREQ_SEL_SHIFT)
11299
11300 #define BXT_DSI_PLL_RATIO_MAX 0x7D
11301 #define BXT_DSI_PLL_RATIO_MIN 0x22
11302 #define GLK_DSI_PLL_RATIO_MAX 0x6F
11303 #define GLK_DSI_PLL_RATIO_MIN 0x22
11304 #define BXT_DSI_PLL_RATIO_MASK 0xFF
11305 #define BXT_REF_CLOCK_KHZ 19200
11306
11307 #define BXT_DSI_PLL_ENABLE _MMIO(0x46080)
11308 #define BXT_DSI_PLL_DO_ENABLE (1 << 31)
11309 #define BXT_DSI_PLL_LOCKED (1 << 30)
11310
11311 #define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190)
11312 #define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700)
11313 #define MIPI_PORT_CTRL(port) _MMIO_MIPI(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL)
11314
11315 /* BXT port control */
11316 #define _BXT_MIPIA_PORT_CTRL 0x6B0C0
11317 #define _BXT_MIPIC_PORT_CTRL 0x6B8C0
11318 #define BXT_MIPI_PORT_CTRL(tc) _MMIO_MIPI(tc, _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL)
11319
11320 /* ICL DSI MODE control */
11321 #define _ICL_DSI_IO_MODECTL_0 0x6B094
11322 #define _ICL_DSI_IO_MODECTL_1 0x6B894
11323 #define ICL_DSI_IO_MODECTL(port) _MMIO_PORT(port, \
11324 _ICL_DSI_IO_MODECTL_0, \
11325 _ICL_DSI_IO_MODECTL_1)
11326 #define COMBO_PHY_MODE_DSI (1 << 0)
11327
11328 /* Display Stream Splitter Control */
11329 #define DSS_CTL1 _MMIO(0x67400)
11330 #define SPLITTER_ENABLE (1 << 31)
11331 #define JOINER_ENABLE (1 << 30)
11332 #define DUAL_LINK_MODE_INTERLEAVE (1 << 24)
11333 #define DUAL_LINK_MODE_FRONTBACK (0 << 24)
11334 #define OVERLAP_PIXELS_MASK (0xf << 16)
11335 #define OVERLAP_PIXELS(pixels) ((pixels) << 16)
11336 #define LEFT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
11337 #define LEFT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
11338 #define MAX_DL_BUFFER_TARGET_DEPTH 0x5a0
11339
11340 #define DSS_CTL2 _MMIO(0x67404)
11341 #define LEFT_BRANCH_VDSC_ENABLE (1 << 31)
11342 #define RIGHT_BRANCH_VDSC_ENABLE (1 << 15)
11343 #define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
11344 #define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
11345
11346 #define _ICL_PIPE_DSS_CTL1_PB 0x78200
11347 #define _ICL_PIPE_DSS_CTL1_PC 0x78400
11348 #define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11349 _ICL_PIPE_DSS_CTL1_PB, \
11350 _ICL_PIPE_DSS_CTL1_PC)
11351 #define BIG_JOINER_ENABLE (1 << 29)
11352 #define MASTER_BIG_JOINER_ENABLE (1 << 28)
11353 #define VGA_CENTERING_ENABLE (1 << 27)
11354
11355 #define _ICL_PIPE_DSS_CTL2_PB 0x78204
11356 #define _ICL_PIPE_DSS_CTL2_PC 0x78404
11357 #define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11358 _ICL_PIPE_DSS_CTL2_PB, \
11359 _ICL_PIPE_DSS_CTL2_PC)
11360
11361 #define BXT_P_DSI_REGULATOR_CFG _MMIO(0x160020)
11362 #define STAP_SELECT (1 << 0)
11363
11364 #define BXT_P_DSI_REGULATOR_TX_CTRL _MMIO(0x160054)
11365 #define HS_IO_CTRL_SELECT (1 << 0)
11366
11367 #define DPI_ENABLE (1 << 31) /* A + C */
11368 #define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27
11369 #define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27)
11370 #define DUAL_LINK_MODE_SHIFT 26
11371 #define DUAL_LINK_MODE_MASK (1 << 26)
11372 #define DUAL_LINK_MODE_FRONT_BACK (0 << 26)
11373 #define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26)
11374 #define DITHERING_ENABLE (1 << 25) /* A + C */
11375 #define FLOPPED_HSTX (1 << 23)
11376 #define DE_INVERT (1 << 19) /* XXX */
11377 #define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18
11378 #define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18)
11379 #define AFE_LATCHOUT (1 << 17)
11380 #define LP_OUTPUT_HOLD (1 << 16)
11381 #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15
11382 #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15)
11383 #define MIPIC_MIPI4DPHY_DELAY_COUNT_SHIFT 11
11384 #define MIPIC_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11)
11385 #define CSB_SHIFT 9
11386 #define CSB_MASK (3 << 9)
11387 #define CSB_20MHZ (0 << 9)
11388 #define CSB_10MHZ (1 << 9)
11389 #define CSB_40MHZ (2 << 9)
11390 #define BANDGAP_MASK (1 << 8)
11391 #define BANDGAP_PNW_CIRCUIT (0 << 8)
11392 #define BANDGAP_LNC_CIRCUIT (1 << 8)
11393 #define MIPIC_FLISDSI_DELAY_COUNT_LOW_SHIFT 5
11394 #define MIPIC_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5)
11395 #define TEARING_EFFECT_DELAY (1 << 4) /* A + C */
11396 #define TEARING_EFFECT_SHIFT 2 /* A + C */
11397 #define TEARING_EFFECT_MASK (3 << 2)
11398 #define TEARING_EFFECT_OFF (0 << 2)
11399 #define TEARING_EFFECT_DSI (1 << 2)
11400 #define TEARING_EFFECT_GPIO (2 << 2)
11401 #define LANE_CONFIGURATION_SHIFT 0
11402 #define LANE_CONFIGURATION_MASK (3 << 0)
11403 #define LANE_CONFIGURATION_4LANE (0 << 0)
11404 #define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0)
11405 #define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0)
11406
11407 #define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194)
11408 #define _MIPIC_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704)
11409 #define MIPI_TEARING_CTRL(port) _MMIO_MIPI(port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL)
11410 #define TEARING_EFFECT_DELAY_SHIFT 0
11411 #define TEARING_EFFECT_DELAY_MASK (0xffff << 0)
11412
11413 /* XXX: all bits reserved */
11414 #define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0)
11415
11416 /* MIPI DSI Controller and D-PHY registers */
11417
11418 #define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000)
11419 #define _MIPIC_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800)
11420 #define MIPI_DEVICE_READY(port) _MMIO_MIPI(port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY)
11421 #define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */
11422 #define ULPS_STATE_MASK (3 << 1)
11423 #define ULPS_STATE_ENTER (2 << 1)
11424 #define ULPS_STATE_EXIT (1 << 1)
11425 #define ULPS_STATE_NORMAL_OPERATION (0 << 1)
11426 #define DEVICE_READY (1 << 0)
11427
11428 #define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004)
11429 #define _MIPIC_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804)
11430 #define MIPI_INTR_STAT(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT)
11431 #define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008)
11432 #define _MIPIC_INTR_EN (dev_priv->mipi_mmio_base + 0xb808)
11433 #define MIPI_INTR_EN(port) _MMIO_MIPI(port, _MIPIA_INTR_EN, _MIPIC_INTR_EN)
11434 #define TEARING_EFFECT (1 << 31)
11435 #define SPL_PKT_SENT_INTERRUPT (1 << 30)
11436 #define GEN_READ_DATA_AVAIL (1 << 29)
11437 #define LP_GENERIC_WR_FIFO_FULL (1 << 28)
11438 #define HS_GENERIC_WR_FIFO_FULL (1 << 27)
11439 #define RX_PROT_VIOLATION (1 << 26)
11440 #define RX_INVALID_TX_LENGTH (1 << 25)
11441 #define ACK_WITH_NO_ERROR (1 << 24)
11442 #define TURN_AROUND_ACK_TIMEOUT (1 << 23)
11443 #define LP_RX_TIMEOUT (1 << 22)
11444 #define HS_TX_TIMEOUT (1 << 21)
11445 #define DPI_FIFO_UNDERRUN (1 << 20)
11446 #define LOW_CONTENTION (1 << 19)
11447 #define HIGH_CONTENTION (1 << 18)
11448 #define TXDSI_VC_ID_INVALID (1 << 17)
11449 #define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16)
11450 #define TXCHECKSUM_ERROR (1 << 15)
11451 #define TXECC_MULTIBIT_ERROR (1 << 14)
11452 #define TXECC_SINGLE_BIT_ERROR (1 << 13)
11453 #define TXFALSE_CONTROL_ERROR (1 << 12)
11454 #define RXDSI_VC_ID_INVALID (1 << 11)
11455 #define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10)
11456 #define RXCHECKSUM_ERROR (1 << 9)
11457 #define RXECC_MULTIBIT_ERROR (1 << 8)
11458 #define RXECC_SINGLE_BIT_ERROR (1 << 7)
11459 #define RXFALSE_CONTROL_ERROR (1 << 6)
11460 #define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5)
11461 #define RX_LP_TX_SYNC_ERROR (1 << 4)
11462 #define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3)
11463 #define RXEOT_SYNC_ERROR (1 << 2)
11464 #define RXSOT_SYNC_ERROR (1 << 1)
11465 #define RXSOT_ERROR (1 << 0)
11466
11467 #define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c)
11468 #define _MIPIC_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c)
11469 #define MIPI_DSI_FUNC_PRG(port) _MMIO_MIPI(port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG)
11470 #define CMD_MODE_DATA_WIDTH_MASK (7 << 13)
11471 #define CMD_MODE_NOT_SUPPORTED (0 << 13)
11472 #define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13)
11473 #define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13)
11474 #define CMD_MODE_DATA_WIDTH_8_BIT (3 << 13)
11475 #define CMD_MODE_DATA_WIDTH_OPTION1 (4 << 13)
11476 #define CMD_MODE_DATA_WIDTH_OPTION2 (5 << 13)
11477 #define VID_MODE_FORMAT_MASK (0xf << 7)
11478 #define VID_MODE_NOT_SUPPORTED (0 << 7)
11479 #define VID_MODE_FORMAT_RGB565 (1 << 7)
11480 #define VID_MODE_FORMAT_RGB666_PACKED (2 << 7)
11481 #define VID_MODE_FORMAT_RGB666 (3 << 7)
11482 #define VID_MODE_FORMAT_RGB888 (4 << 7)
11483 #define CMD_MODE_CHANNEL_NUMBER_SHIFT 5
11484 #define CMD_MODE_CHANNEL_NUMBER_MASK (3 << 5)
11485 #define VID_MODE_CHANNEL_NUMBER_SHIFT 3
11486 #define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3)
11487 #define DATA_LANES_PRG_REG_SHIFT 0
11488 #define DATA_LANES_PRG_REG_MASK (7 << 0)
11489
11490 #define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010)
11491 #define _MIPIC_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810)
11492 #define MIPI_HS_TX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT)
11493 #define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff
11494
11495 #define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014)
11496 #define _MIPIC_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814)
11497 #define MIPI_LP_RX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT)
11498 #define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff
11499
11500 #define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018)
11501 #define _MIPIC_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818)
11502 #define MIPI_TURN_AROUND_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT)
11503 #define TURN_AROUND_TIMEOUT_MASK 0x3f
11504
11505 #define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c)
11506 #define _MIPIC_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c)
11507 #define MIPI_DEVICE_RESET_TIMER(port) _MMIO_MIPI(port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER)
11508 #define DEVICE_RESET_TIMER_MASK 0xffff
11509
11510 #define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020)
11511 #define _MIPIC_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820)
11512 #define MIPI_DPI_RESOLUTION(port) _MMIO_MIPI(port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION)
11513 #define VERTICAL_ADDRESS_SHIFT 16
11514 #define VERTICAL_ADDRESS_MASK (0xffff << 16)
11515 #define HORIZONTAL_ADDRESS_SHIFT 0
11516 #define HORIZONTAL_ADDRESS_MASK 0xffff
11517
11518 #define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024)
11519 #define _MIPIC_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824)
11520 #define MIPI_DBI_FIFO_THROTTLE(port) _MMIO_MIPI(port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE)
11521 #define DBI_FIFO_EMPTY_HALF (0 << 0)
11522 #define DBI_FIFO_EMPTY_QUARTER (1 << 0)
11523 #define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0)
11524
11525 /* regs below are bits 15:0 */
11526 #define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028)
11527 #define _MIPIC_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828)
11528 #define MIPI_HSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT)
11529
11530 #define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c)
11531 #define _MIPIC_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c)
11532 #define MIPI_HBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT)
11533
11534 #define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030)
11535 #define _MIPIC_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830)
11536 #define MIPI_HFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT)
11537
11538 #define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034)
11539 #define _MIPIC_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834)
11540 #define MIPI_HACTIVE_AREA_COUNT(port) _MMIO_MIPI(port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT)
11541
11542 #define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038)
11543 #define _MIPIC_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838)
11544 #define MIPI_VSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT)
11545
11546 #define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c)
11547 #define _MIPIC_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c)
11548 #define MIPI_VBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT)
11549
11550 #define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040)
11551 #define _MIPIC_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840)
11552 #define MIPI_VFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT)
11553
11554 #define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044)
11555 #define _MIPIC_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844)
11556 #define MIPI_HIGH_LOW_SWITCH_COUNT(port) _MMIO_MIPI(port, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT)
11557
11558 /* regs above are bits 15:0 */
11559
11560 #define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048)
11561 #define _MIPIC_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848)
11562 #define MIPI_DPI_CONTROL(port) _MMIO_MIPI(port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL)
11563 #define DPI_LP_MODE (1 << 6)
11564 #define BACKLIGHT_OFF (1 << 5)
11565 #define BACKLIGHT_ON (1 << 4)
11566 #define COLOR_MODE_OFF (1 << 3)
11567 #define COLOR_MODE_ON (1 << 2)
11568 #define TURN_ON (1 << 1)
11569 #define SHUTDOWN (1 << 0)
11570
11571 #define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c)
11572 #define _MIPIC_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c)
11573 #define MIPI_DPI_DATA(port) _MMIO_MIPI(port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA)
11574 #define COMMAND_BYTE_SHIFT 0
11575 #define COMMAND_BYTE_MASK (0x3f << 0)
11576
11577 #define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050)
11578 #define _MIPIC_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850)
11579 #define MIPI_INIT_COUNT(port) _MMIO_MIPI(port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT)
11580 #define MASTER_INIT_TIMER_SHIFT 0
11581 #define MASTER_INIT_TIMER_MASK (0xffff << 0)
11582
11583 #define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054)
11584 #define _MIPIC_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854)
11585 #define MIPI_MAX_RETURN_PKT_SIZE(port) _MMIO_MIPI(port, \
11586 _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE)
11587 #define MAX_RETURN_PKT_SIZE_SHIFT 0
11588 #define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0)
11589
11590 #define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058)
11591 #define _MIPIC_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858)
11592 #define MIPI_VIDEO_MODE_FORMAT(port) _MMIO_MIPI(port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT)
11593 #define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4)
11594 #define DISABLE_VIDEO_BTA (1 << 3)
11595 #define IP_TG_CONFIG (1 << 2)
11596 #define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0)
11597 #define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0)
11598 #define VIDEO_MODE_BURST (3 << 0)
11599
11600 #define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c)
11601 #define _MIPIC_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c)
11602 #define MIPI_EOT_DISABLE(port) _MMIO_MIPI(port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE)
11603 #define BXT_DEFEATURE_DPI_FIFO_CTR (1 << 9)
11604 #define BXT_DPHY_DEFEATURE_EN (1 << 8)
11605 #define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7)
11606 #define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6)
11607 #define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5)
11608 #define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4)
11609 #define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3)
11610 #define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2)
11611 #define CLOCKSTOP (1 << 1)
11612 #define EOT_DISABLE (1 << 0)
11613
11614 #define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060)
11615 #define _MIPIC_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860)
11616 #define MIPI_LP_BYTECLK(port) _MMIO_MIPI(port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK)
11617 #define LP_BYTECLK_SHIFT 0
11618 #define LP_BYTECLK_MASK (0xffff << 0)
11619
11620 #define _MIPIA_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb0a4)
11621 #define _MIPIC_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb8a4)
11622 #define MIPI_TLPX_TIME_COUNT(port) _MMIO_MIPI(port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT)
11623
11624 #define _MIPIA_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb098)
11625 #define _MIPIC_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb898)
11626 #define MIPI_CLK_LANE_TIMING(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING)
11627
11628 /* bits 31:0 */
11629 #define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064)
11630 #define _MIPIC_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864)
11631 #define MIPI_LP_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA)
11632
11633 /* bits 31:0 */
11634 #define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068)
11635 #define _MIPIC_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868)
11636 #define MIPI_HS_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA)
11637
11638 #define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c)
11639 #define _MIPIC_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c)
11640 #define MIPI_LP_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL)
11641 #define _MIPIA_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb070)
11642 #define _MIPIC_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870)
11643 #define MIPI_HS_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL)
11644 #define LONG_PACKET_WORD_COUNT_SHIFT 8
11645 #define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8)
11646 #define SHORT_PACKET_PARAM_SHIFT 8
11647 #define SHORT_PACKET_PARAM_MASK (0xffff << 8)
11648 #define VIRTUAL_CHANNEL_SHIFT 6
11649 #define VIRTUAL_CHANNEL_MASK (3 << 6)
11650 #define DATA_TYPE_SHIFT 0
11651 #define DATA_TYPE_MASK (0x3f << 0)
11652 /* data type values, see include/video/mipi_display.h */
11653
11654 #define _MIPIA_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb074)
11655 #define _MIPIC_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874)
11656 #define MIPI_GEN_FIFO_STAT(port) _MMIO_MIPI(port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT)
11657 #define DPI_FIFO_EMPTY (1 << 28)
11658 #define DBI_FIFO_EMPTY (1 << 27)
11659 #define LP_CTRL_FIFO_EMPTY (1 << 26)
11660 #define LP_CTRL_FIFO_HALF_EMPTY (1 << 25)
11661 #define LP_CTRL_FIFO_FULL (1 << 24)
11662 #define HS_CTRL_FIFO_EMPTY (1 << 18)
11663 #define HS_CTRL_FIFO_HALF_EMPTY (1 << 17)
11664 #define HS_CTRL_FIFO_FULL (1 << 16)
11665 #define LP_DATA_FIFO_EMPTY (1 << 10)
11666 #define LP_DATA_FIFO_HALF_EMPTY (1 << 9)
11667 #define LP_DATA_FIFO_FULL (1 << 8)
11668 #define HS_DATA_FIFO_EMPTY (1 << 2)
11669 #define HS_DATA_FIFO_HALF_EMPTY (1 << 1)
11670 #define HS_DATA_FIFO_FULL (1 << 0)
11671
11672 #define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078)
11673 #define _MIPIC_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878)
11674 #define MIPI_HS_LP_DBI_ENABLE(port) _MMIO_MIPI(port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE)
11675 #define DBI_HS_LP_MODE_MASK (1 << 0)
11676 #define DBI_LP_MODE (1 << 0)
11677 #define DBI_HS_MODE (0 << 0)
11678
11679 #define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080)
11680 #define _MIPIC_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880)
11681 #define MIPI_DPHY_PARAM(port) _MMIO_MIPI(port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM)
11682 #define EXIT_ZERO_COUNT_SHIFT 24
11683 #define EXIT_ZERO_COUNT_MASK (0x3f << 24)
11684 #define TRAIL_COUNT_SHIFT 16
11685 #define TRAIL_COUNT_MASK (0x1f << 16)
11686 #define CLK_ZERO_COUNT_SHIFT 8
11687 #define CLK_ZERO_COUNT_MASK (0xff << 8)
11688 #define PREPARE_COUNT_SHIFT 0
11689 #define PREPARE_COUNT_MASK (0x3f << 0)
11690
11691 #define _ICL_DSI_T_INIT_MASTER_0 0x6b088
11692 #define _ICL_DSI_T_INIT_MASTER_1 0x6b888
11693 #define ICL_DSI_T_INIT_MASTER(port) _MMIO_PORT(port, \
11694 _ICL_DSI_T_INIT_MASTER_0,\
11695 _ICL_DSI_T_INIT_MASTER_1)
11696
11697 #define _DPHY_CLK_TIMING_PARAM_0 0x162180
11698 #define _DPHY_CLK_TIMING_PARAM_1 0x6c180
11699 #define DPHY_CLK_TIMING_PARAM(port) _MMIO_PORT(port, \
11700 _DPHY_CLK_TIMING_PARAM_0,\
11701 _DPHY_CLK_TIMING_PARAM_1)
11702 #define _DSI_CLK_TIMING_PARAM_0 0x6b080
11703 #define _DSI_CLK_TIMING_PARAM_1 0x6b880
11704 #define DSI_CLK_TIMING_PARAM(port) _MMIO_PORT(port, \
11705 _DSI_CLK_TIMING_PARAM_0,\
11706 _DSI_CLK_TIMING_PARAM_1)
11707 #define CLK_PREPARE_OVERRIDE (1 << 31)
11708 #define CLK_PREPARE(x) ((x) << 28)
11709 #define CLK_PREPARE_MASK (0x7 << 28)
11710 #define CLK_PREPARE_SHIFT 28
11711 #define CLK_ZERO_OVERRIDE (1 << 27)
11712 #define CLK_ZERO(x) ((x) << 20)
11713 #define CLK_ZERO_MASK (0xf << 20)
11714 #define CLK_ZERO_SHIFT 20
11715 #define CLK_PRE_OVERRIDE (1 << 19)
11716 #define CLK_PRE(x) ((x) << 16)
11717 #define CLK_PRE_MASK (0x3 << 16)
11718 #define CLK_PRE_SHIFT 16
11719 #define CLK_POST_OVERRIDE (1 << 15)
11720 #define CLK_POST(x) ((x) << 8)
11721 #define CLK_POST_MASK (0x7 << 8)
11722 #define CLK_POST_SHIFT 8
11723 #define CLK_TRAIL_OVERRIDE (1 << 7)
11724 #define CLK_TRAIL(x) ((x) << 0)
11725 #define CLK_TRAIL_MASK (0xf << 0)
11726 #define CLK_TRAIL_SHIFT 0
11727
11728 #define _DPHY_DATA_TIMING_PARAM_0 0x162184
11729 #define _DPHY_DATA_TIMING_PARAM_1 0x6c184
11730 #define DPHY_DATA_TIMING_PARAM(port) _MMIO_PORT(port, \
11731 _DPHY_DATA_TIMING_PARAM_0,\
11732 _DPHY_DATA_TIMING_PARAM_1)
11733 #define _DSI_DATA_TIMING_PARAM_0 0x6B084
11734 #define _DSI_DATA_TIMING_PARAM_1 0x6B884
11735 #define DSI_DATA_TIMING_PARAM(port) _MMIO_PORT(port, \
11736 _DSI_DATA_TIMING_PARAM_0,\
11737 _DSI_DATA_TIMING_PARAM_1)
11738 #define HS_PREPARE_OVERRIDE (1 << 31)
11739 #define HS_PREPARE(x) ((x) << 24)
11740 #define HS_PREPARE_MASK (0x7 << 24)
11741 #define HS_PREPARE_SHIFT 24
11742 #define HS_ZERO_OVERRIDE (1 << 23)
11743 #define HS_ZERO(x) ((x) << 16)
11744 #define HS_ZERO_MASK (0xf << 16)
11745 #define HS_ZERO_SHIFT 16
11746 #define HS_TRAIL_OVERRIDE (1 << 15)
11747 #define HS_TRAIL(x) ((x) << 8)
11748 #define HS_TRAIL_MASK (0x7 << 8)
11749 #define HS_TRAIL_SHIFT 8
11750 #define HS_EXIT_OVERRIDE (1 << 7)
11751 #define HS_EXIT(x) ((x) << 0)
11752 #define HS_EXIT_MASK (0x7 << 0)
11753 #define HS_EXIT_SHIFT 0
11754
11755 #define _DPHY_TA_TIMING_PARAM_0 0x162188
11756 #define _DPHY_TA_TIMING_PARAM_1 0x6c188
11757 #define DPHY_TA_TIMING_PARAM(port) _MMIO_PORT(port, \
11758 _DPHY_TA_TIMING_PARAM_0,\
11759 _DPHY_TA_TIMING_PARAM_1)
11760 #define _DSI_TA_TIMING_PARAM_0 0x6b098
11761 #define _DSI_TA_TIMING_PARAM_1 0x6b898
11762 #define DSI_TA_TIMING_PARAM(port) _MMIO_PORT(port, \
11763 _DSI_TA_TIMING_PARAM_0,\
11764 _DSI_TA_TIMING_PARAM_1)
11765 #define TA_SURE_OVERRIDE (1 << 31)
11766 #define TA_SURE(x) ((x) << 16)
11767 #define TA_SURE_MASK (0x1f << 16)
11768 #define TA_SURE_SHIFT 16
11769 #define TA_GO_OVERRIDE (1 << 15)
11770 #define TA_GO(x) ((x) << 8)
11771 #define TA_GO_MASK (0xf << 8)
11772 #define TA_GO_SHIFT 8
11773 #define TA_GET_OVERRIDE (1 << 7)
11774 #define TA_GET(x) ((x) << 0)
11775 #define TA_GET_MASK (0xf << 0)
11776 #define TA_GET_SHIFT 0
11777
11778 /* DSI transcoder configuration */
11779 #define _DSI_TRANS_FUNC_CONF_0 0x6b030
11780 #define _DSI_TRANS_FUNC_CONF_1 0x6b830
11781 #define DSI_TRANS_FUNC_CONF(tc) _MMIO_DSI(tc, \
11782 _DSI_TRANS_FUNC_CONF_0,\
11783 _DSI_TRANS_FUNC_CONF_1)
11784 #define OP_MODE_MASK (0x3 << 28)
11785 #define OP_MODE_SHIFT 28
11786 #define CMD_MODE_NO_GATE (0x0 << 28)
11787 #define CMD_MODE_TE_GATE (0x1 << 28)
11788 #define VIDEO_MODE_SYNC_EVENT (0x2 << 28)
11789 #define VIDEO_MODE_SYNC_PULSE (0x3 << 28)
11790 #define TE_SOURCE_GPIO (1 << 27)
11791 #define LINK_READY (1 << 20)
11792 #define PIX_FMT_MASK (0x3 << 16)
11793 #define PIX_FMT_SHIFT 16
11794 #define PIX_FMT_RGB565 (0x0 << 16)
11795 #define PIX_FMT_RGB666_PACKED (0x1 << 16)
11796 #define PIX_FMT_RGB666_LOOSE (0x2 << 16)
11797 #define PIX_FMT_RGB888 (0x3 << 16)
11798 #define PIX_FMT_RGB101010 (0x4 << 16)
11799 #define PIX_FMT_RGB121212 (0x5 << 16)
11800 #define PIX_FMT_COMPRESSED (0x6 << 16)
11801 #define BGR_TRANSMISSION (1 << 15)
11802 #define PIX_VIRT_CHAN(x) ((x) << 12)
11803 #define PIX_VIRT_CHAN_MASK (0x3 << 12)
11804 #define PIX_VIRT_CHAN_SHIFT 12
11805 #define PIX_BUF_THRESHOLD_MASK (0x3 << 10)
11806 #define PIX_BUF_THRESHOLD_SHIFT 10
11807 #define PIX_BUF_THRESHOLD_1_4 (0x0 << 10)
11808 #define PIX_BUF_THRESHOLD_1_2 (0x1 << 10)
11809 #define PIX_BUF_THRESHOLD_3_4 (0x2 << 10)
11810 #define PIX_BUF_THRESHOLD_FULL (0x3 << 10)
11811 #define CONTINUOUS_CLK_MASK (0x3 << 8)
11812 #define CONTINUOUS_CLK_SHIFT 8
11813 #define CLK_ENTER_LP_AFTER_DATA (0x0 << 8)
11814 #define CLK_HS_OR_LP (0x2 << 8)
11815 #define CLK_HS_CONTINUOUS (0x3 << 8)
11816 #define LINK_CALIBRATION_MASK (0x3 << 4)
11817 #define LINK_CALIBRATION_SHIFT 4
11818 #define CALIBRATION_DISABLED (0x0 << 4)
11819 #define CALIBRATION_ENABLED_INITIAL_ONLY (0x2 << 4)
11820 #define CALIBRATION_ENABLED_INITIAL_PERIODIC (0x3 << 4)
11821 #define BLANKING_PACKET_ENABLE (1 << 2)
11822 #define S3D_ORIENTATION_LANDSCAPE (1 << 1)
11823 #define EOTP_DISABLED (1 << 0)
11824
11825 #define _DSI_CMD_RXCTL_0 0x6b0d4
11826 #define _DSI_CMD_RXCTL_1 0x6b8d4
11827 #define DSI_CMD_RXCTL(tc) _MMIO_DSI(tc, \
11828 _DSI_CMD_RXCTL_0,\
11829 _DSI_CMD_RXCTL_1)
11830 #define READ_UNLOADS_DW (1 << 16)
11831 #define RECEIVED_UNASSIGNED_TRIGGER (1 << 15)
11832 #define RECEIVED_ACKNOWLEDGE_TRIGGER (1 << 14)
11833 #define RECEIVED_TEAR_EFFECT_TRIGGER (1 << 13)
11834 #define RECEIVED_RESET_TRIGGER (1 << 12)
11835 #define RECEIVED_PAYLOAD_WAS_LOST (1 << 11)
11836 #define RECEIVED_CRC_WAS_LOST (1 << 10)
11837 #define NUMBER_RX_PLOAD_DW_MASK (0xff << 0)
11838 #define NUMBER_RX_PLOAD_DW_SHIFT 0
11839
11840 #define _DSI_CMD_TXCTL_0 0x6b0d0
11841 #define _DSI_CMD_TXCTL_1 0x6b8d0
11842 #define DSI_CMD_TXCTL(tc) _MMIO_DSI(tc, \
11843 _DSI_CMD_TXCTL_0,\
11844 _DSI_CMD_TXCTL_1)
11845 #define KEEP_LINK_IN_HS (1 << 24)
11846 #define FREE_HEADER_CREDIT_MASK (0x1f << 8)
11847 #define FREE_HEADER_CREDIT_SHIFT 0x8
11848 #define FREE_PLOAD_CREDIT_MASK (0xff << 0)
11849 #define FREE_PLOAD_CREDIT_SHIFT 0
11850 #define MAX_HEADER_CREDIT 0x10
11851 #define MAX_PLOAD_CREDIT 0x40
11852
11853 #define _DSI_CMD_TXHDR_0 0x6b100
11854 #define _DSI_CMD_TXHDR_1 0x6b900
11855 #define DSI_CMD_TXHDR(tc) _MMIO_DSI(tc, \
11856 _DSI_CMD_TXHDR_0,\
11857 _DSI_CMD_TXHDR_1)
11858 #define PAYLOAD_PRESENT (1 << 31)
11859 #define LP_DATA_TRANSFER (1 << 30)
11860 #define VBLANK_FENCE (1 << 29)
11861 #define PARAM_WC_MASK (0xffff << 8)
11862 #define PARAM_WC_LOWER_SHIFT 8
11863 #define PARAM_WC_UPPER_SHIFT 16
11864 #define VC_MASK (0x3 << 6)
11865 #define VC_SHIFT 6
11866 #define DT_MASK (0x3f << 0)
11867 #define DT_SHIFT 0
11868
11869 #define _DSI_CMD_TXPYLD_0 0x6b104
11870 #define _DSI_CMD_TXPYLD_1 0x6b904
11871 #define DSI_CMD_TXPYLD(tc) _MMIO_DSI(tc, \
11872 _DSI_CMD_TXPYLD_0,\
11873 _DSI_CMD_TXPYLD_1)
11874
11875 #define _DSI_LP_MSG_0 0x6b0d8
11876 #define _DSI_LP_MSG_1 0x6b8d8
11877 #define DSI_LP_MSG(tc) _MMIO_DSI(tc, \
11878 _DSI_LP_MSG_0,\
11879 _DSI_LP_MSG_1)
11880 #define LPTX_IN_PROGRESS (1 << 17)
11881 #define LINK_IN_ULPS (1 << 16)
11882 #define LINK_ULPS_TYPE_LP11 (1 << 8)
11883 #define LINK_ENTER_ULPS (1 << 0)
11884
11885 /* DSI timeout registers */
11886 #define _DSI_HSTX_TO_0 0x6b044
11887 #define _DSI_HSTX_TO_1 0x6b844
11888 #define DSI_HSTX_TO(tc) _MMIO_DSI(tc, \
11889 _DSI_HSTX_TO_0,\
11890 _DSI_HSTX_TO_1)
11891 #define HSTX_TIMEOUT_VALUE_MASK (0xffff << 16)
11892 #define HSTX_TIMEOUT_VALUE_SHIFT 16
11893 #define HSTX_TIMEOUT_VALUE(x) ((x) << 16)
11894 #define HSTX_TIMED_OUT (1 << 0)
11895
11896 #define _DSI_LPRX_HOST_TO_0 0x6b048
11897 #define _DSI_LPRX_HOST_TO_1 0x6b848
11898 #define DSI_LPRX_HOST_TO(tc) _MMIO_DSI(tc, \
11899 _DSI_LPRX_HOST_TO_0,\
11900 _DSI_LPRX_HOST_TO_1)
11901 #define LPRX_TIMED_OUT (1 << 16)
11902 #define LPRX_TIMEOUT_VALUE_MASK (0xffff << 0)
11903 #define LPRX_TIMEOUT_VALUE_SHIFT 0
11904 #define LPRX_TIMEOUT_VALUE(x) ((x) << 0)
11905
11906 #define _DSI_PWAIT_TO_0 0x6b040
11907 #define _DSI_PWAIT_TO_1 0x6b840
11908 #define DSI_PWAIT_TO(tc) _MMIO_DSI(tc, \
11909 _DSI_PWAIT_TO_0,\
11910 _DSI_PWAIT_TO_1)
11911 #define PRESET_TIMEOUT_VALUE_MASK (0xffff << 16)
11912 #define PRESET_TIMEOUT_VALUE_SHIFT 16
11913 #define PRESET_TIMEOUT_VALUE(x) ((x) << 16)
11914 #define PRESPONSE_TIMEOUT_VALUE_MASK (0xffff << 0)
11915 #define PRESPONSE_TIMEOUT_VALUE_SHIFT 0
11916 #define PRESPONSE_TIMEOUT_VALUE(x) ((x) << 0)
11917
11918 #define _DSI_TA_TO_0 0x6b04c
11919 #define _DSI_TA_TO_1 0x6b84c
11920 #define DSI_TA_TO(tc) _MMIO_DSI(tc, \
11921 _DSI_TA_TO_0,\
11922 _DSI_TA_TO_1)
11923 #define TA_TIMED_OUT (1 << 16)
11924 #define TA_TIMEOUT_VALUE_MASK (0xffff << 0)
11925 #define TA_TIMEOUT_VALUE_SHIFT 0
11926 #define TA_TIMEOUT_VALUE(x) ((x) << 0)
11927
11928 /* bits 31:0 */
11929 #define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084)
11930 #define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884)
11931 #define MIPI_DBI_BW_CTRL(port) _MMIO_MIPI(port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL)
11932
11933 #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb088)
11934 #define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb888)
11935 #define MIPI_CLK_LANE_SWITCH_TIME_CNT(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT)
11936 #define LP_HS_SSW_CNT_SHIFT 16
11937 #define LP_HS_SSW_CNT_MASK (0xffff << 16)
11938 #define HS_LP_PWR_SW_CNT_SHIFT 0
11939 #define HS_LP_PWR_SW_CNT_MASK (0xffff << 0)
11940
11941 #define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c)
11942 #define _MIPIC_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c)
11943 #define MIPI_STOP_STATE_STALL(port) _MMIO_MIPI(port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL)
11944 #define STOP_STATE_STALL_COUNTER_SHIFT 0
11945 #define STOP_STATE_STALL_COUNTER_MASK (0xff << 0)
11946
11947 #define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090)
11948 #define _MIPIC_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890)
11949 #define MIPI_INTR_STAT_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1)
11950 #define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094)
11951 #define _MIPIC_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894)
11952 #define MIPI_INTR_EN_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1)
11953 #define RX_CONTENTION_DETECTED (1 << 0)
11954
11955 /* XXX: only pipe A ?!? */
11956 #define MIPIA_DBI_TYPEC_CTRL (dev_priv->mipi_mmio_base + 0xb100)
11957 #define DBI_TYPEC_ENABLE (1 << 31)
11958 #define DBI_TYPEC_WIP (1 << 30)
11959 #define DBI_TYPEC_OPTION_SHIFT 28
11960 #define DBI_TYPEC_OPTION_MASK (3 << 28)
11961 #define DBI_TYPEC_FREQ_SHIFT 24
11962 #define DBI_TYPEC_FREQ_MASK (0xf << 24)
11963 #define DBI_TYPEC_OVERRIDE (1 << 8)
11964 #define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT 0
11965 #define DBI_TYPEC_OVERRIDE_COUNTER_MASK (0xff << 0)
11966
11967
11968 /* MIPI adapter registers */
11969
11970 #define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104)
11971 #define _MIPIC_CTRL (dev_priv->mipi_mmio_base + 0xb904)
11972 #define MIPI_CTRL(port) _MMIO_MIPI(port, _MIPIA_CTRL, _MIPIC_CTRL)
11973 #define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */
11974 #define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5)
11975 #define ESCAPE_CLOCK_DIVIDER_1 (0 << 5)
11976 #define ESCAPE_CLOCK_DIVIDER_2 (1 << 5)
11977 #define ESCAPE_CLOCK_DIVIDER_4 (2 << 5)
11978 #define READ_REQUEST_PRIORITY_SHIFT 3
11979 #define READ_REQUEST_PRIORITY_MASK (3 << 3)
11980 #define READ_REQUEST_PRIORITY_LOW (0 << 3)
11981 #define READ_REQUEST_PRIORITY_HIGH (3 << 3)
11982 #define RGB_FLIP_TO_BGR (1 << 2)
11983
11984 #define BXT_PIPE_SELECT_SHIFT 7
11985 #define BXT_PIPE_SELECT_MASK (7 << 7)
11986 #define BXT_PIPE_SELECT(pipe) ((pipe) << 7)
11987 #define GLK_PHY_STATUS_PORT_READY (1 << 31) /* RO */
11988 #define GLK_ULPS_NOT_ACTIVE (1 << 30) /* RO */
11989 #define GLK_MIPIIO_RESET_RELEASED (1 << 28)
11990 #define GLK_CLOCK_LANE_STOP_STATE (1 << 27) /* RO */
11991 #define GLK_DATA_LANE_STOP_STATE (1 << 26) /* RO */
11992 #define GLK_LP_WAKE (1 << 22)
11993 #define GLK_LP11_LOW_PWR_MODE (1 << 21)
11994 #define GLK_LP00_LOW_PWR_MODE (1 << 20)
11995 #define GLK_FIREWALL_ENABLE (1 << 16)
11996 #define BXT_PIXEL_OVERLAP_CNT_MASK (0xf << 10)
11997 #define BXT_PIXEL_OVERLAP_CNT_SHIFT 10
11998 #define BXT_DSC_ENABLE (1 << 3)
11999 #define BXT_RGB_FLIP (1 << 2)
12000 #define GLK_MIPIIO_PORT_POWERED (1 << 1) /* RO */
12001 #define GLK_MIPIIO_ENABLE (1 << 0)
12002
12003 #define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108)
12004 #define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908)
12005 #define MIPI_DATA_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS)
12006 #define DATA_MEM_ADDRESS_SHIFT 5
12007 #define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5)
12008 #define DATA_VALID (1 << 0)
12009
12010 #define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c)
12011 #define _MIPIC_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c)
12012 #define MIPI_DATA_LENGTH(port) _MMIO_MIPI(port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH)
12013 #define DATA_LENGTH_SHIFT 0
12014 #define DATA_LENGTH_MASK (0xfffff << 0)
12015
12016 #define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110)
12017 #define _MIPIC_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910)
12018 #define MIPI_COMMAND_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS)
12019 #define COMMAND_MEM_ADDRESS_SHIFT 5
12020 #define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5)
12021 #define AUTO_PWG_ENABLE (1 << 2)
12022 #define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1)
12023 #define COMMAND_VALID (1 << 0)
12024
12025 #define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114)
12026 #define _MIPIC_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914)
12027 #define MIPI_COMMAND_LENGTH(port) _MMIO_MIPI(port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH)
12028 #define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */
12029 #define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n)))
12030
12031 #define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118)
12032 #define _MIPIC_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918)
12033 #define MIPI_READ_DATA_RETURN(port, n) _MMIO(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */
12034
12035 #define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138)
12036 #define _MIPIC_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938)
12037 #define MIPI_READ_DATA_VALID(port) _MMIO_MIPI(port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID)
12038 #define READ_DATA_VALID(n) (1 << (n))
12039
12040 /* MOCS (Memory Object Control State) registers */
12041 #define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */
12042
12043 #define __GEN9_RCS0_MOCS0 0xc800
12044 #define GEN9_GFX_MOCS(i) _MMIO(__GEN9_RCS0_MOCS0 + (i) * 4)
12045 #define __GEN9_VCS0_MOCS0 0xc900
12046 #define GEN9_MFX0_MOCS(i) _MMIO(__GEN9_VCS0_MOCS0 + (i) * 4)
12047 #define __GEN9_VCS1_MOCS0 0xca00
12048 #define GEN9_MFX1_MOCS(i) _MMIO(__GEN9_VCS1_MOCS0 + (i) * 4)
12049 #define __GEN9_VECS0_MOCS0 0xcb00
12050 #define GEN9_VEBOX_MOCS(i) _MMIO(__GEN9_VECS0_MOCS0 + (i) * 4)
12051 #define __GEN9_BCS0_MOCS0 0xcc00
12052 #define GEN9_BLT_MOCS(i) _MMIO(__GEN9_BCS0_MOCS0 + (i) * 4)
12053 #define __GEN11_VCS2_MOCS0 0x10000
12054 #define GEN11_MFX2_MOCS(i) _MMIO(__GEN11_VCS2_MOCS0 + (i) * 4)
12055
12056 #define GEN10_SCRATCH_LNCF2 _MMIO(0xb0a0)
12057 #define PMFLUSHDONE_LNICRSDROP (1 << 20)
12058 #define PMFLUSH_GAPL3UNBLOCK (1 << 21)
12059 #define PMFLUSHDONE_LNEBLK (1 << 22)
12060
12061 #define GEN12_GLOBAL_MOCS(i) _MMIO(0x4000 + (i) * 4) /* Global MOCS regs */
12062
12063 /* gamt regs */
12064 #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
12065 #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for LRA1/2 */
12066 #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV 0x5FF101FF /* max/min for LRA1/2 */
12067 #define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL 0x67F1427F /* " " */
12068 #define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT 0x5FF101FF /* " " */
12069
12070 #define MMCD_MISC_CTRL _MMIO(0x4ddc) /* skl+ */
12071 #define MMCD_PCLA (1 << 31)
12072 #define MMCD_HOTSPOT_EN (1 << 27)
12073
12074 #define _ICL_PHY_MISC_A 0x64C00
12075 #define _ICL_PHY_MISC_B 0x64C04
12076 #define ICL_PHY_MISC(port) _MMIO_PORT(port, _ICL_PHY_MISC_A, \
12077 _ICL_PHY_MISC_B)
12078 #define ICL_PHY_MISC_MUX_DDID (1 << 28)
12079 #define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23)
12080
12081 /* Icelake Display Stream Compression Registers */
12082 #define DSCA_PICTURE_PARAMETER_SET_0 _MMIO(0x6B200)
12083 #define DSCC_PICTURE_PARAMETER_SET_0 _MMIO(0x6BA00)
12084 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB 0x78270
12085 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB 0x78370
12086 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC 0x78470
12087 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC 0x78570
12088 #define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12089 _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \
12090 _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC)
12091 #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12092 _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
12093 _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
12094 #define DSC_VBR_ENABLE (1 << 19)
12095 #define DSC_422_ENABLE (1 << 18)
12096 #define DSC_COLOR_SPACE_CONVERSION (1 << 17)
12097 #define DSC_BLOCK_PREDICTION (1 << 16)
12098 #define DSC_LINE_BUF_DEPTH_SHIFT 12
12099 #define DSC_BPC_SHIFT 8
12100 #define DSC_VER_MIN_SHIFT 4
12101 #define DSC_VER_MAJ (0x1 << 0)
12102
12103 #define DSCA_PICTURE_PARAMETER_SET_1 _MMIO(0x6B204)
12104 #define DSCC_PICTURE_PARAMETER_SET_1 _MMIO(0x6BA04)
12105 #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB 0x78274
12106 #define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB 0x78374
12107 #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC 0x78474
12108 #define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC 0x78574
12109 #define ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12110 _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB, \
12111 _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC)
12112 #define ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12113 _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB, \
12114 _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC)
12115 #define DSC_BPP(bpp) ((bpp) << 0)
12116
12117 #define DSCA_PICTURE_PARAMETER_SET_2 _MMIO(0x6B208)
12118 #define DSCC_PICTURE_PARAMETER_SET_2 _MMIO(0x6BA08)
12119 #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB 0x78278
12120 #define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB 0x78378
12121 #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC 0x78478
12122 #define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC 0x78578
12123 #define ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12124 _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB, \
12125 _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC)
12126 #define ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12127 _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB, \
12128 _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC)
12129 #define DSC_PIC_WIDTH(pic_width) ((pic_width) << 16)
12130 #define DSC_PIC_HEIGHT(pic_height) ((pic_height) << 0)
12131
12132 #define DSCA_PICTURE_PARAMETER_SET_3 _MMIO(0x6B20C)
12133 #define DSCC_PICTURE_PARAMETER_SET_3 _MMIO(0x6BA0C)
12134 #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB 0x7827C
12135 #define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB 0x7837C
12136 #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC 0x7847C
12137 #define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC 0x7857C
12138 #define ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12139 _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB, \
12140 _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC)
12141 #define ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12142 _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB, \
12143 _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC)
12144 #define DSC_SLICE_WIDTH(slice_width) ((slice_width) << 16)
12145 #define DSC_SLICE_HEIGHT(slice_height) ((slice_height) << 0)
12146
12147 #define DSCA_PICTURE_PARAMETER_SET_4 _MMIO(0x6B210)
12148 #define DSCC_PICTURE_PARAMETER_SET_4 _MMIO(0x6BA10)
12149 #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB 0x78280
12150 #define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB 0x78380
12151 #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC 0x78480
12152 #define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC 0x78580
12153 #define ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12154 _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \
12155 _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC)
12156 #define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12157 _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB, \
12158 _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC)
12159 #define DSC_INITIAL_DEC_DELAY(dec_delay) ((dec_delay) << 16)
12160 #define DSC_INITIAL_XMIT_DELAY(xmit_delay) ((xmit_delay) << 0)
12161
12162 #define DSCA_PICTURE_PARAMETER_SET_5 _MMIO(0x6B214)
12163 #define DSCC_PICTURE_PARAMETER_SET_5 _MMIO(0x6BA14)
12164 #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB 0x78284
12165 #define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB 0x78384
12166 #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC 0x78484
12167 #define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC 0x78584
12168 #define ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12169 _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB, \
12170 _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC)
12171 #define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12172 _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB, \
12173 _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC)
12174 #define DSC_SCALE_DEC_INT(scale_dec) ((scale_dec) << 16)
12175 #define DSC_SCALE_INC_INT(scale_inc) ((scale_inc) << 0)
12176
12177 #define DSCA_PICTURE_PARAMETER_SET_6 _MMIO(0x6B218)
12178 #define DSCC_PICTURE_PARAMETER_SET_6 _MMIO(0x6BA18)
12179 #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB 0x78288
12180 #define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB 0x78388
12181 #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC 0x78488
12182 #define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC 0x78588
12183 #define ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12184 _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB, \
12185 _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC)
12186 #define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12187 _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB, \
12188 _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC)
12189 #define DSC_FLATNESS_MAX_QP(max_qp) ((max_qp) << 24)
12190 #define DSC_FLATNESS_MIN_QP(min_qp) ((min_qp) << 16)
12191 #define DSC_FIRST_LINE_BPG_OFFSET(offset) ((offset) << 8)
12192 #define DSC_INITIAL_SCALE_VALUE(value) ((value) << 0)
12193
12194 #define DSCA_PICTURE_PARAMETER_SET_7 _MMIO(0x6B21C)
12195 #define DSCC_PICTURE_PARAMETER_SET_7 _MMIO(0x6BA1C)
12196 #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB 0x7828C
12197 #define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB 0x7838C
12198 #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC 0x7848C
12199 #define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC 0x7858C
12200 #define ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12201 _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB, \
12202 _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC)
12203 #define ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12204 _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB, \
12205 _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC)
12206 #define DSC_NFL_BPG_OFFSET(bpg_offset) ((bpg_offset) << 16)
12207 #define DSC_SLICE_BPG_OFFSET(bpg_offset) ((bpg_offset) << 0)
12208
12209 #define DSCA_PICTURE_PARAMETER_SET_8 _MMIO(0x6B220)
12210 #define DSCC_PICTURE_PARAMETER_SET_8 _MMIO(0x6BA20)
12211 #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB 0x78290
12212 #define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB 0x78390
12213 #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC 0x78490
12214 #define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC 0x78590
12215 #define ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12216 _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB, \
12217 _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC)
12218 #define ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12219 _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB, \
12220 _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC)
12221 #define DSC_INITIAL_OFFSET(initial_offset) ((initial_offset) << 16)
12222 #define DSC_FINAL_OFFSET(final_offset) ((final_offset) << 0)
12223
12224 #define DSCA_PICTURE_PARAMETER_SET_9 _MMIO(0x6B224)
12225 #define DSCC_PICTURE_PARAMETER_SET_9 _MMIO(0x6BA24)
12226 #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB 0x78294
12227 #define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB 0x78394
12228 #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC 0x78494
12229 #define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC 0x78594
12230 #define ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12231 _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB, \
12232 _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC)
12233 #define ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12234 _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB, \
12235 _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC)
12236 #define DSC_RC_EDGE_FACTOR(rc_edge_fact) ((rc_edge_fact) << 16)
12237 #define DSC_RC_MODEL_SIZE(rc_model_size) ((rc_model_size) << 0)
12238
12239 #define DSCA_PICTURE_PARAMETER_SET_10 _MMIO(0x6B228)
12240 #define DSCC_PICTURE_PARAMETER_SET_10 _MMIO(0x6BA28)
12241 #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB 0x78298
12242 #define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB 0x78398
12243 #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC 0x78498
12244 #define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC 0x78598
12245 #define ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12246 _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB, \
12247 _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC)
12248 #define ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12249 _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB, \
12250 _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC)
12251 #define DSC_RC_TARGET_OFF_LOW(rc_tgt_off_low) ((rc_tgt_off_low) << 20)
12252 #define DSC_RC_TARGET_OFF_HIGH(rc_tgt_off_high) ((rc_tgt_off_high) << 16)
12253 #define DSC_RC_QUANT_INC_LIMIT1(lim) ((lim) << 8)
12254 #define DSC_RC_QUANT_INC_LIMIT0(lim) ((lim) << 0)
12255
12256 #define DSCA_PICTURE_PARAMETER_SET_11 _MMIO(0x6B22C)
12257 #define DSCC_PICTURE_PARAMETER_SET_11 _MMIO(0x6BA2C)
12258 #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB 0x7829C
12259 #define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB 0x7839C
12260 #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC 0x7849C
12261 #define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC 0x7859C
12262 #define ICL_DSC0_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12263 _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB, \
12264 _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC)
12265 #define ICL_DSC1_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12266 _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB, \
12267 _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC)
12268
12269 #define DSCA_PICTURE_PARAMETER_SET_12 _MMIO(0x6B260)
12270 #define DSCC_PICTURE_PARAMETER_SET_12 _MMIO(0x6BA60)
12271 #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB 0x782A0
12272 #define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB 0x783A0
12273 #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC 0x784A0
12274 #define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC 0x785A0
12275 #define ICL_DSC0_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12276 _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB, \
12277 _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC)
12278 #define ICL_DSC1_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12279 _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB, \
12280 _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC)
12281
12282 #define DSCA_PICTURE_PARAMETER_SET_13 _MMIO(0x6B264)
12283 #define DSCC_PICTURE_PARAMETER_SET_13 _MMIO(0x6BA64)
12284 #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB 0x782A4
12285 #define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB 0x783A4
12286 #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC 0x784A4
12287 #define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC 0x785A4
12288 #define ICL_DSC0_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12289 _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB, \
12290 _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC)
12291 #define ICL_DSC1_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12292 _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB, \
12293 _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC)
12294
12295 #define DSCA_PICTURE_PARAMETER_SET_14 _MMIO(0x6B268)
12296 #define DSCC_PICTURE_PARAMETER_SET_14 _MMIO(0x6BA68)
12297 #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB 0x782A8
12298 #define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB 0x783A8
12299 #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC 0x784A8
12300 #define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC 0x785A8
12301 #define ICL_DSC0_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12302 _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB, \
12303 _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC)
12304 #define ICL_DSC1_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12305 _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB, \
12306 _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC)
12307
12308 #define DSCA_PICTURE_PARAMETER_SET_15 _MMIO(0x6B26C)
12309 #define DSCC_PICTURE_PARAMETER_SET_15 _MMIO(0x6BA6C)
12310 #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB 0x782AC
12311 #define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB 0x783AC
12312 #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC 0x784AC
12313 #define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC 0x785AC
12314 #define ICL_DSC0_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12315 _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB, \
12316 _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC)
12317 #define ICL_DSC1_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12318 _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB, \
12319 _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC)
12320
12321 #define DSCA_PICTURE_PARAMETER_SET_16 _MMIO(0x6B270)
12322 #define DSCC_PICTURE_PARAMETER_SET_16 _MMIO(0x6BA70)
12323 #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB 0x782B0
12324 #define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB 0x783B0
12325 #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC 0x784B0
12326 #define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC 0x785B0
12327 #define ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12328 _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB, \
12329 _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC)
12330 #define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12331 _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \
12332 _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC)
12333 #define DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame) ((slice_row_per_frame) << 20)
12334 #define DSC_SLICE_PER_LINE(slice_per_line) ((slice_per_line) << 16)
12335 #define DSC_SLICE_CHUNK_SIZE(slice_chunk_size) ((slice_chunk_size) << 0)
12336
12337 /* Icelake Rate Control Buffer Threshold Registers */
12338 #define DSCA_RC_BUF_THRESH_0 _MMIO(0x6B230)
12339 #define DSCA_RC_BUF_THRESH_0_UDW _MMIO(0x6B230 + 4)
12340 #define DSCC_RC_BUF_THRESH_0 _MMIO(0x6BA30)
12341 #define DSCC_RC_BUF_THRESH_0_UDW _MMIO(0x6BA30 + 4)
12342 #define _ICL_DSC0_RC_BUF_THRESH_0_PB (0x78254)
12343 #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB (0x78254 + 4)
12344 #define _ICL_DSC1_RC_BUF_THRESH_0_PB (0x78354)
12345 #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB (0x78354 + 4)
12346 #define _ICL_DSC0_RC_BUF_THRESH_0_PC (0x78454)
12347 #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC (0x78454 + 4)
12348 #define _ICL_DSC1_RC_BUF_THRESH_0_PC (0x78554)
12349 #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC (0x78554 + 4)
12350 #define ICL_DSC0_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12351 _ICL_DSC0_RC_BUF_THRESH_0_PB, \
12352 _ICL_DSC0_RC_BUF_THRESH_0_PC)
12353 #define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12354 _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB, \
12355 _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC)
12356 #define ICL_DSC1_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12357 _ICL_DSC1_RC_BUF_THRESH_0_PB, \
12358 _ICL_DSC1_RC_BUF_THRESH_0_PC)
12359 #define ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12360 _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB, \
12361 _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC)
12362
12363 #define DSCA_RC_BUF_THRESH_1 _MMIO(0x6B238)
12364 #define DSCA_RC_BUF_THRESH_1_UDW _MMIO(0x6B238 + 4)
12365 #define DSCC_RC_BUF_THRESH_1 _MMIO(0x6BA38)
12366 #define DSCC_RC_BUF_THRESH_1_UDW _MMIO(0x6BA38 + 4)
12367 #define _ICL_DSC0_RC_BUF_THRESH_1_PB (0x7825C)
12368 #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB (0x7825C + 4)
12369 #define _ICL_DSC1_RC_BUF_THRESH_1_PB (0x7835C)
12370 #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB (0x7835C + 4)
12371 #define _ICL_DSC0_RC_BUF_THRESH_1_PC (0x7845C)
12372 #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC (0x7845C + 4)
12373 #define _ICL_DSC1_RC_BUF_THRESH_1_PC (0x7855C)
12374 #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC (0x7855C + 4)
12375 #define ICL_DSC0_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12376 _ICL_DSC0_RC_BUF_THRESH_1_PB, \
12377 _ICL_DSC0_RC_BUF_THRESH_1_PC)
12378 #define ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12379 _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB, \
12380 _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC)
12381 #define ICL_DSC1_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12382 _ICL_DSC1_RC_BUF_THRESH_1_PB, \
12383 _ICL_DSC1_RC_BUF_THRESH_1_PC)
12384 #define ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12385 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
12386 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
12387
12388 #define PORT_TX_DFLEXDPSP(fia) _MMIO_FIA((fia), 0x008A0)
12389 #define MODULAR_FIA_MASK (1 << 4)
12390 #define TC_LIVE_STATE_TBT(idx) (1 << ((idx) * 8 + 6))
12391 #define TC_LIVE_STATE_TC(idx) (1 << ((idx) * 8 + 5))
12392 #define DP_LANE_ASSIGNMENT_SHIFT(idx) ((idx) * 8)
12393 #define DP_LANE_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 8))
12394 #define DP_LANE_ASSIGNMENT(idx, x) ((x) << ((idx) * 8))
12395
12396 #define PORT_TX_DFLEXDPPMS(fia) _MMIO_FIA((fia), 0x00890)
12397 #define DP_PHY_MODE_STATUS_COMPLETED(idx) (1 << (idx))
12398
12399 #define PORT_TX_DFLEXDPCSSS(fia) _MMIO_FIA((fia), 0x00894)
12400 #define DP_PHY_MODE_STATUS_NOT_SAFE(idx) (1 << (idx))
12401
12402 #define PORT_TX_DFLEXPA1(fia) _MMIO_FIA((fia), 0x00880)
12403 #define DP_PIN_ASSIGNMENT_SHIFT(idx) ((idx) * 4)
12404 #define DP_PIN_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 4))
12405 #define DP_PIN_ASSIGNMENT(idx, x) ((x) << ((idx) * 4))
12406
12407 /* This register controls the Display State Buffer (DSB) engines. */
12408 #define _DSBSL_INSTANCE_BASE 0x70B00
12409 #define DSBSL_INSTANCE(pipe, id) (_DSBSL_INSTANCE_BASE + \
12410 (pipe) * 0x1000 + (id) * 0x100)
12411 #define DSB_HEAD(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x0)
12412 #define DSB_TAIL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x4)
12413 #define DSB_CTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)
12414 #define DSB_ENABLE (1 << 31)
12415 #define DSB_STATUS (1 << 0)
12416
12417 #define TGL_ROOT_DEVICE_ID 0x9A00
12418 #define TGL_ROOT_DEVICE_MASK 0xFF00
12419 #define TGL_ROOT_DEVICE_SKU_MASK 0xF
12420 #define TGL_ROOT_DEVICE_SKU_ULX 0x2
12421 #define TGL_ROOT_DEVICE_SKU_ULT 0x4
12422
12423 #endif /* _I915_REG_H_ */
Linux with added FPC-III support