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Merge tag 'block-5.11-2021-01-10' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / gpu / drm / i915 / intel_uncore.c
blob1c14a07eba7d6f651b7a66208f1f484b20a8f1e6
1 /*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <linux/pm_runtime.h>
25 #include <asm/iosf_mbi.h>
26
27 #include "i915_drv.h"
28 #include "i915_trace.h"
29 #include "i915_vgpu.h"
30 #include "intel_pm.h"
31
32 #define FORCEWAKE_ACK_TIMEOUT_MS 50
33 #define GT_FIFO_TIMEOUT_MS 10
34
35 #define __raw_posting_read(...) ((void)__raw_uncore_read32(__VA_ARGS__))
36
37 void
38 intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug *mmio_debug)
39 {
40 spin_lock_init(&mmio_debug->lock);
41 mmio_debug->unclaimed_mmio_check = 1;
42 }
43
44 static void mmio_debug_suspend(struct intel_uncore_mmio_debug *mmio_debug)
45 {
46 lockdep_assert_held(&mmio_debug->lock);
47
48 /* Save and disable mmio debugging for the user bypass */
49 if (!mmio_debug->suspend_count++) {
50 mmio_debug->saved_mmio_check = mmio_debug->unclaimed_mmio_check;
51 mmio_debug->unclaimed_mmio_check = 0;
52 }
53 }
54
55 static void mmio_debug_resume(struct intel_uncore_mmio_debug *mmio_debug)
56 {
57 lockdep_assert_held(&mmio_debug->lock);
58
59 if (!--mmio_debug->suspend_count)
60 mmio_debug->unclaimed_mmio_check = mmio_debug->saved_mmio_check;
61 }
62
63 static const char * const forcewake_domain_names[] = {
64 "render",
65 "blitter",
66 "media",
67 "vdbox0",
68 "vdbox1",
69 "vdbox2",
70 "vdbox3",
71 "vebox0",
72 "vebox1",
73 };
74
75 const char *
76 intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id)
77 {
78 BUILD_BUG_ON(ARRAY_SIZE(forcewake_domain_names) != FW_DOMAIN_ID_COUNT);
79
80 if (id >= 0 && id < FW_DOMAIN_ID_COUNT)
81 return forcewake_domain_names[id];
82
83 WARN_ON(id);
84
85 return "unknown";
86 }
87
88 #define fw_ack(d) readl((d)->reg_ack)
89 #define fw_set(d, val) writel(_MASKED_BIT_ENABLE((val)), (d)->reg_set)
90 #define fw_clear(d, val) writel(_MASKED_BIT_DISABLE((val)), (d)->reg_set)
91
92 static inline void
93 fw_domain_reset(const struct intel_uncore_forcewake_domain *d)
94 {
95 /*
96 * We don't really know if the powerwell for the forcewake domain we are
97 * trying to reset here does exist at this point (engines could be fused
98 * off in ICL+), so no waiting for acks
99 */
100 /* WaRsClearFWBitsAtReset:bdw,skl */
101 fw_clear(d, 0xffff);
102 }
103
104 static inline void
105 fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d)
106 {
107 GEM_BUG_ON(d->uncore->fw_domains_timer & d->mask);
108 d->uncore->fw_domains_timer |= d->mask;
109 d->wake_count++;
110 hrtimer_start_range_ns(&d->timer,
111 NSEC_PER_MSEC,
112 NSEC_PER_MSEC,
113 HRTIMER_MODE_REL);
114 }
115
116 static inline int
117 __wait_for_ack(const struct intel_uncore_forcewake_domain *d,
118 const u32 ack,
119 const u32 value)
120 {
121 return wait_for_atomic((fw_ack(d) & ack) == value,
122 FORCEWAKE_ACK_TIMEOUT_MS);
123 }
124
125 static inline int
126 wait_ack_clear(const struct intel_uncore_forcewake_domain *d,
127 const u32 ack)
128 {
129 return __wait_for_ack(d, ack, 0);
130 }
131
132 static inline int
133 wait_ack_set(const struct intel_uncore_forcewake_domain *d,
134 const u32 ack)
135 {
136 return __wait_for_ack(d, ack, ack);
137 }
138
139 static inline void
140 fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d)
141 {
142 if (wait_ack_clear(d, FORCEWAKE_KERNEL)) {
143 DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n",
144 intel_uncore_forcewake_domain_to_str(d->id));
145 add_taint_for_CI(d->uncore->i915, TAINT_WARN); /* CI now unreliable */
146 }
147 }
148
149 enum ack_type {
150 ACK_CLEAR = 0,
151 ACK_SET
152 };
153
154 static int
155 fw_domain_wait_ack_with_fallback(const struct intel_uncore_forcewake_domain *d,
156 const enum ack_type type)
157 {
158 const u32 ack_bit = FORCEWAKE_KERNEL;
159 const u32 value = type == ACK_SET ? ack_bit : 0;
160 unsigned int pass;
161 bool ack_detected;
162
163 /*
164 * There is a possibility of driver's wake request colliding
165 * with hardware's own wake requests and that can cause
166 * hardware to not deliver the driver's ack message.
167 *
168 * Use a fallback bit toggle to kick the gpu state machine
169 * in the hope that the original ack will be delivered along with
170 * the fallback ack.
171 *
172 * This workaround is described in HSDES #1604254524 and it's known as:
173 * WaRsForcewakeAddDelayForAck:skl,bxt,kbl,glk,cfl,cnl,icl
174 * although the name is a bit misleading.
175 */
176
177 pass = 1;
178 do {
179 wait_ack_clear(d, FORCEWAKE_KERNEL_FALLBACK);
180
181 fw_set(d, FORCEWAKE_KERNEL_FALLBACK);
182 /* Give gt some time to relax before the polling frenzy */
183 udelay(10 * pass);
184 wait_ack_set(d, FORCEWAKE_KERNEL_FALLBACK);
185
186 ack_detected = (fw_ack(d) & ack_bit) == value;
187
188 fw_clear(d, FORCEWAKE_KERNEL_FALLBACK);
189 } while (!ack_detected && pass++ < 10);
190
191 DRM_DEBUG_DRIVER("%s had to use fallback to %s ack, 0x%x (passes %u)\n",
192 intel_uncore_forcewake_domain_to_str(d->id),
193 type == ACK_SET ? "set" : "clear",
194 fw_ack(d),
195 pass);
196
197 return ack_detected ? 0 : -ETIMEDOUT;
198 }
199
200 static inline void
201 fw_domain_wait_ack_clear_fallback(const struct intel_uncore_forcewake_domain *d)
202 {
203 if (likely(!wait_ack_clear(d, FORCEWAKE_KERNEL)))
204 return;
205
206 if (fw_domain_wait_ack_with_fallback(d, ACK_CLEAR))
207 fw_domain_wait_ack_clear(d);
208 }
209
210 static inline void
211 fw_domain_get(const struct intel_uncore_forcewake_domain *d)
212 {
213 fw_set(d, FORCEWAKE_KERNEL);
214 }
215
216 static inline void
217 fw_domain_wait_ack_set(const struct intel_uncore_forcewake_domain *d)
218 {
219 if (wait_ack_set(d, FORCEWAKE_KERNEL)) {
220 DRM_ERROR("%s: timed out waiting for forcewake ack request.\n",
221 intel_uncore_forcewake_domain_to_str(d->id));
222 add_taint_for_CI(d->uncore->i915, TAINT_WARN); /* CI now unreliable */
223 }
224 }
225
226 static inline void
227 fw_domain_wait_ack_set_fallback(const struct intel_uncore_forcewake_domain *d)
228 {
229 if (likely(!wait_ack_set(d, FORCEWAKE_KERNEL)))
230 return;
231
232 if (fw_domain_wait_ack_with_fallback(d, ACK_SET))
233 fw_domain_wait_ack_set(d);
234 }
235
236 static inline void
237 fw_domain_put(const struct intel_uncore_forcewake_domain *d)
238 {
239 fw_clear(d, FORCEWAKE_KERNEL);
240 }
241
242 static void
243 fw_domains_get(struct intel_uncore *uncore, enum forcewake_domains fw_domains)
244 {
245 struct intel_uncore_forcewake_domain *d;
246 unsigned int tmp;
247
248 GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
249
250 for_each_fw_domain_masked(d, fw_domains, uncore, tmp) {
251 fw_domain_wait_ack_clear(d);
252 fw_domain_get(d);
253 }
254
255 for_each_fw_domain_masked(d, fw_domains, uncore, tmp)
256 fw_domain_wait_ack_set(d);
257
258 uncore->fw_domains_active |= fw_domains;
259 }
260
261 static void
262 fw_domains_get_with_fallback(struct intel_uncore *uncore,
263 enum forcewake_domains fw_domains)
264 {
265 struct intel_uncore_forcewake_domain *d;
266 unsigned int tmp;
267
268 GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
269
270 for_each_fw_domain_masked(d, fw_domains, uncore, tmp) {
271 fw_domain_wait_ack_clear_fallback(d);
272 fw_domain_get(d);
273 }
274
275 for_each_fw_domain_masked(d, fw_domains, uncore, tmp)
276 fw_domain_wait_ack_set_fallback(d);
277
278 uncore->fw_domains_active |= fw_domains;
279 }
280
281 static void
282 fw_domains_put(struct intel_uncore *uncore, enum forcewake_domains fw_domains)
283 {
284 struct intel_uncore_forcewake_domain *d;
285 unsigned int tmp;
286
287 GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
288
289 for_each_fw_domain_masked(d, fw_domains, uncore, tmp)
290 fw_domain_put(d);
291
292 uncore->fw_domains_active &= ~fw_domains;
293 }
294
295 static void
296 fw_domains_reset(struct intel_uncore *uncore,
297 enum forcewake_domains fw_domains)
298 {
299 struct intel_uncore_forcewake_domain *d;
300 unsigned int tmp;
301
302 if (!fw_domains)
303 return;
304
305 GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
306
307 for_each_fw_domain_masked(d, fw_domains, uncore, tmp)
308 fw_domain_reset(d);
309 }
310
311 static inline u32 gt_thread_status(struct intel_uncore *uncore)
312 {
313 u32 val;
314
315 val = __raw_uncore_read32(uncore, GEN6_GT_THREAD_STATUS_REG);
316 val &= GEN6_GT_THREAD_STATUS_CORE_MASK;
317
318 return val;
319 }
320
321 static void __gen6_gt_wait_for_thread_c0(struct intel_uncore *uncore)
322 {
323 /*
324 * w/a for a sporadic read returning 0 by waiting for the GT
325 * thread to wake up.
326 */
327 drm_WARN_ONCE(&uncore->i915->drm,
328 wait_for_atomic_us(gt_thread_status(uncore) == 0, 5000),
329 "GT thread status wait timed out\n");
330 }
331
332 static void fw_domains_get_with_thread_status(struct intel_uncore *uncore,
333 enum forcewake_domains fw_domains)
334 {
335 fw_domains_get(uncore, fw_domains);
336
337 /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */
338 __gen6_gt_wait_for_thread_c0(uncore);
339 }
340
341 static inline u32 fifo_free_entries(struct intel_uncore *uncore)
342 {
343 u32 count = __raw_uncore_read32(uncore, GTFIFOCTL);
344
345 return count & GT_FIFO_FREE_ENTRIES_MASK;
346 }
347
348 static void __gen6_gt_wait_for_fifo(struct intel_uncore *uncore)
349 {
350 u32 n;
351
352 /* On VLV, FIFO will be shared by both SW and HW.
353 * So, we need to read the FREE_ENTRIES everytime */
354 if (IS_VALLEYVIEW(uncore->i915))
355 n = fifo_free_entries(uncore);
356 else
357 n = uncore->fifo_count;
358
359 if (n <= GT_FIFO_NUM_RESERVED_ENTRIES) {
360 if (wait_for_atomic((n = fifo_free_entries(uncore)) >
361 GT_FIFO_NUM_RESERVED_ENTRIES,
362 GT_FIFO_TIMEOUT_MS)) {
363 drm_dbg(&uncore->i915->drm,
364 "GT_FIFO timeout, entries: %u\n", n);
365 return;
366 }
367 }
368
369 uncore->fifo_count = n - 1;
370 }
371
372 static enum hrtimer_restart
373 intel_uncore_fw_release_timer(struct hrtimer *timer)
374 {
375 struct intel_uncore_forcewake_domain *domain =
376 container_of(timer, struct intel_uncore_forcewake_domain, timer);
377 struct intel_uncore *uncore = domain->uncore;
378 unsigned long irqflags;
379
380 assert_rpm_device_not_suspended(uncore->rpm);
381
382 if (xchg(&domain->active, false))
383 return HRTIMER_RESTART;
384
385 spin_lock_irqsave(&uncore->lock, irqflags);
386
387 uncore->fw_domains_timer &= ~domain->mask;
388
389 GEM_BUG_ON(!domain->wake_count);
390 if (--domain->wake_count == 0)
391 uncore->funcs.force_wake_put(uncore, domain->mask);
392
393 spin_unlock_irqrestore(&uncore->lock, irqflags);
394
395 return HRTIMER_NORESTART;
396 }
397
398 /* Note callers must have acquired the PUNIT->PMIC bus, before calling this. */
399 static unsigned int
400 intel_uncore_forcewake_reset(struct intel_uncore *uncore)
401 {
402 unsigned long irqflags;
403 struct intel_uncore_forcewake_domain *domain;
404 int retry_count = 100;
405 enum forcewake_domains fw, active_domains;
406
407 iosf_mbi_assert_punit_acquired();
408
409 /* Hold uncore.lock across reset to prevent any register access
410 * with forcewake not set correctly. Wait until all pending
411 * timers are run before holding.
412 */
413 while (1) {
414 unsigned int tmp;
415
416 active_domains = 0;
417
418 for_each_fw_domain(domain, uncore, tmp) {
419 smp_store_mb(domain->active, false);
420 if (hrtimer_cancel(&domain->timer) == 0)
421 continue;
422
423 intel_uncore_fw_release_timer(&domain->timer);
424 }
425
426 spin_lock_irqsave(&uncore->lock, irqflags);
427
428 for_each_fw_domain(domain, uncore, tmp) {
429 if (hrtimer_active(&domain->timer))
430 active_domains |= domain->mask;
431 }
432
433 if (active_domains == 0)
434 break;
435
436 if (--retry_count == 0) {
437 drm_err(&uncore->i915->drm, "Timed out waiting for forcewake timers to finish\n");
438 break;
439 }
440
441 spin_unlock_irqrestore(&uncore->lock, irqflags);
442 cond_resched();
443 }
444
445 drm_WARN_ON(&uncore->i915->drm, active_domains);
446
447 fw = uncore->fw_domains_active;
448 if (fw)
449 uncore->funcs.force_wake_put(uncore, fw);
450
451 fw_domains_reset(uncore, uncore->fw_domains);
452 assert_forcewakes_inactive(uncore);
453
454 spin_unlock_irqrestore(&uncore->lock, irqflags);
455
456 return fw; /* track the lost user forcewake domains */
457 }
458
459 static bool
460 fpga_check_for_unclaimed_mmio(struct intel_uncore *uncore)
461 {
462 u32 dbg;
463
464 dbg = __raw_uncore_read32(uncore, FPGA_DBG);
465 if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM)))
466 return false;
467
468 __raw_uncore_write32(uncore, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
469
470 return true;
471 }
472
473 static bool
474 vlv_check_for_unclaimed_mmio(struct intel_uncore *uncore)
475 {
476 u32 cer;
477
478 cer = __raw_uncore_read32(uncore, CLAIM_ER);
479 if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK))))
480 return false;
481
482 __raw_uncore_write32(uncore, CLAIM_ER, CLAIM_ER_CLR);
483
484 return true;
485 }
486
487 static bool
488 gen6_check_for_fifo_debug(struct intel_uncore *uncore)
489 {
490 u32 fifodbg;
491
492 fifodbg = __raw_uncore_read32(uncore, GTFIFODBG);
493
494 if (unlikely(fifodbg)) {
495 drm_dbg(&uncore->i915->drm, "GTFIFODBG = 0x08%x\n", fifodbg);
496 __raw_uncore_write32(uncore, GTFIFODBG, fifodbg);
497 }
498
499 return fifodbg;
500 }
501
502 static bool
503 check_for_unclaimed_mmio(struct intel_uncore *uncore)
504 {
505 bool ret = false;
506
507 lockdep_assert_held(&uncore->debug->lock);
508
509 if (uncore->debug->suspend_count)
510 return false;
511
512 if (intel_uncore_has_fpga_dbg_unclaimed(uncore))
513 ret |= fpga_check_for_unclaimed_mmio(uncore);
514
515 if (intel_uncore_has_dbg_unclaimed(uncore))
516 ret |= vlv_check_for_unclaimed_mmio(uncore);
517
518 if (intel_uncore_has_fifo(uncore))
519 ret |= gen6_check_for_fifo_debug(uncore);
520
521 return ret;
522 }
523
524 static void forcewake_early_sanitize(struct intel_uncore *uncore,
525 unsigned int restore_forcewake)
526 {
527 GEM_BUG_ON(!intel_uncore_has_forcewake(uncore));
528
529 /* WaDisableShadowRegForCpd:chv */
530 if (IS_CHERRYVIEW(uncore->i915)) {
531 __raw_uncore_write32(uncore, GTFIFOCTL,
532 __raw_uncore_read32(uncore, GTFIFOCTL) |
533 GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
534 GT_FIFO_CTL_RC6_POLICY_STALL);
535 }
536
537 iosf_mbi_punit_acquire();
538 intel_uncore_forcewake_reset(uncore);
539 if (restore_forcewake) {
540 spin_lock_irq(&uncore->lock);
541 uncore->funcs.force_wake_get(uncore, restore_forcewake);
542
543 if (intel_uncore_has_fifo(uncore))
544 uncore->fifo_count = fifo_free_entries(uncore);
545 spin_unlock_irq(&uncore->lock);
546 }
547 iosf_mbi_punit_release();
548 }
549
550 void intel_uncore_suspend(struct intel_uncore *uncore)
551 {
552 if (!intel_uncore_has_forcewake(uncore))
553 return;
554
555 iosf_mbi_punit_acquire();
556 iosf_mbi_unregister_pmic_bus_access_notifier_unlocked(
557 &uncore->pmic_bus_access_nb);
558 uncore->fw_domains_saved = intel_uncore_forcewake_reset(uncore);
559 iosf_mbi_punit_release();
560 }
561
562 void intel_uncore_resume_early(struct intel_uncore *uncore)
563 {
564 unsigned int restore_forcewake;
565
566 if (intel_uncore_unclaimed_mmio(uncore))
567 drm_dbg(&uncore->i915->drm, "unclaimed mmio detected on resume, clearing\n");
568
569 if (!intel_uncore_has_forcewake(uncore))
570 return;
571
572 restore_forcewake = fetch_and_zero(&uncore->fw_domains_saved);
573 forcewake_early_sanitize(uncore, restore_forcewake);
574
575 iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb);
576 }
577
578 void intel_uncore_runtime_resume(struct intel_uncore *uncore)
579 {
580 if (!intel_uncore_has_forcewake(uncore))
581 return;
582
583 iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb);
584 }
585
586 static void __intel_uncore_forcewake_get(struct intel_uncore *uncore,
587 enum forcewake_domains fw_domains)
588 {
589 struct intel_uncore_forcewake_domain *domain;
590 unsigned int tmp;
591
592 fw_domains &= uncore->fw_domains;
593
594 for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
595 if (domain->wake_count++) {
596 fw_domains &= ~domain->mask;
597 domain->active = true;
598 }
599 }
600
601 if (fw_domains)
602 uncore->funcs.force_wake_get(uncore, fw_domains);
603 }
604
605 /**
606 * intel_uncore_forcewake_get - grab forcewake domain references
607 * @uncore: the intel_uncore structure
608 * @fw_domains: forcewake domains to get reference on
609 *
610 * This function can be used get GT's forcewake domain references.
611 * Normal register access will handle the forcewake domains automatically.
612 * However if some sequence requires the GT to not power down a particular
613 * forcewake domains this function should be called at the beginning of the
614 * sequence. And subsequently the reference should be dropped by symmetric
615 * call to intel_unforce_forcewake_put(). Usually caller wants all the domains
616 * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL.
617 */
618 void intel_uncore_forcewake_get(struct intel_uncore *uncore,
619 enum forcewake_domains fw_domains)
620 {
621 unsigned long irqflags;
622
623 if (!uncore->funcs.force_wake_get)
624 return;
625
626 assert_rpm_wakelock_held(uncore->rpm);
627
628 spin_lock_irqsave(&uncore->lock, irqflags);
629 __intel_uncore_forcewake_get(uncore, fw_domains);
630 spin_unlock_irqrestore(&uncore->lock, irqflags);
631 }
632
633 /**
634 * intel_uncore_forcewake_user_get - claim forcewake on behalf of userspace
635 * @uncore: the intel_uncore structure
636 *
637 * This function is a wrapper around intel_uncore_forcewake_get() to acquire
638 * the GT powerwell and in the process disable our debugging for the
639 * duration of userspace's bypass.
640 */
641 void intel_uncore_forcewake_user_get(struct intel_uncore *uncore)
642 {
643 spin_lock_irq(&uncore->lock);
644 if (!uncore->user_forcewake_count++) {
645 intel_uncore_forcewake_get__locked(uncore, FORCEWAKE_ALL);
646 spin_lock(&uncore->debug->lock);
647 mmio_debug_suspend(uncore->debug);
648 spin_unlock(&uncore->debug->lock);
649 }
650 spin_unlock_irq(&uncore->lock);
651 }
652
653 /**
654 * intel_uncore_forcewake_user_put - release forcewake on behalf of userspace
655 * @uncore: the intel_uncore structure
656 *
657 * This function complements intel_uncore_forcewake_user_get() and releases
658 * the GT powerwell taken on behalf of the userspace bypass.
659 */
660 void intel_uncore_forcewake_user_put(struct intel_uncore *uncore)
661 {
662 spin_lock_irq(&uncore->lock);
663 if (!--uncore->user_forcewake_count) {
664 spin_lock(&uncore->debug->lock);
665 mmio_debug_resume(uncore->debug);
666
667 if (check_for_unclaimed_mmio(uncore))
668 drm_info(&uncore->i915->drm,
669 "Invalid mmio detected during user access\n");
670 spin_unlock(&uncore->debug->lock);
671
672 intel_uncore_forcewake_put__locked(uncore, FORCEWAKE_ALL);
673 }
674 spin_unlock_irq(&uncore->lock);
675 }
676
677 /**
678 * intel_uncore_forcewake_get__locked - grab forcewake domain references
679 * @uncore: the intel_uncore structure
680 * @fw_domains: forcewake domains to get reference on
681 *
682 * See intel_uncore_forcewake_get(). This variant places the onus
683 * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
684 */
685 void intel_uncore_forcewake_get__locked(struct intel_uncore *uncore,
686 enum forcewake_domains fw_domains)
687 {
688 lockdep_assert_held(&uncore->lock);
689
690 if (!uncore->funcs.force_wake_get)
691 return;
692
693 __intel_uncore_forcewake_get(uncore, fw_domains);
694 }
695
696 static void __intel_uncore_forcewake_put(struct intel_uncore *uncore,
697 enum forcewake_domains fw_domains)
698 {
699 struct intel_uncore_forcewake_domain *domain;
700 unsigned int tmp;
701
702 fw_domains &= uncore->fw_domains;
703
704 for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
705 GEM_BUG_ON(!domain->wake_count);
706
707 if (--domain->wake_count) {
708 domain->active = true;
709 continue;
710 }
711
712 uncore->funcs.force_wake_put(uncore, domain->mask);
713 }
714 }
715
716 /**
717 * intel_uncore_forcewake_put - release a forcewake domain reference
718 * @uncore: the intel_uncore structure
719 * @fw_domains: forcewake domains to put references
720 *
721 * This function drops the device-level forcewakes for specified
722 * domains obtained by intel_uncore_forcewake_get().
723 */
724 void intel_uncore_forcewake_put(struct intel_uncore *uncore,
725 enum forcewake_domains fw_domains)
726 {
727 unsigned long irqflags;
728
729 if (!uncore->funcs.force_wake_put)
730 return;
731
732 spin_lock_irqsave(&uncore->lock, irqflags);
733 __intel_uncore_forcewake_put(uncore, fw_domains);
734 spin_unlock_irqrestore(&uncore->lock, irqflags);
735 }
736
737 /**
738 * intel_uncore_forcewake_flush - flush the delayed release
739 * @uncore: the intel_uncore structure
740 * @fw_domains: forcewake domains to flush
741 */
742 void intel_uncore_forcewake_flush(struct intel_uncore *uncore,
743 enum forcewake_domains fw_domains)
744 {
745 struct intel_uncore_forcewake_domain *domain;
746 unsigned int tmp;
747
748 if (!uncore->funcs.force_wake_put)
749 return;
750
751 fw_domains &= uncore->fw_domains;
752 for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
753 WRITE_ONCE(domain->active, false);
754 if (hrtimer_cancel(&domain->timer))
755 intel_uncore_fw_release_timer(&domain->timer);
756 }
757 }
758
759 /**
760 * intel_uncore_forcewake_put__locked - grab forcewake domain references
761 * @uncore: the intel_uncore structure
762 * @fw_domains: forcewake domains to get reference on
763 *
764 * See intel_uncore_forcewake_put(). This variant places the onus
765 * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
766 */
767 void intel_uncore_forcewake_put__locked(struct intel_uncore *uncore,
768 enum forcewake_domains fw_domains)
769 {
770 lockdep_assert_held(&uncore->lock);
771
772 if (!uncore->funcs.force_wake_put)
773 return;
774
775 __intel_uncore_forcewake_put(uncore, fw_domains);
776 }
777
778 void assert_forcewakes_inactive(struct intel_uncore *uncore)
779 {
780 if (!uncore->funcs.force_wake_get)
781 return;
782
783 drm_WARN(&uncore->i915->drm, uncore->fw_domains_active,
784 "Expected all fw_domains to be inactive, but %08x are still on\n",
785 uncore->fw_domains_active);
786 }
787
788 void assert_forcewakes_active(struct intel_uncore *uncore,
789 enum forcewake_domains fw_domains)
790 {
791 struct intel_uncore_forcewake_domain *domain;
792 unsigned int tmp;
793
794 if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
795 return;
796
797 if (!uncore->funcs.force_wake_get)
798 return;
799
800 spin_lock_irq(&uncore->lock);
801
802 assert_rpm_wakelock_held(uncore->rpm);
803
804 fw_domains &= uncore->fw_domains;
805 drm_WARN(&uncore->i915->drm, fw_domains & ~uncore->fw_domains_active,
806 "Expected %08x fw_domains to be active, but %08x are off\n",
807 fw_domains, fw_domains & ~uncore->fw_domains_active);
808
809 /*
810 * Check that the caller has an explicit wakeref and we don't mistake
811 * it for the auto wakeref.
812 */
813 for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
814 unsigned int actual = READ_ONCE(domain->wake_count);
815 unsigned int expect = 1;
816
817 if (uncore->fw_domains_timer & domain->mask)
818 expect++; /* pending automatic release */
819
820 if (drm_WARN(&uncore->i915->drm, actual < expect,
821 "Expected domain %d to be held awake by caller, count=%d\n",
822 domain->id, actual))
823 break;
824 }
825
826 spin_unlock_irq(&uncore->lock);
827 }
828
829 /* We give fast paths for the really cool registers */
830 #define NEEDS_FORCE_WAKE(reg) ((reg) < 0x40000)
831
832 #define __gen6_reg_read_fw_domains(uncore, offset) \
833 ({ \
834 enum forcewake_domains __fwd; \
835 if (NEEDS_FORCE_WAKE(offset)) \
836 __fwd = FORCEWAKE_RENDER; \
837 else \
838 __fwd = 0; \
839 __fwd; \
840 })
841
842 static int fw_range_cmp(u32 offset, const struct intel_forcewake_range *entry)
843 {
844 if (offset < entry->start)
845 return -1;
846 else if (offset > entry->end)
847 return 1;
848 else
849 return 0;
850 }
851
852 /* Copied and "macroized" from lib/bsearch.c */
853 #define BSEARCH(key, base, num, cmp) ({ \
854 unsigned int start__ = 0, end__ = (num); \
855 typeof(base) result__ = NULL; \
856 while (start__ < end__) { \
857 unsigned int mid__ = start__ + (end__ - start__) / 2; \
858 int ret__ = (cmp)((key), (base) + mid__); \
859 if (ret__ < 0) { \
860 end__ = mid__; \
861 } else if (ret__ > 0) { \
862 start__ = mid__ + 1; \
863 } else { \
864 result__ = (base) + mid__; \
865 break; \
866 } \
867 } \
868 result__; \
869 })
870
871 static enum forcewake_domains
872 find_fw_domain(struct intel_uncore *uncore, u32 offset)
873 {
874 const struct intel_forcewake_range *entry;
875
876 entry = BSEARCH(offset,
877 uncore->fw_domains_table,
878 uncore->fw_domains_table_entries,
879 fw_range_cmp);
880
881 if (!entry)
882 return 0;
883
884 /*
885 * The list of FW domains depends on the SKU in gen11+ so we
886 * can't determine it statically. We use FORCEWAKE_ALL and
887 * translate it here to the list of available domains.
888 */
889 if (entry->domains == FORCEWAKE_ALL)
890 return uncore->fw_domains;
891
892 drm_WARN(&uncore->i915->drm, entry->domains & ~uncore->fw_domains,
893 "Uninitialized forcewake domain(s) 0x%x accessed at 0x%x\n",
894 entry->domains & ~uncore->fw_domains, offset);
895
896 return entry->domains;
897 }
898
899 #define GEN_FW_RANGE(s, e, d) \
900 { .start = (s), .end = (e), .domains = (d) }
901
902 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
903 static const struct intel_forcewake_range __vlv_fw_ranges[] = {
904 GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
905 GEN_FW_RANGE(0x5000, 0x7fff, FORCEWAKE_RENDER),
906 GEN_FW_RANGE(0xb000, 0x11fff, FORCEWAKE_RENDER),
907 GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
908 GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_MEDIA),
909 GEN_FW_RANGE(0x2e000, 0x2ffff, FORCEWAKE_RENDER),
910 GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
911 };
912
913 #define __fwtable_reg_read_fw_domains(uncore, offset) \
914 ({ \
915 enum forcewake_domains __fwd = 0; \
916 if (NEEDS_FORCE_WAKE((offset))) \
917 __fwd = find_fw_domain(uncore, offset); \
918 __fwd; \
919 })
920
921 #define __gen11_fwtable_reg_read_fw_domains(uncore, offset) \
922 find_fw_domain(uncore, offset)
923
924 #define __gen12_fwtable_reg_read_fw_domains(uncore, offset) \
925 find_fw_domain(uncore, offset)
926
927 /* *Must* be sorted by offset! See intel_shadow_table_check(). */
928 static const i915_reg_t gen8_shadowed_regs[] = {
929 RING_TAIL(RENDER_RING_BASE), /* 0x2000 (base) */
930 GEN6_RPNSWREQ, /* 0xA008 */
931 GEN6_RC_VIDEO_FREQ, /* 0xA00C */
932 RING_TAIL(GEN6_BSD_RING_BASE), /* 0x12000 (base) */
933 RING_TAIL(VEBOX_RING_BASE), /* 0x1a000 (base) */
934 RING_TAIL(BLT_RING_BASE), /* 0x22000 (base) */
935 /* TODO: Other registers are not yet used */
936 };
937
938 static const i915_reg_t gen11_shadowed_regs[] = {
939 RING_TAIL(RENDER_RING_BASE), /* 0x2000 (base) */
940 GEN6_RPNSWREQ, /* 0xA008 */
941 GEN6_RC_VIDEO_FREQ, /* 0xA00C */
942 RING_TAIL(BLT_RING_BASE), /* 0x22000 (base) */
943 RING_TAIL(GEN11_BSD_RING_BASE), /* 0x1C0000 (base) */
944 RING_TAIL(GEN11_BSD2_RING_BASE), /* 0x1C4000 (base) */
945 RING_TAIL(GEN11_VEBOX_RING_BASE), /* 0x1C8000 (base) */
946 RING_TAIL(GEN11_BSD3_RING_BASE), /* 0x1D0000 (base) */
947 RING_TAIL(GEN11_BSD4_RING_BASE), /* 0x1D4000 (base) */
948 RING_TAIL(GEN11_VEBOX2_RING_BASE), /* 0x1D8000 (base) */
949 /* TODO: Other registers are not yet used */
950 };
951
952 static const i915_reg_t gen12_shadowed_regs[] = {
953 RING_TAIL(RENDER_RING_BASE), /* 0x2000 (base) */
954 GEN6_RPNSWREQ, /* 0xA008 */
955 GEN6_RC_VIDEO_FREQ, /* 0xA00C */
956 RING_TAIL(BLT_RING_BASE), /* 0x22000 (base) */
957 RING_TAIL(GEN11_BSD_RING_BASE), /* 0x1C0000 (base) */
958 RING_TAIL(GEN11_BSD2_RING_BASE), /* 0x1C4000 (base) */
959 RING_TAIL(GEN11_VEBOX_RING_BASE), /* 0x1C8000 (base) */
960 RING_TAIL(GEN11_BSD3_RING_BASE), /* 0x1D0000 (base) */
961 RING_TAIL(GEN11_BSD4_RING_BASE), /* 0x1D4000 (base) */
962 RING_TAIL(GEN11_VEBOX2_RING_BASE), /* 0x1D8000 (base) */
963 /* TODO: Other registers are not yet used */
964 };
965
966 static int mmio_reg_cmp(u32 key, const i915_reg_t *reg)
967 {
968 u32 offset = i915_mmio_reg_offset(*reg);
969
970 if (key < offset)
971 return -1;
972 else if (key > offset)
973 return 1;
974 else
975 return 0;
976 }
977
978 #define __is_genX_shadowed(x) \
979 static bool is_gen##x##_shadowed(u32 offset) \
980 { \
981 const i915_reg_t *regs = gen##x##_shadowed_regs; \
982 return BSEARCH(offset, regs, ARRAY_SIZE(gen##x##_shadowed_regs), \
983 mmio_reg_cmp); \
984 }
985
986 __is_genX_shadowed(8)
987 __is_genX_shadowed(11)
988 __is_genX_shadowed(12)
989
990 static enum forcewake_domains
991 gen6_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg)
992 {
993 return FORCEWAKE_RENDER;
994 }
995
996 #define __gen8_reg_write_fw_domains(uncore, offset) \
997 ({ \
998 enum forcewake_domains __fwd; \
999 if (NEEDS_FORCE_WAKE(offset) && !is_gen8_shadowed(offset)) \
1000 __fwd = FORCEWAKE_RENDER; \
1001 else \
1002 __fwd = 0; \
1003 __fwd; \
1004 })
1005
1006 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
1007 static const struct intel_forcewake_range __chv_fw_ranges[] = {
1008 GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
1009 GEN_FW_RANGE(0x4000, 0x4fff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
1010 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
1011 GEN_FW_RANGE(0x8000, 0x82ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
1012 GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
1013 GEN_FW_RANGE(0x8500, 0x85ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
1014 GEN_FW_RANGE(0x8800, 0x88ff, FORCEWAKE_MEDIA),
1015 GEN_FW_RANGE(0x9000, 0xafff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
1016 GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
1017 GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA),
1018 GEN_FW_RANGE(0xe000, 0xe7ff, FORCEWAKE_RENDER),
1019 GEN_FW_RANGE(0xf000, 0xffff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
1020 GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
1021 GEN_FW_RANGE(0x1a000, 0x1bfff, FORCEWAKE_MEDIA),
1022 GEN_FW_RANGE(0x1e800, 0x1e9ff, FORCEWAKE_MEDIA),
1023 GEN_FW_RANGE(0x30000, 0x37fff, FORCEWAKE_MEDIA),
1024 };
1025
1026 #define __fwtable_reg_write_fw_domains(uncore, offset) \
1027 ({ \
1028 enum forcewake_domains __fwd = 0; \
1029 if (NEEDS_FORCE_WAKE((offset)) && !is_gen8_shadowed(offset)) \
1030 __fwd = find_fw_domain(uncore, offset); \
1031 __fwd; \
1032 })
1033
1034 #define __gen11_fwtable_reg_write_fw_domains(uncore, offset) \
1035 ({ \
1036 enum forcewake_domains __fwd = 0; \
1037 const u32 __offset = (offset); \
1038 if (!is_gen11_shadowed(__offset)) \
1039 __fwd = find_fw_domain(uncore, __offset); \
1040 __fwd; \
1041 })
1042
1043 #define __gen12_fwtable_reg_write_fw_domains(uncore, offset) \
1044 ({ \
1045 enum forcewake_domains __fwd = 0; \
1046 const u32 __offset = (offset); \
1047 if (!is_gen12_shadowed(__offset)) \
1048 __fwd = find_fw_domain(uncore, __offset); \
1049 __fwd; \
1050 })
1051
1052 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
1053 static const struct intel_forcewake_range __gen9_fw_ranges[] = {
1054 GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_GT),
1055 GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
1056 GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
1057 GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_GT),
1058 GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
1059 GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_GT),
1060 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
1061 GEN_FW_RANGE(0x8000, 0x812f, FORCEWAKE_GT),
1062 GEN_FW_RANGE(0x8130, 0x813f, FORCEWAKE_MEDIA),
1063 GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
1064 GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_GT),
1065 GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
1066 GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_GT),
1067 GEN_FW_RANGE(0x8800, 0x89ff, FORCEWAKE_MEDIA),
1068 GEN_FW_RANGE(0x8a00, 0x8bff, FORCEWAKE_GT),
1069 GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
1070 GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_GT),
1071 GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
1072 GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_GT),
1073 GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
1074 GEN_FW_RANGE(0xb480, 0xcfff, FORCEWAKE_GT),
1075 GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA),
1076 GEN_FW_RANGE(0xd800, 0xdfff, FORCEWAKE_GT),
1077 GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER),
1078 GEN_FW_RANGE(0xe900, 0x11fff, FORCEWAKE_GT),
1079 GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
1080 GEN_FW_RANGE(0x14000, 0x19fff, FORCEWAKE_GT),
1081 GEN_FW_RANGE(0x1a000, 0x1e9ff, FORCEWAKE_MEDIA),
1082 GEN_FW_RANGE(0x1ea00, 0x243ff, FORCEWAKE_GT),
1083 GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER),
1084 GEN_FW_RANGE(0x24800, 0x2ffff, FORCEWAKE_GT),
1085 GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
1086 };
1087
1088 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
1089 static const struct intel_forcewake_range __gen11_fw_ranges[] = {
1090 GEN_FW_RANGE(0x0, 0x1fff, 0), /* uncore range */
1091 GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
1092 GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_GT),
1093 GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
1094 GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_GT),
1095 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
1096 GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_GT),
1097 GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
1098 GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_GT),
1099 GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
1100 GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_GT),
1101 GEN_FW_RANGE(0x8800, 0x8bff, 0),
1102 GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
1103 GEN_FW_RANGE(0x8d00, 0x94cf, FORCEWAKE_GT),
1104 GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER),
1105 GEN_FW_RANGE(0x9560, 0x95ff, 0),
1106 GEN_FW_RANGE(0x9600, 0xafff, FORCEWAKE_GT),
1107 GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
1108 GEN_FW_RANGE(0xb480, 0xdeff, FORCEWAKE_GT),
1109 GEN_FW_RANGE(0xdf00, 0xe8ff, FORCEWAKE_RENDER),
1110 GEN_FW_RANGE(0xe900, 0x16dff, FORCEWAKE_GT),
1111 GEN_FW_RANGE(0x16e00, 0x19fff, FORCEWAKE_RENDER),
1112 GEN_FW_RANGE(0x1a000, 0x23fff, FORCEWAKE_GT),
1113 GEN_FW_RANGE(0x24000, 0x2407f, 0),
1114 GEN_FW_RANGE(0x24080, 0x2417f, FORCEWAKE_GT),
1115 GEN_FW_RANGE(0x24180, 0x242ff, FORCEWAKE_RENDER),
1116 GEN_FW_RANGE(0x24300, 0x243ff, FORCEWAKE_GT),
1117 GEN_FW_RANGE(0x24400, 0x24fff, FORCEWAKE_RENDER),
1118 GEN_FW_RANGE(0x25000, 0x3ffff, FORCEWAKE_GT),
1119 GEN_FW_RANGE(0x40000, 0x1bffff, 0),
1120 GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0),
1121 GEN_FW_RANGE(0x1c4000, 0x1c7fff, 0),
1122 GEN_FW_RANGE(0x1c8000, 0x1cffff, FORCEWAKE_MEDIA_VEBOX0),
1123 GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2),
1124 GEN_FW_RANGE(0x1d4000, 0x1dbfff, 0)
1125 };
1126
1127 /*
1128 * *Must* be sorted by offset ranges! See intel_fw_table_check().
1129 *
1130 * Note that the spec lists several reserved/unused ranges that don't
1131 * actually contain any registers. In the table below we'll combine those
1132 * reserved ranges with either the preceding or following range to keep the
1133 * table small and lookups fast.
1134 */
1135 static const struct intel_forcewake_range __gen12_fw_ranges[] = {
1136 GEN_FW_RANGE(0x0, 0x1fff, 0), /*
1137 0x0 - 0xaff: reserved
1138 0xb00 - 0x1fff: always on */
1139 GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
1140 GEN_FW_RANGE(0x2700, 0x27ff, FORCEWAKE_GT),
1141 GEN_FW_RANGE(0x2800, 0x2aff, FORCEWAKE_RENDER),
1142 GEN_FW_RANGE(0x2b00, 0x2fff, FORCEWAKE_GT),
1143 GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
1144 GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_GT), /*
1145 0x4000 - 0x48ff: gt
1146 0x4900 - 0x51ff: reserved */
1147 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), /*
1148 0x5200 - 0x53ff: render
1149 0x5400 - 0x54ff: reserved
1150 0x5500 - 0x7fff: render */
1151 GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_GT),
1152 GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
1153 GEN_FW_RANGE(0x8160, 0x81ff, 0), /*
1154 0x8160 - 0x817f: reserved
1155 0x8180 - 0x81ff: always on */
1156 GEN_FW_RANGE(0x8200, 0x82ff, FORCEWAKE_GT),
1157 GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
1158 GEN_FW_RANGE(0x8500, 0x94cf, FORCEWAKE_GT), /*
1159 0x8500 - 0x87ff: gt
1160 0x8800 - 0x8fff: reserved
1161 0x9000 - 0x947f: gt
1162 0x9480 - 0x94cf: reserved */
1163 GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER),
1164 GEN_FW_RANGE(0x9560, 0x97ff, 0), /*
1165 0x9560 - 0x95ff: always on
1166 0x9600 - 0x97ff: reserved */
1167 GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_GT),
1168 GEN_FW_RANGE(0xb000, 0xb3ff, FORCEWAKE_RENDER),
1169 GEN_FW_RANGE(0xb400, 0xcfff, FORCEWAKE_GT), /*
1170 0xb400 - 0xbf7f: gt
1171 0xb480 - 0xbfff: reserved
1172 0xc000 - 0xcfff: gt */
1173 GEN_FW_RANGE(0xd000, 0xd7ff, 0),
1174 GEN_FW_RANGE(0xd800, 0xd8ff, FORCEWAKE_RENDER),
1175 GEN_FW_RANGE(0xd900, 0xdbff, FORCEWAKE_GT),
1176 GEN_FW_RANGE(0xdc00, 0xefff, FORCEWAKE_RENDER), /*
1177 0xdc00 - 0xddff: render
1178 0xde00 - 0xde7f: reserved
1179 0xde80 - 0xe8ff: render
1180 0xe900 - 0xefff: reserved */
1181 GEN_FW_RANGE(0xf000, 0x147ff, FORCEWAKE_GT), /*
1182 0xf000 - 0xffff: gt
1183 0x10000 - 0x147ff: reserved */
1184 GEN_FW_RANGE(0x14800, 0x1ffff, FORCEWAKE_RENDER), /*
1185 0x14800 - 0x14fff: render
1186 0x15000 - 0x16dff: reserved
1187 0x16e00 - 0x1bfff: render
1188 0x1c000 - 0x1ffff: reserved */
1189 GEN_FW_RANGE(0x20000, 0x20fff, FORCEWAKE_MEDIA_VDBOX0),
1190 GEN_FW_RANGE(0x21000, 0x21fff, FORCEWAKE_MEDIA_VDBOX2),
1191 GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT),
1192 GEN_FW_RANGE(0x24000, 0x2417f, 0), /*
1193 0x24000 - 0x2407f: always on
1194 0x24080 - 0x2417f: reserved */
1195 GEN_FW_RANGE(0x24180, 0x249ff, FORCEWAKE_GT), /*
1196 0x24180 - 0x241ff: gt
1197 0x24200 - 0x249ff: reserved */
1198 GEN_FW_RANGE(0x24a00, 0x251ff, FORCEWAKE_RENDER), /*
1199 0x24a00 - 0x24a7f: render
1200 0x24a80 - 0x251ff: reserved */
1201 GEN_FW_RANGE(0x25200, 0x255ff, FORCEWAKE_GT), /*
1202 0x25200 - 0x252ff: gt
1203 0x25300 - 0x255ff: reserved */
1204 GEN_FW_RANGE(0x25600, 0x2567f, FORCEWAKE_MEDIA_VDBOX0),
1205 GEN_FW_RANGE(0x25680, 0x259ff, FORCEWAKE_MEDIA_VDBOX2), /*
1206 0x25680 - 0x256ff: VD2
1207 0x25700 - 0x259ff: reserved */
1208 GEN_FW_RANGE(0x25a00, 0x25a7f, FORCEWAKE_MEDIA_VDBOX0),
1209 GEN_FW_RANGE(0x25a80, 0x2ffff, FORCEWAKE_MEDIA_VDBOX2), /*
1210 0x25a80 - 0x25aff: VD2
1211 0x25b00 - 0x2ffff: reserved */
1212 GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_GT),
1213 GEN_FW_RANGE(0x40000, 0x1bffff, 0),
1214 GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), /*
1215 0x1c0000 - 0x1c2bff: VD0
1216 0x1c2c00 - 0x1c2cff: reserved
1217 0x1c2d00 - 0x1c2dff: VD0
1218 0x1c2e00 - 0x1c3eff: reserved
1219 0x1c3f00 - 0x1c3fff: VD0 */
1220 GEN_FW_RANGE(0x1c4000, 0x1c7fff, 0),
1221 GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0), /*
1222 0x1c8000 - 0x1ca0ff: VE0
1223 0x1ca100 - 0x1cbeff: reserved
1224 0x1cbf00 - 0x1cbfff: VE0 */
1225 GEN_FW_RANGE(0x1cc000, 0x1cffff, FORCEWAKE_MEDIA_VDBOX0), /*
1226 0x1cc000 - 0x1ccfff: VD0
1227 0x1cd000 - 0x1cffff: reserved */
1228 GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2), /*
1229 0x1d0000 - 0x1d2bff: VD2
1230 0x1d2c00 - 0x1d2cff: reserved
1231 0x1d2d00 - 0x1d2dff: VD2
1232 0x1d2e00 - 0x1d3eff: reserved
1233 0x1d3f00 - 0x1d3fff: VD2 */
1234 };
1235
1236 static void
1237 ilk_dummy_write(struct intel_uncore *uncore)
1238 {
1239 /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
1240 * the chip from rc6 before touching it for real. MI_MODE is masked,
1241 * hence harmless to write 0 into. */
1242 __raw_uncore_write32(uncore, MI_MODE, 0);
1243 }
1244
1245 static void
1246 __unclaimed_reg_debug(struct intel_uncore *uncore,
1247 const i915_reg_t reg,
1248 const bool read,
1249 const bool before)
1250 {
1251 if (drm_WARN(&uncore->i915->drm,
1252 check_for_unclaimed_mmio(uncore) && !before,
1253 "Unclaimed %s register 0x%x\n",
1254 read ? "read from" : "write to",
1255 i915_mmio_reg_offset(reg)))
1256 /* Only report the first N failures */
1257 uncore->i915->params.mmio_debug--;
1258 }
1259
1260 static inline void
1261 unclaimed_reg_debug(struct intel_uncore *uncore,
1262 const i915_reg_t reg,
1263 const bool read,
1264 const bool before)
1265 {
1266 if (likely(!uncore->i915->params.mmio_debug))
1267 return;
1268
1269 /* interrupts are disabled and re-enabled around uncore->lock usage */
1270 lockdep_assert_held(&uncore->lock);
1271
1272 if (before)
1273 spin_lock(&uncore->debug->lock);
1274
1275 __unclaimed_reg_debug(uncore, reg, read, before);
1276
1277 if (!before)
1278 spin_unlock(&uncore->debug->lock);
1279 }
1280
1281 #define __vgpu_read(x) \
1282 static u##x \
1283 vgpu_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
1284 u##x val = __raw_uncore_read##x(uncore, reg); \
1285 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
1286 return val; \
1287 }
1288 __vgpu_read(8)
1289 __vgpu_read(16)
1290 __vgpu_read(32)
1291 __vgpu_read(64)
1292
1293 #define GEN2_READ_HEADER(x) \
1294 u##x val = 0; \
1295 assert_rpm_wakelock_held(uncore->rpm);
1296
1297 #define GEN2_READ_FOOTER \
1298 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
1299 return val
1300
1301 #define __gen2_read(x) \
1302 static u##x \
1303 gen2_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
1304 GEN2_READ_HEADER(x); \
1305 val = __raw_uncore_read##x(uncore, reg); \
1306 GEN2_READ_FOOTER; \
1307 }
1308
1309 #define __gen5_read(x) \
1310 static u##x \
1311 gen5_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
1312 GEN2_READ_HEADER(x); \
1313 ilk_dummy_write(uncore); \
1314 val = __raw_uncore_read##x(uncore, reg); \
1315 GEN2_READ_FOOTER; \
1316 }
1317
1318 __gen5_read(8)
1319 __gen5_read(16)
1320 __gen5_read(32)
1321 __gen5_read(64)
1322 __gen2_read(8)
1323 __gen2_read(16)
1324 __gen2_read(32)
1325 __gen2_read(64)
1326
1327 #undef __gen5_read
1328 #undef __gen2_read
1329
1330 #undef GEN2_READ_FOOTER
1331 #undef GEN2_READ_HEADER
1332
1333 #define GEN6_READ_HEADER(x) \
1334 u32 offset = i915_mmio_reg_offset(reg); \
1335 unsigned long irqflags; \
1336 u##x val = 0; \
1337 assert_rpm_wakelock_held(uncore->rpm); \
1338 spin_lock_irqsave(&uncore->lock, irqflags); \
1339 unclaimed_reg_debug(uncore, reg, true, true)
1340
1341 #define GEN6_READ_FOOTER \
1342 unclaimed_reg_debug(uncore, reg, true, false); \
1343 spin_unlock_irqrestore(&uncore->lock, irqflags); \
1344 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
1345 return val
1346
1347 static noinline void ___force_wake_auto(struct intel_uncore *uncore,
1348 enum forcewake_domains fw_domains)
1349 {
1350 struct intel_uncore_forcewake_domain *domain;
1351 unsigned int tmp;
1352
1353 GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
1354
1355 for_each_fw_domain_masked(domain, fw_domains, uncore, tmp)
1356 fw_domain_arm_timer(domain);
1357
1358 uncore->funcs.force_wake_get(uncore, fw_domains);
1359 }
1360
1361 static inline void __force_wake_auto(struct intel_uncore *uncore,
1362 enum forcewake_domains fw_domains)
1363 {
1364 GEM_BUG_ON(!fw_domains);
1365
1366 /* Turn on all requested but inactive supported forcewake domains. */
1367 fw_domains &= uncore->fw_domains;
1368 fw_domains &= ~uncore->fw_domains_active;
1369
1370 if (fw_domains)
1371 ___force_wake_auto(uncore, fw_domains);
1372 }
1373
1374 #define __gen_read(func, x) \
1375 static u##x \
1376 func##_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
1377 enum forcewake_domains fw_engine; \
1378 GEN6_READ_HEADER(x); \
1379 fw_engine = __##func##_reg_read_fw_domains(uncore, offset); \
1380 if (fw_engine) \
1381 __force_wake_auto(uncore, fw_engine); \
1382 val = __raw_uncore_read##x(uncore, reg); \
1383 GEN6_READ_FOOTER; \
1384 }
1385
1386 #define __gen_reg_read_funcs(func) \
1387 static enum forcewake_domains \
1388 func##_reg_read_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) { \
1389 return __##func##_reg_read_fw_domains(uncore, i915_mmio_reg_offset(reg)); \
1390 } \
1391 \
1392 __gen_read(func, 8) \
1393 __gen_read(func, 16) \
1394 __gen_read(func, 32) \
1395 __gen_read(func, 64)
1396
1397 __gen_reg_read_funcs(gen12_fwtable);
1398 __gen_reg_read_funcs(gen11_fwtable);
1399 __gen_reg_read_funcs(fwtable);
1400 __gen_reg_read_funcs(gen6);
1401
1402 #undef __gen_reg_read_funcs
1403 #undef GEN6_READ_FOOTER
1404 #undef GEN6_READ_HEADER
1405
1406 #define GEN2_WRITE_HEADER \
1407 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1408 assert_rpm_wakelock_held(uncore->rpm); \
1409
1410 #define GEN2_WRITE_FOOTER
1411
1412 #define __gen2_write(x) \
1413 static void \
1414 gen2_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
1415 GEN2_WRITE_HEADER; \
1416 __raw_uncore_write##x(uncore, reg, val); \
1417 GEN2_WRITE_FOOTER; \
1418 }
1419
1420 #define __gen5_write(x) \
1421 static void \
1422 gen5_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
1423 GEN2_WRITE_HEADER; \
1424 ilk_dummy_write(uncore); \
1425 __raw_uncore_write##x(uncore, reg, val); \
1426 GEN2_WRITE_FOOTER; \
1427 }
1428
1429 __gen5_write(8)
1430 __gen5_write(16)
1431 __gen5_write(32)
1432 __gen2_write(8)
1433 __gen2_write(16)
1434 __gen2_write(32)
1435
1436 #undef __gen5_write
1437 #undef __gen2_write
1438
1439 #undef GEN2_WRITE_FOOTER
1440 #undef GEN2_WRITE_HEADER
1441
1442 #define GEN6_WRITE_HEADER \
1443 u32 offset = i915_mmio_reg_offset(reg); \
1444 unsigned long irqflags; \
1445 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1446 assert_rpm_wakelock_held(uncore->rpm); \
1447 spin_lock_irqsave(&uncore->lock, irqflags); \
1448 unclaimed_reg_debug(uncore, reg, false, true)
1449
1450 #define GEN6_WRITE_FOOTER \
1451 unclaimed_reg_debug(uncore, reg, false, false); \
1452 spin_unlock_irqrestore(&uncore->lock, irqflags)
1453
1454 #define __gen6_write(x) \
1455 static void \
1456 gen6_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
1457 GEN6_WRITE_HEADER; \
1458 if (NEEDS_FORCE_WAKE(offset)) \
1459 __gen6_gt_wait_for_fifo(uncore); \
1460 __raw_uncore_write##x(uncore, reg, val); \
1461 GEN6_WRITE_FOOTER; \
1462 }
1463 __gen6_write(8)
1464 __gen6_write(16)
1465 __gen6_write(32)
1466
1467 #define __gen_write(func, x) \
1468 static void \
1469 func##_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
1470 enum forcewake_domains fw_engine; \
1471 GEN6_WRITE_HEADER; \
1472 fw_engine = __##func##_reg_write_fw_domains(uncore, offset); \
1473 if (fw_engine) \
1474 __force_wake_auto(uncore, fw_engine); \
1475 __raw_uncore_write##x(uncore, reg, val); \
1476 GEN6_WRITE_FOOTER; \
1477 }
1478
1479 #define __gen_reg_write_funcs(func) \
1480 static enum forcewake_domains \
1481 func##_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) { \
1482 return __##func##_reg_write_fw_domains(uncore, i915_mmio_reg_offset(reg)); \
1483 } \
1484 \
1485 __gen_write(func, 8) \
1486 __gen_write(func, 16) \
1487 __gen_write(func, 32)
1488
1489 __gen_reg_write_funcs(gen12_fwtable);
1490 __gen_reg_write_funcs(gen11_fwtable);
1491 __gen_reg_write_funcs(fwtable);
1492 __gen_reg_write_funcs(gen8);
1493
1494 #undef __gen_reg_write_funcs
1495 #undef GEN6_WRITE_FOOTER
1496 #undef GEN6_WRITE_HEADER
1497
1498 #define __vgpu_write(x) \
1499 static void \
1500 vgpu_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
1501 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1502 __raw_uncore_write##x(uncore, reg, val); \
1503 }
1504 __vgpu_write(8)
1505 __vgpu_write(16)
1506 __vgpu_write(32)
1507
1508 #define ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, x) \
1509 do { \
1510 (uncore)->funcs.mmio_writeb = x##_write8; \
1511 (uncore)->funcs.mmio_writew = x##_write16; \
1512 (uncore)->funcs.mmio_writel = x##_write32; \
1513 } while (0)
1514
1515 #define ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, x) \
1516 do { \
1517 (uncore)->funcs.mmio_readb = x##_read8; \
1518 (uncore)->funcs.mmio_readw = x##_read16; \
1519 (uncore)->funcs.mmio_readl = x##_read32; \
1520 (uncore)->funcs.mmio_readq = x##_read64; \
1521 } while (0)
1522
1523 #define ASSIGN_WRITE_MMIO_VFUNCS(uncore, x) \
1524 do { \
1525 ASSIGN_RAW_WRITE_MMIO_VFUNCS((uncore), x); \
1526 (uncore)->funcs.write_fw_domains = x##_reg_write_fw_domains; \
1527 } while (0)
1528
1529 #define ASSIGN_READ_MMIO_VFUNCS(uncore, x) \
1530 do { \
1531 ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, x); \
1532 (uncore)->funcs.read_fw_domains = x##_reg_read_fw_domains; \
1533 } while (0)
1534
1535 static int __fw_domain_init(struct intel_uncore *uncore,
1536 enum forcewake_domain_id domain_id,
1537 i915_reg_t reg_set,
1538 i915_reg_t reg_ack)
1539 {
1540 struct intel_uncore_forcewake_domain *d;
1541
1542 GEM_BUG_ON(domain_id >= FW_DOMAIN_ID_COUNT);
1543 GEM_BUG_ON(uncore->fw_domain[domain_id]);
1544
1545 if (i915_inject_probe_failure(uncore->i915))
1546 return -ENOMEM;
1547
1548 d = kzalloc(sizeof(*d), GFP_KERNEL);
1549 if (!d)
1550 return -ENOMEM;
1551
1552 drm_WARN_ON(&uncore->i915->drm, !i915_mmio_reg_valid(reg_set));
1553 drm_WARN_ON(&uncore->i915->drm, !i915_mmio_reg_valid(reg_ack));
1554
1555 d->uncore = uncore;
1556 d->wake_count = 0;
1557 d->reg_set = uncore->regs + i915_mmio_reg_offset(reg_set);
1558 d->reg_ack = uncore->regs + i915_mmio_reg_offset(reg_ack);
1559
1560 d->id = domain_id;
1561
1562 BUILD_BUG_ON(FORCEWAKE_RENDER != (1 << FW_DOMAIN_ID_RENDER));
1563 BUILD_BUG_ON(FORCEWAKE_GT != (1 << FW_DOMAIN_ID_GT));
1564 BUILD_BUG_ON(FORCEWAKE_MEDIA != (1 << FW_DOMAIN_ID_MEDIA));
1565 BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX0));
1566 BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX1));
1567 BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX2 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX2));
1568 BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX3 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX3));
1569 BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX0));
1570 BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX1));
1571
1572 d->mask = BIT(domain_id);
1573
1574 hrtimer_init(&d->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1575 d->timer.function = intel_uncore_fw_release_timer;
1576
1577 uncore->fw_domains |= BIT(domain_id);
1578
1579 fw_domain_reset(d);
1580
1581 uncore->fw_domain[domain_id] = d;
1582
1583 return 0;
1584 }
1585
1586 static void fw_domain_fini(struct intel_uncore *uncore,
1587 enum forcewake_domain_id domain_id)
1588 {
1589 struct intel_uncore_forcewake_domain *d;
1590
1591 GEM_BUG_ON(domain_id >= FW_DOMAIN_ID_COUNT);
1592
1593 d = fetch_and_zero(&uncore->fw_domain[domain_id]);
1594 if (!d)
1595 return;
1596
1597 uncore->fw_domains &= ~BIT(domain_id);
1598 drm_WARN_ON(&uncore->i915->drm, d->wake_count);
1599 drm_WARN_ON(&uncore->i915->drm, hrtimer_cancel(&d->timer));
1600 kfree(d);
1601 }
1602
1603 static void intel_uncore_fw_domains_fini(struct intel_uncore *uncore)
1604 {
1605 struct intel_uncore_forcewake_domain *d;
1606 int tmp;
1607
1608 for_each_fw_domain(d, uncore, tmp)
1609 fw_domain_fini(uncore, d->id);
1610 }
1611
1612 static int intel_uncore_fw_domains_init(struct intel_uncore *uncore)
1613 {
1614 struct drm_i915_private *i915 = uncore->i915;
1615 int ret = 0;
1616
1617 GEM_BUG_ON(!intel_uncore_has_forcewake(uncore));
1618
1619 #define fw_domain_init(uncore__, id__, set__, ack__) \
1620 (ret ?: (ret = __fw_domain_init((uncore__), (id__), (set__), (ack__))))
1621
1622 if (INTEL_GEN(i915) >= 11) {
1623 /* we'll prune the domains of missing engines later */
1624 intel_engine_mask_t emask = INTEL_INFO(i915)->platform_engine_mask;
1625 int i;
1626
1627 uncore->funcs.force_wake_get = fw_domains_get_with_fallback;
1628 uncore->funcs.force_wake_put = fw_domains_put;
1629 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1630 FORCEWAKE_RENDER_GEN9,
1631 FORCEWAKE_ACK_RENDER_GEN9);
1632 fw_domain_init(uncore, FW_DOMAIN_ID_GT,
1633 FORCEWAKE_GT_GEN9,
1634 FORCEWAKE_ACK_GT_GEN9);
1635
1636 for (i = 0; i < I915_MAX_VCS; i++) {
1637 if (!__HAS_ENGINE(emask, _VCS(i)))
1638 continue;
1639
1640 fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA_VDBOX0 + i,
1641 FORCEWAKE_MEDIA_VDBOX_GEN11(i),
1642 FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(i));
1643 }
1644 for (i = 0; i < I915_MAX_VECS; i++) {
1645 if (!__HAS_ENGINE(emask, _VECS(i)))
1646 continue;
1647
1648 fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA_VEBOX0 + i,
1649 FORCEWAKE_MEDIA_VEBOX_GEN11(i),
1650 FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(i));
1651 }
1652 } else if (IS_GEN_RANGE(i915, 9, 10)) {
1653 uncore->funcs.force_wake_get = fw_domains_get_with_fallback;
1654 uncore->funcs.force_wake_put = fw_domains_put;
1655 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1656 FORCEWAKE_RENDER_GEN9,
1657 FORCEWAKE_ACK_RENDER_GEN9);
1658 fw_domain_init(uncore, FW_DOMAIN_ID_GT,
1659 FORCEWAKE_GT_GEN9,
1660 FORCEWAKE_ACK_GT_GEN9);
1661 fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA,
1662 FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
1663 } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
1664 uncore->funcs.force_wake_get = fw_domains_get;
1665 uncore->funcs.force_wake_put = fw_domains_put;
1666 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1667 FORCEWAKE_VLV, FORCEWAKE_ACK_VLV);
1668 fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA,
1669 FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV);
1670 } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
1671 uncore->funcs.force_wake_get =
1672 fw_domains_get_with_thread_status;
1673 uncore->funcs.force_wake_put = fw_domains_put;
1674 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1675 FORCEWAKE_MT, FORCEWAKE_ACK_HSW);
1676 } else if (IS_IVYBRIDGE(i915)) {
1677 u32 ecobus;
1678
1679 /* IVB configs may use multi-threaded forcewake */
1680
1681 /* A small trick here - if the bios hasn't configured
1682 * MT forcewake, and if the device is in RC6, then
1683 * force_wake_mt_get will not wake the device and the
1684 * ECOBUS read will return zero. Which will be
1685 * (correctly) interpreted by the test below as MT
1686 * forcewake being disabled.
1687 */
1688 uncore->funcs.force_wake_get =
1689 fw_domains_get_with_thread_status;
1690 uncore->funcs.force_wake_put = fw_domains_put;
1691
1692 /* We need to init first for ECOBUS access and then
1693 * determine later if we want to reinit, in case of MT access is
1694 * not working. In this stage we don't know which flavour this
1695 * ivb is, so it is better to reset also the gen6 fw registers
1696 * before the ecobus check.
1697 */
1698
1699 __raw_uncore_write32(uncore, FORCEWAKE, 0);
1700 __raw_posting_read(uncore, ECOBUS);
1701
1702 ret = __fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1703 FORCEWAKE_MT, FORCEWAKE_MT_ACK);
1704 if (ret)
1705 goto out;
1706
1707 spin_lock_irq(&uncore->lock);
1708 fw_domains_get_with_thread_status(uncore, FORCEWAKE_RENDER);
1709 ecobus = __raw_uncore_read32(uncore, ECOBUS);
1710 fw_domains_put(uncore, FORCEWAKE_RENDER);
1711 spin_unlock_irq(&uncore->lock);
1712
1713 if (!(ecobus & FORCEWAKE_MT_ENABLE)) {
1714 drm_info(&i915->drm, "No MT forcewake available on Ivybridge, this can result in issues\n");
1715 drm_info(&i915->drm, "when using vblank-synced partial screen updates.\n");
1716 fw_domain_fini(uncore, FW_DOMAIN_ID_RENDER);
1717 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1718 FORCEWAKE, FORCEWAKE_ACK);
1719 }
1720 } else if (IS_GEN(i915, 6)) {
1721 uncore->funcs.force_wake_get =
1722 fw_domains_get_with_thread_status;
1723 uncore->funcs.force_wake_put = fw_domains_put;
1724 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1725 FORCEWAKE, FORCEWAKE_ACK);
1726 }
1727
1728 #undef fw_domain_init
1729
1730 /* All future platforms are expected to require complex power gating */
1731 drm_WARN_ON(&i915->drm, !ret && uncore->fw_domains == 0);
1732
1733 out:
1734 if (ret)
1735 intel_uncore_fw_domains_fini(uncore);
1736
1737 return ret;
1738 }
1739
1740 #define ASSIGN_FW_DOMAINS_TABLE(uncore, d) \
1741 { \
1742 (uncore)->fw_domains_table = \
1743 (struct intel_forcewake_range *)(d); \
1744 (uncore)->fw_domains_table_entries = ARRAY_SIZE((d)); \
1745 }
1746
1747 static int i915_pmic_bus_access_notifier(struct notifier_block *nb,
1748 unsigned long action, void *data)
1749 {
1750 struct intel_uncore *uncore = container_of(nb,
1751 struct intel_uncore, pmic_bus_access_nb);
1752
1753 switch (action) {
1754 case MBI_PMIC_BUS_ACCESS_BEGIN:
1755 /*
1756 * forcewake all now to make sure that we don't need to do a
1757 * forcewake later which on systems where this notifier gets
1758 * called requires the punit to access to the shared pmic i2c
1759 * bus, which will be busy after this notification, leading to:
1760 * "render: timed out waiting for forcewake ack request."
1761 * errors.
1762 *
1763 * The notifier is unregistered during intel_runtime_suspend(),
1764 * so it's ok to access the HW here without holding a RPM
1765 * wake reference -> disable wakeref asserts for the time of
1766 * the access.
1767 */
1768 disable_rpm_wakeref_asserts(uncore->rpm);
1769 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
1770 enable_rpm_wakeref_asserts(uncore->rpm);
1771 break;
1772 case MBI_PMIC_BUS_ACCESS_END:
1773 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
1774 break;
1775 }
1776
1777 return NOTIFY_OK;
1778 }
1779
1780 static int uncore_mmio_setup(struct intel_uncore *uncore)
1781 {
1782 struct drm_i915_private *i915 = uncore->i915;
1783 struct pci_dev *pdev = i915->drm.pdev;
1784 int mmio_bar;
1785 int mmio_size;
1786
1787 mmio_bar = IS_GEN(i915, 2) ? 1 : 0;
1788 /*
1789 * Before gen4, the registers and the GTT are behind different BARs.
1790 * However, from gen4 onwards, the registers and the GTT are shared
1791 * in the same BAR, so we want to restrict this ioremap from
1792 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
1793 * the register BAR remains the same size for all the earlier
1794 * generations up to Ironlake.
1795 * For dgfx chips register range is expanded to 4MB.
1796 */
1797 if (INTEL_GEN(i915) < 5)
1798 mmio_size = 512 * 1024;
1799 else if (IS_DGFX(i915))
1800 mmio_size = 4 * 1024 * 1024;
1801 else
1802 mmio_size = 2 * 1024 * 1024;
1803
1804 uncore->regs = pci_iomap(pdev, mmio_bar, mmio_size);
1805 if (uncore->regs == NULL) {
1806 drm_err(&i915->drm, "failed to map registers\n");
1807 return -EIO;
1808 }
1809
1810 return 0;
1811 }
1812
1813 static void uncore_mmio_cleanup(struct intel_uncore *uncore)
1814 {
1815 struct pci_dev *pdev = uncore->i915->drm.pdev;
1816
1817 pci_iounmap(pdev, uncore->regs);
1818 }
1819
1820 void intel_uncore_init_early(struct intel_uncore *uncore,
1821 struct drm_i915_private *i915)
1822 {
1823 spin_lock_init(&uncore->lock);
1824 uncore->i915 = i915;
1825 uncore->rpm = &i915->runtime_pm;
1826 uncore->debug = &i915->mmio_debug;
1827 }
1828
1829 static void uncore_raw_init(struct intel_uncore *uncore)
1830 {
1831 GEM_BUG_ON(intel_uncore_has_forcewake(uncore));
1832
1833 if (intel_vgpu_active(uncore->i915)) {
1834 ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, vgpu);
1835 ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, vgpu);
1836 } else if (IS_GEN(uncore->i915, 5)) {
1837 ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, gen5);
1838 ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, gen5);
1839 } else {
1840 ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, gen2);
1841 ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, gen2);
1842 }
1843 }
1844
1845 static int uncore_forcewake_init(struct intel_uncore *uncore)
1846 {
1847 struct drm_i915_private *i915 = uncore->i915;
1848 int ret;
1849
1850 GEM_BUG_ON(!intel_uncore_has_forcewake(uncore));
1851
1852 ret = intel_uncore_fw_domains_init(uncore);
1853 if (ret)
1854 return ret;
1855 forcewake_early_sanitize(uncore, 0);
1856
1857 if (IS_GEN_RANGE(i915, 6, 7)) {
1858 ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen6);
1859
1860 if (IS_VALLEYVIEW(i915)) {
1861 ASSIGN_FW_DOMAINS_TABLE(uncore, __vlv_fw_ranges);
1862 ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
1863 } else {
1864 ASSIGN_READ_MMIO_VFUNCS(uncore, gen6);
1865 }
1866 } else if (IS_GEN(i915, 8)) {
1867 if (IS_CHERRYVIEW(i915)) {
1868 ASSIGN_FW_DOMAINS_TABLE(uncore, __chv_fw_ranges);
1869 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
1870 ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
1871 } else {
1872 ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen8);
1873 ASSIGN_READ_MMIO_VFUNCS(uncore, gen6);
1874 }
1875 } else if (IS_GEN_RANGE(i915, 9, 10)) {
1876 ASSIGN_FW_DOMAINS_TABLE(uncore, __gen9_fw_ranges);
1877 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
1878 ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
1879 } else if (IS_GEN(i915, 11)) {
1880 ASSIGN_FW_DOMAINS_TABLE(uncore, __gen11_fw_ranges);
1881 ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen11_fwtable);
1882 ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable);
1883 } else {
1884 ASSIGN_FW_DOMAINS_TABLE(uncore, __gen12_fw_ranges);
1885 ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen12_fwtable);
1886 ASSIGN_READ_MMIO_VFUNCS(uncore, gen12_fwtable);
1887 }
1888
1889 uncore->pmic_bus_access_nb.notifier_call = i915_pmic_bus_access_notifier;
1890 iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb);
1891
1892 return 0;
1893 }
1894
1895 int intel_uncore_init_mmio(struct intel_uncore *uncore)
1896 {
1897 struct drm_i915_private *i915 = uncore->i915;
1898 int ret;
1899
1900 ret = uncore_mmio_setup(uncore);
1901 if (ret)
1902 return ret;
1903
1904 if (INTEL_GEN(i915) > 5 && !intel_vgpu_active(i915))
1905 uncore->flags |= UNCORE_HAS_FORCEWAKE;
1906
1907 if (!intel_uncore_has_forcewake(uncore)) {
1908 uncore_raw_init(uncore);
1909 } else {
1910 ret = uncore_forcewake_init(uncore);
1911 if (ret)
1912 goto out_mmio_cleanup;
1913 }
1914
1915 /* make sure fw funcs are set if and only if we have fw*/
1916 GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.force_wake_get);
1917 GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.force_wake_put);
1918 GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.read_fw_domains);
1919 GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.write_fw_domains);
1920
1921 if (HAS_FPGA_DBG_UNCLAIMED(i915))
1922 uncore->flags |= UNCORE_HAS_FPGA_DBG_UNCLAIMED;
1923
1924 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
1925 uncore->flags |= UNCORE_HAS_DBG_UNCLAIMED;
1926
1927 if (IS_GEN_RANGE(i915, 6, 7))
1928 uncore->flags |= UNCORE_HAS_FIFO;
1929
1930 /* clear out unclaimed reg detection bit */
1931 if (intel_uncore_unclaimed_mmio(uncore))
1932 drm_dbg(&i915->drm, "unclaimed mmio detected on uncore init, clearing\n");
1933
1934 return 0;
1935
1936 out_mmio_cleanup:
1937 uncore_mmio_cleanup(uncore);
1938
1939 return ret;
1940 }
1941
1942 /*
1943 * We might have detected that some engines are fused off after we initialized
1944 * the forcewake domains. Prune them, to make sure they only reference existing
1945 * engines.
1946 */
1947 void intel_uncore_prune_engine_fw_domains(struct intel_uncore *uncore,
1948 struct intel_gt *gt)
1949 {
1950 enum forcewake_domains fw_domains = uncore->fw_domains;
1951 enum forcewake_domain_id domain_id;
1952 int i;
1953
1954 if (!intel_uncore_has_forcewake(uncore) || INTEL_GEN(uncore->i915) < 11)
1955 return;
1956
1957 for (i = 0; i < I915_MAX_VCS; i++) {
1958 domain_id = FW_DOMAIN_ID_MEDIA_VDBOX0 + i;
1959
1960 if (HAS_ENGINE(gt, _VCS(i)))
1961 continue;
1962
1963 if (fw_domains & BIT(domain_id))
1964 fw_domain_fini(uncore, domain_id);
1965 }
1966
1967 for (i = 0; i < I915_MAX_VECS; i++) {
1968 domain_id = FW_DOMAIN_ID_MEDIA_VEBOX0 + i;
1969
1970 if (HAS_ENGINE(gt, _VECS(i)))
1971 continue;
1972
1973 if (fw_domains & BIT(domain_id))
1974 fw_domain_fini(uncore, domain_id);
1975 }
1976 }
1977
1978 void intel_uncore_fini_mmio(struct intel_uncore *uncore)
1979 {
1980 if (intel_uncore_has_forcewake(uncore)) {
1981 iosf_mbi_punit_acquire();
1982 iosf_mbi_unregister_pmic_bus_access_notifier_unlocked(
1983 &uncore->pmic_bus_access_nb);
1984 intel_uncore_forcewake_reset(uncore);
1985 intel_uncore_fw_domains_fini(uncore);
1986 iosf_mbi_punit_release();
1987 }
1988
1989 uncore_mmio_cleanup(uncore);
1990 }
1991
1992 static const struct reg_whitelist {
1993 i915_reg_t offset_ldw;
1994 i915_reg_t offset_udw;
1995 u16 gen_mask;
1996 u8 size;
1997 } reg_read_whitelist[] = { {
1998 .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
1999 .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
2000 .gen_mask = INTEL_GEN_MASK(4, 12),
2001 .size = 8
2002 } };
2003
2004 int i915_reg_read_ioctl(struct drm_device *dev,
2005 void *data, struct drm_file *file)
2006 {
2007 struct drm_i915_private *i915 = to_i915(dev);
2008 struct intel_uncore *uncore = &i915->uncore;
2009 struct drm_i915_reg_read *reg = data;
2010 struct reg_whitelist const *entry;
2011 intel_wakeref_t wakeref;
2012 unsigned int flags;
2013 int remain;
2014 int ret = 0;
2015
2016 entry = reg_read_whitelist;
2017 remain = ARRAY_SIZE(reg_read_whitelist);
2018 while (remain) {
2019 u32 entry_offset = i915_mmio_reg_offset(entry->offset_ldw);
2020
2021 GEM_BUG_ON(!is_power_of_2(entry->size));
2022 GEM_BUG_ON(entry->size > 8);
2023 GEM_BUG_ON(entry_offset & (entry->size - 1));
2024
2025 if (INTEL_INFO(i915)->gen_mask & entry->gen_mask &&
2026 entry_offset == (reg->offset & -entry->size))
2027 break;
2028 entry++;
2029 remain--;
2030 }
2031
2032 if (!remain)
2033 return -EINVAL;
2034
2035 flags = reg->offset & (entry->size - 1);
2036
2037 with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
2038 if (entry->size == 8 && flags == I915_REG_READ_8B_WA)
2039 reg->val = intel_uncore_read64_2x32(uncore,
2040 entry->offset_ldw,
2041 entry->offset_udw);
2042 else if (entry->size == 8 && flags == 0)
2043 reg->val = intel_uncore_read64(uncore,
2044 entry->offset_ldw);
2045 else if (entry->size == 4 && flags == 0)
2046 reg->val = intel_uncore_read(uncore, entry->offset_ldw);
2047 else if (entry->size == 2 && flags == 0)
2048 reg->val = intel_uncore_read16(uncore,
2049 entry->offset_ldw);
2050 else if (entry->size == 1 && flags == 0)
2051 reg->val = intel_uncore_read8(uncore,
2052 entry->offset_ldw);
2053 else
2054 ret = -EINVAL;
2055 }
2056
2057 return ret;
2058 }
2059
2060 /**
2061 * __intel_wait_for_register_fw - wait until register matches expected state
2062 * @uncore: the struct intel_uncore
2063 * @reg: the register to read
2064 * @mask: mask to apply to register value
2065 * @value: expected value
2066 * @fast_timeout_us: fast timeout in microsecond for atomic/tight wait
2067 * @slow_timeout_ms: slow timeout in millisecond
2068 * @out_value: optional placeholder to hold registry value
2069 *
2070 * This routine waits until the target register @reg contains the expected
2071 * @value after applying the @mask, i.e. it waits until ::
2072 *
2073 * (I915_READ_FW(reg) & mask) == value
2074 *
2075 * Otherwise, the wait will timeout after @slow_timeout_ms milliseconds.
2076 * For atomic context @slow_timeout_ms must be zero and @fast_timeout_us
2077 * must be not larger than 20,0000 microseconds.
2078 *
2079 * Note that this routine assumes the caller holds forcewake asserted, it is
2080 * not suitable for very long waits. See intel_wait_for_register() if you
2081 * wish to wait without holding forcewake for the duration (i.e. you expect
2082 * the wait to be slow).
2083 *
2084 * Return: 0 if the register matches the desired condition, or -ETIMEDOUT.
2085 */
2086 int __intel_wait_for_register_fw(struct intel_uncore *uncore,
2087 i915_reg_t reg,
2088 u32 mask,
2089 u32 value,
2090 unsigned int fast_timeout_us,
2091 unsigned int slow_timeout_ms,
2092 u32 *out_value)
2093 {
2094 u32 reg_value = 0;
2095 #define done (((reg_value = intel_uncore_read_fw(uncore, reg)) & mask) == value)
2096 int ret;
2097
2098 /* Catch any overuse of this function */
2099 might_sleep_if(slow_timeout_ms);
2100 GEM_BUG_ON(fast_timeout_us > 20000);
2101 GEM_BUG_ON(!fast_timeout_us && !slow_timeout_ms);
2102
2103 ret = -ETIMEDOUT;
2104 if (fast_timeout_us && fast_timeout_us <= 20000)
2105 ret = _wait_for_atomic(done, fast_timeout_us, 0);
2106 if (ret && slow_timeout_ms)
2107 ret = wait_for(done, slow_timeout_ms);
2108
2109 if (out_value)
2110 *out_value = reg_value;
2111
2112 return ret;
2113 #undef done
2114 }
2115
2116 /**
2117 * __intel_wait_for_register - wait until register matches expected state
2118 * @uncore: the struct intel_uncore
2119 * @reg: the register to read
2120 * @mask: mask to apply to register value
2121 * @value: expected value
2122 * @fast_timeout_us: fast timeout in microsecond for atomic/tight wait
2123 * @slow_timeout_ms: slow timeout in millisecond
2124 * @out_value: optional placeholder to hold registry value
2125 *
2126 * This routine waits until the target register @reg contains the expected
2127 * @value after applying the @mask, i.e. it waits until ::
2128 *
2129 * (I915_READ(reg) & mask) == value
2130 *
2131 * Otherwise, the wait will timeout after @timeout_ms milliseconds.
2132 *
2133 * Return: 0 if the register matches the desired condition, or -ETIMEDOUT.
2134 */
2135 int __intel_wait_for_register(struct intel_uncore *uncore,
2136 i915_reg_t reg,
2137 u32 mask,
2138 u32 value,
2139 unsigned int fast_timeout_us,
2140 unsigned int slow_timeout_ms,
2141 u32 *out_value)
2142 {
2143 unsigned fw =
2144 intel_uncore_forcewake_for_reg(uncore, reg, FW_REG_READ);
2145 u32 reg_value;
2146 int ret;
2147
2148 might_sleep_if(slow_timeout_ms);
2149
2150 spin_lock_irq(&uncore->lock);
2151 intel_uncore_forcewake_get__locked(uncore, fw);
2152
2153 ret = __intel_wait_for_register_fw(uncore,
2154 reg, mask, value,
2155 fast_timeout_us, 0, &reg_value);
2156
2157 intel_uncore_forcewake_put__locked(uncore, fw);
2158 spin_unlock_irq(&uncore->lock);
2159
2160 if (ret && slow_timeout_ms)
2161 ret = __wait_for(reg_value = intel_uncore_read_notrace(uncore,
2162 reg),
2163 (reg_value & mask) == value,
2164 slow_timeout_ms * 1000, 10, 1000);
2165
2166 /* just trace the final value */
2167 trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true);
2168
2169 if (out_value)
2170 *out_value = reg_value;
2171
2172 return ret;
2173 }
2174
2175 bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore)
2176 {
2177 bool ret;
2178
2179 spin_lock_irq(&uncore->debug->lock);
2180 ret = check_for_unclaimed_mmio(uncore);
2181 spin_unlock_irq(&uncore->debug->lock);
2182
2183 return ret;
2184 }
2185
2186 bool
2187 intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore)
2188 {
2189 bool ret = false;
2190
2191 spin_lock_irq(&uncore->debug->lock);
2192
2193 if (unlikely(uncore->debug->unclaimed_mmio_check <= 0))
2194 goto out;
2195
2196 if (unlikely(check_for_unclaimed_mmio(uncore))) {
2197 if (!uncore->i915->params.mmio_debug) {
2198 drm_dbg(&uncore->i915->drm,
2199 "Unclaimed register detected, "
2200 "enabling oneshot unclaimed register reporting. "
2201 "Please use i915.mmio_debug=N for more information.\n");
2202 uncore->i915->params.mmio_debug++;
2203 }
2204 uncore->debug->unclaimed_mmio_check--;
2205 ret = true;
2206 }
2207
2208 out:
2209 spin_unlock_irq(&uncore->debug->lock);
2210
2211 return ret;
2212 }
2213
2214 /**
2215 * intel_uncore_forcewake_for_reg - which forcewake domains are needed to access
2216 * a register
2217 * @uncore: pointer to struct intel_uncore
2218 * @reg: register in question
2219 * @op: operation bitmask of FW_REG_READ and/or FW_REG_WRITE
2220 *
2221 * Returns a set of forcewake domains required to be taken with for example
2222 * intel_uncore_forcewake_get for the specified register to be accessible in the
2223 * specified mode (read, write or read/write) with raw mmio accessors.
2224 *
2225 * NOTE: On Gen6 and Gen7 write forcewake domain (FORCEWAKE_RENDER) requires the
2226 * callers to do FIFO management on their own or risk losing writes.
2227 */
2228 enum forcewake_domains
2229 intel_uncore_forcewake_for_reg(struct intel_uncore *uncore,
2230 i915_reg_t reg, unsigned int op)
2231 {
2232 enum forcewake_domains fw_domains = 0;
2233
2234 drm_WARN_ON(&uncore->i915->drm, !op);
2235
2236 if (!intel_uncore_has_forcewake(uncore))
2237 return 0;
2238
2239 if (op & FW_REG_READ)
2240 fw_domains = uncore->funcs.read_fw_domains(uncore, reg);
2241
2242 if (op & FW_REG_WRITE)
2243 fw_domains |= uncore->funcs.write_fw_domains(uncore, reg);
2244
2245 drm_WARN_ON(&uncore->i915->drm, fw_domains & ~uncore->fw_domains);
2246
2247 return fw_domains;
2248 }
2249
2250 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2251 #include "selftests/mock_uncore.c"
2252 #include "selftests/intel_uncore.c"
2253 #endif
Linux with added FPC-III support