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Merge tag 'block-5.11-2021-01-10' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / gpu / drm / msm / adreno / a4xx.xml.h
bloba7eaf2c83fe23ebd1894a1f8659162754db42e50
1 #ifndef A4XX_XML
2 #define A4XX_XML
3
4 /* Autogenerated file, DO NOT EDIT manually!
5
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
9
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14)
12 - /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
13 - /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14)
14 - /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14)
15 - /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14)
16 - /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14)
17 - /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14)
18 - /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14)
19 - /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14)
20 - /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14)
21 - /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14)
22 - /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14)
23 - /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14)
24
25 Copyright (C) 2013-2020 by the following authors:
26 - Rob Clark <robdclark@gmail.com> (robclark)
27 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
28
29 Permission is hereby granted, free of charge, to any person obtaining
30 a copy of this software and associated documentation files (the
31 "Software"), to deal in the Software without restriction, including
32 without limitation the rights to use, copy, modify, merge, publish,
33 distribute, sublicense, and/or sell copies of the Software, and to
34 permit persons to whom the Software is furnished to do so, subject to
35 the following conditions:
36
37 The above copyright notice and this permission notice (including the
38 next paragraph) shall be included in all copies or substantial
39 portions of the Software.
40
41 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
42 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
43 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
44 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
45 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
46 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
47 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
48 */
49
50
51 enum a4xx_color_fmt {
52 RB4_A8_UNORM = 1,
53 RB4_R8_UNORM = 2,
54 RB4_R8_SNORM = 3,
55 RB4_R8_UINT = 4,
56 RB4_R8_SINT = 5,
57 RB4_R4G4B4A4_UNORM = 8,
58 RB4_R5G5B5A1_UNORM = 10,
59 RB4_R5G6B5_UNORM = 14,
60 RB4_R8G8_UNORM = 15,
61 RB4_R8G8_SNORM = 16,
62 RB4_R8G8_UINT = 17,
63 RB4_R8G8_SINT = 18,
64 RB4_R16_UNORM = 19,
65 RB4_R16_SNORM = 20,
66 RB4_R16_FLOAT = 21,
67 RB4_R16_UINT = 22,
68 RB4_R16_SINT = 23,
69 RB4_R8G8B8_UNORM = 25,
70 RB4_R8G8B8A8_UNORM = 26,
71 RB4_R8G8B8A8_SNORM = 28,
72 RB4_R8G8B8A8_UINT = 29,
73 RB4_R8G8B8A8_SINT = 30,
74 RB4_R10G10B10A2_UNORM = 31,
75 RB4_R10G10B10A2_UINT = 34,
76 RB4_R11G11B10_FLOAT = 39,
77 RB4_R16G16_UNORM = 40,
78 RB4_R16G16_SNORM = 41,
79 RB4_R16G16_FLOAT = 42,
80 RB4_R16G16_UINT = 43,
81 RB4_R16G16_SINT = 44,
82 RB4_R32_FLOAT = 45,
83 RB4_R32_UINT = 46,
84 RB4_R32_SINT = 47,
85 RB4_R16G16B16A16_UNORM = 52,
86 RB4_R16G16B16A16_SNORM = 53,
87 RB4_R16G16B16A16_FLOAT = 54,
88 RB4_R16G16B16A16_UINT = 55,
89 RB4_R16G16B16A16_SINT = 56,
90 RB4_R32G32_FLOAT = 57,
91 RB4_R32G32_UINT = 58,
92 RB4_R32G32_SINT = 59,
93 RB4_R32G32B32A32_FLOAT = 60,
94 RB4_R32G32B32A32_UINT = 61,
95 RB4_R32G32B32A32_SINT = 62,
96 RB4_NONE = 255,
97 };
98
99 enum a4xx_tile_mode {
100 TILE4_LINEAR = 0,
101 TILE4_2 = 2,
102 TILE4_3 = 3,
103 };
104
105 enum a4xx_vtx_fmt {
106 VFMT4_32_FLOAT = 1,
107 VFMT4_32_32_FLOAT = 2,
108 VFMT4_32_32_32_FLOAT = 3,
109 VFMT4_32_32_32_32_FLOAT = 4,
110 VFMT4_16_FLOAT = 5,
111 VFMT4_16_16_FLOAT = 6,
112 VFMT4_16_16_16_FLOAT = 7,
113 VFMT4_16_16_16_16_FLOAT = 8,
114 VFMT4_32_FIXED = 9,
115 VFMT4_32_32_FIXED = 10,
116 VFMT4_32_32_32_FIXED = 11,
117 VFMT4_32_32_32_32_FIXED = 12,
118 VFMT4_11_11_10_FLOAT = 13,
119 VFMT4_16_SINT = 16,
120 VFMT4_16_16_SINT = 17,
121 VFMT4_16_16_16_SINT = 18,
122 VFMT4_16_16_16_16_SINT = 19,
123 VFMT4_16_UINT = 20,
124 VFMT4_16_16_UINT = 21,
125 VFMT4_16_16_16_UINT = 22,
126 VFMT4_16_16_16_16_UINT = 23,
127 VFMT4_16_SNORM = 24,
128 VFMT4_16_16_SNORM = 25,
129 VFMT4_16_16_16_SNORM = 26,
130 VFMT4_16_16_16_16_SNORM = 27,
131 VFMT4_16_UNORM = 28,
132 VFMT4_16_16_UNORM = 29,
133 VFMT4_16_16_16_UNORM = 30,
134 VFMT4_16_16_16_16_UNORM = 31,
135 VFMT4_32_UINT = 32,
136 VFMT4_32_32_UINT = 33,
137 VFMT4_32_32_32_UINT = 34,
138 VFMT4_32_32_32_32_UINT = 35,
139 VFMT4_32_SINT = 36,
140 VFMT4_32_32_SINT = 37,
141 VFMT4_32_32_32_SINT = 38,
142 VFMT4_32_32_32_32_SINT = 39,
143 VFMT4_8_UINT = 40,
144 VFMT4_8_8_UINT = 41,
145 VFMT4_8_8_8_UINT = 42,
146 VFMT4_8_8_8_8_UINT = 43,
147 VFMT4_8_UNORM = 44,
148 VFMT4_8_8_UNORM = 45,
149 VFMT4_8_8_8_UNORM = 46,
150 VFMT4_8_8_8_8_UNORM = 47,
151 VFMT4_8_SINT = 48,
152 VFMT4_8_8_SINT = 49,
153 VFMT4_8_8_8_SINT = 50,
154 VFMT4_8_8_8_8_SINT = 51,
155 VFMT4_8_SNORM = 52,
156 VFMT4_8_8_SNORM = 53,
157 VFMT4_8_8_8_SNORM = 54,
158 VFMT4_8_8_8_8_SNORM = 55,
159 VFMT4_10_10_10_2_UINT = 56,
160 VFMT4_10_10_10_2_UNORM = 57,
161 VFMT4_10_10_10_2_SINT = 58,
162 VFMT4_10_10_10_2_SNORM = 59,
163 VFMT4_2_10_10_10_UINT = 60,
164 VFMT4_2_10_10_10_UNORM = 61,
165 VFMT4_2_10_10_10_SINT = 62,
166 VFMT4_2_10_10_10_SNORM = 63,
167 VFMT4_NONE = 255,
168 };
169
170 enum a4xx_tex_fmt {
171 TFMT4_A8_UNORM = 3,
172 TFMT4_8_UNORM = 4,
173 TFMT4_8_SNORM = 5,
174 TFMT4_8_UINT = 6,
175 TFMT4_8_SINT = 7,
176 TFMT4_4_4_4_4_UNORM = 8,
177 TFMT4_5_5_5_1_UNORM = 9,
178 TFMT4_5_6_5_UNORM = 11,
179 TFMT4_L8_A8_UNORM = 13,
180 TFMT4_8_8_UNORM = 14,
181 TFMT4_8_8_SNORM = 15,
182 TFMT4_8_8_UINT = 16,
183 TFMT4_8_8_SINT = 17,
184 TFMT4_16_UNORM = 18,
185 TFMT4_16_SNORM = 19,
186 TFMT4_16_FLOAT = 20,
187 TFMT4_16_UINT = 21,
188 TFMT4_16_SINT = 22,
189 TFMT4_8_8_8_8_UNORM = 28,
190 TFMT4_8_8_8_8_SNORM = 29,
191 TFMT4_8_8_8_8_UINT = 30,
192 TFMT4_8_8_8_8_SINT = 31,
193 TFMT4_9_9_9_E5_FLOAT = 32,
194 TFMT4_10_10_10_2_UNORM = 33,
195 TFMT4_10_10_10_2_UINT = 34,
196 TFMT4_11_11_10_FLOAT = 37,
197 TFMT4_16_16_UNORM = 38,
198 TFMT4_16_16_SNORM = 39,
199 TFMT4_16_16_FLOAT = 40,
200 TFMT4_16_16_UINT = 41,
201 TFMT4_16_16_SINT = 42,
202 TFMT4_32_FLOAT = 43,
203 TFMT4_32_UINT = 44,
204 TFMT4_32_SINT = 45,
205 TFMT4_16_16_16_16_UNORM = 51,
206 TFMT4_16_16_16_16_SNORM = 52,
207 TFMT4_16_16_16_16_FLOAT = 53,
208 TFMT4_16_16_16_16_UINT = 54,
209 TFMT4_16_16_16_16_SINT = 55,
210 TFMT4_32_32_FLOAT = 56,
211 TFMT4_32_32_UINT = 57,
212 TFMT4_32_32_SINT = 58,
213 TFMT4_32_32_32_FLOAT = 59,
214 TFMT4_32_32_32_UINT = 60,
215 TFMT4_32_32_32_SINT = 61,
216 TFMT4_32_32_32_32_FLOAT = 63,
217 TFMT4_32_32_32_32_UINT = 64,
218 TFMT4_32_32_32_32_SINT = 65,
219 TFMT4_X8Z24_UNORM = 71,
220 TFMT4_DXT1 = 86,
221 TFMT4_DXT3 = 87,
222 TFMT4_DXT5 = 88,
223 TFMT4_RGTC1_UNORM = 90,
224 TFMT4_RGTC1_SNORM = 91,
225 TFMT4_RGTC2_UNORM = 94,
226 TFMT4_RGTC2_SNORM = 95,
227 TFMT4_BPTC_UFLOAT = 97,
228 TFMT4_BPTC_FLOAT = 98,
229 TFMT4_BPTC = 99,
230 TFMT4_ATC_RGB = 100,
231 TFMT4_ATC_RGBA_EXPLICIT = 101,
232 TFMT4_ATC_RGBA_INTERPOLATED = 102,
233 TFMT4_ETC2_RG11_UNORM = 103,
234 TFMT4_ETC2_RG11_SNORM = 104,
235 TFMT4_ETC2_R11_UNORM = 105,
236 TFMT4_ETC2_R11_SNORM = 106,
237 TFMT4_ETC1 = 107,
238 TFMT4_ETC2_RGB8 = 108,
239 TFMT4_ETC2_RGBA8 = 109,
240 TFMT4_ETC2_RGB8A1 = 110,
241 TFMT4_ASTC_4x4 = 111,
242 TFMT4_ASTC_5x4 = 112,
243 TFMT4_ASTC_5x5 = 113,
244 TFMT4_ASTC_6x5 = 114,
245 TFMT4_ASTC_6x6 = 115,
246 TFMT4_ASTC_8x5 = 116,
247 TFMT4_ASTC_8x6 = 117,
248 TFMT4_ASTC_8x8 = 118,
249 TFMT4_ASTC_10x5 = 119,
250 TFMT4_ASTC_10x6 = 120,
251 TFMT4_ASTC_10x8 = 121,
252 TFMT4_ASTC_10x10 = 122,
253 TFMT4_ASTC_12x10 = 123,
254 TFMT4_ASTC_12x12 = 124,
255 TFMT4_NONE = 255,
256 };
257
258 enum a4xx_depth_format {
259 DEPTH4_NONE = 0,
260 DEPTH4_16 = 1,
261 DEPTH4_24_8 = 2,
262 DEPTH4_32 = 3,
263 };
264
265 enum a4xx_ccu_perfcounter_select {
266 CCU_BUSY_CYCLES = 0,
267 CCU_RB_DEPTH_RETURN_STALL = 2,
268 CCU_RB_COLOR_RETURN_STALL = 3,
269 CCU_DEPTH_BLOCKS = 6,
270 CCU_COLOR_BLOCKS = 7,
271 CCU_DEPTH_BLOCK_HIT = 8,
272 CCU_COLOR_BLOCK_HIT = 9,
273 CCU_DEPTH_FLAG1_COUNT = 10,
274 CCU_DEPTH_FLAG2_COUNT = 11,
275 CCU_DEPTH_FLAG3_COUNT = 12,
276 CCU_DEPTH_FLAG4_COUNT = 13,
277 CCU_COLOR_FLAG1_COUNT = 14,
278 CCU_COLOR_FLAG2_COUNT = 15,
279 CCU_COLOR_FLAG3_COUNT = 16,
280 CCU_COLOR_FLAG4_COUNT = 17,
281 CCU_PARTIAL_BLOCK_READ = 18,
282 };
283
284 enum a4xx_cp_perfcounter_select {
285 CP_ALWAYS_COUNT = 0,
286 CP_BUSY = 1,
287 CP_PFP_IDLE = 2,
288 CP_PFP_BUSY_WORKING = 3,
289 CP_PFP_STALL_CYCLES_ANY = 4,
290 CP_PFP_STARVE_CYCLES_ANY = 5,
291 CP_PFP_STARVED_PER_LOAD_ADDR = 6,
292 CP_PFP_STALLED_PER_STORE_ADDR = 7,
293 CP_PFP_PC_PROFILE = 8,
294 CP_PFP_MATCH_PM4_PKT_PROFILE = 9,
295 CP_PFP_COND_INDIRECT_DISCARDED = 10,
296 CP_LONG_RESUMPTIONS = 11,
297 CP_RESUME_CYCLES = 12,
298 CP_RESUME_TO_BOUNDARY_CYCLES = 13,
299 CP_LONG_PREEMPTIONS = 14,
300 CP_PREEMPT_CYCLES = 15,
301 CP_PREEMPT_TO_BOUNDARY_CYCLES = 16,
302 CP_ME_FIFO_EMPTY_PFP_IDLE = 17,
303 CP_ME_FIFO_EMPTY_PFP_BUSY = 18,
304 CP_ME_FIFO_NOT_EMPTY_NOT_FULL = 19,
305 CP_ME_FIFO_FULL_ME_BUSY = 20,
306 CP_ME_FIFO_FULL_ME_NON_WORKING = 21,
307 CP_ME_WAITING_FOR_PACKETS = 22,
308 CP_ME_BUSY_WORKING = 23,
309 CP_ME_STARVE_CYCLES_ANY = 24,
310 CP_ME_STARVE_CYCLES_PER_PROFILE = 25,
311 CP_ME_STALL_CYCLES_PER_PROFILE = 26,
312 CP_ME_PC_PROFILE = 27,
313 CP_RCIU_FIFO_EMPTY = 28,
314 CP_RCIU_FIFO_NOT_EMPTY_NOT_FULL = 29,
315 CP_RCIU_FIFO_FULL = 30,
316 CP_RCIU_FIFO_FULL_NO_CONTEXT = 31,
317 CP_RCIU_FIFO_FULL_AHB_MASTER = 32,
318 CP_RCIU_FIFO_FULL_OTHER = 33,
319 CP_AHB_IDLE = 34,
320 CP_AHB_STALL_ON_GRANT_NO_SPLIT = 35,
321 CP_AHB_STALL_ON_GRANT_SPLIT = 36,
322 CP_AHB_STALL_ON_GRANT_SPLIT_PROFILE = 37,
323 CP_AHB_BUSY_WORKING = 38,
324 CP_AHB_BUSY_STALL_ON_HRDY = 39,
325 CP_AHB_BUSY_STALL_ON_HRDY_PROFILE = 40,
326 };
327
328 enum a4xx_gras_ras_perfcounter_select {
329 RAS_SUPER_TILES = 0,
330 RAS_8X8_TILES = 1,
331 RAS_4X4_TILES = 2,
332 RAS_BUSY_CYCLES = 3,
333 RAS_STALL_CYCLES_BY_RB = 4,
334 RAS_STALL_CYCLES_BY_VSC = 5,
335 RAS_STARVE_CYCLES_BY_TSE = 6,
336 RAS_SUPERTILE_CYCLES = 7,
337 RAS_TILE_CYCLES = 8,
338 RAS_FULLY_COVERED_SUPER_TILES = 9,
339 RAS_FULLY_COVERED_8X8_TILES = 10,
340 RAS_4X4_PRIM = 11,
341 RAS_8X4_4X8_PRIM = 12,
342 RAS_8X8_PRIM = 13,
343 };
344
345 enum a4xx_gras_tse_perfcounter_select {
346 TSE_INPUT_PRIM = 0,
347 TSE_INPUT_NULL_PRIM = 1,
348 TSE_TRIVAL_REJ_PRIM = 2,
349 TSE_CLIPPED_PRIM = 3,
350 TSE_NEW_PRIM = 4,
351 TSE_ZERO_AREA_PRIM = 5,
352 TSE_FACENESS_CULLED_PRIM = 6,
353 TSE_ZERO_PIXEL_PRIM = 7,
354 TSE_OUTPUT_NULL_PRIM = 8,
355 TSE_OUTPUT_VISIBLE_PRIM = 9,
356 TSE_PRE_CLIP_PRIM = 10,
357 TSE_POST_CLIP_PRIM = 11,
358 TSE_BUSY_CYCLES = 12,
359 TSE_PC_STARVE = 13,
360 TSE_RAS_STALL = 14,
361 TSE_STALL_BARYPLANE_FIFO_FULL = 15,
362 TSE_STALL_ZPLANE_FIFO_FULL = 16,
363 };
364
365 enum a4xx_hlsq_perfcounter_select {
366 HLSQ_SP_VS_STAGE_CONSTANT = 0,
367 HLSQ_SP_VS_STAGE_INSTRUCTIONS = 1,
368 HLSQ_SP_FS_STAGE_CONSTANT = 2,
369 HLSQ_SP_FS_STAGE_INSTRUCTIONS = 3,
370 HLSQ_TP_STATE = 4,
371 HLSQ_QUADS = 5,
372 HLSQ_PIXELS = 6,
373 HLSQ_VERTICES = 7,
374 HLSQ_SP_VS_STAGE_DATA_BYTES = 13,
375 HLSQ_SP_FS_STAGE_DATA_BYTES = 14,
376 HLSQ_BUSY_CYCLES = 15,
377 HLSQ_STALL_CYCLES_SP_STATE = 16,
378 HLSQ_STALL_CYCLES_SP_VS_STAGE = 17,
379 HLSQ_STALL_CYCLES_SP_FS_STAGE = 18,
380 HLSQ_STALL_CYCLES_UCHE = 19,
381 HLSQ_RBBM_LOAD_CYCLES = 20,
382 HLSQ_DI_TO_VS_START_SP = 21,
383 HLSQ_DI_TO_FS_START_SP = 22,
384 HLSQ_VS_STAGE_START_TO_DONE_SP = 23,
385 HLSQ_FS_STAGE_START_TO_DONE_SP = 24,
386 HLSQ_SP_STATE_COPY_CYCLES_VS_STAGE = 25,
387 HLSQ_SP_STATE_COPY_CYCLES_FS_STAGE = 26,
388 HLSQ_UCHE_LATENCY_CYCLES = 27,
389 HLSQ_UCHE_LATENCY_COUNT = 28,
390 HLSQ_STARVE_CYCLES_VFD = 29,
391 };
392
393 enum a4xx_pc_perfcounter_select {
394 PC_VIS_STREAMS_LOADED = 0,
395 PC_VPC_PRIMITIVES = 2,
396 PC_DEAD_PRIM = 3,
397 PC_LIVE_PRIM = 4,
398 PC_DEAD_DRAWCALLS = 5,
399 PC_LIVE_DRAWCALLS = 6,
400 PC_VERTEX_MISSES = 7,
401 PC_STALL_CYCLES_VFD = 9,
402 PC_STALL_CYCLES_TSE = 10,
403 PC_STALL_CYCLES_UCHE = 11,
404 PC_WORKING_CYCLES = 12,
405 PC_IA_VERTICES = 13,
406 PC_GS_PRIMITIVES = 14,
407 PC_HS_INVOCATIONS = 15,
408 PC_DS_INVOCATIONS = 16,
409 PC_DS_PRIMITIVES = 17,
410 PC_STARVE_CYCLES_FOR_INDEX = 20,
411 PC_STARVE_CYCLES_FOR_TESS_FACTOR = 21,
412 PC_STARVE_CYCLES_FOR_VIZ_STREAM = 22,
413 PC_STALL_CYCLES_TESS = 23,
414 PC_STARVE_CYCLES_FOR_POSITION = 24,
415 PC_MODE0_DRAWCALL = 25,
416 PC_MODE1_DRAWCALL = 26,
417 PC_MODE2_DRAWCALL = 27,
418 PC_MODE3_DRAWCALL = 28,
419 PC_MODE4_DRAWCALL = 29,
420 PC_PREDICATED_DEAD_DRAWCALL = 30,
421 PC_STALL_CYCLES_BY_TSE_ONLY = 31,
422 PC_STALL_CYCLES_BY_VPC_ONLY = 32,
423 PC_VPC_POS_DATA_TRANSACTION = 33,
424 PC_BUSY_CYCLES = 34,
425 PC_STARVE_CYCLES_DI = 35,
426 PC_STALL_CYCLES_VPC = 36,
427 TESS_WORKING_CYCLES = 37,
428 TESS_NUM_CYCLES_SETUP_WORKING = 38,
429 TESS_NUM_CYCLES_PTGEN_WORKING = 39,
430 TESS_NUM_CYCLES_CONNGEN_WORKING = 40,
431 TESS_BUSY_CYCLES = 41,
432 TESS_STARVE_CYCLES_PC = 42,
433 TESS_STALL_CYCLES_PC = 43,
434 };
435
436 enum a4xx_pwr_perfcounter_select {
437 PWR_CORE_CLOCK_CYCLES = 0,
438 PWR_BUSY_CLOCK_CYCLES = 1,
439 };
440
441 enum a4xx_rb_perfcounter_select {
442 RB_BUSY_CYCLES = 0,
443 RB_BUSY_CYCLES_BINNING = 1,
444 RB_BUSY_CYCLES_RENDERING = 2,
445 RB_BUSY_CYCLES_RESOLVE = 3,
446 RB_STARVE_CYCLES_BY_SP = 4,
447 RB_STARVE_CYCLES_BY_RAS = 5,
448 RB_STARVE_CYCLES_BY_MARB = 6,
449 RB_STALL_CYCLES_BY_MARB = 7,
450 RB_STALL_CYCLES_BY_HLSQ = 8,
451 RB_RB_RB_MARB_DATA = 9,
452 RB_SP_RB_QUAD = 10,
453 RB_RAS_RB_Z_QUADS = 11,
454 RB_GMEM_CH0_READ = 12,
455 RB_GMEM_CH1_READ = 13,
456 RB_GMEM_CH0_WRITE = 14,
457 RB_GMEM_CH1_WRITE = 15,
458 RB_CP_CONTEXT_DONE = 16,
459 RB_CP_CACHE_FLUSH = 17,
460 RB_CP_ZPASS_DONE = 18,
461 RB_STALL_FIFO0_FULL = 19,
462 RB_STALL_FIFO1_FULL = 20,
463 RB_STALL_FIFO2_FULL = 21,
464 RB_STALL_FIFO3_FULL = 22,
465 RB_RB_HLSQ_TRANSACTIONS = 23,
466 RB_Z_READ = 24,
467 RB_Z_WRITE = 25,
468 RB_C_READ = 26,
469 RB_C_WRITE = 27,
470 RB_C_READ_LATENCY = 28,
471 RB_Z_READ_LATENCY = 29,
472 RB_STALL_BY_UCHE = 30,
473 RB_MARB_UCHE_TRANSACTIONS = 31,
474 RB_CACHE_STALL_MISS = 32,
475 RB_CACHE_STALL_FIFO_FULL = 33,
476 RB_8BIT_BLENDER_UNITS_ACTIVE = 34,
477 RB_16BIT_BLENDER_UNITS_ACTIVE = 35,
478 RB_SAMPLER_UNITS_ACTIVE = 36,
479 RB_TOTAL_PASS = 38,
480 RB_Z_PASS = 39,
481 RB_Z_FAIL = 40,
482 RB_S_FAIL = 41,
483 RB_POWER0 = 42,
484 RB_POWER1 = 43,
485 RB_POWER2 = 44,
486 RB_POWER3 = 45,
487 RB_POWER4 = 46,
488 RB_POWER5 = 47,
489 RB_POWER6 = 48,
490 RB_POWER7 = 49,
491 };
492
493 enum a4xx_rbbm_perfcounter_select {
494 RBBM_ALWAYS_ON = 0,
495 RBBM_VBIF_BUSY = 1,
496 RBBM_TSE_BUSY = 2,
497 RBBM_RAS_BUSY = 3,
498 RBBM_PC_DCALL_BUSY = 4,
499 RBBM_PC_VSD_BUSY = 5,
500 RBBM_VFD_BUSY = 6,
501 RBBM_VPC_BUSY = 7,
502 RBBM_UCHE_BUSY = 8,
503 RBBM_VSC_BUSY = 9,
504 RBBM_HLSQ_BUSY = 10,
505 RBBM_ANY_RB_BUSY = 11,
506 RBBM_ANY_TPL1_BUSY = 12,
507 RBBM_ANY_SP_BUSY = 13,
508 RBBM_ANY_MARB_BUSY = 14,
509 RBBM_ANY_ARB_BUSY = 15,
510 RBBM_AHB_STATUS_BUSY = 16,
511 RBBM_AHB_STATUS_STALLED = 17,
512 RBBM_AHB_STATUS_TXFR = 18,
513 RBBM_AHB_STATUS_TXFR_SPLIT = 19,
514 RBBM_AHB_STATUS_TXFR_ERROR = 20,
515 RBBM_AHB_STATUS_LONG_STALL = 21,
516 RBBM_STATUS_MASKED = 22,
517 RBBM_CP_BUSY_GFX_CORE_IDLE = 23,
518 RBBM_TESS_BUSY = 24,
519 RBBM_COM_BUSY = 25,
520 RBBM_DCOM_BUSY = 32,
521 RBBM_ANY_CCU_BUSY = 33,
522 RBBM_DPM_BUSY = 34,
523 };
524
525 enum a4xx_sp_perfcounter_select {
526 SP_LM_LOAD_INSTRUCTIONS = 0,
527 SP_LM_STORE_INSTRUCTIONS = 1,
528 SP_LM_ATOMICS = 2,
529 SP_GM_LOAD_INSTRUCTIONS = 3,
530 SP_GM_STORE_INSTRUCTIONS = 4,
531 SP_GM_ATOMICS = 5,
532 SP_VS_STAGE_TEX_INSTRUCTIONS = 6,
533 SP_VS_STAGE_CFLOW_INSTRUCTIONS = 7,
534 SP_VS_STAGE_EFU_INSTRUCTIONS = 8,
535 SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 9,
536 SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 10,
537 SP_FS_STAGE_TEX_INSTRUCTIONS = 11,
538 SP_FS_STAGE_CFLOW_INSTRUCTIONS = 12,
539 SP_FS_STAGE_EFU_INSTRUCTIONS = 13,
540 SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 14,
541 SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 15,
542 SP_VS_INSTRUCTIONS = 17,
543 SP_FS_INSTRUCTIONS = 18,
544 SP_ADDR_LOCK_COUNT = 19,
545 SP_UCHE_READ_TRANS = 20,
546 SP_UCHE_WRITE_TRANS = 21,
547 SP_EXPORT_VPC_TRANS = 22,
548 SP_EXPORT_RB_TRANS = 23,
549 SP_PIXELS_KILLED = 24,
550 SP_ICL1_REQUESTS = 25,
551 SP_ICL1_MISSES = 26,
552 SP_ICL0_REQUESTS = 27,
553 SP_ICL0_MISSES = 28,
554 SP_ALU_WORKING_CYCLES = 29,
555 SP_EFU_WORKING_CYCLES = 30,
556 SP_STALL_CYCLES_BY_VPC = 31,
557 SP_STALL_CYCLES_BY_TP = 32,
558 SP_STALL_CYCLES_BY_UCHE = 33,
559 SP_STALL_CYCLES_BY_RB = 34,
560 SP_BUSY_CYCLES = 35,
561 SP_HS_INSTRUCTIONS = 36,
562 SP_DS_INSTRUCTIONS = 37,
563 SP_GS_INSTRUCTIONS = 38,
564 SP_CS_INSTRUCTIONS = 39,
565 SP_SCHEDULER_NON_WORKING = 40,
566 SP_WAVE_CONTEXTS = 41,
567 SP_WAVE_CONTEXT_CYCLES = 42,
568 SP_POWER0 = 43,
569 SP_POWER1 = 44,
570 SP_POWER2 = 45,
571 SP_POWER3 = 46,
572 SP_POWER4 = 47,
573 SP_POWER5 = 48,
574 SP_POWER6 = 49,
575 SP_POWER7 = 50,
576 SP_POWER8 = 51,
577 SP_POWER9 = 52,
578 SP_POWER10 = 53,
579 SP_POWER11 = 54,
580 SP_POWER12 = 55,
581 SP_POWER13 = 56,
582 SP_POWER14 = 57,
583 SP_POWER15 = 58,
584 };
585
586 enum a4xx_tp_perfcounter_select {
587 TP_L1_REQUESTS = 0,
588 TP_L1_MISSES = 1,
589 TP_QUADS_OFFSET = 8,
590 TP_QUAD_SHADOW = 9,
591 TP_QUADS_ARRAY = 10,
592 TP_QUADS_GRADIENT = 11,
593 TP_QUADS_1D2D = 12,
594 TP_QUADS_3DCUBE = 13,
595 TP_BUSY_CYCLES = 16,
596 TP_STALL_CYCLES_BY_ARB = 17,
597 TP_STATE_CACHE_REQUESTS = 20,
598 TP_STATE_CACHE_MISSES = 21,
599 TP_POWER0 = 22,
600 TP_POWER1 = 23,
601 TP_POWER2 = 24,
602 TP_POWER3 = 25,
603 TP_POWER4 = 26,
604 TP_POWER5 = 27,
605 TP_POWER6 = 28,
606 TP_POWER7 = 29,
607 };
608
609 enum a4xx_uche_perfcounter_select {
610 UCHE_VBIF_READ_BEATS_TP = 0,
611 UCHE_VBIF_READ_BEATS_VFD = 1,
612 UCHE_VBIF_READ_BEATS_HLSQ = 2,
613 UCHE_VBIF_READ_BEATS_MARB = 3,
614 UCHE_VBIF_READ_BEATS_SP = 4,
615 UCHE_READ_REQUESTS_TP = 5,
616 UCHE_READ_REQUESTS_VFD = 6,
617 UCHE_READ_REQUESTS_HLSQ = 7,
618 UCHE_READ_REQUESTS_MARB = 8,
619 UCHE_READ_REQUESTS_SP = 9,
620 UCHE_WRITE_REQUESTS_MARB = 10,
621 UCHE_WRITE_REQUESTS_SP = 11,
622 UCHE_TAG_CHECK_FAILS = 12,
623 UCHE_EVICTS = 13,
624 UCHE_FLUSHES = 14,
625 UCHE_VBIF_LATENCY_CYCLES = 15,
626 UCHE_VBIF_LATENCY_SAMPLES = 16,
627 UCHE_BUSY_CYCLES = 17,
628 UCHE_VBIF_READ_BEATS_PC = 18,
629 UCHE_READ_REQUESTS_PC = 19,
630 UCHE_WRITE_REQUESTS_VPC = 20,
631 UCHE_STALL_BY_VBIF = 21,
632 UCHE_WRITE_REQUESTS_VSC = 22,
633 UCHE_POWER0 = 23,
634 UCHE_POWER1 = 24,
635 UCHE_POWER2 = 25,
636 UCHE_POWER3 = 26,
637 UCHE_POWER4 = 27,
638 UCHE_POWER5 = 28,
639 UCHE_POWER6 = 29,
640 UCHE_POWER7 = 30,
641 };
642
643 enum a4xx_vbif_perfcounter_select {
644 AXI_READ_REQUESTS_ID_0 = 0,
645 AXI_READ_REQUESTS_ID_1 = 1,
646 AXI_READ_REQUESTS_ID_2 = 2,
647 AXI_READ_REQUESTS_ID_3 = 3,
648 AXI_READ_REQUESTS_ID_4 = 4,
649 AXI_READ_REQUESTS_ID_5 = 5,
650 AXI_READ_REQUESTS_ID_6 = 6,
651 AXI_READ_REQUESTS_ID_7 = 7,
652 AXI_READ_REQUESTS_ID_8 = 8,
653 AXI_READ_REQUESTS_ID_9 = 9,
654 AXI_READ_REQUESTS_ID_10 = 10,
655 AXI_READ_REQUESTS_ID_11 = 11,
656 AXI_READ_REQUESTS_ID_12 = 12,
657 AXI_READ_REQUESTS_ID_13 = 13,
658 AXI_READ_REQUESTS_ID_14 = 14,
659 AXI_READ_REQUESTS_ID_15 = 15,
660 AXI0_READ_REQUESTS_TOTAL = 16,
661 AXI1_READ_REQUESTS_TOTAL = 17,
662 AXI2_READ_REQUESTS_TOTAL = 18,
663 AXI3_READ_REQUESTS_TOTAL = 19,
664 AXI_READ_REQUESTS_TOTAL = 20,
665 AXI_WRITE_REQUESTS_ID_0 = 21,
666 AXI_WRITE_REQUESTS_ID_1 = 22,
667 AXI_WRITE_REQUESTS_ID_2 = 23,
668 AXI_WRITE_REQUESTS_ID_3 = 24,
669 AXI_WRITE_REQUESTS_ID_4 = 25,
670 AXI_WRITE_REQUESTS_ID_5 = 26,
671 AXI_WRITE_REQUESTS_ID_6 = 27,
672 AXI_WRITE_REQUESTS_ID_7 = 28,
673 AXI_WRITE_REQUESTS_ID_8 = 29,
674 AXI_WRITE_REQUESTS_ID_9 = 30,
675 AXI_WRITE_REQUESTS_ID_10 = 31,
676 AXI_WRITE_REQUESTS_ID_11 = 32,
677 AXI_WRITE_REQUESTS_ID_12 = 33,
678 AXI_WRITE_REQUESTS_ID_13 = 34,
679 AXI_WRITE_REQUESTS_ID_14 = 35,
680 AXI_WRITE_REQUESTS_ID_15 = 36,
681 AXI0_WRITE_REQUESTS_TOTAL = 37,
682 AXI1_WRITE_REQUESTS_TOTAL = 38,
683 AXI2_WRITE_REQUESTS_TOTAL = 39,
684 AXI3_WRITE_REQUESTS_TOTAL = 40,
685 AXI_WRITE_REQUESTS_TOTAL = 41,
686 AXI_TOTAL_REQUESTS = 42,
687 AXI_READ_DATA_BEATS_ID_0 = 43,
688 AXI_READ_DATA_BEATS_ID_1 = 44,
689 AXI_READ_DATA_BEATS_ID_2 = 45,
690 AXI_READ_DATA_BEATS_ID_3 = 46,
691 AXI_READ_DATA_BEATS_ID_4 = 47,
692 AXI_READ_DATA_BEATS_ID_5 = 48,
693 AXI_READ_DATA_BEATS_ID_6 = 49,
694 AXI_READ_DATA_BEATS_ID_7 = 50,
695 AXI_READ_DATA_BEATS_ID_8 = 51,
696 AXI_READ_DATA_BEATS_ID_9 = 52,
697 AXI_READ_DATA_BEATS_ID_10 = 53,
698 AXI_READ_DATA_BEATS_ID_11 = 54,
699 AXI_READ_DATA_BEATS_ID_12 = 55,
700 AXI_READ_DATA_BEATS_ID_13 = 56,
701 AXI_READ_DATA_BEATS_ID_14 = 57,
702 AXI_READ_DATA_BEATS_ID_15 = 58,
703 AXI0_READ_DATA_BEATS_TOTAL = 59,
704 AXI1_READ_DATA_BEATS_TOTAL = 60,
705 AXI2_READ_DATA_BEATS_TOTAL = 61,
706 AXI3_READ_DATA_BEATS_TOTAL = 62,
707 AXI_READ_DATA_BEATS_TOTAL = 63,
708 AXI_WRITE_DATA_BEATS_ID_0 = 64,
709 AXI_WRITE_DATA_BEATS_ID_1 = 65,
710 AXI_WRITE_DATA_BEATS_ID_2 = 66,
711 AXI_WRITE_DATA_BEATS_ID_3 = 67,
712 AXI_WRITE_DATA_BEATS_ID_4 = 68,
713 AXI_WRITE_DATA_BEATS_ID_5 = 69,
714 AXI_WRITE_DATA_BEATS_ID_6 = 70,
715 AXI_WRITE_DATA_BEATS_ID_7 = 71,
716 AXI_WRITE_DATA_BEATS_ID_8 = 72,
717 AXI_WRITE_DATA_BEATS_ID_9 = 73,
718 AXI_WRITE_DATA_BEATS_ID_10 = 74,
719 AXI_WRITE_DATA_BEATS_ID_11 = 75,
720 AXI_WRITE_DATA_BEATS_ID_12 = 76,
721 AXI_WRITE_DATA_BEATS_ID_13 = 77,
722 AXI_WRITE_DATA_BEATS_ID_14 = 78,
723 AXI_WRITE_DATA_BEATS_ID_15 = 79,
724 AXI0_WRITE_DATA_BEATS_TOTAL = 80,
725 AXI1_WRITE_DATA_BEATS_TOTAL = 81,
726 AXI2_WRITE_DATA_BEATS_TOTAL = 82,
727 AXI3_WRITE_DATA_BEATS_TOTAL = 83,
728 AXI_WRITE_DATA_BEATS_TOTAL = 84,
729 AXI_DATA_BEATS_TOTAL = 85,
730 CYCLES_HELD_OFF_ID_0 = 86,
731 CYCLES_HELD_OFF_ID_1 = 87,
732 CYCLES_HELD_OFF_ID_2 = 88,
733 CYCLES_HELD_OFF_ID_3 = 89,
734 CYCLES_HELD_OFF_ID_4 = 90,
735 CYCLES_HELD_OFF_ID_5 = 91,
736 CYCLES_HELD_OFF_ID_6 = 92,
737 CYCLES_HELD_OFF_ID_7 = 93,
738 CYCLES_HELD_OFF_ID_8 = 94,
739 CYCLES_HELD_OFF_ID_9 = 95,
740 CYCLES_HELD_OFF_ID_10 = 96,
741 CYCLES_HELD_OFF_ID_11 = 97,
742 CYCLES_HELD_OFF_ID_12 = 98,
743 CYCLES_HELD_OFF_ID_13 = 99,
744 CYCLES_HELD_OFF_ID_14 = 100,
745 CYCLES_HELD_OFF_ID_15 = 101,
746 AXI_READ_REQUEST_HELD_OFF = 102,
747 AXI_WRITE_REQUEST_HELD_OFF = 103,
748 AXI_REQUEST_HELD_OFF = 104,
749 AXI_WRITE_DATA_HELD_OFF = 105,
750 OCMEM_AXI_READ_REQUEST_HELD_OFF = 106,
751 OCMEM_AXI_WRITE_REQUEST_HELD_OFF = 107,
752 OCMEM_AXI_REQUEST_HELD_OFF = 108,
753 OCMEM_AXI_WRITE_DATA_HELD_OFF = 109,
754 ELAPSED_CYCLES_DDR = 110,
755 ELAPSED_CYCLES_OCMEM = 111,
756 };
757
758 enum a4xx_vfd_perfcounter_select {
759 VFD_UCHE_BYTE_FETCHED = 0,
760 VFD_UCHE_TRANS = 1,
761 VFD_FETCH_INSTRUCTIONS = 3,
762 VFD_BUSY_CYCLES = 5,
763 VFD_STALL_CYCLES_UCHE = 6,
764 VFD_STALL_CYCLES_HLSQ = 7,
765 VFD_STALL_CYCLES_VPC_BYPASS = 8,
766 VFD_STALL_CYCLES_VPC_ALLOC = 9,
767 VFD_MODE_0_FIBERS = 13,
768 VFD_MODE_1_FIBERS = 14,
769 VFD_MODE_2_FIBERS = 15,
770 VFD_MODE_3_FIBERS = 16,
771 VFD_MODE_4_FIBERS = 17,
772 VFD_BFIFO_STALL = 18,
773 VFD_NUM_VERTICES_TOTAL = 19,
774 VFD_PACKER_FULL = 20,
775 VFD_UCHE_REQUEST_FIFO_FULL = 21,
776 VFD_STARVE_CYCLES_PC = 22,
777 VFD_STARVE_CYCLES_UCHE = 23,
778 };
779
780 enum a4xx_vpc_perfcounter_select {
781 VPC_SP_LM_COMPONENTS = 2,
782 VPC_SP0_LM_BYTES = 3,
783 VPC_SP1_LM_BYTES = 4,
784 VPC_SP2_LM_BYTES = 5,
785 VPC_SP3_LM_BYTES = 6,
786 VPC_WORKING_CYCLES = 7,
787 VPC_STALL_CYCLES_LM = 8,
788 VPC_STARVE_CYCLES_RAS = 9,
789 VPC_STREAMOUT_CYCLES = 10,
790 VPC_UCHE_TRANSACTIONS = 12,
791 VPC_STALL_CYCLES_UCHE = 13,
792 VPC_BUSY_CYCLES = 14,
793 VPC_STARVE_CYCLES_SP = 15,
794 };
795
796 enum a4xx_vsc_perfcounter_select {
797 VSC_BUSY_CYCLES = 0,
798 VSC_WORKING_CYCLES = 1,
799 VSC_STALL_CYCLES_UCHE = 2,
800 VSC_STARVE_CYCLES_RAS = 3,
801 VSC_EOT_NUM = 4,
802 };
803
804 enum a4xx_tex_filter {
805 A4XX_TEX_NEAREST = 0,
806 A4XX_TEX_LINEAR = 1,
807 A4XX_TEX_ANISO = 2,
808 };
809
810 enum a4xx_tex_clamp {
811 A4XX_TEX_REPEAT = 0,
812 A4XX_TEX_CLAMP_TO_EDGE = 1,
813 A4XX_TEX_MIRROR_REPEAT = 2,
814 A4XX_TEX_CLAMP_TO_BORDER = 3,
815 A4XX_TEX_MIRROR_CLAMP = 4,
816 };
817
818 enum a4xx_tex_aniso {
819 A4XX_TEX_ANISO_1 = 0,
820 A4XX_TEX_ANISO_2 = 1,
821 A4XX_TEX_ANISO_4 = 2,
822 A4XX_TEX_ANISO_8 = 3,
823 A4XX_TEX_ANISO_16 = 4,
824 };
825
826 enum a4xx_tex_swiz {
827 A4XX_TEX_X = 0,
828 A4XX_TEX_Y = 1,
829 A4XX_TEX_Z = 2,
830 A4XX_TEX_W = 3,
831 A4XX_TEX_ZERO = 4,
832 A4XX_TEX_ONE = 5,
833 };
834
835 enum a4xx_tex_type {
836 A4XX_TEX_1D = 0,
837 A4XX_TEX_2D = 1,
838 A4XX_TEX_CUBE = 2,
839 A4XX_TEX_3D = 3,
840 };
841
842 #define A4XX_CGC_HLSQ_EARLY_CYC__MASK 0x00700000
843 #define A4XX_CGC_HLSQ_EARLY_CYC__SHIFT 20
844 static inline uint32_t A4XX_CGC_HLSQ_EARLY_CYC(uint32_t val)
845 {
846 return ((val) << A4XX_CGC_HLSQ_EARLY_CYC__SHIFT) & A4XX_CGC_HLSQ_EARLY_CYC__MASK;
847 }
848 #define A4XX_INT0_RBBM_GPU_IDLE 0x00000001
849 #define A4XX_INT0_RBBM_AHB_ERROR 0x00000002
850 #define A4XX_INT0_RBBM_REG_TIMEOUT 0x00000004
851 #define A4XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008
852 #define A4XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010
853 #define A4XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00000020
854 #define A4XX_INT0_VFD_ERROR 0x00000040
855 #define A4XX_INT0_CP_SW_INT 0x00000080
856 #define A4XX_INT0_CP_T0_PACKET_IN_IB 0x00000100
857 #define A4XX_INT0_CP_OPCODE_ERROR 0x00000200
858 #define A4XX_INT0_CP_RESERVED_BIT_ERROR 0x00000400
859 #define A4XX_INT0_CP_HW_FAULT 0x00000800
860 #define A4XX_INT0_CP_DMA 0x00001000
861 #define A4XX_INT0_CP_IB2_INT 0x00002000
862 #define A4XX_INT0_CP_IB1_INT 0x00004000
863 #define A4XX_INT0_CP_RB_INT 0x00008000
864 #define A4XX_INT0_CP_REG_PROTECT_FAULT 0x00010000
865 #define A4XX_INT0_CP_RB_DONE_TS 0x00020000
866 #define A4XX_INT0_CP_VS_DONE_TS 0x00040000
867 #define A4XX_INT0_CP_PS_DONE_TS 0x00080000
868 #define A4XX_INT0_CACHE_FLUSH_TS 0x00100000
869 #define A4XX_INT0_CP_AHB_ERROR_HALT 0x00200000
870 #define A4XX_INT0_MISC_HANG_DETECT 0x01000000
871 #define A4XX_INT0_UCHE_OOB_ACCESS 0x02000000
872 #define REG_A4XX_RB_GMEM_BASE_ADDR 0x00000cc0
873
874 #define REG_A4XX_RB_PERFCTR_RB_SEL_0 0x00000cc7
875
876 #define REG_A4XX_RB_PERFCTR_RB_SEL_1 0x00000cc8
877
878 #define REG_A4XX_RB_PERFCTR_RB_SEL_2 0x00000cc9
879
880 #define REG_A4XX_RB_PERFCTR_RB_SEL_3 0x00000cca
881
882 #define REG_A4XX_RB_PERFCTR_RB_SEL_4 0x00000ccb
883
884 #define REG_A4XX_RB_PERFCTR_RB_SEL_5 0x00000ccc
885
886 #define REG_A4XX_RB_PERFCTR_RB_SEL_6 0x00000ccd
887
888 #define REG_A4XX_RB_PERFCTR_RB_SEL_7 0x00000cce
889
890 #define REG_A4XX_RB_PERFCTR_CCU_SEL_0 0x00000ccf
891
892 #define REG_A4XX_RB_PERFCTR_CCU_SEL_1 0x00000cd0
893
894 #define REG_A4XX_RB_PERFCTR_CCU_SEL_2 0x00000cd1
895
896 #define REG_A4XX_RB_PERFCTR_CCU_SEL_3 0x00000cd2
897
898 #define REG_A4XX_RB_FRAME_BUFFER_DIMENSION 0x00000ce0
899 #define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK 0x00003fff
900 #define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT 0
901 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val)
902 {
903 return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK;
904 }
905 #define A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK 0x3fff0000
906 #define A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT 16
907 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val)
908 {
909 return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK;
910 }
911
912 #define REG_A4XX_RB_CLEAR_COLOR_DW0 0x000020cc
913
914 #define REG_A4XX_RB_CLEAR_COLOR_DW1 0x000020cd
915
916 #define REG_A4XX_RB_CLEAR_COLOR_DW2 0x000020ce
917
918 #define REG_A4XX_RB_CLEAR_COLOR_DW3 0x000020cf
919
920 #define REG_A4XX_RB_MODE_CONTROL 0x000020a0
921 #define A4XX_RB_MODE_CONTROL_WIDTH__MASK 0x0000003f
922 #define A4XX_RB_MODE_CONTROL_WIDTH__SHIFT 0
923 static inline uint32_t A4XX_RB_MODE_CONTROL_WIDTH(uint32_t val)
924 {
925 return ((val >> 5) << A4XX_RB_MODE_CONTROL_WIDTH__SHIFT) & A4XX_RB_MODE_CONTROL_WIDTH__MASK;
926 }
927 #define A4XX_RB_MODE_CONTROL_HEIGHT__MASK 0x00003f00
928 #define A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT 8
929 static inline uint32_t A4XX_RB_MODE_CONTROL_HEIGHT(uint32_t val)
930 {
931 return ((val >> 5) << A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT) & A4XX_RB_MODE_CONTROL_HEIGHT__MASK;
932 }
933 #define A4XX_RB_MODE_CONTROL_ENABLE_GMEM 0x00010000
934
935 #define REG_A4XX_RB_RENDER_CONTROL 0x000020a1
936 #define A4XX_RB_RENDER_CONTROL_BINNING_PASS 0x00000001
937 #define A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE 0x00000020
938
939 #define REG_A4XX_RB_MSAA_CONTROL 0x000020a2
940 #define A4XX_RB_MSAA_CONTROL_DISABLE 0x00001000
941 #define A4XX_RB_MSAA_CONTROL_SAMPLES__MASK 0x0000e000
942 #define A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT 13
943 static inline uint32_t A4XX_RB_MSAA_CONTROL_SAMPLES(uint32_t val)
944 {
945 return ((val) << A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT) & A4XX_RB_MSAA_CONTROL_SAMPLES__MASK;
946 }
947
948 #define REG_A4XX_RB_RENDER_CONTROL2 0x000020a3
949 #define A4XX_RB_RENDER_CONTROL2_COORD_MASK__MASK 0x0000000f
950 #define A4XX_RB_RENDER_CONTROL2_COORD_MASK__SHIFT 0
951 static inline uint32_t A4XX_RB_RENDER_CONTROL2_COORD_MASK(uint32_t val)
952 {
953 return ((val) << A4XX_RB_RENDER_CONTROL2_COORD_MASK__SHIFT) & A4XX_RB_RENDER_CONTROL2_COORD_MASK__MASK;
954 }
955 #define A4XX_RB_RENDER_CONTROL2_SAMPLEMASK 0x00000010
956 #define A4XX_RB_RENDER_CONTROL2_FACENESS 0x00000020
957 #define A4XX_RB_RENDER_CONTROL2_SAMPLEID 0x00000040
958 #define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK 0x00000380
959 #define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT 7
960 static inline uint32_t A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(uint32_t val)
961 {
962 return ((val) << A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT) & A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK;
963 }
964 #define A4XX_RB_RENDER_CONTROL2_SAMPLEID_HR 0x00000800
965 #define A4XX_RB_RENDER_CONTROL2_IJ_PERSP_PIXEL 0x00001000
966 #define A4XX_RB_RENDER_CONTROL2_IJ_PERSP_CENTROID 0x00002000
967 #define A4XX_RB_RENDER_CONTROL2_IJ_PERSP_SAMPLE 0x00004000
968 #define A4XX_RB_RENDER_CONTROL2_SIZE 0x00008000
969
970 static inline uint32_t REG_A4XX_RB_MRT(uint32_t i0) { return 0x000020a4 + 0x5*i0; }
971
972 static inline uint32_t REG_A4XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020a4 + 0x5*i0; }
973 #define A4XX_RB_MRT_CONTROL_READ_DEST_ENABLE 0x00000008
974 #define A4XX_RB_MRT_CONTROL_BLEND 0x00000010
975 #define A4XX_RB_MRT_CONTROL_BLEND2 0x00000020
976 #define A4XX_RB_MRT_CONTROL_ROP_ENABLE 0x00000040
977 #define A4XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000f00
978 #define A4XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 8
979 static inline uint32_t A4XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val)
980 {
981 return ((val) << A4XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A4XX_RB_MRT_CONTROL_ROP_CODE__MASK;
982 }
983 #define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x0f000000
984 #define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 24
985 static inline uint32_t A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
986 {
987 return ((val) << A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
988 }
989
990 static inline uint32_t REG_A4XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020a5 + 0x5*i0; }
991 #define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x0000003f
992 #define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0
993 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a4xx_color_fmt val)
994 {
995 return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK;
996 }
997 #define A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x000000c0
998 #define A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 6
999 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a4xx_tile_mode val)
1000 {
1001 return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK;
1002 }
1003 #define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK 0x00000600
1004 #define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT 9
1005 static inline uint32_t A4XX_RB_MRT_BUF_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
1006 {
1007 return ((val) << A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT) & A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK;
1008 }
1009 #define A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00001800
1010 #define A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 11
1011 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
1012 {
1013 return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;
1014 }
1015 #define A4XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00002000
1016 #define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK 0xffffc000
1017 #define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT 14
1018 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val)
1019 {
1020 return ((val >> 4) << A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK;
1021 }
1022
1023 static inline uint32_t REG_A4XX_RB_MRT_BASE(uint32_t i0) { return 0x000020a6 + 0x5*i0; }
1024
1025 static inline uint32_t REG_A4XX_RB_MRT_CONTROL3(uint32_t i0) { return 0x000020a7 + 0x5*i0; }
1026 #define A4XX_RB_MRT_CONTROL3_STRIDE__MASK 0x03fffff8
1027 #define A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT 3
1028 static inline uint32_t A4XX_RB_MRT_CONTROL3_STRIDE(uint32_t val)
1029 {
1030 return ((val) << A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT) & A4XX_RB_MRT_CONTROL3_STRIDE__MASK;
1031 }
1032
1033 static inline uint32_t REG_A4XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020a8 + 0x5*i0; }
1034 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f
1035 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0
1036 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)
1037 {
1038 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK;
1039 }
1040 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0
1041 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5
1042 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
1043 {
1044 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK;
1045 }
1046 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00
1047 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8
1048 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val)
1049 {
1050 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK;
1051 }
1052 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000
1053 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16
1054 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val)
1055 {
1056 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK;
1057 }
1058 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000
1059 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21
1060 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
1061 {
1062 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK;
1063 }
1064 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000
1065 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24
1066 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val)
1067 {
1068 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK;
1069 }
1070
1071 #define REG_A4XX_RB_BLEND_RED 0x000020f0
1072 #define A4XX_RB_BLEND_RED_UINT__MASK 0x000000ff
1073 #define A4XX_RB_BLEND_RED_UINT__SHIFT 0
1074 static inline uint32_t A4XX_RB_BLEND_RED_UINT(uint32_t val)
1075 {
1076 return ((val) << A4XX_RB_BLEND_RED_UINT__SHIFT) & A4XX_RB_BLEND_RED_UINT__MASK;
1077 }
1078 #define A4XX_RB_BLEND_RED_SINT__MASK 0x0000ff00
1079 #define A4XX_RB_BLEND_RED_SINT__SHIFT 8
1080 static inline uint32_t A4XX_RB_BLEND_RED_SINT(uint32_t val)
1081 {
1082 return ((val) << A4XX_RB_BLEND_RED_SINT__SHIFT) & A4XX_RB_BLEND_RED_SINT__MASK;
1083 }
1084 #define A4XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000
1085 #define A4XX_RB_BLEND_RED_FLOAT__SHIFT 16
1086 static inline uint32_t A4XX_RB_BLEND_RED_FLOAT(float val)
1087 {
1088 return ((util_float_to_half(val)) << A4XX_RB_BLEND_RED_FLOAT__SHIFT) & A4XX_RB_BLEND_RED_FLOAT__MASK;
1089 }
1090
1091 #define REG_A4XX_RB_BLEND_RED_F32 0x000020f1
1092 #define A4XX_RB_BLEND_RED_F32__MASK 0xffffffff
1093 #define A4XX_RB_BLEND_RED_F32__SHIFT 0
1094 static inline uint32_t A4XX_RB_BLEND_RED_F32(float val)
1095 {
1096 return ((fui(val)) << A4XX_RB_BLEND_RED_F32__SHIFT) & A4XX_RB_BLEND_RED_F32__MASK;
1097 }
1098
1099 #define REG_A4XX_RB_BLEND_GREEN 0x000020f2
1100 #define A4XX_RB_BLEND_GREEN_UINT__MASK 0x000000ff
1101 #define A4XX_RB_BLEND_GREEN_UINT__SHIFT 0
1102 static inline uint32_t A4XX_RB_BLEND_GREEN_UINT(uint32_t val)
1103 {
1104 return ((val) << A4XX_RB_BLEND_GREEN_UINT__SHIFT) & A4XX_RB_BLEND_GREEN_UINT__MASK;
1105 }
1106 #define A4XX_RB_BLEND_GREEN_SINT__MASK 0x0000ff00
1107 #define A4XX_RB_BLEND_GREEN_SINT__SHIFT 8
1108 static inline uint32_t A4XX_RB_BLEND_GREEN_SINT(uint32_t val)
1109 {
1110 return ((val) << A4XX_RB_BLEND_GREEN_SINT__SHIFT) & A4XX_RB_BLEND_GREEN_SINT__MASK;
1111 }
1112 #define A4XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000
1113 #define A4XX_RB_BLEND_GREEN_FLOAT__SHIFT 16
1114 static inline uint32_t A4XX_RB_BLEND_GREEN_FLOAT(float val)
1115 {
1116 return ((util_float_to_half(val)) << A4XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A4XX_RB_BLEND_GREEN_FLOAT__MASK;
1117 }
1118
1119 #define REG_A4XX_RB_BLEND_GREEN_F32 0x000020f3
1120 #define A4XX_RB_BLEND_GREEN_F32__MASK 0xffffffff
1121 #define A4XX_RB_BLEND_GREEN_F32__SHIFT 0
1122 static inline uint32_t A4XX_RB_BLEND_GREEN_F32(float val)
1123 {
1124 return ((fui(val)) << A4XX_RB_BLEND_GREEN_F32__SHIFT) & A4XX_RB_BLEND_GREEN_F32__MASK;
1125 }
1126
1127 #define REG_A4XX_RB_BLEND_BLUE 0x000020f4
1128 #define A4XX_RB_BLEND_BLUE_UINT__MASK 0x000000ff
1129 #define A4XX_RB_BLEND_BLUE_UINT__SHIFT 0
1130 static inline uint32_t A4XX_RB_BLEND_BLUE_UINT(uint32_t val)
1131 {
1132 return ((val) << A4XX_RB_BLEND_BLUE_UINT__SHIFT) & A4XX_RB_BLEND_BLUE_UINT__MASK;
1133 }
1134 #define A4XX_RB_BLEND_BLUE_SINT__MASK 0x0000ff00
1135 #define A4XX_RB_BLEND_BLUE_SINT__SHIFT 8
1136 static inline uint32_t A4XX_RB_BLEND_BLUE_SINT(uint32_t val)
1137 {
1138 return ((val) << A4XX_RB_BLEND_BLUE_SINT__SHIFT) & A4XX_RB_BLEND_BLUE_SINT__MASK;
1139 }
1140 #define A4XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000
1141 #define A4XX_RB_BLEND_BLUE_FLOAT__SHIFT 16
1142 static inline uint32_t A4XX_RB_BLEND_BLUE_FLOAT(float val)
1143 {
1144 return ((util_float_to_half(val)) << A4XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A4XX_RB_BLEND_BLUE_FLOAT__MASK;
1145 }
1146
1147 #define REG_A4XX_RB_BLEND_BLUE_F32 0x000020f5
1148 #define A4XX_RB_BLEND_BLUE_F32__MASK 0xffffffff
1149 #define A4XX_RB_BLEND_BLUE_F32__SHIFT 0
1150 static inline uint32_t A4XX_RB_BLEND_BLUE_F32(float val)
1151 {
1152 return ((fui(val)) << A4XX_RB_BLEND_BLUE_F32__SHIFT) & A4XX_RB_BLEND_BLUE_F32__MASK;
1153 }
1154
1155 #define REG_A4XX_RB_BLEND_ALPHA 0x000020f6
1156 #define A4XX_RB_BLEND_ALPHA_UINT__MASK 0x000000ff
1157 #define A4XX_RB_BLEND_ALPHA_UINT__SHIFT 0
1158 static inline uint32_t A4XX_RB_BLEND_ALPHA_UINT(uint32_t val)
1159 {
1160 return ((val) << A4XX_RB_BLEND_ALPHA_UINT__SHIFT) & A4XX_RB_BLEND_ALPHA_UINT__MASK;
1161 }
1162 #define A4XX_RB_BLEND_ALPHA_SINT__MASK 0x0000ff00
1163 #define A4XX_RB_BLEND_ALPHA_SINT__SHIFT 8
1164 static inline uint32_t A4XX_RB_BLEND_ALPHA_SINT(uint32_t val)
1165 {
1166 return ((val) << A4XX_RB_BLEND_ALPHA_SINT__SHIFT) & A4XX_RB_BLEND_ALPHA_SINT__MASK;
1167 }
1168 #define A4XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000
1169 #define A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16
1170 static inline uint32_t A4XX_RB_BLEND_ALPHA_FLOAT(float val)
1171 {
1172 return ((util_float_to_half(val)) << A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A4XX_RB_BLEND_ALPHA_FLOAT__MASK;
1173 }
1174
1175 #define REG_A4XX_RB_BLEND_ALPHA_F32 0x000020f7
1176 #define A4XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff
1177 #define A4XX_RB_BLEND_ALPHA_F32__SHIFT 0
1178 static inline uint32_t A4XX_RB_BLEND_ALPHA_F32(float val)
1179 {
1180 return ((fui(val)) << A4XX_RB_BLEND_ALPHA_F32__SHIFT) & A4XX_RB_BLEND_ALPHA_F32__MASK;
1181 }
1182
1183 #define REG_A4XX_RB_ALPHA_CONTROL 0x000020f8
1184 #define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff
1185 #define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0
1186 static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val)
1187 {
1188 return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK;
1189 }
1190 #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100
1191 #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00
1192 #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9
1193 static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val)
1194 {
1195 return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK;
1196 }
1197
1198 #define REG_A4XX_RB_FS_OUTPUT 0x000020f9
1199 #define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK 0x000000ff
1200 #define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT 0
1201 static inline uint32_t A4XX_RB_FS_OUTPUT_ENABLE_BLEND(uint32_t val)
1202 {
1203 return ((val) << A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT) & A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK;
1204 }
1205 #define A4XX_RB_FS_OUTPUT_INDEPENDENT_BLEND 0x00000100
1206 #define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK 0xffff0000
1207 #define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT 16
1208 static inline uint32_t A4XX_RB_FS_OUTPUT_SAMPLE_MASK(uint32_t val)
1209 {
1210 return ((val) << A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT) & A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK;
1211 }
1212
1213 #define REG_A4XX_RB_SAMPLE_COUNT_CONTROL 0x000020fa
1214 #define A4XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002
1215 #define A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK 0xfffffffc
1216 #define A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT 2
1217 static inline uint32_t A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR(uint32_t val)
1218 {
1219 return ((val >> 2) << A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT) & A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK;
1220 }
1221
1222 #define REG_A4XX_RB_RENDER_COMPONENTS 0x000020fb
1223 #define A4XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f
1224 #define A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0
1225 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT0(uint32_t val)
1226 {
1227 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT0__MASK;
1228 }
1229 #define A4XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0
1230 #define A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4
1231 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT1(uint32_t val)
1232 {
1233 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT1__MASK;
1234 }
1235 #define A4XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00
1236 #define A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8
1237 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT2(uint32_t val)
1238 {
1239 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT2__MASK;
1240 }
1241 #define A4XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000
1242 #define A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12
1243 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT3(uint32_t val)
1244 {
1245 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT3__MASK;
1246 }
1247 #define A4XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000
1248 #define A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16
1249 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT4(uint32_t val)
1250 {
1251 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT4__MASK;
1252 }
1253 #define A4XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000
1254 #define A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20
1255 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT5(uint32_t val)
1256 {
1257 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT5__MASK;
1258 }
1259 #define A4XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000
1260 #define A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24
1261 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT6(uint32_t val)
1262 {
1263 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT6__MASK;
1264 }
1265 #define A4XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000
1266 #define A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28
1267 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT7(uint32_t val)
1268 {
1269 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT7__MASK;
1270 }
1271
1272 #define REG_A4XX_RB_COPY_CONTROL 0x000020fc
1273 #define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK 0x00000003
1274 #define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT 0
1275 static inline uint32_t A4XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val)
1276 {
1277 return ((val) << A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT) & A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK;
1278 }
1279 #define A4XX_RB_COPY_CONTROL_MODE__MASK 0x00000070
1280 #define A4XX_RB_COPY_CONTROL_MODE__SHIFT 4
1281 static inline uint32_t A4XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val)
1282 {
1283 return ((val) << A4XX_RB_COPY_CONTROL_MODE__SHIFT) & A4XX_RB_COPY_CONTROL_MODE__MASK;
1284 }
1285 #define A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK 0x00000f00
1286 #define A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT 8
1287 static inline uint32_t A4XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val)
1288 {
1289 return ((val) << A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT) & A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK;
1290 }
1291 #define A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK 0xffffc000
1292 #define A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT 14
1293 static inline uint32_t A4XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val)
1294 {
1295 return ((val >> 14) << A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK;
1296 }
1297
1298 #define REG_A4XX_RB_COPY_DEST_BASE 0x000020fd
1299 #define A4XX_RB_COPY_DEST_BASE_BASE__MASK 0xffffffe0
1300 #define A4XX_RB_COPY_DEST_BASE_BASE__SHIFT 5
1301 static inline uint32_t A4XX_RB_COPY_DEST_BASE_BASE(uint32_t val)
1302 {
1303 return ((val >> 5) << A4XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A4XX_RB_COPY_DEST_BASE_BASE__MASK;
1304 }
1305
1306 #define REG_A4XX_RB_COPY_DEST_PITCH 0x000020fe
1307 #define A4XX_RB_COPY_DEST_PITCH_PITCH__MASK 0xffffffff
1308 #define A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT 0
1309 static inline uint32_t A4XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val)
1310 {
1311 return ((val >> 5) << A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A4XX_RB_COPY_DEST_PITCH_PITCH__MASK;
1312 }
1313
1314 #define REG_A4XX_RB_COPY_DEST_INFO 0x000020ff
1315 #define A4XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000fc
1316 #define A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 2
1317 static inline uint32_t A4XX_RB_COPY_DEST_INFO_FORMAT(enum a4xx_color_fmt val)
1318 {
1319 return ((val) << A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A4XX_RB_COPY_DEST_INFO_FORMAT__MASK;
1320 }
1321 #define A4XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300
1322 #define A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8
1323 static inline uint32_t A4XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val)
1324 {
1325 return ((val) << A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A4XX_RB_COPY_DEST_INFO_SWAP__MASK;
1326 }
1327 #define A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00
1328 #define A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10
1329 static inline uint32_t A4XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
1330 {
1331 return ((val) << A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK;
1332 }
1333 #define A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK 0x0003c000
1334 #define A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT 14
1335 static inline uint32_t A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val)
1336 {
1337 return ((val) << A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT) & A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK;
1338 }
1339 #define A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK 0x001c0000
1340 #define A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT 18
1341 static inline uint32_t A4XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val)
1342 {
1343 return ((val) << A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT) & A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK;
1344 }
1345 #define A4XX_RB_COPY_DEST_INFO_TILE__MASK 0x03000000
1346 #define A4XX_RB_COPY_DEST_INFO_TILE__SHIFT 24
1347 static inline uint32_t A4XX_RB_COPY_DEST_INFO_TILE(enum a4xx_tile_mode val)
1348 {
1349 return ((val) << A4XX_RB_COPY_DEST_INFO_TILE__SHIFT) & A4XX_RB_COPY_DEST_INFO_TILE__MASK;
1350 }
1351
1352 #define REG_A4XX_RB_FS_OUTPUT_REG 0x00002100
1353 #define A4XX_RB_FS_OUTPUT_REG_MRT__MASK 0x0000000f
1354 #define A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT 0
1355 static inline uint32_t A4XX_RB_FS_OUTPUT_REG_MRT(uint32_t val)
1356 {
1357 return ((val) << A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_RB_FS_OUTPUT_REG_MRT__MASK;
1358 }
1359 #define A4XX_RB_FS_OUTPUT_REG_FRAG_WRITES_Z 0x00000020
1360
1361 #define REG_A4XX_RB_DEPTH_CONTROL 0x00002101
1362 #define A4XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z 0x00000001
1363 #define A4XX_RB_DEPTH_CONTROL_Z_ENABLE 0x00000002
1364 #define A4XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE 0x00000004
1365 #define A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK 0x00000070
1366 #define A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT 4
1367 static inline uint32_t A4XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val)
1368 {
1369 return ((val) << A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK;
1370 }
1371 #define A4XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE 0x00000080
1372 #define A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00010000
1373 #define A4XX_RB_DEPTH_CONTROL_FORCE_FRAGZ_TO_FS 0x00020000
1374 #define A4XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x80000000
1375
1376 #define REG_A4XX_RB_DEPTH_CLEAR 0x00002102
1377
1378 #define REG_A4XX_RB_DEPTH_INFO 0x00002103
1379 #define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000003
1380 #define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0
1381 static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum a4xx_depth_format val)
1382 {
1383 return ((val) << A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK;
1384 }
1385 #define A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff000
1386 #define A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 12
1387 static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val)
1388 {
1389 return ((val >> 12) << A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK;
1390 }
1391
1392 #define REG_A4XX_RB_DEPTH_PITCH 0x00002104
1393 #define A4XX_RB_DEPTH_PITCH__MASK 0xffffffff
1394 #define A4XX_RB_DEPTH_PITCH__SHIFT 0
1395 static inline uint32_t A4XX_RB_DEPTH_PITCH(uint32_t val)
1396 {
1397 return ((val >> 5) << A4XX_RB_DEPTH_PITCH__SHIFT) & A4XX_RB_DEPTH_PITCH__MASK;
1398 }
1399
1400 #define REG_A4XX_RB_DEPTH_PITCH2 0x00002105
1401 #define A4XX_RB_DEPTH_PITCH2__MASK 0xffffffff
1402 #define A4XX_RB_DEPTH_PITCH2__SHIFT 0
1403 static inline uint32_t A4XX_RB_DEPTH_PITCH2(uint32_t val)
1404 {
1405 return ((val >> 5) << A4XX_RB_DEPTH_PITCH2__SHIFT) & A4XX_RB_DEPTH_PITCH2__MASK;
1406 }
1407
1408 #define REG_A4XX_RB_STENCIL_CONTROL 0x00002106
1409 #define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001
1410 #define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002
1411 #define A4XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004
1412 #define A4XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700
1413 #define A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8
1414 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val)
1415 {
1416 return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC__MASK;
1417 }
1418 #define A4XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800
1419 #define A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11
1420 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val)
1421 {
1422 return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL__MASK;
1423 }
1424 #define A4XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000
1425 #define A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14
1426 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val)
1427 {
1428 return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS__MASK;
1429 }
1430 #define A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000
1431 #define A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17
1432 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val)
1433 {
1434 return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK;
1435 }
1436 #define A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000
1437 #define A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20
1438 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val)
1439 {
1440 return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK;
1441 }
1442 #define A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000
1443 #define A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23
1444 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val)
1445 {
1446 return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK;
1447 }
1448 #define A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000
1449 #define A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26
1450 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val)
1451 {
1452 return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK;
1453 }
1454 #define A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000
1455 #define A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29
1456 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val)
1457 {
1458 return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK;
1459 }
1460
1461 #define REG_A4XX_RB_STENCIL_CONTROL2 0x00002107
1462 #define A4XX_RB_STENCIL_CONTROL2_STENCIL_BUFFER 0x00000001
1463
1464 #define REG_A4XX_RB_STENCIL_INFO 0x00002108
1465 #define A4XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001
1466 #define A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK 0xfffff000
1467 #define A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT 12
1468 static inline uint32_t A4XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val)
1469 {
1470 return ((val >> 12) << A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK;
1471 }
1472
1473 #define REG_A4XX_RB_STENCIL_PITCH 0x00002109
1474 #define A4XX_RB_STENCIL_PITCH__MASK 0xffffffff
1475 #define A4XX_RB_STENCIL_PITCH__SHIFT 0
1476 static inline uint32_t A4XX_RB_STENCIL_PITCH(uint32_t val)
1477 {
1478 return ((val >> 5) << A4XX_RB_STENCIL_PITCH__SHIFT) & A4XX_RB_STENCIL_PITCH__MASK;
1479 }
1480
1481 #define REG_A4XX_RB_STENCILREFMASK 0x0000210b
1482 #define A4XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff
1483 #define A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0
1484 static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILREF(uint32_t val)
1485 {
1486 return ((val) << A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILREF__MASK;
1487 }
1488 #define A4XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00
1489 #define A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8
1490 static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val)
1491 {
1492 return ((val) << A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILMASK__MASK;
1493 }
1494 #define A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000
1495 #define A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16
1496 static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val)
1497 {
1498 return ((val) << A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK;
1499 }
1500
1501 #define REG_A4XX_RB_STENCILREFMASK_BF 0x0000210c
1502 #define A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff
1503 #define A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0
1504 static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val)
1505 {
1506 return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK;
1507 }
1508 #define A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00
1509 #define A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8
1510 static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val)
1511 {
1512 return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK;
1513 }
1514 #define A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000
1515 #define A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16
1516 static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val)
1517 {
1518 return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK;
1519 }
1520
1521 #define REG_A4XX_RB_BIN_OFFSET 0x0000210d
1522 #define A4XX_RB_BIN_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000
1523 #define A4XX_RB_BIN_OFFSET_X__MASK 0x00007fff
1524 #define A4XX_RB_BIN_OFFSET_X__SHIFT 0
1525 static inline uint32_t A4XX_RB_BIN_OFFSET_X(uint32_t val)
1526 {
1527 return ((val) << A4XX_RB_BIN_OFFSET_X__SHIFT) & A4XX_RB_BIN_OFFSET_X__MASK;
1528 }
1529 #define A4XX_RB_BIN_OFFSET_Y__MASK 0x7fff0000
1530 #define A4XX_RB_BIN_OFFSET_Y__SHIFT 16
1531 static inline uint32_t A4XX_RB_BIN_OFFSET_Y(uint32_t val)
1532 {
1533 return ((val) << A4XX_RB_BIN_OFFSET_Y__SHIFT) & A4XX_RB_BIN_OFFSET_Y__MASK;
1534 }
1535
1536 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP(uint32_t i0) { return 0x00002120 + 0x2*i0; }
1537
1538 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MIN(uint32_t i0) { return 0x00002120 + 0x2*i0; }
1539
1540 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MAX(uint32_t i0) { return 0x00002121 + 0x2*i0; }
1541
1542 #define REG_A4XX_RBBM_HW_VERSION 0x00000000
1543
1544 #define REG_A4XX_RBBM_HW_CONFIGURATION 0x00000002
1545
1546 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP(uint32_t i0) { return 0x00000004 + 0x1*i0; }
1547
1548 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP_REG(uint32_t i0) { return 0x00000004 + 0x1*i0; }
1549
1550 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP(uint32_t i0) { return 0x00000008 + 0x1*i0; }
1551
1552 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP_REG(uint32_t i0) { return 0x00000008 + 0x1*i0; }
1553
1554 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP(uint32_t i0) { return 0x0000000c + 0x1*i0; }
1555
1556 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP_REG(uint32_t i0) { return 0x0000000c + 0x1*i0; }
1557
1558 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP(uint32_t i0) { return 0x00000010 + 0x1*i0; }
1559
1560 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP_REG(uint32_t i0) { return 0x00000010 + 0x1*i0; }
1561
1562 #define REG_A4XX_RBBM_CLOCK_CTL_UCHE 0x00000014
1563
1564 #define REG_A4XX_RBBM_CLOCK_CTL2_UCHE 0x00000015
1565
1566 #define REG_A4XX_RBBM_CLOCK_CTL3_UCHE 0x00000016
1567
1568 #define REG_A4XX_RBBM_CLOCK_CTL4_UCHE 0x00000017
1569
1570 #define REG_A4XX_RBBM_CLOCK_HYST_UCHE 0x00000018
1571
1572 #define REG_A4XX_RBBM_CLOCK_DELAY_UCHE 0x00000019
1573
1574 #define REG_A4XX_RBBM_CLOCK_MODE_GPC 0x0000001a
1575
1576 #define REG_A4XX_RBBM_CLOCK_DELAY_GPC 0x0000001b
1577
1578 #define REG_A4XX_RBBM_CLOCK_HYST_GPC 0x0000001c
1579
1580 #define REG_A4XX_RBBM_CLOCK_CTL_TSE_RAS_RBBM 0x0000001d
1581
1582 #define REG_A4XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x0000001e
1583
1584 #define REG_A4XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x0000001f
1585
1586 #define REG_A4XX_RBBM_CLOCK_CTL 0x00000020
1587
1588 #define REG_A4XX_RBBM_SP_HYST_CNT 0x00000021
1589
1590 #define REG_A4XX_RBBM_SW_RESET_CMD 0x00000022
1591
1592 #define REG_A4XX_RBBM_AHB_CTL0 0x00000023
1593
1594 #define REG_A4XX_RBBM_AHB_CTL1 0x00000024
1595
1596 #define REG_A4XX_RBBM_AHB_CMD 0x00000025
1597
1598 #define REG_A4XX_RBBM_RB_SUB_BLOCK_SEL_CTL 0x00000026
1599
1600 #define REG_A4XX_RBBM_RAM_ACC_63_32 0x00000028
1601
1602 #define REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL 0x0000002b
1603
1604 #define REG_A4XX_RBBM_INTERFACE_HANG_INT_CTL 0x0000002f
1605
1606 #define REG_A4XX_RBBM_INTERFACE_HANG_MASK_CTL4 0x00000034
1607
1608 #define REG_A4XX_RBBM_INT_CLEAR_CMD 0x00000036
1609
1610 #define REG_A4XX_RBBM_INT_0_MASK 0x00000037
1611
1612 #define REG_A4XX_RBBM_RBBM_CTL 0x0000003e
1613
1614 #define REG_A4XX_RBBM_AHB_DEBUG_CTL 0x0000003f
1615
1616 #define REG_A4XX_RBBM_VBIF_DEBUG_CTL 0x00000041
1617
1618 #define REG_A4XX_RBBM_CLOCK_CTL2 0x00000042
1619
1620 #define REG_A4XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045
1621
1622 #define REG_A4XX_RBBM_RESET_CYCLES 0x00000047
1623
1624 #define REG_A4XX_RBBM_EXT_TRACE_BUS_CTL 0x00000049
1625
1626 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_A 0x0000004a
1627
1628 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_B 0x0000004b
1629
1630 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_C 0x0000004c
1631
1632 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_D 0x0000004d
1633
1634 #define REG_A4XX_RBBM_POWER_CNTL_IP 0x00000098
1635 #define A4XX_RBBM_POWER_CNTL_IP_SW_COLLAPSE 0x00000001
1636 #define A4XX_RBBM_POWER_CNTL_IP_SP_TP_PWR_ON 0x00100000
1637
1638 #define REG_A4XX_RBBM_PERFCTR_CP_0_LO 0x0000009c
1639
1640 #define REG_A4XX_RBBM_PERFCTR_CP_0_HI 0x0000009d
1641
1642 #define REG_A4XX_RBBM_PERFCTR_CP_1_LO 0x0000009e
1643
1644 #define REG_A4XX_RBBM_PERFCTR_CP_1_HI 0x0000009f
1645
1646 #define REG_A4XX_RBBM_PERFCTR_CP_2_LO 0x000000a0
1647
1648 #define REG_A4XX_RBBM_PERFCTR_CP_2_HI 0x000000a1
1649
1650 #define REG_A4XX_RBBM_PERFCTR_CP_3_LO 0x000000a2
1651
1652 #define REG_A4XX_RBBM_PERFCTR_CP_3_HI 0x000000a3
1653
1654 #define REG_A4XX_RBBM_PERFCTR_CP_4_LO 0x000000a4
1655
1656 #define REG_A4XX_RBBM_PERFCTR_CP_4_HI 0x000000a5
1657
1658 #define REG_A4XX_RBBM_PERFCTR_CP_5_LO 0x000000a6
1659
1660 #define REG_A4XX_RBBM_PERFCTR_CP_5_HI 0x000000a7
1661
1662 #define REG_A4XX_RBBM_PERFCTR_CP_6_LO 0x000000a8
1663
1664 #define REG_A4XX_RBBM_PERFCTR_CP_6_HI 0x000000a9
1665
1666 #define REG_A4XX_RBBM_PERFCTR_CP_7_LO 0x000000aa
1667
1668 #define REG_A4XX_RBBM_PERFCTR_CP_7_HI 0x000000ab
1669
1670 #define REG_A4XX_RBBM_PERFCTR_RBBM_0_LO 0x000000ac
1671
1672 #define REG_A4XX_RBBM_PERFCTR_RBBM_0_HI 0x000000ad
1673
1674 #define REG_A4XX_RBBM_PERFCTR_RBBM_1_LO 0x000000ae
1675
1676 #define REG_A4XX_RBBM_PERFCTR_RBBM_1_HI 0x000000af
1677
1678 #define REG_A4XX_RBBM_PERFCTR_RBBM_2_LO 0x000000b0
1679
1680 #define REG_A4XX_RBBM_PERFCTR_RBBM_2_HI 0x000000b1
1681
1682 #define REG_A4XX_RBBM_PERFCTR_RBBM_3_LO 0x000000b2
1683
1684 #define REG_A4XX_RBBM_PERFCTR_RBBM_3_HI 0x000000b3
1685
1686 #define REG_A4XX_RBBM_PERFCTR_PC_0_LO 0x000000b4
1687
1688 #define REG_A4XX_RBBM_PERFCTR_PC_0_HI 0x000000b5
1689
1690 #define REG_A4XX_RBBM_PERFCTR_PC_1_LO 0x000000b6
1691
1692 #define REG_A4XX_RBBM_PERFCTR_PC_1_HI 0x000000b7
1693
1694 #define REG_A4XX_RBBM_PERFCTR_PC_2_LO 0x000000b8
1695
1696 #define REG_A4XX_RBBM_PERFCTR_PC_2_HI 0x000000b9
1697
1698 #define REG_A4XX_RBBM_PERFCTR_PC_3_LO 0x000000ba
1699
1700 #define REG_A4XX_RBBM_PERFCTR_PC_3_HI 0x000000bb
1701
1702 #define REG_A4XX_RBBM_PERFCTR_PC_4_LO 0x000000bc
1703
1704 #define REG_A4XX_RBBM_PERFCTR_PC_4_HI 0x000000bd
1705
1706 #define REG_A4XX_RBBM_PERFCTR_PC_5_LO 0x000000be
1707
1708 #define REG_A4XX_RBBM_PERFCTR_PC_5_HI 0x000000bf
1709
1710 #define REG_A4XX_RBBM_PERFCTR_PC_6_LO 0x000000c0
1711
1712 #define REG_A4XX_RBBM_PERFCTR_PC_6_HI 0x000000c1
1713
1714 #define REG_A4XX_RBBM_PERFCTR_PC_7_LO 0x000000c2
1715
1716 #define REG_A4XX_RBBM_PERFCTR_PC_7_HI 0x000000c3
1717
1718 #define REG_A4XX_RBBM_PERFCTR_VFD_0_LO 0x000000c4
1719
1720 #define REG_A4XX_RBBM_PERFCTR_VFD_0_HI 0x000000c5
1721
1722 #define REG_A4XX_RBBM_PERFCTR_VFD_1_LO 0x000000c6
1723
1724 #define REG_A4XX_RBBM_PERFCTR_VFD_1_HI 0x000000c7
1725
1726 #define REG_A4XX_RBBM_PERFCTR_VFD_2_LO 0x000000c8
1727
1728 #define REG_A4XX_RBBM_PERFCTR_VFD_2_HI 0x000000c9
1729
1730 #define REG_A4XX_RBBM_PERFCTR_VFD_3_LO 0x000000ca
1731
1732 #define REG_A4XX_RBBM_PERFCTR_VFD_3_HI 0x000000cb
1733
1734 #define REG_A4XX_RBBM_PERFCTR_VFD_4_LO 0x000000cc
1735
1736 #define REG_A4XX_RBBM_PERFCTR_VFD_4_HI 0x000000cd
1737
1738 #define REG_A4XX_RBBM_PERFCTR_VFD_5_LO 0x000000ce
1739
1740 #define REG_A4XX_RBBM_PERFCTR_VFD_5_HI 0x000000cf
1741
1742 #define REG_A4XX_RBBM_PERFCTR_VFD_6_LO 0x000000d0
1743
1744 #define REG_A4XX_RBBM_PERFCTR_VFD_6_HI 0x000000d1
1745
1746 #define REG_A4XX_RBBM_PERFCTR_VFD_7_LO 0x000000d2
1747
1748 #define REG_A4XX_RBBM_PERFCTR_VFD_7_HI 0x000000d3
1749
1750 #define REG_A4XX_RBBM_PERFCTR_HLSQ_0_LO 0x000000d4
1751
1752 #define REG_A4XX_RBBM_PERFCTR_HLSQ_0_HI 0x000000d5
1753
1754 #define REG_A4XX_RBBM_PERFCTR_HLSQ_1_LO 0x000000d6
1755
1756 #define REG_A4XX_RBBM_PERFCTR_HLSQ_1_HI 0x000000d7
1757
1758 #define REG_A4XX_RBBM_PERFCTR_HLSQ_2_LO 0x000000d8
1759
1760 #define REG_A4XX_RBBM_PERFCTR_HLSQ_2_HI 0x000000d9
1761
1762 #define REG_A4XX_RBBM_PERFCTR_HLSQ_3_LO 0x000000da
1763
1764 #define REG_A4XX_RBBM_PERFCTR_HLSQ_3_HI 0x000000db
1765
1766 #define REG_A4XX_RBBM_PERFCTR_HLSQ_4_LO 0x000000dc
1767
1768 #define REG_A4XX_RBBM_PERFCTR_HLSQ_4_HI 0x000000dd
1769
1770 #define REG_A4XX_RBBM_PERFCTR_HLSQ_5_LO 0x000000de
1771
1772 #define REG_A4XX_RBBM_PERFCTR_HLSQ_5_HI 0x000000df
1773
1774 #define REG_A4XX_RBBM_PERFCTR_HLSQ_6_LO 0x000000e0
1775
1776 #define REG_A4XX_RBBM_PERFCTR_HLSQ_6_HI 0x000000e1
1777
1778 #define REG_A4XX_RBBM_PERFCTR_HLSQ_7_LO 0x000000e2
1779
1780 #define REG_A4XX_RBBM_PERFCTR_HLSQ_7_HI 0x000000e3
1781
1782 #define REG_A4XX_RBBM_PERFCTR_VPC_0_LO 0x000000e4
1783
1784 #define REG_A4XX_RBBM_PERFCTR_VPC_0_HI 0x000000e5
1785
1786 #define REG_A4XX_RBBM_PERFCTR_VPC_1_LO 0x000000e6
1787
1788 #define REG_A4XX_RBBM_PERFCTR_VPC_1_HI 0x000000e7
1789
1790 #define REG_A4XX_RBBM_PERFCTR_VPC_2_LO 0x000000e8
1791
1792 #define REG_A4XX_RBBM_PERFCTR_VPC_2_HI 0x000000e9
1793
1794 #define REG_A4XX_RBBM_PERFCTR_VPC_3_LO 0x000000ea
1795
1796 #define REG_A4XX_RBBM_PERFCTR_VPC_3_HI 0x000000eb
1797
1798 #define REG_A4XX_RBBM_PERFCTR_CCU_0_LO 0x000000ec
1799
1800 #define REG_A4XX_RBBM_PERFCTR_CCU_0_HI 0x000000ed
1801
1802 #define REG_A4XX_RBBM_PERFCTR_CCU_1_LO 0x000000ee
1803
1804 #define REG_A4XX_RBBM_PERFCTR_CCU_1_HI 0x000000ef
1805
1806 #define REG_A4XX_RBBM_PERFCTR_CCU_2_LO 0x000000f0
1807
1808 #define REG_A4XX_RBBM_PERFCTR_CCU_2_HI 0x000000f1
1809
1810 #define REG_A4XX_RBBM_PERFCTR_CCU_3_LO 0x000000f2
1811
1812 #define REG_A4XX_RBBM_PERFCTR_CCU_3_HI 0x000000f3
1813
1814 #define REG_A4XX_RBBM_PERFCTR_TSE_0_LO 0x000000f4
1815
1816 #define REG_A4XX_RBBM_PERFCTR_TSE_0_HI 0x000000f5
1817
1818 #define REG_A4XX_RBBM_PERFCTR_TSE_1_LO 0x000000f6
1819
1820 #define REG_A4XX_RBBM_PERFCTR_TSE_1_HI 0x000000f7
1821
1822 #define REG_A4XX_RBBM_PERFCTR_TSE_2_LO 0x000000f8
1823
1824 #define REG_A4XX_RBBM_PERFCTR_TSE_2_HI 0x000000f9
1825
1826 #define REG_A4XX_RBBM_PERFCTR_TSE_3_LO 0x000000fa
1827
1828 #define REG_A4XX_RBBM_PERFCTR_TSE_3_HI 0x000000fb
1829
1830 #define REG_A4XX_RBBM_PERFCTR_RAS_0_LO 0x000000fc
1831
1832 #define REG_A4XX_RBBM_PERFCTR_RAS_0_HI 0x000000fd
1833
1834 #define REG_A4XX_RBBM_PERFCTR_RAS_1_LO 0x000000fe
1835
1836 #define REG_A4XX_RBBM_PERFCTR_RAS_1_HI 0x000000ff
1837
1838 #define REG_A4XX_RBBM_PERFCTR_RAS_2_LO 0x00000100
1839
1840 #define REG_A4XX_RBBM_PERFCTR_RAS_2_HI 0x00000101
1841
1842 #define REG_A4XX_RBBM_PERFCTR_RAS_3_LO 0x00000102
1843
1844 #define REG_A4XX_RBBM_PERFCTR_RAS_3_HI 0x00000103
1845
1846 #define REG_A4XX_RBBM_PERFCTR_UCHE_0_LO 0x00000104
1847
1848 #define REG_A4XX_RBBM_PERFCTR_UCHE_0_HI 0x00000105
1849
1850 #define REG_A4XX_RBBM_PERFCTR_UCHE_1_LO 0x00000106
1851
1852 #define REG_A4XX_RBBM_PERFCTR_UCHE_1_HI 0x00000107
1853
1854 #define REG_A4XX_RBBM_PERFCTR_UCHE_2_LO 0x00000108
1855
1856 #define REG_A4XX_RBBM_PERFCTR_UCHE_2_HI 0x00000109
1857
1858 #define REG_A4XX_RBBM_PERFCTR_UCHE_3_LO 0x0000010a
1859
1860 #define REG_A4XX_RBBM_PERFCTR_UCHE_3_HI 0x0000010b
1861
1862 #define REG_A4XX_RBBM_PERFCTR_UCHE_4_LO 0x0000010c
1863
1864 #define REG_A4XX_RBBM_PERFCTR_UCHE_4_HI 0x0000010d
1865
1866 #define REG_A4XX_RBBM_PERFCTR_UCHE_5_LO 0x0000010e
1867
1868 #define REG_A4XX_RBBM_PERFCTR_UCHE_5_HI 0x0000010f
1869
1870 #define REG_A4XX_RBBM_PERFCTR_UCHE_6_LO 0x00000110
1871
1872 #define REG_A4XX_RBBM_PERFCTR_UCHE_6_HI 0x00000111
1873
1874 #define REG_A4XX_RBBM_PERFCTR_UCHE_7_LO 0x00000112
1875
1876 #define REG_A4XX_RBBM_PERFCTR_UCHE_7_HI 0x00000113
1877
1878 #define REG_A4XX_RBBM_PERFCTR_TP_0_LO 0x00000114
1879
1880 #define REG_A4XX_RBBM_PERFCTR_TP_0_HI 0x00000115
1881
1882 #define REG_A4XX_RBBM_PERFCTR_TP_1_LO 0x00000116
1883
1884 #define REG_A4XX_RBBM_PERFCTR_TP_1_HI 0x00000117
1885
1886 #define REG_A4XX_RBBM_PERFCTR_TP_2_LO 0x00000118
1887
1888 #define REG_A4XX_RBBM_PERFCTR_TP_2_HI 0x00000119
1889
1890 #define REG_A4XX_RBBM_PERFCTR_TP_3_LO 0x0000011a
1891
1892 #define REG_A4XX_RBBM_PERFCTR_TP_3_HI 0x0000011b
1893
1894 #define REG_A4XX_RBBM_PERFCTR_TP_4_LO 0x0000011c
1895
1896 #define REG_A4XX_RBBM_PERFCTR_TP_4_HI 0x0000011d
1897
1898 #define REG_A4XX_RBBM_PERFCTR_TP_5_LO 0x0000011e
1899
1900 #define REG_A4XX_RBBM_PERFCTR_TP_5_HI 0x0000011f
1901
1902 #define REG_A4XX_RBBM_PERFCTR_TP_6_LO 0x00000120
1903
1904 #define REG_A4XX_RBBM_PERFCTR_TP_6_HI 0x00000121
1905
1906 #define REG_A4XX_RBBM_PERFCTR_TP_7_LO 0x00000122
1907
1908 #define REG_A4XX_RBBM_PERFCTR_TP_7_HI 0x00000123
1909
1910 #define REG_A4XX_RBBM_PERFCTR_SP_0_LO 0x00000124
1911
1912 #define REG_A4XX_RBBM_PERFCTR_SP_0_HI 0x00000125
1913
1914 #define REG_A4XX_RBBM_PERFCTR_SP_1_LO 0x00000126
1915
1916 #define REG_A4XX_RBBM_PERFCTR_SP_1_HI 0x00000127
1917
1918 #define REG_A4XX_RBBM_PERFCTR_SP_2_LO 0x00000128
1919
1920 #define REG_A4XX_RBBM_PERFCTR_SP_2_HI 0x00000129
1921
1922 #define REG_A4XX_RBBM_PERFCTR_SP_3_LO 0x0000012a
1923
1924 #define REG_A4XX_RBBM_PERFCTR_SP_3_HI 0x0000012b
1925
1926 #define REG_A4XX_RBBM_PERFCTR_SP_4_LO 0x0000012c
1927
1928 #define REG_A4XX_RBBM_PERFCTR_SP_4_HI 0x0000012d
1929
1930 #define REG_A4XX_RBBM_PERFCTR_SP_5_LO 0x0000012e
1931
1932 #define REG_A4XX_RBBM_PERFCTR_SP_5_HI 0x0000012f
1933
1934 #define REG_A4XX_RBBM_PERFCTR_SP_6_LO 0x00000130
1935
1936 #define REG_A4XX_RBBM_PERFCTR_SP_6_HI 0x00000131
1937
1938 #define REG_A4XX_RBBM_PERFCTR_SP_7_LO 0x00000132
1939
1940 #define REG_A4XX_RBBM_PERFCTR_SP_7_HI 0x00000133
1941
1942 #define REG_A4XX_RBBM_PERFCTR_SP_8_LO 0x00000134
1943
1944 #define REG_A4XX_RBBM_PERFCTR_SP_8_HI 0x00000135
1945
1946 #define REG_A4XX_RBBM_PERFCTR_SP_9_LO 0x00000136
1947
1948 #define REG_A4XX_RBBM_PERFCTR_SP_9_HI 0x00000137
1949
1950 #define REG_A4XX_RBBM_PERFCTR_SP_10_LO 0x00000138
1951
1952 #define REG_A4XX_RBBM_PERFCTR_SP_10_HI 0x00000139
1953
1954 #define REG_A4XX_RBBM_PERFCTR_SP_11_LO 0x0000013a
1955
1956 #define REG_A4XX_RBBM_PERFCTR_SP_11_HI 0x0000013b
1957
1958 #define REG_A4XX_RBBM_PERFCTR_RB_0_LO 0x0000013c
1959
1960 #define REG_A4XX_RBBM_PERFCTR_RB_0_HI 0x0000013d
1961
1962 #define REG_A4XX_RBBM_PERFCTR_RB_1_LO 0x0000013e
1963
1964 #define REG_A4XX_RBBM_PERFCTR_RB_1_HI 0x0000013f
1965
1966 #define REG_A4XX_RBBM_PERFCTR_RB_2_LO 0x00000140
1967
1968 #define REG_A4XX_RBBM_PERFCTR_RB_2_HI 0x00000141
1969
1970 #define REG_A4XX_RBBM_PERFCTR_RB_3_LO 0x00000142
1971
1972 #define REG_A4XX_RBBM_PERFCTR_RB_3_HI 0x00000143
1973
1974 #define REG_A4XX_RBBM_PERFCTR_RB_4_LO 0x00000144
1975
1976 #define REG_A4XX_RBBM_PERFCTR_RB_4_HI 0x00000145
1977
1978 #define REG_A4XX_RBBM_PERFCTR_RB_5_LO 0x00000146
1979
1980 #define REG_A4XX_RBBM_PERFCTR_RB_5_HI 0x00000147
1981
1982 #define REG_A4XX_RBBM_PERFCTR_RB_6_LO 0x00000148
1983
1984 #define REG_A4XX_RBBM_PERFCTR_RB_6_HI 0x00000149
1985
1986 #define REG_A4XX_RBBM_PERFCTR_RB_7_LO 0x0000014a
1987
1988 #define REG_A4XX_RBBM_PERFCTR_RB_7_HI 0x0000014b
1989
1990 #define REG_A4XX_RBBM_PERFCTR_VSC_0_LO 0x0000014c
1991
1992 #define REG_A4XX_RBBM_PERFCTR_VSC_0_HI 0x0000014d
1993
1994 #define REG_A4XX_RBBM_PERFCTR_VSC_1_LO 0x0000014e
1995
1996 #define REG_A4XX_RBBM_PERFCTR_VSC_1_HI 0x0000014f
1997
1998 #define REG_A4XX_RBBM_PERFCTR_PWR_0_LO 0x00000166
1999
2000 #define REG_A4XX_RBBM_PERFCTR_PWR_0_HI 0x00000167
2001
2002 #define REG_A4XX_RBBM_PERFCTR_PWR_1_LO 0x00000168
2003
2004 #define REG_A4XX_RBBM_PERFCTR_PWR_1_HI 0x00000169
2005
2006 #define REG_A4XX_RBBM_ALWAYSON_COUNTER_LO 0x0000016e
2007
2008 #define REG_A4XX_RBBM_ALWAYSON_COUNTER_HI 0x0000016f
2009
2010 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP(uint32_t i0) { return 0x00000068 + 0x1*i0; }
2011
2012 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP_REG(uint32_t i0) { return 0x00000068 + 0x1*i0; }
2013
2014 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP(uint32_t i0) { return 0x0000006c + 0x1*i0; }
2015
2016 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP_REG(uint32_t i0) { return 0x0000006c + 0x1*i0; }
2017
2018 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP(uint32_t i0) { return 0x00000070 + 0x1*i0; }
2019
2020 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP_REG(uint32_t i0) { return 0x00000070 + 0x1*i0; }
2021
2022 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP(uint32_t i0) { return 0x00000074 + 0x1*i0; }
2023
2024 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP_REG(uint32_t i0) { return 0x00000074 + 0x1*i0; }
2025
2026 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB(uint32_t i0) { return 0x00000078 + 0x1*i0; }
2027
2028 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB_REG(uint32_t i0) { return 0x00000078 + 0x1*i0; }
2029
2030 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB(uint32_t i0) { return 0x0000007c + 0x1*i0; }
2031
2032 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB_REG(uint32_t i0) { return 0x0000007c + 0x1*i0; }
2033
2034 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU(uint32_t i0) { return 0x00000082 + 0x1*i0; }
2035
2036 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU_REG(uint32_t i0) { return 0x00000082 + 0x1*i0; }
2037
2038 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU(uint32_t i0) { return 0x00000086 + 0x1*i0; }
2039
2040 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU_REG(uint32_t i0) { return 0x00000086 + 0x1*i0; }
2041
2042 #define REG_A4XX_RBBM_CLOCK_HYST_COM_DCOM 0x00000080
2043
2044 #define REG_A4XX_RBBM_CLOCK_CTL_COM_DCOM 0x00000081
2045
2046 #define REG_A4XX_RBBM_CLOCK_CTL_HLSQ 0x0000008a
2047
2048 #define REG_A4XX_RBBM_CLOCK_HYST_HLSQ 0x0000008b
2049
2050 #define REG_A4XX_RBBM_CLOCK_DELAY_HLSQ 0x0000008c
2051
2052 #define REG_A4XX_RBBM_CLOCK_DELAY_COM_DCOM 0x0000008d
2053
2054 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1(uint32_t i0) { return 0x0000008e + 0x1*i0; }
2055
2056 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0) { return 0x0000008e + 0x1*i0; }
2057
2058 #define REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_0 0x00000099
2059
2060 #define REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_1 0x0000009a
2061
2062 #define REG_A4XX_RBBM_PERFCTR_CTL 0x00000170
2063
2064 #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD0 0x00000171
2065
2066 #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD1 0x00000172
2067
2068 #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD2 0x00000173
2069
2070 #define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000174
2071
2072 #define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000175
2073
2074 #define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_0 0x00000176
2075
2076 #define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_1 0x00000177
2077
2078 #define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_2 0x00000178
2079
2080 #define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_3 0x00000179
2081
2082 #define REG_A4XX_RBBM_GPU_BUSY_MASKED 0x0000017a
2083
2084 #define REG_A4XX_RBBM_INT_0_STATUS 0x0000017d
2085
2086 #define REG_A4XX_RBBM_CLOCK_STATUS 0x00000182
2087
2088 #define REG_A4XX_RBBM_AHB_STATUS 0x00000189
2089
2090 #define REG_A4XX_RBBM_AHB_ME_SPLIT_STATUS 0x0000018c
2091
2092 #define REG_A4XX_RBBM_AHB_PFP_SPLIT_STATUS 0x0000018d
2093
2094 #define REG_A4XX_RBBM_AHB_ERROR_STATUS 0x0000018f
2095
2096 #define REG_A4XX_RBBM_STATUS 0x00000191
2097 #define A4XX_RBBM_STATUS_HI_BUSY 0x00000001
2098 #define A4XX_RBBM_STATUS_CP_ME_BUSY 0x00000002
2099 #define A4XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004
2100 #define A4XX_RBBM_STATUS_CP_NRT_BUSY 0x00004000
2101 #define A4XX_RBBM_STATUS_VBIF_BUSY 0x00008000
2102 #define A4XX_RBBM_STATUS_TSE_BUSY 0x00010000
2103 #define A4XX_RBBM_STATUS_RAS_BUSY 0x00020000
2104 #define A4XX_RBBM_STATUS_RB_BUSY 0x00040000
2105 #define A4XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000
2106 #define A4XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000
2107 #define A4XX_RBBM_STATUS_VFD_BUSY 0x00200000
2108 #define A4XX_RBBM_STATUS_VPC_BUSY 0x00400000
2109 #define A4XX_RBBM_STATUS_UCHE_BUSY 0x00800000
2110 #define A4XX_RBBM_STATUS_SP_BUSY 0x01000000
2111 #define A4XX_RBBM_STATUS_TPL1_BUSY 0x02000000
2112 #define A4XX_RBBM_STATUS_MARB_BUSY 0x04000000
2113 #define A4XX_RBBM_STATUS_VSC_BUSY 0x08000000
2114 #define A4XX_RBBM_STATUS_ARB_BUSY 0x10000000
2115 #define A4XX_RBBM_STATUS_HLSQ_BUSY 0x20000000
2116 #define A4XX_RBBM_STATUS_GPU_BUSY_NOHC 0x40000000
2117 #define A4XX_RBBM_STATUS_GPU_BUSY 0x80000000
2118
2119 #define REG_A4XX_RBBM_INTERFACE_RRDY_STATUS5 0x0000019f
2120
2121 #define REG_A4XX_RBBM_POWER_STATUS 0x000001b0
2122 #define A4XX_RBBM_POWER_STATUS_SP_TP_PWR_ON 0x00100000
2123
2124 #define REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL2 0x000001b8
2125
2126 #define REG_A4XX_CP_SCRATCH_UMASK 0x00000228
2127
2128 #define REG_A4XX_CP_SCRATCH_ADDR 0x00000229
2129
2130 #define REG_A4XX_CP_RB_BASE 0x00000200
2131
2132 #define REG_A4XX_CP_RB_CNTL 0x00000201
2133
2134 #define REG_A4XX_CP_RB_WPTR 0x00000205
2135
2136 #define REG_A4XX_CP_RB_RPTR_ADDR 0x00000203
2137
2138 #define REG_A4XX_CP_RB_RPTR 0x00000204
2139
2140 #define REG_A4XX_CP_IB1_BASE 0x00000206
2141
2142 #define REG_A4XX_CP_IB1_BUFSZ 0x00000207
2143
2144 #define REG_A4XX_CP_IB2_BASE 0x00000208
2145
2146 #define REG_A4XX_CP_IB2_BUFSZ 0x00000209
2147
2148 #define REG_A4XX_CP_ME_NRT_ADDR 0x0000020c
2149
2150 #define REG_A4XX_CP_ME_NRT_DATA 0x0000020d
2151
2152 #define REG_A4XX_CP_ME_RB_DONE_DATA 0x00000217
2153
2154 #define REG_A4XX_CP_QUEUE_THRESH2 0x00000219
2155
2156 #define REG_A4XX_CP_MERCIU_SIZE 0x0000021b
2157
2158 #define REG_A4XX_CP_ROQ_ADDR 0x0000021c
2159
2160 #define REG_A4XX_CP_ROQ_DATA 0x0000021d
2161
2162 #define REG_A4XX_CP_MEQ_ADDR 0x0000021e
2163
2164 #define REG_A4XX_CP_MEQ_DATA 0x0000021f
2165
2166 #define REG_A4XX_CP_MERCIU_ADDR 0x00000220
2167
2168 #define REG_A4XX_CP_MERCIU_DATA 0x00000221
2169
2170 #define REG_A4XX_CP_MERCIU_DATA2 0x00000222
2171
2172 #define REG_A4XX_CP_PFP_UCODE_ADDR 0x00000223
2173
2174 #define REG_A4XX_CP_PFP_UCODE_DATA 0x00000224
2175
2176 #define REG_A4XX_CP_ME_RAM_WADDR 0x00000225
2177
2178 #define REG_A4XX_CP_ME_RAM_RADDR 0x00000226
2179
2180 #define REG_A4XX_CP_ME_RAM_DATA 0x00000227
2181
2182 #define REG_A4XX_CP_PREEMPT 0x0000022a
2183
2184 #define REG_A4XX_CP_CNTL 0x0000022c
2185
2186 #define REG_A4XX_CP_ME_CNTL 0x0000022d
2187
2188 #define REG_A4XX_CP_DEBUG 0x0000022e
2189
2190 #define REG_A4XX_CP_DEBUG_ECO_CONTROL 0x00000231
2191
2192 #define REG_A4XX_CP_DRAW_STATE_ADDR 0x00000232
2193
2194 static inline uint32_t REG_A4XX_CP_PROTECT(uint32_t i0) { return 0x00000240 + 0x1*i0; }
2195
2196 static inline uint32_t REG_A4XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000240 + 0x1*i0; }
2197 #define A4XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0001ffff
2198 #define A4XX_CP_PROTECT_REG_BASE_ADDR__SHIFT 0
2199 static inline uint32_t A4XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val)
2200 {
2201 return ((val) << A4XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A4XX_CP_PROTECT_REG_BASE_ADDR__MASK;
2202 }
2203 #define A4XX_CP_PROTECT_REG_MASK_LEN__MASK 0x1f000000
2204 #define A4XX_CP_PROTECT_REG_MASK_LEN__SHIFT 24
2205 static inline uint32_t A4XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)
2206 {
2207 return ((val) << A4XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A4XX_CP_PROTECT_REG_MASK_LEN__MASK;
2208 }
2209 #define A4XX_CP_PROTECT_REG_TRAP_WRITE__MASK 0x20000000
2210 #define A4XX_CP_PROTECT_REG_TRAP_WRITE__SHIFT 29
2211 static inline uint32_t A4XX_CP_PROTECT_REG_TRAP_WRITE(uint32_t val)
2212 {
2213 return ((val) << A4XX_CP_PROTECT_REG_TRAP_WRITE__SHIFT) & A4XX_CP_PROTECT_REG_TRAP_WRITE__MASK;
2214 }
2215 #define A4XX_CP_PROTECT_REG_TRAP_READ__MASK 0x40000000
2216 #define A4XX_CP_PROTECT_REG_TRAP_READ__SHIFT 30
2217 static inline uint32_t A4XX_CP_PROTECT_REG_TRAP_READ(uint32_t val)
2218 {
2219 return ((val) << A4XX_CP_PROTECT_REG_TRAP_READ__SHIFT) & A4XX_CP_PROTECT_REG_TRAP_READ__MASK;
2220 }
2221
2222 #define REG_A4XX_CP_PROTECT_CTRL 0x00000250
2223
2224 #define REG_A4XX_CP_ST_BASE 0x000004c0
2225
2226 #define REG_A4XX_CP_STQ_AVAIL 0x000004ce
2227
2228 #define REG_A4XX_CP_MERCIU_STAT 0x000004d0
2229
2230 #define REG_A4XX_CP_WFI_PEND_CTR 0x000004d2
2231
2232 #define REG_A4XX_CP_HW_FAULT 0x000004d8
2233
2234 #define REG_A4XX_CP_PROTECT_STATUS 0x000004da
2235
2236 #define REG_A4XX_CP_EVENTS_IN_FLIGHT 0x000004dd
2237
2238 #define REG_A4XX_CP_PERFCTR_CP_SEL_0 0x00000500
2239
2240 #define REG_A4XX_CP_PERFCTR_CP_SEL_1 0x00000501
2241
2242 #define REG_A4XX_CP_PERFCTR_CP_SEL_2 0x00000502
2243
2244 #define REG_A4XX_CP_PERFCTR_CP_SEL_3 0x00000503
2245
2246 #define REG_A4XX_CP_PERFCTR_CP_SEL_4 0x00000504
2247
2248 #define REG_A4XX_CP_PERFCTR_CP_SEL_5 0x00000505
2249
2250 #define REG_A4XX_CP_PERFCTR_CP_SEL_6 0x00000506
2251
2252 #define REG_A4XX_CP_PERFCTR_CP_SEL_7 0x00000507
2253
2254 #define REG_A4XX_CP_PERFCOMBINER_SELECT 0x0000050b
2255
2256 static inline uint32_t REG_A4XX_CP_SCRATCH(uint32_t i0) { return 0x00000578 + 0x1*i0; }
2257
2258 static inline uint32_t REG_A4XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000578 + 0x1*i0; }
2259
2260 #define REG_A4XX_SP_VS_STATUS 0x00000ec0
2261
2262 #define REG_A4XX_SP_MODE_CONTROL 0x00000ec3
2263
2264 #define REG_A4XX_SP_PERFCTR_SP_SEL_0 0x00000ec4
2265
2266 #define REG_A4XX_SP_PERFCTR_SP_SEL_1 0x00000ec5
2267
2268 #define REG_A4XX_SP_PERFCTR_SP_SEL_2 0x00000ec6
2269
2270 #define REG_A4XX_SP_PERFCTR_SP_SEL_3 0x00000ec7
2271
2272 #define REG_A4XX_SP_PERFCTR_SP_SEL_4 0x00000ec8
2273
2274 #define REG_A4XX_SP_PERFCTR_SP_SEL_5 0x00000ec9
2275
2276 #define REG_A4XX_SP_PERFCTR_SP_SEL_6 0x00000eca
2277
2278 #define REG_A4XX_SP_PERFCTR_SP_SEL_7 0x00000ecb
2279
2280 #define REG_A4XX_SP_PERFCTR_SP_SEL_8 0x00000ecc
2281
2282 #define REG_A4XX_SP_PERFCTR_SP_SEL_9 0x00000ecd
2283
2284 #define REG_A4XX_SP_PERFCTR_SP_SEL_10 0x00000ece
2285
2286 #define REG_A4XX_SP_PERFCTR_SP_SEL_11 0x00000ecf
2287
2288 #define REG_A4XX_SP_SP_CTRL_REG 0x000022c0
2289 #define A4XX_SP_SP_CTRL_REG_BINNING_PASS 0x00080000
2290
2291 #define REG_A4XX_SP_INSTR_CACHE_CTRL 0x000022c1
2292 #define A4XX_SP_INSTR_CACHE_CTRL_VS_BUFFER 0x00000080
2293 #define A4XX_SP_INSTR_CACHE_CTRL_FS_BUFFER 0x00000100
2294 #define A4XX_SP_INSTR_CACHE_CTRL_INSTR_BUFFER 0x00000400
2295
2296 #define REG_A4XX_SP_VS_CTRL_REG0 0x000022c4
2297 #define A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001
2298 #define A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0
2299 static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
2300 {
2301 return ((val) << A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK;
2302 }
2303 #define A4XX_SP_VS_CTRL_REG0_VARYING 0x00000002
2304 #define A4XX_SP_VS_CTRL_REG0_CACHEINVALID 0x00000004
2305 #define A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
2306 #define A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
2307 static inline uint32_t A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
2308 {
2309 return ((val) << A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
2310 }
2311 #define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
2312 #define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
2313 static inline uint32_t A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
2314 {
2315 return ((val) << A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
2316 }
2317 #define A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000
2318 #define A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18
2319 static inline uint32_t A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val)
2320 {
2321 return ((val) << A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK;
2322 }
2323 #define A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000
2324 #define A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20
2325 static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
2326 {
2327 return ((val) << A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK;
2328 }
2329 #define A4XX_SP_VS_CTRL_REG0_SUPERTHREADMODE 0x00200000
2330 #define A4XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00400000
2331
2332 #define REG_A4XX_SP_VS_CTRL_REG1 0x000022c5
2333 #define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK 0x000000ff
2334 #define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT 0
2335 static inline uint32_t A4XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val)
2336 {
2337 return ((val) << A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK;
2338 }
2339 #define A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x7f000000
2340 #define A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 24
2341 static inline uint32_t A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val)
2342 {
2343 return ((val) << A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK;
2344 }
2345
2346 #define REG_A4XX_SP_VS_PARAM_REG 0x000022c6
2347 #define A4XX_SP_VS_PARAM_REG_POSREGID__MASK 0x000000ff
2348 #define A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT 0
2349 static inline uint32_t A4XX_SP_VS_PARAM_REG_POSREGID(uint32_t val)
2350 {
2351 return ((val) << A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_POSREGID__MASK;
2352 }
2353 #define A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK 0x0000ff00
2354 #define A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT 8
2355 static inline uint32_t A4XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val)
2356 {
2357 return ((val) << A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK;
2358 }
2359 #define A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK 0xfff00000
2360 #define A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT 20
2361 static inline uint32_t A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val)
2362 {
2363 return ((val) << A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK;
2364 }
2365
2366 static inline uint32_t REG_A4XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
2367
2368 static inline uint32_t REG_A4XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
2369 #define A4XX_SP_VS_OUT_REG_A_REGID__MASK 0x000001ff
2370 #define A4XX_SP_VS_OUT_REG_A_REGID__SHIFT 0
2371 static inline uint32_t A4XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
2372 {
2373 return ((val) << A4XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_A_REGID__MASK;
2374 }
2375 #define A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00001e00
2376 #define A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 9
2377 static inline uint32_t A4XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)
2378 {
2379 return ((val) << A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK;
2380 }
2381 #define A4XX_SP_VS_OUT_REG_B_REGID__MASK 0x01ff0000
2382 #define A4XX_SP_VS_OUT_REG_B_REGID__SHIFT 16
2383 static inline uint32_t A4XX_SP_VS_OUT_REG_B_REGID(uint32_t val)
2384 {
2385 return ((val) << A4XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_B_REGID__MASK;
2386 }
2387 #define A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x1e000000
2388 #define A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 25
2389 static inline uint32_t A4XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
2390 {
2391 return ((val) << A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK;
2392 }
2393
2394 static inline uint32_t REG_A4XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d8 + 0x1*i0; }
2395
2396 static inline uint32_t REG_A4XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d8 + 0x1*i0; }
2397 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
2398 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0
2399 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)
2400 {
2401 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK;
2402 }
2403 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
2404 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8
2405 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)
2406 {
2407 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK;
2408 }
2409 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
2410 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16
2411 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)
2412 {
2413 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK;
2414 }
2415 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
2416 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24
2417 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
2418 {
2419 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK;
2420 }
2421
2422 #define REG_A4XX_SP_VS_OBJ_OFFSET_REG 0x000022e0
2423 #define A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
2424 #define A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
2425 static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
2426 {
2427 return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
2428 }
2429 #define A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
2430 #define A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
2431 static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
2432 {
2433 return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
2434 }
2435
2436 #define REG_A4XX_SP_VS_OBJ_START 0x000022e1
2437
2438 #define REG_A4XX_SP_VS_PVT_MEM_PARAM 0x000022e2
2439
2440 #define REG_A4XX_SP_VS_PVT_MEM_ADDR 0x000022e3
2441
2442 #define REG_A4XX_SP_VS_LENGTH_REG 0x000022e5
2443
2444 #define REG_A4XX_SP_FS_CTRL_REG0 0x000022e8
2445 #define A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001
2446 #define A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0
2447 static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
2448 {
2449 return ((val) << A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK;
2450 }
2451 #define A4XX_SP_FS_CTRL_REG0_VARYING 0x00000002
2452 #define A4XX_SP_FS_CTRL_REG0_CACHEINVALID 0x00000004
2453 #define A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
2454 #define A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
2455 static inline uint32_t A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
2456 {
2457 return ((val) << A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
2458 }
2459 #define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
2460 #define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
2461 static inline uint32_t A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
2462 {
2463 return ((val) << A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
2464 }
2465 #define A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000
2466 #define A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18
2467 static inline uint32_t A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val)
2468 {
2469 return ((val) << A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK;
2470 }
2471 #define A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000
2472 #define A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20
2473 static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
2474 {
2475 return ((val) << A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
2476 }
2477 #define A4XX_SP_FS_CTRL_REG0_SUPERTHREADMODE 0x00200000
2478 #define A4XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00400000
2479
2480 #define REG_A4XX_SP_FS_CTRL_REG1 0x000022e9
2481 #define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK 0x000000ff
2482 #define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT 0
2483 static inline uint32_t A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val)
2484 {
2485 return ((val) << A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK;
2486 }
2487 #define A4XX_SP_FS_CTRL_REG1_FACENESS 0x00080000
2488 #define A4XX_SP_FS_CTRL_REG1_VARYING 0x00100000
2489 #define A4XX_SP_FS_CTRL_REG1_FRAGCOORD 0x00200000
2490
2491 #define REG_A4XX_SP_FS_OBJ_OFFSET_REG 0x000022ea
2492 #define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
2493 #define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
2494 static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
2495 {
2496 return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
2497 }
2498 #define A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
2499 #define A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
2500 static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
2501 {
2502 return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
2503 }
2504
2505 #define REG_A4XX_SP_FS_OBJ_START 0x000022eb
2506
2507 #define REG_A4XX_SP_FS_PVT_MEM_PARAM 0x000022ec
2508
2509 #define REG_A4XX_SP_FS_PVT_MEM_ADDR 0x000022ed
2510
2511 #define REG_A4XX_SP_FS_LENGTH_REG 0x000022ef
2512
2513 #define REG_A4XX_SP_FS_OUTPUT_REG 0x000022f0
2514 #define A4XX_SP_FS_OUTPUT_REG_MRT__MASK 0x0000000f
2515 #define A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT 0
2516 static inline uint32_t A4XX_SP_FS_OUTPUT_REG_MRT(uint32_t val)
2517 {
2518 return ((val) << A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_SP_FS_OUTPUT_REG_MRT__MASK;
2519 }
2520 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE 0x00000080
2521 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK 0x0000ff00
2522 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT 8
2523 static inline uint32_t A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val)
2524 {
2525 return ((val) << A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK;
2526 }
2527 #define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK 0xff000000
2528 #define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT 24
2529 static inline uint32_t A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID(uint32_t val)
2530 {
2531 return ((val) << A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK;
2532 }
2533
2534 static inline uint32_t REG_A4XX_SP_FS_MRT(uint32_t i0) { return 0x000022f1 + 0x1*i0; }
2535
2536 static inline uint32_t REG_A4XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f1 + 0x1*i0; }
2537 #define A4XX_SP_FS_MRT_REG_REGID__MASK 0x000000ff
2538 #define A4XX_SP_FS_MRT_REG_REGID__SHIFT 0
2539 static inline uint32_t A4XX_SP_FS_MRT_REG_REGID(uint32_t val)
2540 {
2541 return ((val) << A4XX_SP_FS_MRT_REG_REGID__SHIFT) & A4XX_SP_FS_MRT_REG_REGID__MASK;
2542 }
2543 #define A4XX_SP_FS_MRT_REG_HALF_PRECISION 0x00000100
2544 #define A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK 0x0003f000
2545 #define A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT 12
2546 static inline uint32_t A4XX_SP_FS_MRT_REG_MRTFORMAT(enum a4xx_color_fmt val)
2547 {
2548 return ((val) << A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT) & A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK;
2549 }
2550 #define A4XX_SP_FS_MRT_REG_COLOR_SRGB 0x00040000
2551
2552 #define REG_A4XX_SP_CS_CTRL_REG0 0x00002300
2553
2554 #define REG_A4XX_SP_CS_OBJ_OFFSET_REG 0x00002301
2555
2556 #define REG_A4XX_SP_CS_OBJ_START 0x00002302
2557
2558 #define REG_A4XX_SP_CS_PVT_MEM_PARAM 0x00002303
2559
2560 #define REG_A4XX_SP_CS_PVT_MEM_ADDR 0x00002304
2561
2562 #define REG_A4XX_SP_CS_PVT_MEM_SIZE 0x00002305
2563
2564 #define REG_A4XX_SP_CS_LENGTH_REG 0x00002306
2565
2566 #define REG_A4XX_SP_HS_OBJ_OFFSET_REG 0x0000230d
2567 #define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
2568 #define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
2569 static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
2570 {
2571 return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
2572 }
2573 #define A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
2574 #define A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
2575 static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
2576 {
2577 return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
2578 }
2579
2580 #define REG_A4XX_SP_HS_OBJ_START 0x0000230e
2581
2582 #define REG_A4XX_SP_HS_PVT_MEM_PARAM 0x0000230f
2583
2584 #define REG_A4XX_SP_HS_PVT_MEM_ADDR 0x00002310
2585
2586 #define REG_A4XX_SP_HS_LENGTH_REG 0x00002312
2587
2588 #define REG_A4XX_SP_DS_PARAM_REG 0x0000231a
2589 #define A4XX_SP_DS_PARAM_REG_POSREGID__MASK 0x000000ff
2590 #define A4XX_SP_DS_PARAM_REG_POSREGID__SHIFT 0
2591 static inline uint32_t A4XX_SP_DS_PARAM_REG_POSREGID(uint32_t val)
2592 {
2593 return ((val) << A4XX_SP_DS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_DS_PARAM_REG_POSREGID__MASK;
2594 }
2595 #define A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK 0xfff00000
2596 #define A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__SHIFT 20
2597 static inline uint32_t A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR(uint32_t val)
2598 {
2599 return ((val) << A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK;
2600 }
2601
2602 static inline uint32_t REG_A4XX_SP_DS_OUT(uint32_t i0) { return 0x0000231b + 0x1*i0; }
2603
2604 static inline uint32_t REG_A4XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000231b + 0x1*i0; }
2605 #define A4XX_SP_DS_OUT_REG_A_REGID__MASK 0x000001ff
2606 #define A4XX_SP_DS_OUT_REG_A_REGID__SHIFT 0
2607 static inline uint32_t A4XX_SP_DS_OUT_REG_A_REGID(uint32_t val)
2608 {
2609 return ((val) << A4XX_SP_DS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_DS_OUT_REG_A_REGID__MASK;
2610 }
2611 #define A4XX_SP_DS_OUT_REG_A_COMPMASK__MASK 0x00001e00
2612 #define A4XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT 9
2613 static inline uint32_t A4XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val)
2614 {
2615 return ((val) << A4XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_DS_OUT_REG_A_COMPMASK__MASK;
2616 }
2617 #define A4XX_SP_DS_OUT_REG_B_REGID__MASK 0x01ff0000
2618 #define A4XX_SP_DS_OUT_REG_B_REGID__SHIFT 16
2619 static inline uint32_t A4XX_SP_DS_OUT_REG_B_REGID(uint32_t val)
2620 {
2621 return ((val) << A4XX_SP_DS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_DS_OUT_REG_B_REGID__MASK;
2622 }
2623 #define A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK 0x1e000000
2624 #define A4XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT 25
2625 static inline uint32_t A4XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val)
2626 {
2627 return ((val) << A4XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK;
2628 }
2629
2630 static inline uint32_t REG_A4XX_SP_DS_VPC_DST(uint32_t i0) { return 0x0000232c + 0x1*i0; }
2631
2632 static inline uint32_t REG_A4XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000232c + 0x1*i0; }
2633 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
2634 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT 0
2635 static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val)
2636 {
2637 return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK;
2638 }
2639 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
2640 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT 8
2641 static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val)
2642 {
2643 return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK;
2644 }
2645 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
2646 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT 16
2647 static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val)
2648 {
2649 return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK;
2650 }
2651 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
2652 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT 24
2653 static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val)
2654 {
2655 return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK;
2656 }
2657
2658 #define REG_A4XX_SP_DS_OBJ_OFFSET_REG 0x00002334
2659 #define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
2660 #define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
2661 static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
2662 {
2663 return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
2664 }
2665 #define A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
2666 #define A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
2667 static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
2668 {
2669 return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
2670 }
2671
2672 #define REG_A4XX_SP_DS_OBJ_START 0x00002335
2673
2674 #define REG_A4XX_SP_DS_PVT_MEM_PARAM 0x00002336
2675
2676 #define REG_A4XX_SP_DS_PVT_MEM_ADDR 0x00002337
2677
2678 #define REG_A4XX_SP_DS_LENGTH_REG 0x00002339
2679
2680 #define REG_A4XX_SP_GS_PARAM_REG 0x00002341
2681 #define A4XX_SP_GS_PARAM_REG_POSREGID__MASK 0x000000ff
2682 #define A4XX_SP_GS_PARAM_REG_POSREGID__SHIFT 0
2683 static inline uint32_t A4XX_SP_GS_PARAM_REG_POSREGID(uint32_t val)
2684 {
2685 return ((val) << A4XX_SP_GS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_GS_PARAM_REG_POSREGID__MASK;
2686 }
2687 #define A4XX_SP_GS_PARAM_REG_PRIMREGID__MASK 0x0000ff00
2688 #define A4XX_SP_GS_PARAM_REG_PRIMREGID__SHIFT 8
2689 static inline uint32_t A4XX_SP_GS_PARAM_REG_PRIMREGID(uint32_t val)
2690 {
2691 return ((val) << A4XX_SP_GS_PARAM_REG_PRIMREGID__SHIFT) & A4XX_SP_GS_PARAM_REG_PRIMREGID__MASK;
2692 }
2693 #define A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK 0xfff00000
2694 #define A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__SHIFT 20
2695 static inline uint32_t A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR(uint32_t val)
2696 {
2697 return ((val) << A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK;
2698 }
2699
2700 static inline uint32_t REG_A4XX_SP_GS_OUT(uint32_t i0) { return 0x00002342 + 0x1*i0; }
2701
2702 static inline uint32_t REG_A4XX_SP_GS_OUT_REG(uint32_t i0) { return 0x00002342 + 0x1*i0; }
2703 #define A4XX_SP_GS_OUT_REG_A_REGID__MASK 0x000001ff
2704 #define A4XX_SP_GS_OUT_REG_A_REGID__SHIFT 0
2705 static inline uint32_t A4XX_SP_GS_OUT_REG_A_REGID(uint32_t val)
2706 {
2707 return ((val) << A4XX_SP_GS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_GS_OUT_REG_A_REGID__MASK;
2708 }
2709 #define A4XX_SP_GS_OUT_REG_A_COMPMASK__MASK 0x00001e00
2710 #define A4XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT 9
2711 static inline uint32_t A4XX_SP_GS_OUT_REG_A_COMPMASK(uint32_t val)
2712 {
2713 return ((val) << A4XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_GS_OUT_REG_A_COMPMASK__MASK;
2714 }
2715 #define A4XX_SP_GS_OUT_REG_B_REGID__MASK 0x01ff0000
2716 #define A4XX_SP_GS_OUT_REG_B_REGID__SHIFT 16
2717 static inline uint32_t A4XX_SP_GS_OUT_REG_B_REGID(uint32_t val)
2718 {
2719 return ((val) << A4XX_SP_GS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_GS_OUT_REG_B_REGID__MASK;
2720 }
2721 #define A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK 0x1e000000
2722 #define A4XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT 25
2723 static inline uint32_t A4XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val)
2724 {
2725 return ((val) << A4XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK;
2726 }
2727
2728 static inline uint32_t REG_A4XX_SP_GS_VPC_DST(uint32_t i0) { return 0x00002353 + 0x1*i0; }
2729
2730 static inline uint32_t REG_A4XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x00002353 + 0x1*i0; }
2731 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
2732 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT 0
2733 static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC0(uint32_t val)
2734 {
2735 return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK;
2736 }
2737 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
2738 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT 8
2739 static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC1(uint32_t val)
2740 {
2741 return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK;
2742 }
2743 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
2744 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT 16
2745 static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC2(uint32_t val)
2746 {
2747 return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK;
2748 }
2749 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
2750 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT 24
2751 static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val)
2752 {
2753 return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK;
2754 }
2755
2756 #define REG_A4XX_SP_GS_OBJ_OFFSET_REG 0x0000235b
2757 #define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
2758 #define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
2759 static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
2760 {
2761 return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
2762 }
2763 #define A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
2764 #define A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
2765 static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
2766 {
2767 return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
2768 }
2769
2770 #define REG_A4XX_SP_GS_OBJ_START 0x0000235c
2771
2772 #define REG_A4XX_SP_GS_PVT_MEM_PARAM 0x0000235d
2773
2774 #define REG_A4XX_SP_GS_PVT_MEM_ADDR 0x0000235e
2775
2776 #define REG_A4XX_SP_GS_LENGTH_REG 0x00002360
2777
2778 #define REG_A4XX_VPC_DEBUG_RAM_SEL 0x00000e60
2779
2780 #define REG_A4XX_VPC_DEBUG_RAM_READ 0x00000e61
2781
2782 #define REG_A4XX_VPC_DEBUG_ECO_CONTROL 0x00000e64
2783
2784 #define REG_A4XX_VPC_PERFCTR_VPC_SEL_0 0x00000e65
2785
2786 #define REG_A4XX_VPC_PERFCTR_VPC_SEL_1 0x00000e66
2787
2788 #define REG_A4XX_VPC_PERFCTR_VPC_SEL_2 0x00000e67
2789
2790 #define REG_A4XX_VPC_PERFCTR_VPC_SEL_3 0x00000e68
2791
2792 #define REG_A4XX_VPC_ATTR 0x00002140
2793 #define A4XX_VPC_ATTR_TOTALATTR__MASK 0x000001ff
2794 #define A4XX_VPC_ATTR_TOTALATTR__SHIFT 0
2795 static inline uint32_t A4XX_VPC_ATTR_TOTALATTR(uint32_t val)
2796 {
2797 return ((val) << A4XX_VPC_ATTR_TOTALATTR__SHIFT) & A4XX_VPC_ATTR_TOTALATTR__MASK;
2798 }
2799 #define A4XX_VPC_ATTR_PSIZE 0x00000200
2800 #define A4XX_VPC_ATTR_THRDASSIGN__MASK 0x00003000
2801 #define A4XX_VPC_ATTR_THRDASSIGN__SHIFT 12
2802 static inline uint32_t A4XX_VPC_ATTR_THRDASSIGN(uint32_t val)
2803 {
2804 return ((val) << A4XX_VPC_ATTR_THRDASSIGN__SHIFT) & A4XX_VPC_ATTR_THRDASSIGN__MASK;
2805 }
2806 #define A4XX_VPC_ATTR_ENABLE 0x02000000
2807
2808 #define REG_A4XX_VPC_PACK 0x00002141
2809 #define A4XX_VPC_PACK_NUMBYPASSVAR__MASK 0x000000ff
2810 #define A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT 0
2811 static inline uint32_t A4XX_VPC_PACK_NUMBYPASSVAR(uint32_t val)
2812 {
2813 return ((val) << A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT) & A4XX_VPC_PACK_NUMBYPASSVAR__MASK;
2814 }
2815 #define A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK 0x0000ff00
2816 #define A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT 8
2817 static inline uint32_t A4XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val)
2818 {
2819 return ((val) << A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT) & A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK;
2820 }
2821 #define A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK 0x00ff0000
2822 #define A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT 16
2823 static inline uint32_t A4XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val)
2824 {
2825 return ((val) << A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK;
2826 }
2827
2828 static inline uint32_t REG_A4XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002142 + 0x1*i0; }
2829
2830 static inline uint32_t REG_A4XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002142 + 0x1*i0; }
2831
2832 static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x0000214a + 0x1*i0; }
2833
2834 static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000214a + 0x1*i0; }
2835
2836 #define REG_A4XX_VPC_SO_FLUSH_WADDR_3 0x0000216e
2837
2838 #define REG_A4XX_VSC_BIN_SIZE 0x00000c00
2839 #define A4XX_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f
2840 #define A4XX_VSC_BIN_SIZE_WIDTH__SHIFT 0
2841 static inline uint32_t A4XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
2842 {
2843 return ((val >> 5) << A4XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A4XX_VSC_BIN_SIZE_WIDTH__MASK;
2844 }
2845 #define A4XX_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0
2846 #define A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT 5
2847 static inline uint32_t A4XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
2848 {
2849 return ((val >> 5) << A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A4XX_VSC_BIN_SIZE_HEIGHT__MASK;
2850 }
2851
2852 #define REG_A4XX_VSC_SIZE_ADDRESS 0x00000c01
2853
2854 #define REG_A4XX_VSC_SIZE_ADDRESS2 0x00000c02
2855
2856 #define REG_A4XX_VSC_DEBUG_ECO_CONTROL 0x00000c03
2857
2858 static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c08 + 0x1*i0; }
2859
2860 static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c08 + 0x1*i0; }
2861 #define A4XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff
2862 #define A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0
2863 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_X(uint32_t val)
2864 {
2865 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_X__MASK;
2866 }
2867 #define A4XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00
2868 #define A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10
2869 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val)
2870 {
2871 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_Y__MASK;
2872 }
2873 #define A4XX_VSC_PIPE_CONFIG_REG_W__MASK 0x00f00000
2874 #define A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20
2875 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_W(uint32_t val)
2876 {
2877 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_W__MASK;
2878 }
2879 #define A4XX_VSC_PIPE_CONFIG_REG_H__MASK 0x0f000000
2880 #define A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT 24
2881 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_H(uint32_t val)
2882 {
2883 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_H__MASK;
2884 }
2885
2886 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
2887
2888 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
2889
2890 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c18 + 0x1*i0; }
2891
2892 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c18 + 0x1*i0; }
2893
2894 #define REG_A4XX_VSC_PIPE_PARTIAL_POSN_1 0x00000c41
2895
2896 #define REG_A4XX_VSC_PERFCTR_VSC_SEL_0 0x00000c50
2897
2898 #define REG_A4XX_VSC_PERFCTR_VSC_SEL_1 0x00000c51
2899
2900 #define REG_A4XX_VFD_DEBUG_CONTROL 0x00000e40
2901
2902 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_0 0x00000e43
2903
2904 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_1 0x00000e44
2905
2906 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_2 0x00000e45
2907
2908 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_3 0x00000e46
2909
2910 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_4 0x00000e47
2911
2912 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_5 0x00000e48
2913
2914 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_6 0x00000e49
2915
2916 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_7 0x00000e4a
2917
2918 #define REG_A4XX_VGT_CL_INITIATOR 0x000021d0
2919
2920 #define REG_A4XX_VGT_EVENT_INITIATOR 0x000021d9
2921
2922 #define REG_A4XX_VFD_CONTROL_0 0x00002200
2923 #define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK 0x000000ff
2924 #define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT 0
2925 static inline uint32_t A4XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val)
2926 {
2927 return ((val) << A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT) & A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK;
2928 }
2929 #define A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK 0x0001fe00
2930 #define A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT 9
2931 static inline uint32_t A4XX_VFD_CONTROL_0_BYPASSATTROVS(uint32_t val)
2932 {
2933 return ((val) << A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT) & A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK;
2934 }
2935 #define A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK 0x03f00000
2936 #define A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT 20
2937 static inline uint32_t A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val)
2938 {
2939 return ((val) << A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK;
2940 }
2941 #define A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK 0xfc000000
2942 #define A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT 26
2943 static inline uint32_t A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val)
2944 {
2945 return ((val) << A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK;
2946 }
2947
2948 #define REG_A4XX_VFD_CONTROL_1 0x00002201
2949 #define A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK 0x0000ffff
2950 #define A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT 0
2951 static inline uint32_t A4XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val)
2952 {
2953 return ((val) << A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT) & A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK;
2954 }
2955 #define A4XX_VFD_CONTROL_1_REGID4VTX__MASK 0x00ff0000
2956 #define A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT 16
2957 static inline uint32_t A4XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)
2958 {
2959 return ((val) << A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A4XX_VFD_CONTROL_1_REGID4VTX__MASK;
2960 }
2961 #define A4XX_VFD_CONTROL_1_REGID4INST__MASK 0xff000000
2962 #define A4XX_VFD_CONTROL_1_REGID4INST__SHIFT 24
2963 static inline uint32_t A4XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
2964 {
2965 return ((val) << A4XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A4XX_VFD_CONTROL_1_REGID4INST__MASK;
2966 }
2967
2968 #define REG_A4XX_VFD_CONTROL_2 0x00002202
2969
2970 #define REG_A4XX_VFD_CONTROL_3 0x00002203
2971 #define A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK 0x0000ff00
2972 #define A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT 8
2973 static inline uint32_t A4XX_VFD_CONTROL_3_REGID_VTXCNT(uint32_t val)
2974 {
2975 return ((val) << A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT) & A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK;
2976 }
2977 #define A4XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000
2978 #define A4XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16
2979 static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val)
2980 {
2981 return ((val) << A4XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A4XX_VFD_CONTROL_3_REGID_TESSX__MASK;
2982 }
2983 #define A4XX_VFD_CONTROL_3_REGID_TESSY__MASK 0xff000000
2984 #define A4XX_VFD_CONTROL_3_REGID_TESSY__SHIFT 24
2985 static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val)
2986 {
2987 return ((val) << A4XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A4XX_VFD_CONTROL_3_REGID_TESSY__MASK;
2988 }
2989
2990 #define REG_A4XX_VFD_CONTROL_4 0x00002204
2991
2992 #define REG_A4XX_VFD_INDEX_OFFSET 0x00002208
2993
2994 static inline uint32_t REG_A4XX_VFD_FETCH(uint32_t i0) { return 0x0000220a + 0x4*i0; }
2995
2996 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x0000220a + 0x4*i0; }
2997 #define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK 0x0000007f
2998 #define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT 0
2999 static inline uint32_t A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val)
3000 {
3001 return ((val) << A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK;
3002 }
3003 #define A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK 0x0001ff80
3004 #define A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT 7
3005 static inline uint32_t A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val)
3006 {
3007 return ((val) << A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK;
3008 }
3009 #define A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT 0x00080000
3010 #define A4XX_VFD_FETCH_INSTR_0_INSTANCED 0x00100000
3011
3012 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x0000220b + 0x4*i0; }
3013
3014 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_2(uint32_t i0) { return 0x0000220c + 0x4*i0; }
3015 #define A4XX_VFD_FETCH_INSTR_2_SIZE__MASK 0xffffffff
3016 #define A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT 0
3017 static inline uint32_t A4XX_VFD_FETCH_INSTR_2_SIZE(uint32_t val)
3018 {
3019 return ((val) << A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_2_SIZE__MASK;
3020 }
3021
3022 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_3(uint32_t i0) { return 0x0000220d + 0x4*i0; }
3023 #define A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK 0x000001ff
3024 #define A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT 0
3025 static inline uint32_t A4XX_VFD_FETCH_INSTR_3_STEPRATE(uint32_t val)
3026 {
3027 return ((val) << A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT) & A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK;
3028 }
3029
3030 static inline uint32_t REG_A4XX_VFD_DECODE(uint32_t i0) { return 0x0000228a + 0x1*i0; }
3031
3032 static inline uint32_t REG_A4XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000228a + 0x1*i0; }
3033 #define A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK 0x0000000f
3034 #define A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT 0
3035 static inline uint32_t A4XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val)
3036 {
3037 return ((val) << A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT) & A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK;
3038 }
3039 #define A4XX_VFD_DECODE_INSTR_CONSTFILL 0x00000010
3040 #define A4XX_VFD_DECODE_INSTR_FORMAT__MASK 0x00000fc0
3041 #define A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT 6
3042 static inline uint32_t A4XX_VFD_DECODE_INSTR_FORMAT(enum a4xx_vtx_fmt val)
3043 {
3044 return ((val) << A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A4XX_VFD_DECODE_INSTR_FORMAT__MASK;
3045 }
3046 #define A4XX_VFD_DECODE_INSTR_REGID__MASK 0x000ff000
3047 #define A4XX_VFD_DECODE_INSTR_REGID__SHIFT 12
3048 static inline uint32_t A4XX_VFD_DECODE_INSTR_REGID(uint32_t val)
3049 {
3050 return ((val) << A4XX_VFD_DECODE_INSTR_REGID__SHIFT) & A4XX_VFD_DECODE_INSTR_REGID__MASK;
3051 }
3052 #define A4XX_VFD_DECODE_INSTR_INT 0x00100000
3053 #define A4XX_VFD_DECODE_INSTR_SWAP__MASK 0x00c00000
3054 #define A4XX_VFD_DECODE_INSTR_SWAP__SHIFT 22
3055 static inline uint32_t A4XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)
3056 {
3057 return ((val) << A4XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A4XX_VFD_DECODE_INSTR_SWAP__MASK;
3058 }
3059 #define A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK 0x1f000000
3060 #define A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT 24
3061 static inline uint32_t A4XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val)
3062 {
3063 return ((val) << A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT) & A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK;
3064 }
3065 #define A4XX_VFD_DECODE_INSTR_LASTCOMPVALID 0x20000000
3066 #define A4XX_VFD_DECODE_INSTR_SWITCHNEXT 0x40000000
3067
3068 #define REG_A4XX_TPL1_DEBUG_ECO_CONTROL 0x00000f00
3069
3070 #define REG_A4XX_TPL1_TP_MODE_CONTROL 0x00000f03
3071
3072 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_0 0x00000f04
3073
3074 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_1 0x00000f05
3075
3076 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_2 0x00000f06
3077
3078 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_3 0x00000f07
3079
3080 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_4 0x00000f08
3081
3082 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_5 0x00000f09
3083
3084 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_6 0x00000f0a
3085
3086 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_7 0x00000f0b
3087
3088 #define REG_A4XX_TPL1_TP_TEX_OFFSET 0x00002380
3089
3090 #define REG_A4XX_TPL1_TP_TEX_COUNT 0x00002381
3091 #define A4XX_TPL1_TP_TEX_COUNT_VS__MASK 0x000000ff
3092 #define A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT 0
3093 static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_VS(uint32_t val)
3094 {
3095 return ((val) << A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_VS__MASK;
3096 }
3097 #define A4XX_TPL1_TP_TEX_COUNT_HS__MASK 0x0000ff00
3098 #define A4XX_TPL1_TP_TEX_COUNT_HS__SHIFT 8
3099 static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_HS(uint32_t val)
3100 {
3101 return ((val) << A4XX_TPL1_TP_TEX_COUNT_HS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_HS__MASK;
3102 }
3103 #define A4XX_TPL1_TP_TEX_COUNT_DS__MASK 0x00ff0000
3104 #define A4XX_TPL1_TP_TEX_COUNT_DS__SHIFT 16
3105 static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_DS(uint32_t val)
3106 {
3107 return ((val) << A4XX_TPL1_TP_TEX_COUNT_DS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_DS__MASK;
3108 }
3109 #define A4XX_TPL1_TP_TEX_COUNT_GS__MASK 0xff000000
3110 #define A4XX_TPL1_TP_TEX_COUNT_GS__SHIFT 24
3111 static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_GS(uint32_t val)
3112 {
3113 return ((val) << A4XX_TPL1_TP_TEX_COUNT_GS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_GS__MASK;
3114 }
3115
3116 #define REG_A4XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR 0x00002384
3117
3118 #define REG_A4XX_TPL1_TP_HS_BORDER_COLOR_BASE_ADDR 0x00002387
3119
3120 #define REG_A4XX_TPL1_TP_DS_BORDER_COLOR_BASE_ADDR 0x0000238a
3121
3122 #define REG_A4XX_TPL1_TP_GS_BORDER_COLOR_BASE_ADDR 0x0000238d
3123
3124 #define REG_A4XX_TPL1_TP_FS_TEX_COUNT 0x000023a0
3125
3126 #define REG_A4XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR 0x000023a1
3127
3128 #define REG_A4XX_TPL1_TP_CS_BORDER_COLOR_BASE_ADDR 0x000023a4
3129
3130 #define REG_A4XX_TPL1_TP_CS_SAMPLER_BASE_ADDR 0x000023a5
3131
3132 #define REG_A4XX_TPL1_TP_CS_TEXMEMOBJ_BASE_ADDR 0x000023a6
3133
3134 #define REG_A4XX_GRAS_TSE_STATUS 0x00000c80
3135
3136 #define REG_A4XX_GRAS_DEBUG_ECO_CONTROL 0x00000c81
3137
3138 #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_0 0x00000c88
3139
3140 #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_1 0x00000c89
3141
3142 #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_2 0x00000c8a
3143
3144 #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_3 0x00000c8b
3145
3146 #define REG_A4XX_GRAS_PERFCTR_RAS_SEL_0 0x00000c8c
3147
3148 #define REG_A4XX_GRAS_PERFCTR_RAS_SEL_1 0x00000c8d
3149
3150 #define REG_A4XX_GRAS_PERFCTR_RAS_SEL_2 0x00000c8e
3151
3152 #define REG_A4XX_GRAS_PERFCTR_RAS_SEL_3 0x00000c8f
3153
3154 #define REG_A4XX_GRAS_CL_CLIP_CNTL 0x00002000
3155 #define A4XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE 0x00008000
3156 #define A4XX_GRAS_CL_CLIP_CNTL_ZNEAR_CLIP_DISABLE 0x00010000
3157 #define A4XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE 0x00020000
3158 #define A4XX_GRAS_CL_CLIP_CNTL_ZERO_GB_SCALE_Z 0x00400000
3159
3160 #define REG_A4XX_GRAS_CNTL 0x00002003
3161 #define A4XX_GRAS_CNTL_IJ_PERSP 0x00000001
3162 #define A4XX_GRAS_CNTL_IJ_LINEAR 0x00000002
3163
3164 #define REG_A4XX_GRAS_CL_GB_CLIP_ADJ 0x00002004
3165 #define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK 0x000003ff
3166 #define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT 0
3167 static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val)
3168 {
3169 return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK;
3170 }
3171 #define A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK 0x000ffc00
3172 #define A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT 10
3173 static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val)
3174 {
3175 return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK;
3176 }
3177
3178 #define REG_A4XX_GRAS_CL_VPORT_XOFFSET_0 0x00002008
3179 #define A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK 0xffffffff
3180 #define A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT 0
3181 static inline uint32_t A4XX_GRAS_CL_VPORT_XOFFSET_0(float val)
3182 {
3183 return ((fui(val)) << A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK;
3184 }
3185
3186 #define REG_A4XX_GRAS_CL_VPORT_XSCALE_0 0x00002009
3187 #define A4XX_GRAS_CL_VPORT_XSCALE_0__MASK 0xffffffff
3188 #define A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT 0
3189 static inline uint32_t A4XX_GRAS_CL_VPORT_XSCALE_0(float val)
3190 {
3191 return ((fui(val)) << A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_XSCALE_0__MASK;
3192 }
3193
3194 #define REG_A4XX_GRAS_CL_VPORT_YOFFSET_0 0x0000200a
3195 #define A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK 0xffffffff
3196 #define A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT 0
3197 static inline uint32_t A4XX_GRAS_CL_VPORT_YOFFSET_0(float val)
3198 {
3199 return ((fui(val)) << A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK;
3200 }
3201
3202 #define REG_A4XX_GRAS_CL_VPORT_YSCALE_0 0x0000200b
3203 #define A4XX_GRAS_CL_VPORT_YSCALE_0__MASK 0xffffffff
3204 #define A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT 0
3205 static inline uint32_t A4XX_GRAS_CL_VPORT_YSCALE_0(float val)
3206 {
3207 return ((fui(val)) << A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_YSCALE_0__MASK;
3208 }
3209
3210 #define REG_A4XX_GRAS_CL_VPORT_ZOFFSET_0 0x0000200c
3211 #define A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK 0xffffffff
3212 #define A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT 0
3213 static inline uint32_t A4XX_GRAS_CL_VPORT_ZOFFSET_0(float val)
3214 {
3215 return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK;
3216 }
3217
3218 #define REG_A4XX_GRAS_CL_VPORT_ZSCALE_0 0x0000200d
3219 #define A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK 0xffffffff
3220 #define A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT 0
3221 static inline uint32_t A4XX_GRAS_CL_VPORT_ZSCALE_0(float val)
3222 {
3223 return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK;
3224 }
3225
3226 #define REG_A4XX_GRAS_SU_POINT_MINMAX 0x00002070
3227 #define A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff
3228 #define A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0
3229 static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MIN(float val)
3230 {
3231 return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK;
3232 }
3233 #define A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000
3234 #define A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16
3235 static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MAX(float val)
3236 {
3237 return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK;
3238 }
3239
3240 #define REG_A4XX_GRAS_SU_POINT_SIZE 0x00002071
3241 #define A4XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff
3242 #define A4XX_GRAS_SU_POINT_SIZE__SHIFT 0
3243 static inline uint32_t A4XX_GRAS_SU_POINT_SIZE(float val)
3244 {
3245 return ((((int32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_SIZE__SHIFT) & A4XX_GRAS_SU_POINT_SIZE__MASK;
3246 }
3247
3248 #define REG_A4XX_GRAS_ALPHA_CONTROL 0x00002073
3249 #define A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE 0x00000004
3250 #define A4XX_GRAS_ALPHA_CONTROL_FORCE_FRAGZ_TO_FS 0x00000008
3251
3252 #define REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE 0x00002074
3253 #define A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff
3254 #define A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0
3255 static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_SCALE(float val)
3256 {
3257 return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK;
3258 }
3259
3260 #define REG_A4XX_GRAS_SU_POLY_OFFSET_OFFSET 0x00002075
3261 #define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff
3262 #define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0
3263 static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
3264 {
3265 return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;
3266 }
3267
3268 #define REG_A4XX_GRAS_SU_POLY_OFFSET_CLAMP 0x00002076
3269 #define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK 0xffffffff
3270 #define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT 0
3271 static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_CLAMP(float val)
3272 {
3273 return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK;
3274 }
3275
3276 #define REG_A4XX_GRAS_DEPTH_CONTROL 0x00002077
3277 #define A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK 0x00000003
3278 #define A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT 0
3279 static inline uint32_t A4XX_GRAS_DEPTH_CONTROL_FORMAT(enum a4xx_depth_format val)
3280 {
3281 return ((val) << A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT) & A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK;
3282 }
3283
3284 #define REG_A4XX_GRAS_SU_MODE_CONTROL 0x00002078
3285 #define A4XX_GRAS_SU_MODE_CONTROL_CULL_FRONT 0x00000001
3286 #define A4XX_GRAS_SU_MODE_CONTROL_CULL_BACK 0x00000002
3287 #define A4XX_GRAS_SU_MODE_CONTROL_FRONT_CW 0x00000004
3288 #define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK 0x000007f8
3289 #define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT 3
3290 static inline uint32_t A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val)
3291 {
3292 return ((((int32_t)(val * 4.0))) << A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK;
3293 }
3294 #define A4XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET 0x00000800
3295 #define A4XX_GRAS_SU_MODE_CONTROL_MSAA_ENABLE 0x00002000
3296 #define A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS 0x00100000
3297
3298 #define REG_A4XX_GRAS_SC_CONTROL 0x0000207b
3299 #define A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK 0x0000000c
3300 #define A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT 2
3301 static inline uint32_t A4XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val)
3302 {
3303 return ((val) << A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK;
3304 }
3305 #define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK 0x00000380
3306 #define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT 7
3307 static inline uint32_t A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(uint32_t val)
3308 {
3309 return ((val) << A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT) & A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK;
3310 }
3311 #define A4XX_GRAS_SC_CONTROL_MSAA_DISABLE 0x00000800
3312 #define A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK 0x0000f000
3313 #define A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT 12
3314 static inline uint32_t A4XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val)
3315 {
3316 return ((val) << A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK;
3317 }
3318
3319 #define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL 0x0000207c
3320 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
3321 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff
3322 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT 0
3323 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val)
3324 {
3325 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK;
3326 }
3327 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000
3328 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16
3329 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val)
3330 {
3331 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK;
3332 }
3333
3334 #define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_BR 0x0000207d
3335 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
3336 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff
3337 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT 0
3338 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val)
3339 {
3340 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK;
3341 }
3342 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000
3343 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16
3344 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val)
3345 {
3346 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK;
3347 }
3348
3349 #define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000209c
3350 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
3351 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff
3352 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0
3353 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
3354 {
3355 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK;
3356 }
3357 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000
3358 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16
3359 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
3360 {
3361 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK;
3362 }
3363
3364 #define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_TL 0x0000209d
3365 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
3366 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff
3367 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0
3368 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
3369 {
3370 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK;
3371 }
3372 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000
3373 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16
3374 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
3375 {
3376 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK;
3377 }
3378
3379 #define REG_A4XX_GRAS_SC_EXTENT_WINDOW_BR 0x0000209e
3380 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_WINDOW_OFFSET_DISABLE 0x80000000
3381 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK 0x00007fff
3382 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT 0
3383 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_X(uint32_t val)
3384 {
3385 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK;
3386 }
3387 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK 0x7fff0000
3388 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT 16
3389 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y(uint32_t val)
3390 {
3391 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK;
3392 }
3393
3394 #define REG_A4XX_GRAS_SC_EXTENT_WINDOW_TL 0x0000209f
3395 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_WINDOW_OFFSET_DISABLE 0x80000000
3396 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK 0x00007fff
3397 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT 0
3398 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_X(uint32_t val)
3399 {
3400 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK;
3401 }
3402 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK 0x7fff0000
3403 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT 16
3404 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y(uint32_t val)
3405 {
3406 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK;
3407 }
3408
3409 #define REG_A4XX_UCHE_CACHE_MODE_CONTROL 0x00000e80
3410
3411 #define REG_A4XX_UCHE_TRAP_BASE_LO 0x00000e83
3412
3413 #define REG_A4XX_UCHE_TRAP_BASE_HI 0x00000e84
3414
3415 #define REG_A4XX_UCHE_CACHE_STATUS 0x00000e88
3416
3417 #define REG_A4XX_UCHE_INVALIDATE0 0x00000e8a
3418
3419 #define REG_A4XX_UCHE_INVALIDATE1 0x00000e8b
3420
3421 #define REG_A4XX_UCHE_CACHE_WAYS_VFD 0x00000e8c
3422
3423 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_0 0x00000e8e
3424
3425 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_1 0x00000e8f
3426
3427 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_2 0x00000e90
3428
3429 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_3 0x00000e91
3430
3431 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_4 0x00000e92
3432
3433 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_5 0x00000e93
3434
3435 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_6 0x00000e94
3436
3437 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000e95
3438
3439 #define REG_A4XX_HLSQ_TIMEOUT_THRESHOLD 0x00000e00
3440
3441 #define REG_A4XX_HLSQ_DEBUG_ECO_CONTROL 0x00000e04
3442
3443 #define REG_A4XX_HLSQ_MODE_CONTROL 0x00000e05
3444
3445 #define REG_A4XX_HLSQ_PERF_PIPE_MASK 0x00000e0e
3446
3447 #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_0 0x00000e06
3448
3449 #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_1 0x00000e07
3450
3451 #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_2 0x00000e08
3452
3453 #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_3 0x00000e09
3454
3455 #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_4 0x00000e0a
3456
3457 #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_5 0x00000e0b
3458
3459 #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_6 0x00000e0c
3460
3461 #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_7 0x00000e0d
3462
3463 #define REG_A4XX_HLSQ_CONTROL_0_REG 0x000023c0
3464 #define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000010
3465 #define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 4
3466 static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val)
3467 {
3468 return ((val) << A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK;
3469 }
3470 #define A4XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE 0x00000040
3471 #define A4XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART 0x00000200
3472 #define A4XX_HLSQ_CONTROL_0_REG_RESERVED2 0x00000400
3473 #define A4XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE 0x04000000
3474 #define A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK 0x08000000
3475 #define A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT 27
3476 static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val)
3477 {
3478 return ((val) << A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK;
3479 }
3480 #define A4XX_HLSQ_CONTROL_0_REG_LAZYUPDATEDISABLE 0x10000000
3481 #define A4XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE 0x20000000
3482 #define A4XX_HLSQ_CONTROL_0_REG_TPFULLUPDATE 0x40000000
3483 #define A4XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT 0x80000000
3484
3485 #define REG_A4XX_HLSQ_CONTROL_1_REG 0x000023c1
3486 #define A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK 0x00000040
3487 #define A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT 6
3488 static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val)
3489 {
3490 return ((val) << A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK;
3491 }
3492 #define A4XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE 0x00000100
3493 #define A4XX_HLSQ_CONTROL_1_REG_RESERVED1 0x00000200
3494 #define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK 0x00ff0000
3495 #define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT 16
3496 static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_COORDREGID(uint32_t val)
3497 {
3498 return ((val) << A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK;
3499 }
3500 #define A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK 0xff000000
3501 #define A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__SHIFT 24
3502 static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID(uint32_t val)
3503 {
3504 return ((val) << A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK;
3505 }
3506
3507 #define REG_A4XX_HLSQ_CONTROL_2_REG 0x000023c2
3508 #define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK 0xfc000000
3509 #define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT 26
3510 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val)
3511 {
3512 return ((val) << A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK;
3513 }
3514 #define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000003fc
3515 #define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 2
3516 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)
3517 {
3518 return ((val) << A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK;
3519 }
3520 #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK 0x0003fc00
3521 #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT 10
3522 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID(uint32_t val)
3523 {
3524 return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK;
3525 }
3526 #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK 0x03fc0000
3527 #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT 18
3528 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID(uint32_t val)
3529 {
3530 return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK;
3531 }
3532
3533 #define REG_A4XX_HLSQ_CONTROL_3_REG 0x000023c3
3534 #define A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK 0x000000ff
3535 #define A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT 0
3536 static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val)
3537 {
3538 return ((val) << A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK;
3539 }
3540 #define A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK 0x0000ff00
3541 #define A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT 8
3542 static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val)
3543 {
3544 return ((val) << A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK;
3545 }
3546 #define A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK 0x00ff0000
3547 #define A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT 16
3548 static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val)
3549 {
3550 return ((val) << A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK;
3551 }
3552 #define A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK 0xff000000
3553 #define A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT 24
3554 static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val)
3555 {
3556 return ((val) << A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK;
3557 }
3558
3559 #define REG_A4XX_HLSQ_CONTROL_4_REG 0x000023c4
3560 #define A4XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK 0x000000ff
3561 #define A4XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT 0
3562 static inline uint32_t A4XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val)
3563 {
3564 return ((val) << A4XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT) & A4XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK;
3565 }
3566 #define A4XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK 0x0000ff00
3567 #define A4XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT 8
3568 static inline uint32_t A4XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val)
3569 {
3570 return ((val) << A4XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT) & A4XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK;
3571 }
3572
3573 #define REG_A4XX_HLSQ_VS_CONTROL_REG 0x000023c5
3574 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
3575 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT 0
3576 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val)
3577 {
3578 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK;
3579 }
3580 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00
3581 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
3582 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
3583 {
3584 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
3585 }
3586 #define A4XX_HLSQ_VS_CONTROL_REG_SSBO_ENABLE 0x00008000
3587 #define A4XX_HLSQ_VS_CONTROL_REG_ENABLED 0x00010000
3588 #define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
3589 #define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
3590 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
3591 {
3592 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK;
3593 }
3594 #define A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
3595 #define A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT 24
3596 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val)
3597 {
3598 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK;
3599 }
3600
3601 #define REG_A4XX_HLSQ_FS_CONTROL_REG 0x000023c6
3602 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
3603 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT 0
3604 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val)
3605 {
3606 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK;
3607 }
3608 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00
3609 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
3610 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
3611 {
3612 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
3613 }
3614 #define A4XX_HLSQ_FS_CONTROL_REG_SSBO_ENABLE 0x00008000
3615 #define A4XX_HLSQ_FS_CONTROL_REG_ENABLED 0x00010000
3616 #define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
3617 #define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
3618 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
3619 {
3620 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK;
3621 }
3622 #define A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
3623 #define A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT 24
3624 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val)
3625 {
3626 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK;
3627 }
3628
3629 #define REG_A4XX_HLSQ_HS_CONTROL_REG 0x000023c7
3630 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
3631 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT 0
3632 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH(uint32_t val)
3633 {
3634 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK;
3635 }
3636 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00
3637 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
3638 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
3639 {
3640 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
3641 }
3642 #define A4XX_HLSQ_HS_CONTROL_REG_SSBO_ENABLE 0x00008000
3643 #define A4XX_HLSQ_HS_CONTROL_REG_ENABLED 0x00010000
3644 #define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
3645 #define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
3646 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
3647 {
3648 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK;
3649 }
3650 #define A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
3651 #define A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT 24
3652 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH(uint32_t val)
3653 {
3654 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK;
3655 }
3656
3657 #define REG_A4XX_HLSQ_DS_CONTROL_REG 0x000023c8
3658 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
3659 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT 0
3660 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH(uint32_t val)
3661 {
3662 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK;
3663 }
3664 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00
3665 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
3666 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
3667 {
3668 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
3669 }
3670 #define A4XX_HLSQ_DS_CONTROL_REG_SSBO_ENABLE 0x00008000
3671 #define A4XX_HLSQ_DS_CONTROL_REG_ENABLED 0x00010000
3672 #define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
3673 #define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
3674 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
3675 {
3676 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK;
3677 }
3678 #define A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
3679 #define A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT 24
3680 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH(uint32_t val)
3681 {
3682 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK;
3683 }
3684
3685 #define REG_A4XX_HLSQ_GS_CONTROL_REG 0x000023c9
3686 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
3687 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT 0
3688 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH(uint32_t val)
3689 {
3690 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK;
3691 }
3692 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00
3693 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
3694 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
3695 {
3696 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
3697 }
3698 #define A4XX_HLSQ_GS_CONTROL_REG_SSBO_ENABLE 0x00008000
3699 #define A4XX_HLSQ_GS_CONTROL_REG_ENABLED 0x00010000
3700 #define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
3701 #define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
3702 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
3703 {
3704 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK;
3705 }
3706 #define A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
3707 #define A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT 24
3708 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val)
3709 {
3710 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK;
3711 }
3712
3713 #define REG_A4XX_HLSQ_CS_CONTROL_REG 0x000023ca
3714 #define A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
3715 #define A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH__SHIFT 0
3716 static inline uint32_t A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH(uint32_t val)
3717 {
3718 return ((val) << A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH__MASK;
3719 }
3720 #define A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00
3721 #define A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
3722 static inline uint32_t A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
3723 {
3724 return ((val) << A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
3725 }
3726 #define A4XX_HLSQ_CS_CONTROL_REG_SSBO_ENABLE 0x00008000
3727 #define A4XX_HLSQ_CS_CONTROL_REG_ENABLED 0x00010000
3728 #define A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
3729 #define A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
3730 static inline uint32_t A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
3731 {
3732 return ((val) << A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET__MASK;
3733 }
3734 #define A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
3735 #define A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH__SHIFT 24
3736 static inline uint32_t A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH(uint32_t val)
3737 {
3738 return ((val) << A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH__MASK;
3739 }
3740
3741 #define REG_A4XX_HLSQ_CL_NDRANGE_0 0x000023cd
3742 #define A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM__MASK 0x00000003
3743 #define A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM__SHIFT 0
3744 static inline uint32_t A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM(uint32_t val)
3745 {
3746 return ((val) << A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM__SHIFT) & A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM__MASK;
3747 }
3748 #define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX__MASK 0x00000ffc
3749 #define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX__SHIFT 2
3750 static inline uint32_t A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX(uint32_t val)
3751 {
3752 return ((val) << A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX__SHIFT) & A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX__MASK;
3753 }
3754 #define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY__MASK 0x003ff000
3755 #define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY__SHIFT 12
3756 static inline uint32_t A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY(uint32_t val)
3757 {
3758 return ((val) << A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY__SHIFT) & A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY__MASK;
3759 }
3760 #define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ__MASK 0xffc00000
3761 #define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ__SHIFT 22
3762 static inline uint32_t A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ(uint32_t val)
3763 {
3764 return ((val) << A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ__SHIFT) & A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ__MASK;
3765 }
3766
3767 #define REG_A4XX_HLSQ_CL_NDRANGE_1 0x000023ce
3768 #define A4XX_HLSQ_CL_NDRANGE_1_SIZE_X__MASK 0xffffffff
3769 #define A4XX_HLSQ_CL_NDRANGE_1_SIZE_X__SHIFT 0
3770 static inline uint32_t A4XX_HLSQ_CL_NDRANGE_1_SIZE_X(uint32_t val)
3771 {
3772 return ((val) << A4XX_HLSQ_CL_NDRANGE_1_SIZE_X__SHIFT) & A4XX_HLSQ_CL_NDRANGE_1_SIZE_X__MASK;
3773 }
3774
3775 #define REG_A4XX_HLSQ_CL_NDRANGE_2 0x000023cf
3776
3777 #define REG_A4XX_HLSQ_CL_NDRANGE_3 0x000023d0
3778 #define A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y__MASK 0xffffffff
3779 #define A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y__SHIFT 0
3780 static inline uint32_t A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y(uint32_t val)
3781 {
3782 return ((val) << A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y__SHIFT) & A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y__MASK;
3783 }
3784
3785 #define REG_A4XX_HLSQ_CL_NDRANGE_4 0x000023d1
3786
3787 #define REG_A4XX_HLSQ_CL_NDRANGE_5 0x000023d2
3788 #define A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z__MASK 0xffffffff
3789 #define A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z__SHIFT 0
3790 static inline uint32_t A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z(uint32_t val)
3791 {
3792 return ((val) << A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z__SHIFT) & A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z__MASK;
3793 }
3794
3795 #define REG_A4XX_HLSQ_CL_NDRANGE_6 0x000023d3
3796
3797 #define REG_A4XX_HLSQ_CL_CONTROL_0 0x000023d4
3798 #define A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__MASK 0x000000ff
3799 #define A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__SHIFT 0
3800 static inline uint32_t A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID(uint32_t val)
3801 {
3802 return ((val) << A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__SHIFT) & A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__MASK;
3803 }
3804 #define A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID__MASK 0xff000000
3805 #define A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID__SHIFT 24
3806 static inline uint32_t A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID(uint32_t val)
3807 {
3808 return ((val) << A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID__SHIFT) & A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID__MASK;
3809 }
3810
3811 #define REG_A4XX_HLSQ_CL_CONTROL_1 0x000023d5
3812
3813 #define REG_A4XX_HLSQ_CL_KERNEL_CONST 0x000023d6
3814
3815 #define REG_A4XX_HLSQ_CL_KERNEL_GROUP_X 0x000023d7
3816
3817 #define REG_A4XX_HLSQ_CL_KERNEL_GROUP_Y 0x000023d8
3818
3819 #define REG_A4XX_HLSQ_CL_KERNEL_GROUP_Z 0x000023d9
3820
3821 #define REG_A4XX_HLSQ_CL_WG_OFFSET 0x000023da
3822
3823 #define REG_A4XX_HLSQ_UPDATE_CONTROL 0x000023db
3824
3825 #define REG_A4XX_PC_BINNING_COMMAND 0x00000d00
3826 #define A4XX_PC_BINNING_COMMAND_BINNING_ENABLE 0x00000001
3827
3828 #define REG_A4XX_PC_TESSFACTOR_ADDR 0x00000d08
3829
3830 #define REG_A4XX_PC_DRAWCALL_SETUP_OVERRIDE 0x00000d0c
3831
3832 #define REG_A4XX_PC_PERFCTR_PC_SEL_0 0x00000d10
3833
3834 #define REG_A4XX_PC_PERFCTR_PC_SEL_1 0x00000d11
3835
3836 #define REG_A4XX_PC_PERFCTR_PC_SEL_2 0x00000d12
3837
3838 #define REG_A4XX_PC_PERFCTR_PC_SEL_3 0x00000d13
3839
3840 #define REG_A4XX_PC_PERFCTR_PC_SEL_4 0x00000d14
3841
3842 #define REG_A4XX_PC_PERFCTR_PC_SEL_5 0x00000d15
3843
3844 #define REG_A4XX_PC_PERFCTR_PC_SEL_6 0x00000d16
3845
3846 #define REG_A4XX_PC_PERFCTR_PC_SEL_7 0x00000d17
3847
3848 #define REG_A4XX_PC_BIN_BASE 0x000021c0
3849
3850 #define REG_A4XX_PC_VSTREAM_CONTROL 0x000021c2
3851 #define A4XX_PC_VSTREAM_CONTROL_SIZE__MASK 0x003f0000
3852 #define A4XX_PC_VSTREAM_CONTROL_SIZE__SHIFT 16
3853 static inline uint32_t A4XX_PC_VSTREAM_CONTROL_SIZE(uint32_t val)
3854 {
3855 return ((val) << A4XX_PC_VSTREAM_CONTROL_SIZE__SHIFT) & A4XX_PC_VSTREAM_CONTROL_SIZE__MASK;
3856 }
3857 #define A4XX_PC_VSTREAM_CONTROL_N__MASK 0x07c00000
3858 #define A4XX_PC_VSTREAM_CONTROL_N__SHIFT 22
3859 static inline uint32_t A4XX_PC_VSTREAM_CONTROL_N(uint32_t val)
3860 {
3861 return ((val) << A4XX_PC_VSTREAM_CONTROL_N__SHIFT) & A4XX_PC_VSTREAM_CONTROL_N__MASK;
3862 }
3863
3864 #define REG_A4XX_PC_PRIM_VTX_CNTL 0x000021c4
3865 #define A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK 0x0000000f
3866 #define A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT 0
3867 static inline uint32_t A4XX_PC_PRIM_VTX_CNTL_VAROUT(uint32_t val)
3868 {
3869 return ((val) << A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT) & A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK;
3870 }
3871 #define A4XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART 0x00100000
3872 #define A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST 0x02000000
3873 #define A4XX_PC_PRIM_VTX_CNTL_PSIZE 0x04000000
3874
3875 #define REG_A4XX_PC_PRIM_VTX_CNTL2 0x000021c5
3876 #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__MASK 0x00000007
3877 #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__SHIFT 0
3878 static inline uint32_t A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val)
3879 {
3880 return ((val) << A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__SHIFT) & A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__MASK;
3881 }
3882 #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__MASK 0x00000038
3883 #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__SHIFT 3
3884 static inline uint32_t A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val)
3885 {
3886 return ((val) << A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__SHIFT) & A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__MASK;
3887 }
3888 #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_ENABLE 0x00000040
3889
3890 #define REG_A4XX_PC_RESTART_INDEX 0x000021c6
3891
3892 #define REG_A4XX_PC_GS_PARAM 0x000021e5
3893 #define A4XX_PC_GS_PARAM_MAX_VERTICES__MASK 0x000003ff
3894 #define A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT 0
3895 static inline uint32_t A4XX_PC_GS_PARAM_MAX_VERTICES(uint32_t val)
3896 {
3897 return ((val) << A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT) & A4XX_PC_GS_PARAM_MAX_VERTICES__MASK;
3898 }
3899 #define A4XX_PC_GS_PARAM_INVOCATIONS__MASK 0x0000f800
3900 #define A4XX_PC_GS_PARAM_INVOCATIONS__SHIFT 11
3901 static inline uint32_t A4XX_PC_GS_PARAM_INVOCATIONS(uint32_t val)
3902 {
3903 return ((val) << A4XX_PC_GS_PARAM_INVOCATIONS__SHIFT) & A4XX_PC_GS_PARAM_INVOCATIONS__MASK;
3904 }
3905 #define A4XX_PC_GS_PARAM_PRIMTYPE__MASK 0x01800000
3906 #define A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT 23
3907 static inline uint32_t A4XX_PC_GS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val)
3908 {
3909 return ((val) << A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT) & A4XX_PC_GS_PARAM_PRIMTYPE__MASK;
3910 }
3911 #define A4XX_PC_GS_PARAM_LAYER 0x80000000
3912
3913 #define REG_A4XX_PC_HS_PARAM 0x000021e7
3914 #define A4XX_PC_HS_PARAM_VERTICES_OUT__MASK 0x0000003f
3915 #define A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT 0
3916 static inline uint32_t A4XX_PC_HS_PARAM_VERTICES_OUT(uint32_t val)
3917 {
3918 return ((val) << A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT) & A4XX_PC_HS_PARAM_VERTICES_OUT__MASK;
3919 }
3920 #define A4XX_PC_HS_PARAM_SPACING__MASK 0x00600000
3921 #define A4XX_PC_HS_PARAM_SPACING__SHIFT 21
3922 static inline uint32_t A4XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val)
3923 {
3924 return ((val) << A4XX_PC_HS_PARAM_SPACING__SHIFT) & A4XX_PC_HS_PARAM_SPACING__MASK;
3925 }
3926 #define A4XX_PC_HS_PARAM_CW 0x00800000
3927 #define A4XX_PC_HS_PARAM_CONNECTED 0x01000000
3928
3929 #define REG_A4XX_VBIF_VERSION 0x00003000
3930
3931 #define REG_A4XX_VBIF_CLKON 0x00003001
3932 #define A4XX_VBIF_CLKON_FORCE_ON_TESTBUS 0x00000001
3933
3934 #define REG_A4XX_VBIF_ABIT_SORT 0x0000301c
3935
3936 #define REG_A4XX_VBIF_ABIT_SORT_CONF 0x0000301d
3937
3938 #define REG_A4XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a
3939
3940 #define REG_A4XX_VBIF_IN_RD_LIM_CONF0 0x0000302c
3941
3942 #define REG_A4XX_VBIF_IN_RD_LIM_CONF1 0x0000302d
3943
3944 #define REG_A4XX_VBIF_IN_WR_LIM_CONF0 0x00003030
3945
3946 #define REG_A4XX_VBIF_IN_WR_LIM_CONF1 0x00003031
3947
3948 #define REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049
3949
3950 #define REG_A4XX_VBIF_PERF_CNT_EN0 0x000030c0
3951
3952 #define REG_A4XX_VBIF_PERF_CNT_EN1 0x000030c1
3953
3954 #define REG_A4XX_VBIF_PERF_CNT_EN2 0x000030c2
3955
3956 #define REG_A4XX_VBIF_PERF_CNT_EN3 0x000030c3
3957
3958 #define REG_A4XX_VBIF_PERF_CNT_SEL0 0x000030d0
3959
3960 #define REG_A4XX_VBIF_PERF_CNT_SEL1 0x000030d1
3961
3962 #define REG_A4XX_VBIF_PERF_CNT_SEL2 0x000030d2
3963
3964 #define REG_A4XX_VBIF_PERF_CNT_SEL3 0x000030d3
3965
3966 #define REG_A4XX_VBIF_PERF_CNT_LOW0 0x000030d8
3967
3968 #define REG_A4XX_VBIF_PERF_CNT_LOW1 0x000030d9
3969
3970 #define REG_A4XX_VBIF_PERF_CNT_LOW2 0x000030da
3971
3972 #define REG_A4XX_VBIF_PERF_CNT_LOW3 0x000030db
3973
3974 #define REG_A4XX_VBIF_PERF_CNT_HIGH0 0x000030e0
3975
3976 #define REG_A4XX_VBIF_PERF_CNT_HIGH1 0x000030e1
3977
3978 #define REG_A4XX_VBIF_PERF_CNT_HIGH2 0x000030e2
3979
3980 #define REG_A4XX_VBIF_PERF_CNT_HIGH3 0x000030e3
3981
3982 #define REG_A4XX_VBIF_PERF_PWR_CNT_EN0 0x00003100
3983
3984 #define REG_A4XX_VBIF_PERF_PWR_CNT_EN1 0x00003101
3985
3986 #define REG_A4XX_VBIF_PERF_PWR_CNT_EN2 0x00003102
3987
3988 #define REG_A4XX_UNKNOWN_0CC5 0x00000cc5
3989
3990 #define REG_A4XX_UNKNOWN_0CC6 0x00000cc6
3991
3992 #define REG_A4XX_UNKNOWN_0D01 0x00000d01
3993
3994 #define REG_A4XX_UNKNOWN_0E42 0x00000e42
3995
3996 #define REG_A4XX_UNKNOWN_0EC2 0x00000ec2
3997
3998 #define REG_A4XX_UNKNOWN_2001 0x00002001
3999
4000 #define REG_A4XX_UNKNOWN_209B 0x0000209b
4001
4002 #define REG_A4XX_UNKNOWN_20EF 0x000020ef
4003
4004 #define REG_A4XX_UNKNOWN_2152 0x00002152
4005
4006 #define REG_A4XX_UNKNOWN_2153 0x00002153
4007
4008 #define REG_A4XX_UNKNOWN_2154 0x00002154
4009
4010 #define REG_A4XX_UNKNOWN_2155 0x00002155
4011
4012 #define REG_A4XX_UNKNOWN_2156 0x00002156
4013
4014 #define REG_A4XX_UNKNOWN_2157 0x00002157
4015
4016 #define REG_A4XX_UNKNOWN_21C3 0x000021c3
4017
4018 #define REG_A4XX_UNKNOWN_21E6 0x000021e6
4019
4020 #define REG_A4XX_UNKNOWN_2209 0x00002209
4021
4022 #define REG_A4XX_UNKNOWN_22D7 0x000022d7
4023
4024 #define REG_A4XX_UNKNOWN_2352 0x00002352
4025
4026 #define REG_A4XX_TEX_SAMP_0 0x00000000
4027 #define A4XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001
4028 #define A4XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006
4029 #define A4XX_TEX_SAMP_0_XY_MAG__SHIFT 1
4030 static inline uint32_t A4XX_TEX_SAMP_0_XY_MAG(enum a4xx_tex_filter val)
4031 {
4032 return ((val) << A4XX_TEX_SAMP_0_XY_MAG__SHIFT) & A4XX_TEX_SAMP_0_XY_MAG__MASK;
4033 }
4034 #define A4XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018
4035 #define A4XX_TEX_SAMP_0_XY_MIN__SHIFT 3
4036 static inline uint32_t A4XX_TEX_SAMP_0_XY_MIN(enum a4xx_tex_filter val)
4037 {
4038 return ((val) << A4XX_TEX_SAMP_0_XY_MIN__SHIFT) & A4XX_TEX_SAMP_0_XY_MIN__MASK;
4039 }
4040 #define A4XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0
4041 #define A4XX_TEX_SAMP_0_WRAP_S__SHIFT 5
4042 static inline uint32_t A4XX_TEX_SAMP_0_WRAP_S(enum a4xx_tex_clamp val)
4043 {
4044 return ((val) << A4XX_TEX_SAMP_0_WRAP_S__SHIFT) & A4XX_TEX_SAMP_0_WRAP_S__MASK;
4045 }
4046 #define A4XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700
4047 #define A4XX_TEX_SAMP_0_WRAP_T__SHIFT 8
4048 static inline uint32_t A4XX_TEX_SAMP_0_WRAP_T(enum a4xx_tex_clamp val)
4049 {
4050 return ((val) << A4XX_TEX_SAMP_0_WRAP_T__SHIFT) & A4XX_TEX_SAMP_0_WRAP_T__MASK;
4051 }
4052 #define A4XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800
4053 #define A4XX_TEX_SAMP_0_WRAP_R__SHIFT 11
4054 static inline uint32_t A4XX_TEX_SAMP_0_WRAP_R(enum a4xx_tex_clamp val)
4055 {
4056 return ((val) << A4XX_TEX_SAMP_0_WRAP_R__SHIFT) & A4XX_TEX_SAMP_0_WRAP_R__MASK;
4057 }
4058 #define A4XX_TEX_SAMP_0_ANISO__MASK 0x0001c000
4059 #define A4XX_TEX_SAMP_0_ANISO__SHIFT 14
4060 static inline uint32_t A4XX_TEX_SAMP_0_ANISO(enum a4xx_tex_aniso val)
4061 {
4062 return ((val) << A4XX_TEX_SAMP_0_ANISO__SHIFT) & A4XX_TEX_SAMP_0_ANISO__MASK;
4063 }
4064 #define A4XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000
4065 #define A4XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19
4066 static inline uint32_t A4XX_TEX_SAMP_0_LOD_BIAS(float val)
4067 {
4068 return ((((int32_t)(val * 256.0))) << A4XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A4XX_TEX_SAMP_0_LOD_BIAS__MASK;
4069 }
4070
4071 #define REG_A4XX_TEX_SAMP_1 0x00000001
4072 #define A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e
4073 #define A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1
4074 static inline uint32_t A4XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val)
4075 {
4076 return ((val) << A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK;
4077 }
4078 #define A4XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010
4079 #define A4XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020
4080 #define A4XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040
4081 #define A4XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00
4082 #define A4XX_TEX_SAMP_1_MAX_LOD__SHIFT 8
4083 static inline uint32_t A4XX_TEX_SAMP_1_MAX_LOD(float val)
4084 {
4085 return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A4XX_TEX_SAMP_1_MAX_LOD__MASK;
4086 }
4087 #define A4XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000
4088 #define A4XX_TEX_SAMP_1_MIN_LOD__SHIFT 20
4089 static inline uint32_t A4XX_TEX_SAMP_1_MIN_LOD(float val)
4090 {
4091 return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A4XX_TEX_SAMP_1_MIN_LOD__MASK;
4092 }
4093
4094 #define REG_A4XX_TEX_CONST_0 0x00000000
4095 #define A4XX_TEX_CONST_0_TILED 0x00000001
4096 #define A4XX_TEX_CONST_0_SRGB 0x00000004
4097 #define A4XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070
4098 #define A4XX_TEX_CONST_0_SWIZ_X__SHIFT 4
4099 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_X(enum a4xx_tex_swiz val)
4100 {
4101 return ((val) << A4XX_TEX_CONST_0_SWIZ_X__SHIFT) & A4XX_TEX_CONST_0_SWIZ_X__MASK;
4102 }
4103 #define A4XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380
4104 #define A4XX_TEX_CONST_0_SWIZ_Y__SHIFT 7
4105 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Y(enum a4xx_tex_swiz val)
4106 {
4107 return ((val) << A4XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Y__MASK;
4108 }
4109 #define A4XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00
4110 #define A4XX_TEX_CONST_0_SWIZ_Z__SHIFT 10
4111 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Z(enum a4xx_tex_swiz val)
4112 {
4113 return ((val) << A4XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Z__MASK;
4114 }
4115 #define A4XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000
4116 #define A4XX_TEX_CONST_0_SWIZ_W__SHIFT 13
4117 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_W(enum a4xx_tex_swiz val)
4118 {
4119 return ((val) << A4XX_TEX_CONST_0_SWIZ_W__SHIFT) & A4XX_TEX_CONST_0_SWIZ_W__MASK;
4120 }
4121 #define A4XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000
4122 #define A4XX_TEX_CONST_0_MIPLVLS__SHIFT 16
4123 static inline uint32_t A4XX_TEX_CONST_0_MIPLVLS(uint32_t val)
4124 {
4125 return ((val) << A4XX_TEX_CONST_0_MIPLVLS__SHIFT) & A4XX_TEX_CONST_0_MIPLVLS__MASK;
4126 }
4127 #define A4XX_TEX_CONST_0_FMT__MASK 0x1fc00000
4128 #define A4XX_TEX_CONST_0_FMT__SHIFT 22
4129 static inline uint32_t A4XX_TEX_CONST_0_FMT(enum a4xx_tex_fmt val)
4130 {
4131 return ((val) << A4XX_TEX_CONST_0_FMT__SHIFT) & A4XX_TEX_CONST_0_FMT__MASK;
4132 }
4133 #define A4XX_TEX_CONST_0_TYPE__MASK 0x60000000
4134 #define A4XX_TEX_CONST_0_TYPE__SHIFT 29
4135 static inline uint32_t A4XX_TEX_CONST_0_TYPE(enum a4xx_tex_type val)
4136 {
4137 return ((val) << A4XX_TEX_CONST_0_TYPE__SHIFT) & A4XX_TEX_CONST_0_TYPE__MASK;
4138 }
4139
4140 #define REG_A4XX_TEX_CONST_1 0x00000001
4141 #define A4XX_TEX_CONST_1_HEIGHT__MASK 0x00007fff
4142 #define A4XX_TEX_CONST_1_HEIGHT__SHIFT 0
4143 static inline uint32_t A4XX_TEX_CONST_1_HEIGHT(uint32_t val)
4144 {
4145 return ((val) << A4XX_TEX_CONST_1_HEIGHT__SHIFT) & A4XX_TEX_CONST_1_HEIGHT__MASK;
4146 }
4147 #define A4XX_TEX_CONST_1_WIDTH__MASK 0x3fff8000
4148 #define A4XX_TEX_CONST_1_WIDTH__SHIFT 15
4149 static inline uint32_t A4XX_TEX_CONST_1_WIDTH(uint32_t val)
4150 {
4151 return ((val) << A4XX_TEX_CONST_1_WIDTH__SHIFT) & A4XX_TEX_CONST_1_WIDTH__MASK;
4152 }
4153
4154 #define REG_A4XX_TEX_CONST_2 0x00000002
4155 #define A4XX_TEX_CONST_2_PITCHALIGN__MASK 0x0000000f
4156 #define A4XX_TEX_CONST_2_PITCHALIGN__SHIFT 0
4157 static inline uint32_t A4XX_TEX_CONST_2_PITCHALIGN(uint32_t val)
4158 {
4159 return ((val) << A4XX_TEX_CONST_2_PITCHALIGN__SHIFT) & A4XX_TEX_CONST_2_PITCHALIGN__MASK;
4160 }
4161 #define A4XX_TEX_CONST_2_PITCH__MASK 0x3ffffe00
4162 #define A4XX_TEX_CONST_2_PITCH__SHIFT 9
4163 static inline uint32_t A4XX_TEX_CONST_2_PITCH(uint32_t val)
4164 {
4165 return ((val) << A4XX_TEX_CONST_2_PITCH__SHIFT) & A4XX_TEX_CONST_2_PITCH__MASK;
4166 }
4167 #define A4XX_TEX_CONST_2_SWAP__MASK 0xc0000000
4168 #define A4XX_TEX_CONST_2_SWAP__SHIFT 30
4169 static inline uint32_t A4XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val)
4170 {
4171 return ((val) << A4XX_TEX_CONST_2_SWAP__SHIFT) & A4XX_TEX_CONST_2_SWAP__MASK;
4172 }
4173
4174 #define REG_A4XX_TEX_CONST_3 0x00000003
4175 #define A4XX_TEX_CONST_3_LAYERSZ__MASK 0x00003fff
4176 #define A4XX_TEX_CONST_3_LAYERSZ__SHIFT 0
4177 static inline uint32_t A4XX_TEX_CONST_3_LAYERSZ(uint32_t val)
4178 {
4179 return ((val >> 12) << A4XX_TEX_CONST_3_LAYERSZ__SHIFT) & A4XX_TEX_CONST_3_LAYERSZ__MASK;
4180 }
4181 #define A4XX_TEX_CONST_3_DEPTH__MASK 0x7ffc0000
4182 #define A4XX_TEX_CONST_3_DEPTH__SHIFT 18
4183 static inline uint32_t A4XX_TEX_CONST_3_DEPTH(uint32_t val)
4184 {
4185 return ((val) << A4XX_TEX_CONST_3_DEPTH__SHIFT) & A4XX_TEX_CONST_3_DEPTH__MASK;
4186 }
4187
4188 #define REG_A4XX_TEX_CONST_4 0x00000004
4189 #define A4XX_TEX_CONST_4_LAYERSZ__MASK 0x0000000f
4190 #define A4XX_TEX_CONST_4_LAYERSZ__SHIFT 0
4191 static inline uint32_t A4XX_TEX_CONST_4_LAYERSZ(uint32_t val)
4192 {
4193 return ((val >> 12) << A4XX_TEX_CONST_4_LAYERSZ__SHIFT) & A4XX_TEX_CONST_4_LAYERSZ__MASK;
4194 }
4195 #define A4XX_TEX_CONST_4_BASE__MASK 0xffffffe0
4196 #define A4XX_TEX_CONST_4_BASE__SHIFT 5
4197 static inline uint32_t A4XX_TEX_CONST_4_BASE(uint32_t val)
4198 {
4199 return ((val >> 5) << A4XX_TEX_CONST_4_BASE__SHIFT) & A4XX_TEX_CONST_4_BASE__MASK;
4200 }
4201
4202 #define REG_A4XX_TEX_CONST_5 0x00000005
4203
4204 #define REG_A4XX_TEX_CONST_6 0x00000006
4205
4206 #define REG_A4XX_TEX_CONST_7 0x00000007
4207
4208 #define REG_A4XX_SSBO_0_0 0x00000000
4209 #define A4XX_SSBO_0_0_BASE__MASK 0xffffffe0
4210 #define A4XX_SSBO_0_0_BASE__SHIFT 5
4211 static inline uint32_t A4XX_SSBO_0_0_BASE(uint32_t val)
4212 {
4213 return ((val >> 5) << A4XX_SSBO_0_0_BASE__SHIFT) & A4XX_SSBO_0_0_BASE__MASK;
4214 }
4215
4216 #define REG_A4XX_SSBO_0_1 0x00000001
4217 #define A4XX_SSBO_0_1_PITCH__MASK 0x003fffff
4218 #define A4XX_SSBO_0_1_PITCH__SHIFT 0
4219 static inline uint32_t A4XX_SSBO_0_1_PITCH(uint32_t val)
4220 {
4221 return ((val) << A4XX_SSBO_0_1_PITCH__SHIFT) & A4XX_SSBO_0_1_PITCH__MASK;
4222 }
4223
4224 #define REG_A4XX_SSBO_0_2 0x00000002
4225 #define A4XX_SSBO_0_2_ARRAY_PITCH__MASK 0x03fff000
4226 #define A4XX_SSBO_0_2_ARRAY_PITCH__SHIFT 12
4227 static inline uint32_t A4XX_SSBO_0_2_ARRAY_PITCH(uint32_t val)
4228 {
4229 return ((val >> 12) << A4XX_SSBO_0_2_ARRAY_PITCH__SHIFT) & A4XX_SSBO_0_2_ARRAY_PITCH__MASK;
4230 }
4231
4232 #define REG_A4XX_SSBO_0_3 0x00000003
4233 #define A4XX_SSBO_0_3_CPP__MASK 0x0000003f
4234 #define A4XX_SSBO_0_3_CPP__SHIFT 0
4235 static inline uint32_t A4XX_SSBO_0_3_CPP(uint32_t val)
4236 {
4237 return ((val) << A4XX_SSBO_0_3_CPP__SHIFT) & A4XX_SSBO_0_3_CPP__MASK;
4238 }
4239
4240 #define REG_A4XX_SSBO_1_0 0x00000000
4241 #define A4XX_SSBO_1_0_CPP__MASK 0x0000001f
4242 #define A4XX_SSBO_1_0_CPP__SHIFT 0
4243 static inline uint32_t A4XX_SSBO_1_0_CPP(uint32_t val)
4244 {
4245 return ((val) << A4XX_SSBO_1_0_CPP__SHIFT) & A4XX_SSBO_1_0_CPP__MASK;
4246 }
4247 #define A4XX_SSBO_1_0_FMT__MASK 0x0000ff00
4248 #define A4XX_SSBO_1_0_FMT__SHIFT 8
4249 static inline uint32_t A4XX_SSBO_1_0_FMT(enum a4xx_color_fmt val)
4250 {
4251 return ((val) << A4XX_SSBO_1_0_FMT__SHIFT) & A4XX_SSBO_1_0_FMT__MASK;
4252 }
4253 #define A4XX_SSBO_1_0_WIDTH__MASK 0xffff0000
4254 #define A4XX_SSBO_1_0_WIDTH__SHIFT 16
4255 static inline uint32_t A4XX_SSBO_1_0_WIDTH(uint32_t val)
4256 {
4257 return ((val) << A4XX_SSBO_1_0_WIDTH__SHIFT) & A4XX_SSBO_1_0_WIDTH__MASK;
4258 }
4259
4260 #define REG_A4XX_SSBO_1_1 0x00000001
4261 #define A4XX_SSBO_1_1_HEIGHT__MASK 0x0000ffff
4262 #define A4XX_SSBO_1_1_HEIGHT__SHIFT 0
4263 static inline uint32_t A4XX_SSBO_1_1_HEIGHT(uint32_t val)
4264 {
4265 return ((val) << A4XX_SSBO_1_1_HEIGHT__SHIFT) & A4XX_SSBO_1_1_HEIGHT__MASK;
4266 }
4267 #define A4XX_SSBO_1_1_DEPTH__MASK 0xffff0000
4268 #define A4XX_SSBO_1_1_DEPTH__SHIFT 16
4269 static inline uint32_t A4XX_SSBO_1_1_DEPTH(uint32_t val)
4270 {
4271 return ((val) << A4XX_SSBO_1_1_DEPTH__SHIFT) & A4XX_SSBO_1_1_DEPTH__MASK;
4272 }
4273
4274
4275 #endif /* A4XX_XML */
Linux with added FPC-III support