Merge tag 'block-5.11-2021-01-10' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / gpu / drm / msm / adreno / adreno_device.c
blob12e75ba360f95548f8af4864aa0c599c9dd57ce8
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2013-2014 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
6 * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved.
7 */
9 #include "adreno_gpu.h"
11 #define ANY_ID 0xff
13 bool hang_debug = false;
14 MODULE_PARM_DESC(hang_debug, "Dump registers when hang is detected (can be slow!)");
15 module_param_named(hang_debug, hang_debug, bool, 0600);
17 bool snapshot_debugbus = false;
18 MODULE_PARM_DESC(snapshot_debugbus, "Include debugbus sections in GPU devcoredump (if not fused off)");
19 module_param_named(snapshot_debugbus, snapshot_debugbus, bool, 0600);
21 bool allow_vram_carveout = false;
22 MODULE_PARM_DESC(allow_vram_carveout, "Allow using VRAM Carveout, in place of IOMMU");
23 module_param_named(allow_vram_carveout, allow_vram_carveout, bool, 0600);
25 static const struct adreno_info gpulist[] = {
27 .rev = ADRENO_REV(2, 0, 0, 0),
28 .revn = 200,
29 .name = "A200",
30 .fw = {
31 [ADRENO_FW_PM4] = "yamato_pm4.fw",
32 [ADRENO_FW_PFP] = "yamato_pfp.fw",
34 .gmem = SZ_256K,
35 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
36 .init = a2xx_gpu_init,
37 }, { /* a200 on i.mx51 has only 128kib gmem */
38 .rev = ADRENO_REV(2, 0, 0, 1),
39 .revn = 201,
40 .name = "A200",
41 .fw = {
42 [ADRENO_FW_PM4] = "yamato_pm4.fw",
43 [ADRENO_FW_PFP] = "yamato_pfp.fw",
45 .gmem = SZ_128K,
46 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
47 .init = a2xx_gpu_init,
48 }, {
49 .rev = ADRENO_REV(2, 2, 0, ANY_ID),
50 .revn = 220,
51 .name = "A220",
52 .fw = {
53 [ADRENO_FW_PM4] = "leia_pm4_470.fw",
54 [ADRENO_FW_PFP] = "leia_pfp_470.fw",
56 .gmem = SZ_512K,
57 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
58 .init = a2xx_gpu_init,
59 }, {
60 .rev = ADRENO_REV(3, 0, 5, ANY_ID),
61 .revn = 305,
62 .name = "A305",
63 .fw = {
64 [ADRENO_FW_PM4] = "a300_pm4.fw",
65 [ADRENO_FW_PFP] = "a300_pfp.fw",
67 .gmem = SZ_256K,
68 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
69 .init = a3xx_gpu_init,
70 }, {
71 .rev = ADRENO_REV(3, 0, 6, 0),
72 .revn = 307, /* because a305c is revn==306 */
73 .name = "A306",
74 .fw = {
75 [ADRENO_FW_PM4] = "a300_pm4.fw",
76 [ADRENO_FW_PFP] = "a300_pfp.fw",
78 .gmem = SZ_128K,
79 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
80 .init = a3xx_gpu_init,
81 }, {
82 .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID),
83 .revn = 320,
84 .name = "A320",
85 .fw = {
86 [ADRENO_FW_PM4] = "a300_pm4.fw",
87 [ADRENO_FW_PFP] = "a300_pfp.fw",
89 .gmem = SZ_512K,
90 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
91 .init = a3xx_gpu_init,
92 }, {
93 .rev = ADRENO_REV(3, 3, 0, ANY_ID),
94 .revn = 330,
95 .name = "A330",
96 .fw = {
97 [ADRENO_FW_PM4] = "a330_pm4.fw",
98 [ADRENO_FW_PFP] = "a330_pfp.fw",
100 .gmem = SZ_1M,
101 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
102 .init = a3xx_gpu_init,
103 }, {
104 .rev = ADRENO_REV(4, 0, 5, ANY_ID),
105 .revn = 405,
106 .name = "A405",
107 .fw = {
108 [ADRENO_FW_PM4] = "a420_pm4.fw",
109 [ADRENO_FW_PFP] = "a420_pfp.fw",
111 .gmem = SZ_256K,
112 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
113 .init = a4xx_gpu_init,
114 }, {
115 .rev = ADRENO_REV(4, 2, 0, ANY_ID),
116 .revn = 420,
117 .name = "A420",
118 .fw = {
119 [ADRENO_FW_PM4] = "a420_pm4.fw",
120 [ADRENO_FW_PFP] = "a420_pfp.fw",
122 .gmem = (SZ_1M + SZ_512K),
123 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
124 .init = a4xx_gpu_init,
125 }, {
126 .rev = ADRENO_REV(4, 3, 0, ANY_ID),
127 .revn = 430,
128 .name = "A430",
129 .fw = {
130 [ADRENO_FW_PM4] = "a420_pm4.fw",
131 [ADRENO_FW_PFP] = "a420_pfp.fw",
133 .gmem = (SZ_1M + SZ_512K),
134 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
135 .init = a4xx_gpu_init,
136 }, {
137 .rev = ADRENO_REV(5, 1, 0, ANY_ID),
138 .revn = 510,
139 .name = "A510",
140 .fw = {
141 [ADRENO_FW_PM4] = "a530_pm4.fw",
142 [ADRENO_FW_PFP] = "a530_pfp.fw",
144 .gmem = SZ_256K,
146 * Increase inactive period to 250 to avoid bouncing
147 * the GDSC which appears to make it grumpy
149 .inactive_period = 250,
150 .init = a5xx_gpu_init,
151 }, {
152 .rev = ADRENO_REV(5, 3, 0, 2),
153 .revn = 530,
154 .name = "A530",
155 .fw = {
156 [ADRENO_FW_PM4] = "a530_pm4.fw",
157 [ADRENO_FW_PFP] = "a530_pfp.fw",
158 [ADRENO_FW_GPMU] = "a530v3_gpmu.fw2",
160 .gmem = SZ_1M,
162 * Increase inactive period to 250 to avoid bouncing
163 * the GDSC which appears to make it grumpy
165 .inactive_period = 250,
166 .quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI |
167 ADRENO_QUIRK_FAULT_DETECT_MASK,
168 .init = a5xx_gpu_init,
169 .zapfw = "a530_zap.mdt",
170 }, {
171 .rev = ADRENO_REV(5, 4, 0, 2),
172 .revn = 540,
173 .name = "A540",
174 .fw = {
175 [ADRENO_FW_PM4] = "a530_pm4.fw",
176 [ADRENO_FW_PFP] = "a530_pfp.fw",
177 [ADRENO_FW_GPMU] = "a540_gpmu.fw2",
179 .gmem = SZ_1M,
181 * Increase inactive period to 250 to avoid bouncing
182 * the GDSC which appears to make it grumpy
184 .inactive_period = 250,
185 .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE,
186 .init = a5xx_gpu_init,
187 .zapfw = "a540_zap.mdt",
188 }, {
189 .rev = ADRENO_REV(6, 1, 8, ANY_ID),
190 .revn = 618,
191 .name = "A618",
192 .fw = {
193 [ADRENO_FW_SQE] = "a630_sqe.fw",
194 [ADRENO_FW_GMU] = "a630_gmu.bin",
196 .gmem = SZ_512K,
197 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
198 .init = a6xx_gpu_init,
199 }, {
200 .rev = ADRENO_REV(6, 3, 0, ANY_ID),
201 .revn = 630,
202 .name = "A630",
203 .fw = {
204 [ADRENO_FW_SQE] = "a630_sqe.fw",
205 [ADRENO_FW_GMU] = "a630_gmu.bin",
207 .gmem = SZ_1M,
208 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
209 .init = a6xx_gpu_init,
210 .zapfw = "a630_zap.mdt",
211 .hwcg = a630_hwcg,
212 }, {
213 .rev = ADRENO_REV(6, 4, 0, ANY_ID),
214 .revn = 640,
215 .name = "A640",
216 .fw = {
217 [ADRENO_FW_SQE] = "a630_sqe.fw",
218 [ADRENO_FW_GMU] = "a640_gmu.bin",
220 .gmem = SZ_1M,
221 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
222 .init = a6xx_gpu_init,
223 .zapfw = "a640_zap.mdt",
224 .hwcg = a640_hwcg,
225 }, {
226 .rev = ADRENO_REV(6, 5, 0, ANY_ID),
227 .revn = 650,
228 .name = "A650",
229 .fw = {
230 [ADRENO_FW_SQE] = "a650_sqe.fw",
231 [ADRENO_FW_GMU] = "a650_gmu.bin",
233 .gmem = SZ_1M + SZ_128K,
234 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
235 .init = a6xx_gpu_init,
236 .zapfw = "a650_zap.mdt",
237 .hwcg = a650_hwcg,
241 MODULE_FIRMWARE("qcom/a300_pm4.fw");
242 MODULE_FIRMWARE("qcom/a300_pfp.fw");
243 MODULE_FIRMWARE("qcom/a330_pm4.fw");
244 MODULE_FIRMWARE("qcom/a330_pfp.fw");
245 MODULE_FIRMWARE("qcom/a420_pm4.fw");
246 MODULE_FIRMWARE("qcom/a420_pfp.fw");
247 MODULE_FIRMWARE("qcom/a530_pm4.fw");
248 MODULE_FIRMWARE("qcom/a530_pfp.fw");
249 MODULE_FIRMWARE("qcom/a530v3_gpmu.fw2");
250 MODULE_FIRMWARE("qcom/a530_zap.mdt");
251 MODULE_FIRMWARE("qcom/a530_zap.b00");
252 MODULE_FIRMWARE("qcom/a530_zap.b01");
253 MODULE_FIRMWARE("qcom/a530_zap.b02");
254 MODULE_FIRMWARE("qcom/a630_sqe.fw");
255 MODULE_FIRMWARE("qcom/a630_gmu.bin");
256 MODULE_FIRMWARE("qcom/a630_zap.mbn");
258 static inline bool _rev_match(uint8_t entry, uint8_t id)
260 return (entry == ANY_ID) || (entry == id);
263 const struct adreno_info *adreno_info(struct adreno_rev rev)
265 int i;
267 /* identify gpu: */
268 for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
269 const struct adreno_info *info = &gpulist[i];
270 if (_rev_match(info->rev.core, rev.core) &&
271 _rev_match(info->rev.major, rev.major) &&
272 _rev_match(info->rev.minor, rev.minor) &&
273 _rev_match(info->rev.patchid, rev.patchid))
274 return info;
277 return NULL;
280 struct msm_gpu *adreno_load_gpu(struct drm_device *dev)
282 struct msm_drm_private *priv = dev->dev_private;
283 struct platform_device *pdev = priv->gpu_pdev;
284 struct msm_gpu *gpu = NULL;
285 struct adreno_gpu *adreno_gpu;
286 int ret;
288 if (pdev)
289 gpu = dev_to_gpu(&pdev->dev);
291 if (!gpu) {
292 dev_err_once(dev->dev, "no GPU device was found\n");
293 return NULL;
296 adreno_gpu = to_adreno_gpu(gpu);
299 * The number one reason for HW init to fail is if the firmware isn't
300 * loaded yet. Try that first and don't bother continuing on
301 * otherwise
304 ret = adreno_load_fw(adreno_gpu);
305 if (ret)
306 return NULL;
308 /* Make sure pm runtime is active and reset any previous errors */
309 pm_runtime_set_active(&pdev->dev);
311 ret = pm_runtime_get_sync(&pdev->dev);
312 if (ret < 0) {
313 pm_runtime_put_sync(&pdev->dev);
314 DRM_DEV_ERROR(dev->dev, "Couldn't power up the GPU: %d\n", ret);
315 return NULL;
318 mutex_lock(&dev->struct_mutex);
319 ret = msm_gpu_hw_init(gpu);
320 mutex_unlock(&dev->struct_mutex);
321 pm_runtime_put_autosuspend(&pdev->dev);
322 if (ret) {
323 DRM_DEV_ERROR(dev->dev, "gpu hw init failed: %d\n", ret);
324 return NULL;
327 #ifdef CONFIG_DEBUG_FS
328 if (gpu->funcs->debugfs_init) {
329 gpu->funcs->debugfs_init(gpu, dev->primary);
330 gpu->funcs->debugfs_init(gpu, dev->render);
332 #endif
334 return gpu;
337 static void set_gpu_pdev(struct drm_device *dev,
338 struct platform_device *pdev)
340 struct msm_drm_private *priv = dev->dev_private;
341 priv->gpu_pdev = pdev;
344 static int find_chipid(struct device *dev, struct adreno_rev *rev)
346 struct device_node *node = dev->of_node;
347 const char *compat;
348 int ret;
349 u32 chipid;
351 /* first search the compat strings for qcom,adreno-XYZ.W: */
352 ret = of_property_read_string_index(node, "compatible", 0, &compat);
353 if (ret == 0) {
354 unsigned int r, patch;
356 if (sscanf(compat, "qcom,adreno-%u.%u", &r, &patch) == 2 ||
357 sscanf(compat, "amd,imageon-%u.%u", &r, &patch) == 2) {
358 rev->core = r / 100;
359 r %= 100;
360 rev->major = r / 10;
361 r %= 10;
362 rev->minor = r;
363 rev->patchid = patch;
365 return 0;
369 /* and if that fails, fall back to legacy "qcom,chipid" property: */
370 ret = of_property_read_u32(node, "qcom,chipid", &chipid);
371 if (ret) {
372 DRM_DEV_ERROR(dev, "could not parse qcom,chipid: %d\n", ret);
373 return ret;
376 rev->core = (chipid >> 24) & 0xff;
377 rev->major = (chipid >> 16) & 0xff;
378 rev->minor = (chipid >> 8) & 0xff;
379 rev->patchid = (chipid & 0xff);
381 dev_warn(dev, "Using legacy qcom,chipid binding!\n");
382 dev_warn(dev, "Use compatible qcom,adreno-%u%u%u.%u instead.\n",
383 rev->core, rev->major, rev->minor, rev->patchid);
385 return 0;
388 static int adreno_bind(struct device *dev, struct device *master, void *data)
390 static struct adreno_platform_config config = {};
391 const struct adreno_info *info;
392 struct drm_device *drm = dev_get_drvdata(master);
393 struct msm_drm_private *priv = drm->dev_private;
394 struct msm_gpu *gpu;
395 int ret;
397 ret = find_chipid(dev, &config.rev);
398 if (ret)
399 return ret;
401 dev->platform_data = &config;
402 set_gpu_pdev(drm, to_platform_device(dev));
404 info = adreno_info(config.rev);
406 if (!info) {
407 dev_warn(drm->dev, "Unknown GPU revision: %u.%u.%u.%u\n",
408 config.rev.core, config.rev.major,
409 config.rev.minor, config.rev.patchid);
410 return -ENXIO;
413 DBG("Found GPU: %u.%u.%u.%u", config.rev.core, config.rev.major,
414 config.rev.minor, config.rev.patchid);
416 priv->is_a2xx = config.rev.core == 2;
418 gpu = info->init(drm);
419 if (IS_ERR(gpu)) {
420 dev_warn(drm->dev, "failed to load adreno gpu\n");
421 return PTR_ERR(gpu);
424 return 0;
427 static void adreno_unbind(struct device *dev, struct device *master,
428 void *data)
430 struct msm_gpu *gpu = dev_to_gpu(dev);
432 pm_runtime_force_suspend(dev);
433 gpu->funcs->destroy(gpu);
435 set_gpu_pdev(dev_get_drvdata(master), NULL);
438 static const struct component_ops a3xx_ops = {
439 .bind = adreno_bind,
440 .unbind = adreno_unbind,
443 static void adreno_device_register_headless(void)
445 /* on imx5, we don't have a top-level mdp/dpu node
446 * this creates a dummy node for the driver for that case
448 struct platform_device_info dummy_info = {
449 .parent = NULL,
450 .name = "msm",
451 .id = -1,
452 .res = NULL,
453 .num_res = 0,
454 .data = NULL,
455 .size_data = 0,
456 .dma_mask = ~0,
458 platform_device_register_full(&dummy_info);
461 static int adreno_probe(struct platform_device *pdev)
464 int ret;
466 ret = component_add(&pdev->dev, &a3xx_ops);
467 if (ret)
468 return ret;
470 if (of_device_is_compatible(pdev->dev.of_node, "amd,imageon"))
471 adreno_device_register_headless();
473 return 0;
476 static int adreno_remove(struct platform_device *pdev)
478 component_del(&pdev->dev, &a3xx_ops);
479 return 0;
482 static void adreno_shutdown(struct platform_device *pdev)
484 pm_runtime_force_suspend(&pdev->dev);
487 static const struct of_device_id dt_match[] = {
488 { .compatible = "qcom,adreno" },
489 { .compatible = "qcom,adreno-3xx" },
490 /* for compatibility with imx5 gpu: */
491 { .compatible = "amd,imageon" },
492 /* for backwards compat w/ downstream kgsl DT files: */
493 { .compatible = "qcom,kgsl-3d0" },
497 #ifdef CONFIG_PM
498 static int adreno_resume(struct device *dev)
500 struct msm_gpu *gpu = dev_to_gpu(dev);
502 return gpu->funcs->pm_resume(gpu);
505 static int adreno_suspend(struct device *dev)
507 struct msm_gpu *gpu = dev_to_gpu(dev);
509 return gpu->funcs->pm_suspend(gpu);
511 #endif
513 static const struct dev_pm_ops adreno_pm_ops = {
514 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
515 SET_RUNTIME_PM_OPS(adreno_suspend, adreno_resume, NULL)
518 static struct platform_driver adreno_driver = {
519 .probe = adreno_probe,
520 .remove = adreno_remove,
521 .shutdown = adreno_shutdown,
522 .driver = {
523 .name = "adreno",
524 .of_match_table = dt_match,
525 .pm = &adreno_pm_ops,
529 void __init adreno_register(void)
531 platform_driver_register(&adreno_driver);
534 void __exit adreno_unregister(void)
536 platform_driver_unregister(&adreno_driver);