drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
   3  */
   4
   5 #ifndef _DPU_HW_UTIL_H
   6 #define _DPU_HW_UTIL_H
   7
   8 #include <linux/io.h>
   9 #include <linux/slab.h>
  10 #include "dpu_hw_mdss.h"
  11
  12 #define REG_MASK(n)                     ((BIT(n)) - 1)
  13
  14 /*
  15  * This is the common struct maintained by each sub block
  16  * for mapping the register offsets in this block to the
  17  * absoulute IO address
  18  * @base_off:     mdp register mapped offset
  19  * @blk_off:      pipe offset relative to mdss offset
  20  * @length        length of register block offset
  21  * @xin_id        xin id
  22  * @hwversion     mdss hw version number
  23  */
  24 struct dpu_hw_blk_reg_map {
  25         void __iomem *base_off;
  26         u32 blk_off;
  27         u32 length;
  28         u32 xin_id;
  29         u32 hwversion;
  30         u32 log_mask;
  31 };
  32
  33 /**
  34  * struct dpu_hw_scaler3_de_cfg : QSEEDv3 detail enhancer configuration
  35  * @enable:         detail enhancer enable/disable
  36  * @sharpen_level1: sharpening strength for noise
  37  * @sharpen_level2: sharpening strength for signal
  38  * @ clip:          clip shift
  39  * @ limit:         limit value
  40  * @ thr_quiet:     quiet threshold
  41  * @ thr_dieout:    dieout threshold
  42  * @ thr_high:      low threshold
  43  * @ thr_high:      high threshold
  44  * @ prec_shift:    precision shift
  45  * @ adjust_a:      A-coefficients for mapping curve
  46  * @ adjust_b:      B-coefficients for mapping curve
  47  * @ adjust_c:      C-coefficients for mapping curve
  48  */
  49 struct dpu_hw_scaler3_de_cfg {
  50         u32 enable;
  51         int16_t sharpen_level1;
  52         int16_t sharpen_level2;
  53         uint16_t clip;
  54         uint16_t limit;
  55         uint16_t thr_quiet;
  56         uint16_t thr_dieout;
  57         uint16_t thr_low;
  58         uint16_t thr_high;
  59         uint16_t prec_shift;
  60         int16_t adjust_a[DPU_MAX_DE_CURVES];
  61         int16_t adjust_b[DPU_MAX_DE_CURVES];
  62         int16_t adjust_c[DPU_MAX_DE_CURVES];
  63 };
  64
  65
  66 /**
  67  * struct dpu_hw_scaler3_cfg : QSEEDv3 configuration
  68  * @enable:        scaler enable
  69  * @dir_en:        direction detection block enable
  70  * @ init_phase_x: horizontal initial phase
  71  * @ phase_step_x: horizontal phase step
  72  * @ init_phase_y: vertical initial phase
  73  * @ phase_step_y: vertical phase step
  74  * @ preload_x:    horizontal preload value
  75  * @ preload_y:    vertical preload value
  76  * @ src_width:    source width
  77  * @ src_height:   source height
  78  * @ dst_width:    destination width
  79  * @ dst_height:   destination height
  80  * @ y_rgb_filter_cfg: y/rgb plane filter configuration
  81  * @ uv_filter_cfg: uv plane filter configuration
  82  * @ alpha_filter_cfg: alpha filter configuration
  83  * @ blend_cfg:    blend coefficients configuration
  84  * @ lut_flag:     scaler LUT update flags
  85  *                 0x1 swap LUT bank
  86  *                 0x2 update 2D filter LUT
  87  *                 0x4 update y circular filter LUT
  88  *                 0x8 update uv circular filter LUT
  89  *                 0x10 update y separable filter LUT
  90  *                 0x20 update uv separable filter LUT
  91  * @ dir_lut_idx:  2D filter LUT index
  92  * @ y_rgb_cir_lut_idx: y circular filter LUT index
  93  * @ uv_cir_lut_idx: uv circular filter LUT index
  94  * @ y_rgb_sep_lut_idx: y circular filter LUT index
  95  * @ uv_sep_lut_idx: uv separable filter LUT index
  96  * @ dir_lut:      pointer to 2D LUT
  97  * @ cir_lut:      pointer to circular filter LUT
  98  * @ sep_lut:      pointer to separable filter LUT
  99  * @ de: detail enhancer configuration
 100  */
 101 struct dpu_hw_scaler3_cfg {
 102         u32 enable;
 103         u32 dir_en;
 104         int32_t init_phase_x[DPU_MAX_PLANES];
 105         int32_t phase_step_x[DPU_MAX_PLANES];
 106         int32_t init_phase_y[DPU_MAX_PLANES];
 107         int32_t phase_step_y[DPU_MAX_PLANES];
 108
 109         u32 preload_x[DPU_MAX_PLANES];
 110         u32 preload_y[DPU_MAX_PLANES];
 111         u32 src_width[DPU_MAX_PLANES];
 112         u32 src_height[DPU_MAX_PLANES];
 113
 114         u32 dst_width;
 115         u32 dst_height;
 116
 117         u32 y_rgb_filter_cfg;
 118         u32 uv_filter_cfg;
 119         u32 alpha_filter_cfg;
 120         u32 blend_cfg;
 121
 122         u32 lut_flag;
 123         u32 dir_lut_idx;
 124
 125         u32 y_rgb_cir_lut_idx;
 126         u32 uv_cir_lut_idx;
 127         u32 y_rgb_sep_lut_idx;
 128         u32 uv_sep_lut_idx;
 129         u32 *dir_lut;
 130         size_t dir_len;
 131         u32 *cir_lut;
 132         size_t cir_len;
 133         u32 *sep_lut;
 134         size_t sep_len;
 135
 136         /*
 137          * Detail enhancer settings
 138          */
 139         struct dpu_hw_scaler3_de_cfg de;
 140 };
 141
 142 /**
 143  * struct dpu_drm_pix_ext_v1 - version 1 of pixel ext structure
 144  * @num_ext_pxls_lr: Number of total horizontal pixels
 145  * @num_ext_pxls_tb: Number of total vertical lines
 146  * @left_ftch:       Number of extra pixels to overfetch from left
 147  * @right_ftch:      Number of extra pixels to overfetch from right
 148  * @top_ftch:        Number of extra lines to overfetch from top
 149  * @btm_ftch:        Number of extra lines to overfetch from bottom
 150  * @left_rpt:        Number of extra pixels to repeat from left
 151  * @right_rpt:       Number of extra pixels to repeat from right
 152  * @top_rpt:         Number of extra lines to repeat from top
 153  * @btm_rpt:         Number of extra lines to repeat from bottom
 154  */
 155 struct dpu_drm_pix_ext_v1 {
 156         /*
 157          * Number of pixels ext in left, right, top and bottom direction
 158          * for all color components.
 159          */
 160         int32_t num_ext_pxls_lr[DPU_MAX_PLANES];
 161         int32_t num_ext_pxls_tb[DPU_MAX_PLANES];
 162
 163         /*
 164          * Number of pixels needs to be overfetched in left, right, top
 165          * and bottom directions from source image for scaling.
 166          */
 167         int32_t left_ftch[DPU_MAX_PLANES];
 168         int32_t right_ftch[DPU_MAX_PLANES];
 169         int32_t top_ftch[DPU_MAX_PLANES];
 170         int32_t btm_ftch[DPU_MAX_PLANES];
 171         /*
 172          * Number of pixels needs to be repeated in left, right, top and
 173          * bottom directions for scaling.
 174          */
 175         int32_t left_rpt[DPU_MAX_PLANES];
 176         int32_t right_rpt[DPU_MAX_PLANES];
 177         int32_t top_rpt[DPU_MAX_PLANES];
 178         int32_t btm_rpt[DPU_MAX_PLANES];
 179
 180 };
 181
 182 /**
 183  * struct dpu_drm_de_v1 - version 1 of detail enhancer structure
 184  * @enable:         Enables/disables detail enhancer
 185  * @sharpen_level1: Sharpening strength for noise
 186  * @sharpen_level2: Sharpening strength for context
 187  * @clip:           Clip coefficient
 188  * @limit:          Detail enhancer limit factor
 189  * @thr_quiet:      Quite zone threshold
 190  * @thr_dieout:     Die-out zone threshold
 191  * @thr_low:        Linear zone left threshold
 192  * @thr_high:       Linear zone right threshold
 193  * @prec_shift:     Detail enhancer precision
 194  * @adjust_a:       Mapping curves A coefficients
 195  * @adjust_b:       Mapping curves B coefficients
 196  * @adjust_c:       Mapping curves C coefficients
 197  */
 198 struct dpu_drm_de_v1 {
 199         uint32_t enable;
 200         int16_t sharpen_level1;
 201         int16_t sharpen_level2;
 202         uint16_t clip;
 203         uint16_t limit;
 204         uint16_t thr_quiet;
 205         uint16_t thr_dieout;
 206         uint16_t thr_low;
 207         uint16_t thr_high;
 208         uint16_t prec_shift;
 209         int16_t adjust_a[DPU_MAX_DE_CURVES];
 210         int16_t adjust_b[DPU_MAX_DE_CURVES];
 211         int16_t adjust_c[DPU_MAX_DE_CURVES];
 212 };
 213
 214 /**
 215  * struct dpu_drm_scaler_v2 - version 2 of struct dpu_drm_scaler
 216  * @enable:            Scaler enable
 217  * @dir_en:            Detail enhancer enable
 218  * @pe:                Pixel extension settings
 219  * @horz_decimate:     Horizontal decimation factor
 220  * @vert_decimate:     Vertical decimation factor
 221  * @init_phase_x:      Initial scaler phase values for x
 222  * @phase_step_x:      Phase step values for x
 223  * @init_phase_y:      Initial scaler phase values for y
 224  * @phase_step_y:      Phase step values for y
 225  * @preload_x:         Horizontal preload value
 226  * @preload_y:         Vertical preload value
 227  * @src_width:         Source width
 228  * @src_height:        Source height
 229  * @dst_width:         Destination width
 230  * @dst_height:        Destination height
 231  * @y_rgb_filter_cfg:  Y/RGB plane filter configuration
 232  * @uv_filter_cfg:     UV plane filter configuration
 233  * @alpha_filter_cfg:  Alpha filter configuration
 234  * @blend_cfg:         Selection of blend coefficients
 235  * @lut_flag:          LUT configuration flags
 236  * @dir_lut_idx:       2d 4x4 LUT index
 237  * @y_rgb_cir_lut_idx: Y/RGB circular LUT index
 238  * @uv_cir_lut_idx:    UV circular LUT index
 239  * @y_rgb_sep_lut_idx: Y/RGB separable LUT index
 240  * @uv_sep_lut_idx:    UV separable LUT index
 241  * @de:                Detail enhancer settings
 242  */
 243 struct dpu_drm_scaler_v2 {
 244         /*
 245          * General definitions
 246          */
 247         uint32_t enable;
 248         uint32_t dir_en;
 249
 250         /*
 251          * Pix ext settings
 252          */
 253         struct dpu_drm_pix_ext_v1 pe;
 254
 255         /*
 256          * Decimation settings
 257          */
 258         uint32_t horz_decimate;
 259         uint32_t vert_decimate;
 260
 261         /*
 262          * Phase settings
 263          */
 264         int32_t init_phase_x[DPU_MAX_PLANES];
 265         int32_t phase_step_x[DPU_MAX_PLANES];
 266         int32_t init_phase_y[DPU_MAX_PLANES];
 267         int32_t phase_step_y[DPU_MAX_PLANES];
 268
 269         uint32_t preload_x[DPU_MAX_PLANES];
 270         uint32_t preload_y[DPU_MAX_PLANES];
 271         uint32_t src_width[DPU_MAX_PLANES];
 272         uint32_t src_height[DPU_MAX_PLANES];
 273
 274         uint32_t dst_width;
 275         uint32_t dst_height;
 276
 277         uint32_t y_rgb_filter_cfg;
 278         uint32_t uv_filter_cfg;
 279         uint32_t alpha_filter_cfg;
 280         uint32_t blend_cfg;
 281
 282         uint32_t lut_flag;
 283         uint32_t dir_lut_idx;
 284
 285         /* for Y(RGB) and UV planes*/
 286         uint32_t y_rgb_cir_lut_idx;
 287         uint32_t uv_cir_lut_idx;
 288         uint32_t y_rgb_sep_lut_idx;
 289         uint32_t uv_sep_lut_idx;
 290
 291         /*
 292          * Detail enhancer settings
 293          */
 294         struct dpu_drm_de_v1 de;
 295 };
 296
 297
 298 u32 *dpu_hw_util_get_log_mask_ptr(void);
 299
 300 void dpu_reg_write(struct dpu_hw_blk_reg_map *c,
 301                 u32 reg_off,
 302                 u32 val,
 303                 const char *name);
 304 int dpu_reg_read(struct dpu_hw_blk_reg_map *c, u32 reg_off);
 305
 306 #define DPU_REG_WRITE(c, off, val) dpu_reg_write(c, off, val, #off)
 307 #define DPU_REG_READ(c, off) dpu_reg_read(c, off)
 308
 309 void *dpu_hw_util_get_dir(void);
 310
 311 void dpu_hw_setup_scaler3(struct dpu_hw_blk_reg_map *c,
 312                 struct dpu_hw_scaler3_cfg *scaler3_cfg,
 313                 u32 scaler_offset, u32 scaler_version,
 314                 const struct dpu_format *format);
 315
 316 u32 dpu_hw_get_scaler3_ver(struct dpu_hw_blk_reg_map *c,
 317                 u32 scaler_offset);
 318
 319 void dpu_hw_csc_setup(struct dpu_hw_blk_reg_map  *c,
 320                 u32 csc_reg_off,
 321                 struct dpu_csc_cfg *data, bool csc10);
 322
 323 #endif /* _DPU_HW_UTIL_H */