drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (C) 2013 Red Hat
   4  * Author: Rob Clark <robdclark@gmail.com>
   5  */
   6
   7 #ifndef __MDP5_KMS_H__
   8 #define __MDP5_KMS_H__
   9
  10 #include "msm_drv.h"
  11 #include "msm_kms.h"
  12 #include "disp/mdp_kms.h"
  13 #include "mdp5_cfg.h"   /* must be included before mdp5.xml.h */
  14 #include "mdp5.xml.h"
  15 #include "mdp5_pipe.h"
  16 #include "mdp5_mixer.h"
  17 #include "mdp5_ctl.h"
  18 #include "mdp5_smp.h"
  19
  20 struct mdp5_kms {
  21         struct mdp_kms base;
  22
  23         struct drm_device *dev;
  24
  25         struct platform_device *pdev;
  26
  27         unsigned num_hwpipes;
  28         struct mdp5_hw_pipe *hwpipes[SSPP_MAX];
  29
  30         unsigned num_hwmixers;
  31         struct mdp5_hw_mixer *hwmixers[8];
  32
  33         unsigned num_intfs;
  34         struct mdp5_interface *intfs[5];
  35
  36         struct mdp5_cfg_handler *cfg;
  37         uint32_t caps;  /* MDP capabilities (MDP_CAP_XXX bits) */
  38
  39         /*
  40          * Global private object state, Do not access directly, use
  41          * mdp5_global_get_state()
  42          */
  43         struct drm_modeset_lock glob_state_lock;
  44         struct drm_private_obj glob_state;
  45
  46         struct mdp5_smp *smp;
  47         struct mdp5_ctl_manager *ctlm;
  48
  49         /* io/register spaces: */
  50         void __iomem *mmio;
  51
  52         struct clk *axi_clk;
  53         struct clk *ahb_clk;
  54         struct clk *core_clk;
  55         struct clk *lut_clk;
  56         struct clk *tbu_clk;
  57         struct clk *tbu_rt_clk;
  58         struct clk *vsync_clk;
  59
  60         /*
  61          * lock to protect access to global resources: ie., following register:
  62          *      - REG_MDP5_DISP_INTF_SEL
  63          */
  64         spinlock_t resource_lock;
  65
  66         bool rpm_enabled;
  67
  68         struct mdp_irq error_handler;
  69
  70         int enable_count;
  71 };
  72 #define to_mdp5_kms(x) container_of(x, struct mdp5_kms, base)
  73
  74 /* Global private object state for tracking resources that are shared across
  75  * multiple kms objects (planes/crtcs/etc).
  76  */
  77 #define to_mdp5_global_state(x) container_of(x, struct mdp5_global_state, base)
  78 struct mdp5_global_state {
  79         struct drm_private_state base;
  80
  81         struct drm_atomic_state *state;
  82         struct mdp5_kms *mdp5_kms;
  83
  84         struct mdp5_hw_pipe_state hwpipe;
  85         struct mdp5_hw_mixer_state hwmixer;
  86         struct mdp5_smp_state smp;
  87 };
  88
  89 struct mdp5_global_state * mdp5_get_existing_global_state(struct mdp5_kms *mdp5_kms);
  90 struct mdp5_global_state *__must_check mdp5_get_global_state(struct drm_atomic_state *s);
  91
  92 /* Atomic plane state.  Subclasses the base drm_plane_state in order to
  93  * track assigned hwpipe and hw specific state.
  94  */
  95 struct mdp5_plane_state {
  96         struct drm_plane_state base;
  97
  98         struct mdp5_hw_pipe *hwpipe;
  99         struct mdp5_hw_pipe *r_hwpipe;  /* right hwpipe */
 100
 101         /* aligned with property */
 102         uint8_t premultiplied;
 103         uint8_t zpos;
 104         uint8_t alpha;
 105
 106         /* assigned by crtc blender */
 107         enum mdp_mixer_stage_id stage;
 108 };
 109 #define to_mdp5_plane_state(x) \
 110                 container_of(x, struct mdp5_plane_state, base)
 111
 112 struct mdp5_pipeline {
 113         struct mdp5_interface *intf;
 114         struct mdp5_hw_mixer *mixer;
 115         struct mdp5_hw_mixer *r_mixer;  /* right mixer */
 116 };
 117
 118 struct mdp5_crtc_state {
 119         struct drm_crtc_state base;
 120
 121         struct mdp5_ctl *ctl;
 122         struct mdp5_pipeline pipeline;
 123
 124         /* these are derivatives of intf/mixer state in mdp5_pipeline */
 125         u32 vblank_irqmask;
 126         u32 err_irqmask;
 127         u32 pp_done_irqmask;
 128
 129         bool cmd_mode;
 130
 131         /* should we not write CTL[n].START register on flush?  If the
 132          * encoder has changed this is set to true, since encoder->enable()
 133          * is called after crtc state is committed, but we only want to
 134          * write the CTL[n].START register once.  This lets us defer
 135          * writing CTL[n].START until encoder->enable()
 136          */
 137         bool defer_start;
 138 };
 139 #define to_mdp5_crtc_state(x) \
 140                 container_of(x, struct mdp5_crtc_state, base)
 141
 142 enum mdp5_intf_mode {
 143         MDP5_INTF_MODE_NONE = 0,
 144
 145         /* Modes used for DSI interface (INTF_DSI type): */
 146         MDP5_INTF_DSI_MODE_VIDEO,
 147         MDP5_INTF_DSI_MODE_COMMAND,
 148
 149         /* Modes used for WB interface (INTF_WB type):  */
 150         MDP5_INTF_WB_MODE_BLOCK,
 151         MDP5_INTF_WB_MODE_LINE,
 152 };
 153
 154 struct mdp5_interface {
 155         int idx;
 156         int num; /* display interface number */
 157         enum mdp5_intf_type type;
 158         enum mdp5_intf_mode mode;
 159 };
 160
 161 struct mdp5_encoder {
 162         struct drm_encoder base;
 163         spinlock_t intf_lock;   /* protect REG_MDP5_INTF_* registers */
 164         bool enabled;
 165         uint32_t bsc;
 166
 167         struct mdp5_interface *intf;
 168         struct mdp5_ctl *ctl;
 169 };
 170 #define to_mdp5_encoder(x) container_of(x, struct mdp5_encoder, base)
 171
 172 static inline void mdp5_write(struct mdp5_kms *mdp5_kms, u32 reg, u32 data)
 173 {
 174         WARN_ON(mdp5_kms->enable_count <= 0);
 175         msm_writel(data, mdp5_kms->mmio + reg);
 176 }
 177
 178 static inline u32 mdp5_read(struct mdp5_kms *mdp5_kms, u32 reg)
 179 {
 180         WARN_ON(mdp5_kms->enable_count <= 0);
 181         return msm_readl(mdp5_kms->mmio + reg);
 182 }
 183
 184 static inline const char *stage2name(enum mdp_mixer_stage_id stage)
 185 {
 186         static const char *names[] = {
 187 #define NAME(n) [n] = #n
 188                 NAME(STAGE_UNUSED), NAME(STAGE_BASE),
 189                 NAME(STAGE0), NAME(STAGE1), NAME(STAGE2),
 190                 NAME(STAGE3), NAME(STAGE4), NAME(STAGE6),
 191 #undef NAME
 192         };
 193         return names[stage];
 194 }
 195
 196 static inline const char *pipe2name(enum mdp5_pipe pipe)
 197 {
 198         static const char *names[] = {
 199 #define NAME(n) [SSPP_ ## n] = #n
 200                 NAME(VIG0), NAME(VIG1), NAME(VIG2),
 201                 NAME(RGB0), NAME(RGB1), NAME(RGB2),
 202                 NAME(DMA0), NAME(DMA1),
 203                 NAME(VIG3), NAME(RGB3),
 204                 NAME(CURSOR0), NAME(CURSOR1),
 205 #undef NAME
 206         };
 207         return names[pipe];
 208 }
 209
 210 static inline int pipe2nclients(enum mdp5_pipe pipe)
 211 {
 212         switch (pipe) {
 213         case SSPP_RGB0:
 214         case SSPP_RGB1:
 215         case SSPP_RGB2:
 216         case SSPP_RGB3:
 217                 return 1;
 218         default:
 219                 return 3;
 220         }
 221 }
 222
 223 static inline uint32_t intf2err(int intf_num)
 224 {
 225         switch (intf_num) {
 226         case 0:  return MDP5_IRQ_INTF0_UNDER_RUN;
 227         case 1:  return MDP5_IRQ_INTF1_UNDER_RUN;
 228         case 2:  return MDP5_IRQ_INTF2_UNDER_RUN;
 229         case 3:  return MDP5_IRQ_INTF3_UNDER_RUN;
 230         default: return 0;
 231         }
 232 }
 233
 234 static inline uint32_t intf2vblank(struct mdp5_hw_mixer *mixer,
 235                                    struct mdp5_interface *intf)
 236 {
 237         /*
 238          * In case of DSI Command Mode, the Ping Pong's read pointer IRQ
 239          * acts as a Vblank signal. The Ping Pong buffer used is bound to
 240          * layer mixer.
 241          */
 242
 243         if ((intf->type == INTF_DSI) &&
 244                         (intf->mode == MDP5_INTF_DSI_MODE_COMMAND))
 245                 return MDP5_IRQ_PING_PONG_0_RD_PTR << mixer->pp;
 246
 247         if (intf->type == INTF_WB)
 248                 return MDP5_IRQ_WB_2_DONE;
 249
 250         switch (intf->num) {
 251         case 0:  return MDP5_IRQ_INTF0_VSYNC;
 252         case 1:  return MDP5_IRQ_INTF1_VSYNC;
 253         case 2:  return MDP5_IRQ_INTF2_VSYNC;
 254         case 3:  return MDP5_IRQ_INTF3_VSYNC;
 255         default: return 0;
 256         }
 257 }
 258
 259 static inline uint32_t lm2ppdone(struct mdp5_hw_mixer *mixer)
 260 {
 261         return MDP5_IRQ_PING_PONG_0_DONE << mixer->pp;
 262 }
 263
 264 void mdp5_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask,
 265                 uint32_t old_irqmask);
 266 void mdp5_irq_preinstall(struct msm_kms *kms);
 267 int mdp5_irq_postinstall(struct msm_kms *kms);
 268 void mdp5_irq_uninstall(struct msm_kms *kms);
 269 irqreturn_t mdp5_irq(struct msm_kms *kms);
 270 int mdp5_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);
 271 void mdp5_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);
 272 int mdp5_irq_domain_init(struct mdp5_kms *mdp5_kms);
 273 void mdp5_irq_domain_fini(struct mdp5_kms *mdp5_kms);
 274
 275 uint32_t mdp5_plane_get_flush(struct drm_plane *plane);
 276 enum mdp5_pipe mdp5_plane_pipe(struct drm_plane *plane);
 277 enum mdp5_pipe mdp5_plane_right_pipe(struct drm_plane *plane);
 278 struct drm_plane *mdp5_plane_init(struct drm_device *dev,
 279                                   enum drm_plane_type type);
 280
 281 struct mdp5_ctl *mdp5_crtc_get_ctl(struct drm_crtc *crtc);
 282 uint32_t mdp5_crtc_vblank(struct drm_crtc *crtc);
 283
 284 struct mdp5_hw_mixer *mdp5_crtc_get_mixer(struct drm_crtc *crtc);
 285 struct mdp5_pipeline *mdp5_crtc_get_pipeline(struct drm_crtc *crtc);
 286 void mdp5_crtc_set_pipeline(struct drm_crtc *crtc);
 287 void mdp5_crtc_wait_for_commit_done(struct drm_crtc *crtc);
 288 struct drm_crtc *mdp5_crtc_init(struct drm_device *dev,
 289                                 struct drm_plane *plane,
 290                                 struct drm_plane *cursor_plane, int id);
 291
 292 struct drm_encoder *mdp5_encoder_init(struct drm_device *dev,
 293                 struct mdp5_interface *intf, struct mdp5_ctl *ctl);
 294 int mdp5_vid_encoder_set_split_display(struct drm_encoder *encoder,
 295                                        struct drm_encoder *slave_encoder);
 296 void mdp5_encoder_set_intf_mode(struct drm_encoder *encoder, bool cmd_mode);
 297 int mdp5_encoder_get_linecount(struct drm_encoder *encoder);
 298 u32 mdp5_encoder_get_framecount(struct drm_encoder *encoder);
 299
 300 #ifdef CONFIG_DRM_MSM_DSI
 301 void mdp5_cmd_encoder_mode_set(struct drm_encoder *encoder,
 302                                struct drm_display_mode *mode,
 303                                struct drm_display_mode *adjusted_mode);
 304 void mdp5_cmd_encoder_disable(struct drm_encoder *encoder);
 305 void mdp5_cmd_encoder_enable(struct drm_encoder *encoder);
 306 int mdp5_cmd_encoder_set_split_display(struct drm_encoder *encoder,
 307                                        struct drm_encoder *slave_encoder);
 308 #else
 309 static inline void mdp5_cmd_encoder_mode_set(struct drm_encoder *encoder,
 310                                              struct drm_display_mode *mode,
 311                                              struct drm_display_mode *adjusted_mode)
 312 {
 313 }
 314 static inline void mdp5_cmd_encoder_disable(struct drm_encoder *encoder)
 315 {
 316 }
 317 static inline void mdp5_cmd_encoder_enable(struct drm_encoder *encoder)
 318 {
 319 }
 320 static inline int mdp5_cmd_encoder_set_split_display(
 321         struct drm_encoder *encoder, struct drm_encoder *slave_encoder)
 322 {
 323         return -EINVAL;
 324 }
 325 #endif
 326
 327 #endif /* __MDP5_KMS_H__ */