drivers/gpu/drm/msm/msm_drv.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
   4  * Copyright (C) 2013 Red Hat
   5  * Author: Rob Clark <robdclark@gmail.com>
   6  */
   7
   8 #ifndef __MSM_DRV_H__
   9 #define __MSM_DRV_H__
  10
  11 #include <linux/kernel.h>
  12 #include <linux/clk.h>
  13 #include <linux/cpufreq.h>
  14 #include <linux/module.h>
  15 #include <linux/component.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/pm.h>
  18 #include <linux/pm_runtime.h>
  19 #include <linux/slab.h>
  20 #include <linux/list.h>
  21 #include <linux/iommu.h>
  22 #include <linux/types.h>
  23 #include <linux/of_graph.h>
  24 #include <linux/of_device.h>
  25 #include <linux/sizes.h>
  26 #include <linux/kthread.h>
  27
  28 #include <drm/drm_atomic.h>
  29 #include <drm/drm_atomic_helper.h>
  30 #include <drm/drm_plane_helper.h>
  31 #include <drm/drm_probe_helper.h>
  32 #include <drm/drm_fb_helper.h>
  33 #include <drm/msm_drm.h>
  34 #include <drm/drm_gem.h>
  35
  36 struct msm_kms;
  37 struct msm_gpu;
  38 struct msm_mmu;
  39 struct msm_mdss;
  40 struct msm_rd_state;
  41 struct msm_perf_state;
  42 struct msm_gem_submit;
  43 struct msm_fence_context;
  44 struct msm_gem_address_space;
  45 struct msm_gem_vma;
  46
  47 #define MAX_CRTCS      8
  48 #define MAX_PLANES     20
  49 #define MAX_ENCODERS   8
  50 #define MAX_BRIDGES    8
  51 #define MAX_CONNECTORS 8
  52
  53 #define FRAC_16_16(mult, div)    (((mult) << 16) / (div))
  54
  55 struct msm_file_private {
  56         rwlock_t queuelock;
  57         struct list_head submitqueues;
  58         int queueid;
  59         struct msm_gem_address_space *aspace;
  60         struct kref ref;
  61 };
  62
  63 enum msm_mdp_plane_property {
  64         PLANE_PROP_ZPOS,
  65         PLANE_PROP_ALPHA,
  66         PLANE_PROP_PREMULTIPLIED,
  67         PLANE_PROP_MAX_NUM
  68 };
  69
  70 #define MSM_GPU_MAX_RINGS 4
  71 #define MAX_H_TILES_PER_DISPLAY 2
  72
  73 /**
  74  * enum msm_display_caps - features/capabilities supported by displays
  75  * @MSM_DISPLAY_CAP_VID_MODE:           Video or "active" mode supported
  76  * @MSM_DISPLAY_CAP_CMD_MODE:           Command mode supported
  77  * @MSM_DISPLAY_CAP_HOT_PLUG:           Hot plug detection supported
  78  * @MSM_DISPLAY_CAP_EDID:               EDID supported
  79  */
  80 enum msm_display_caps {
  81         MSM_DISPLAY_CAP_VID_MODE        = BIT(0),
  82         MSM_DISPLAY_CAP_CMD_MODE        = BIT(1),
  83         MSM_DISPLAY_CAP_HOT_PLUG        = BIT(2),
  84         MSM_DISPLAY_CAP_EDID            = BIT(3),
  85 };
  86
  87 /**
  88  * enum msm_event_wait - type of HW events to wait for
  89  * @MSM_ENC_COMMIT_DONE - wait for the driver to flush the registers to HW
  90  * @MSM_ENC_TX_COMPLETE - wait for the HW to transfer the frame to panel
  91  * @MSM_ENC_VBLANK - wait for the HW VBLANK event (for driver-internal waiters)
  92  */
  93 enum msm_event_wait {
  94         MSM_ENC_COMMIT_DONE = 0,
  95         MSM_ENC_TX_COMPLETE,
  96         MSM_ENC_VBLANK,
  97 };
  98
  99 /**
 100  * struct msm_display_topology - defines a display topology pipeline
 101  * @num_lm:       number of layer mixers used
 102  * @num_enc:      number of compression encoder blocks used
 103  * @num_intf:     number of interfaces the panel is mounted on
 104  */
 105 struct msm_display_topology {
 106         u32 num_lm;
 107         u32 num_enc;
 108         u32 num_intf;
 109         u32 num_dspp;
 110 };
 111
 112 /**
 113  * struct msm_display_info - defines display properties
 114  * @intf_type:          DRM_MODE_ENCODER_ type
 115  * @capabilities:       Bitmask of display flags
 116  * @num_of_h_tiles:     Number of horizontal tiles in case of split interface
 117  * @h_tile_instance:    Controller instance used per tile. Number of elements is
 118  *                      based on num_of_h_tiles
 119  * @is_te_using_watchdog_timer:  Boolean to indicate watchdog TE is
 120  *                               used instead of panel TE in cmd mode panels
 121  */
 122 struct msm_display_info {
 123         int intf_type;
 124         uint32_t capabilities;
 125         uint32_t num_of_h_tiles;
 126         uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY];
 127         bool is_te_using_watchdog_timer;
 128 };
 129
 130 /* Commit/Event thread specific structure */
 131 struct msm_drm_thread {
 132         struct drm_device *dev;
 133         unsigned int crtc_id;
 134         struct kthread_worker *worker;
 135 };
 136
 137 struct msm_drm_private {
 138
 139         struct drm_device *dev;
 140
 141         struct msm_kms *kms;
 142
 143         /* subordinate devices, if present: */
 144         struct platform_device *gpu_pdev;
 145
 146         /* top level MDSS wrapper device (for MDP5/DPU only) */
 147         struct msm_mdss *mdss;
 148
 149         /* possibly this should be in the kms component, but it is
 150          * shared by both mdp4 and mdp5..
 151          */
 152         struct hdmi *hdmi;
 153
 154         /* eDP is for mdp5 only, but kms has not been created
 155          * when edp_bind() and edp_init() are called. Here is the only
 156          * place to keep the edp instance.
 157          */
 158         struct msm_edp *edp;
 159
 160         /* DSI is shared by mdp4 and mdp5 */
 161         struct msm_dsi *dsi[2];
 162
 163         struct msm_dp *dp;
 164
 165         /* when we have more than one 'msm_gpu' these need to be an array: */
 166         struct msm_gpu *gpu;
 167         struct msm_file_private *lastctx;
 168         /* gpu is only set on open(), but we need this info earlier */
 169         bool is_a2xx;
 170
 171         struct drm_fb_helper *fbdev;
 172
 173         struct msm_rd_state *rd;       /* debugfs to dump all submits */
 174         struct msm_rd_state *hangrd;   /* debugfs to dump hanging submits */
 175         struct msm_perf_state *perf;
 176
 177         /*
 178          * Lists of inactive GEM objects.  Every bo is either in one of the
 179          * inactive lists (depending on whether or not it is shrinkable) or
 180          * gpu->active_list (for the gpu it is active on[1])
 181          *
 182          * These lists are protected by mm_lock.  If struct_mutex is involved, it
 183          * should be aquired prior to mm_lock.  One should *not* hold mm_lock in
 184          * get_pages()/vmap()/etc paths, as they can trigger the shrinker.
 185          *
 186          * [1] if someone ever added support for the old 2d cores, there could be
 187          *     more than one gpu object
 188          */
 189         struct list_head inactive_willneed;  /* inactive + !shrinkable */
 190         struct list_head inactive_dontneed;  /* inactive +  shrinkable */
 191         struct mutex mm_lock;
 192
 193         struct workqueue_struct *wq;
 194
 195         unsigned int num_planes;
 196         struct drm_plane *planes[MAX_PLANES];
 197
 198         unsigned int num_crtcs;
 199         struct drm_crtc *crtcs[MAX_CRTCS];
 200
 201         struct msm_drm_thread event_thread[MAX_CRTCS];
 202
 203         unsigned int num_encoders;
 204         struct drm_encoder *encoders[MAX_ENCODERS];
 205
 206         unsigned int num_bridges;
 207         struct drm_bridge *bridges[MAX_BRIDGES];
 208
 209         unsigned int num_connectors;
 210         struct drm_connector *connectors[MAX_CONNECTORS];
 211
 212         /* Properties */
 213         struct drm_property *plane_property[PLANE_PROP_MAX_NUM];
 214
 215         /* VRAM carveout, used when no IOMMU: */
 216         struct {
 217                 unsigned long size;
 218                 dma_addr_t paddr;
 219                 /* NOTE: mm managed at the page level, size is in # of pages
 220                  * and position mm_node->start is in # of pages:
 221                  */
 222                 struct drm_mm mm;
 223                 spinlock_t lock; /* Protects drm_mm node allocation/removal */
 224         } vram;
 225
 226         struct notifier_block vmap_notifier;
 227         struct shrinker shrinker;
 228
 229         struct drm_atomic_state *pm_state;
 230 };
 231
 232 struct msm_format {
 233         uint32_t pixel_format;
 234 };
 235
 236 struct msm_pending_timer;
 237
 238 int msm_atomic_prepare_fb(struct drm_plane *plane,
 239                           struct drm_plane_state *new_state);
 240 int msm_atomic_init_pending_timer(struct msm_pending_timer *timer,
 241                 struct msm_kms *kms, int crtc_idx);
 242 void msm_atomic_destroy_pending_timer(struct msm_pending_timer *timer);
 243 void msm_atomic_commit_tail(struct drm_atomic_state *state);
 244 struct drm_atomic_state *msm_atomic_state_alloc(struct drm_device *dev);
 245 void msm_atomic_state_clear(struct drm_atomic_state *state);
 246 void msm_atomic_state_free(struct drm_atomic_state *state);
 247
 248 int msm_crtc_enable_vblank(struct drm_crtc *crtc);
 249 void msm_crtc_disable_vblank(struct drm_crtc *crtc);
 250
 251 int msm_gem_init_vma(struct msm_gem_address_space *aspace,
 252                 struct msm_gem_vma *vma, int npages,
 253                 u64 range_start, u64 range_end);
 254 void msm_gem_purge_vma(struct msm_gem_address_space *aspace,
 255                 struct msm_gem_vma *vma);
 256 void msm_gem_unmap_vma(struct msm_gem_address_space *aspace,
 257                 struct msm_gem_vma *vma);
 258 int msm_gem_map_vma(struct msm_gem_address_space *aspace,
 259                 struct msm_gem_vma *vma, int prot,
 260                 struct sg_table *sgt, int npages);
 261 void msm_gem_close_vma(struct msm_gem_address_space *aspace,
 262                 struct msm_gem_vma *vma);
 263
 264
 265 struct msm_gem_address_space *
 266 msm_gem_address_space_get(struct msm_gem_address_space *aspace);
 267
 268 void msm_gem_address_space_put(struct msm_gem_address_space *aspace);
 269
 270 struct msm_gem_address_space *
 271 msm_gem_address_space_create(struct msm_mmu *mmu, const char *name,
 272                 u64 va_start, u64 size);
 273
 274 int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu);
 275 void msm_unregister_mmu(struct drm_device *dev, struct msm_mmu *mmu);
 276
 277 bool msm_use_mmu(struct drm_device *dev);
 278
 279 int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
 280                 struct drm_file *file);
 281
 282 void msm_gem_shrinker_init(struct drm_device *dev);
 283 void msm_gem_shrinker_cleanup(struct drm_device *dev);
 284
 285 struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj);
 286 int msm_gem_prime_vmap(struct drm_gem_object *obj, struct dma_buf_map *map);
 287 void msm_gem_prime_vunmap(struct drm_gem_object *obj, struct dma_buf_map *map);
 288 int msm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
 289 struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev,
 290                 struct dma_buf_attachment *attach, struct sg_table *sg);
 291 int msm_gem_prime_pin(struct drm_gem_object *obj);
 292 void msm_gem_prime_unpin(struct drm_gem_object *obj);
 293
 294 int msm_framebuffer_prepare(struct drm_framebuffer *fb,
 295                 struct msm_gem_address_space *aspace);
 296 void msm_framebuffer_cleanup(struct drm_framebuffer *fb,
 297                 struct msm_gem_address_space *aspace);
 298 uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb,
 299                 struct msm_gem_address_space *aspace, int plane);
 300 struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane);
 301 const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb);
 302 struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev,
 303                 struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd);
 304 struct drm_framebuffer * msm_alloc_stolen_fb(struct drm_device *dev,
 305                 int w, int h, int p, uint32_t format);
 306
 307 struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev);
 308 void msm_fbdev_free(struct drm_device *dev);
 309
 310 struct hdmi;
 311 int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev,
 312                 struct drm_encoder *encoder);
 313 void __init msm_hdmi_register(void);
 314 void __exit msm_hdmi_unregister(void);
 315
 316 struct msm_edp;
 317 void __init msm_edp_register(void);
 318 void __exit msm_edp_unregister(void);
 319 int msm_edp_modeset_init(struct msm_edp *edp, struct drm_device *dev,
 320                 struct drm_encoder *encoder);
 321
 322 struct msm_dsi;
 323 #ifdef CONFIG_DRM_MSM_DSI
 324 void __init msm_dsi_register(void);
 325 void __exit msm_dsi_unregister(void);
 326 int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev,
 327                          struct drm_encoder *encoder);
 328 #else
 329 static inline void __init msm_dsi_register(void)
 330 {
 331 }
 332 static inline void __exit msm_dsi_unregister(void)
 333 {
 334 }
 335 static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi,
 336                                        struct drm_device *dev,
 337                                        struct drm_encoder *encoder)
 338 {
 339         return -EINVAL;
 340 }
 341 #endif
 342
 343 #ifdef CONFIG_DRM_MSM_DP
 344 int __init msm_dp_register(void);
 345 void __exit msm_dp_unregister(void);
 346 int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev,
 347                          struct drm_encoder *encoder);
 348 int msm_dp_display_enable(struct msm_dp *dp, struct drm_encoder *encoder);
 349 int msm_dp_display_disable(struct msm_dp *dp, struct drm_encoder *encoder);
 350 int msm_dp_display_pre_disable(struct msm_dp *dp, struct drm_encoder *encoder);
 351 void msm_dp_display_mode_set(struct msm_dp *dp, struct drm_encoder *encoder,
 352                                 struct drm_display_mode *mode,
 353                                 struct drm_display_mode *adjusted_mode);
 354 void msm_dp_irq_postinstall(struct msm_dp *dp_display);
 355
 356 void msm_dp_debugfs_init(struct msm_dp *dp_display, struct drm_minor *minor);
 357
 358 #else
 359 static inline int __init msm_dp_register(void)
 360 {
 361         return -EINVAL;
 362 }
 363 static inline void __exit msm_dp_unregister(void)
 364 {
 365 }
 366 static inline int msm_dp_modeset_init(struct msm_dp *dp_display,
 367                                        struct drm_device *dev,
 368                                        struct drm_encoder *encoder)
 369 {
 370         return -EINVAL;
 371 }
 372 static inline int msm_dp_display_enable(struct msm_dp *dp,
 373                                         struct drm_encoder *encoder)
 374 {
 375         return -EINVAL;
 376 }
 377 static inline int msm_dp_display_disable(struct msm_dp *dp,
 378                                         struct drm_encoder *encoder)
 379 {
 380         return -EINVAL;
 381 }
 382 static inline int msm_dp_display_pre_disable(struct msm_dp *dp,
 383                                         struct drm_encoder *encoder)
 384 {
 385         return -EINVAL;
 386 }
 387 static inline void msm_dp_display_mode_set(struct msm_dp *dp,
 388                                 struct drm_encoder *encoder,
 389                                 struct drm_display_mode *mode,
 390                                 struct drm_display_mode *adjusted_mode)
 391 {
 392 }
 393
 394 static inline void msm_dp_irq_postinstall(struct msm_dp *dp_display)
 395 {
 396 }
 397
 398 static inline void msm_dp_debugfs_init(struct msm_dp *dp_display,
 399                 struct drm_minor *minor)
 400 {
 401 }
 402
 403 #endif
 404
 405 void __init msm_mdp_register(void);
 406 void __exit msm_mdp_unregister(void);
 407 void __init msm_dpu_register(void);
 408 void __exit msm_dpu_unregister(void);
 409
 410 #ifdef CONFIG_DEBUG_FS
 411 void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m);
 412 int msm_debugfs_late_init(struct drm_device *dev);
 413 int msm_rd_debugfs_init(struct drm_minor *minor);
 414 void msm_rd_debugfs_cleanup(struct msm_drm_private *priv);
 415 __printf(3, 4)
 416 void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit,
 417                 const char *fmt, ...);
 418 int msm_perf_debugfs_init(struct drm_minor *minor);
 419 void msm_perf_debugfs_cleanup(struct msm_drm_private *priv);
 420 #else
 421 static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; }
 422 __printf(3, 4)
 423 static inline void msm_rd_dump_submit(struct msm_rd_state *rd,
 424                         struct msm_gem_submit *submit,
 425                         const char *fmt, ...) {}
 426 static inline void msm_rd_debugfs_cleanup(struct msm_drm_private *priv) {}
 427 static inline void msm_perf_debugfs_cleanup(struct msm_drm_private *priv) {}
 428 #endif
 429
 430 struct clk *msm_clk_get(struct platform_device *pdev, const char *name);
 431
 432 struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count,
 433         const char *name);
 434 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
 435                 const char *dbgname);
 436 void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name,
 437                 const char *dbgname);
 438 void msm_writel(u32 data, void __iomem *addr);
 439 u32 msm_readl(const void __iomem *addr);
 440 void msm_rmw(void __iomem *addr, u32 mask, u32 or);
 441
 442 struct msm_gpu_submitqueue;
 443 int msm_submitqueue_init(struct drm_device *drm, struct msm_file_private *ctx);
 444 struct msm_gpu_submitqueue *msm_submitqueue_get(struct msm_file_private *ctx,
 445                 u32 id);
 446 int msm_submitqueue_create(struct drm_device *drm,
 447                 struct msm_file_private *ctx,
 448                 u32 prio, u32 flags, u32 *id);
 449 int msm_submitqueue_query(struct drm_device *drm, struct msm_file_private *ctx,
 450                 struct drm_msm_submitqueue_query *args);
 451 int msm_submitqueue_remove(struct msm_file_private *ctx, u32 id);
 452 void msm_submitqueue_close(struct msm_file_private *ctx);
 453
 454 void msm_submitqueue_destroy(struct kref *kref);
 455
 456 static inline void __msm_file_private_destroy(struct kref *kref)
 457 {
 458         struct msm_file_private *ctx = container_of(kref,
 459                 struct msm_file_private, ref);
 460
 461         msm_gem_address_space_put(ctx->aspace);
 462         kfree(ctx);
 463 }
 464
 465 static inline void msm_file_private_put(struct msm_file_private *ctx)
 466 {
 467         kref_put(&ctx->ref, __msm_file_private_destroy);
 468 }
 469
 470 static inline struct msm_file_private *msm_file_private_get(
 471         struct msm_file_private *ctx)
 472 {
 473         kref_get(&ctx->ref);
 474         return ctx;
 475 }
 476
 477 #define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
 478 #define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
 479
 480 static inline int align_pitch(int width, int bpp)
 481 {
 482         int bytespp = (bpp + 7) / 8;
 483         /* adreno needs pitch aligned to 32 pixels: */
 484         return bytespp * ALIGN(width, 32);
 485 }
 486
 487 /* for the generated headers: */
 488 #define INVALID_IDX(idx) ({BUG(); 0;})
 489 #define fui(x)                ({BUG(); 0;})
 490 #define util_float_to_half(x) ({BUG(); 0;})
 491
 492
 493 #define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)
 494
 495 /* for conditionally setting boolean flag(s): */
 496 #define COND(bool, val) ((bool) ? (val) : 0)
 497
 498 static inline unsigned long timeout_to_jiffies(const ktime_t *timeout)
 499 {
 500         ktime_t now = ktime_get();
 501         unsigned long remaining_jiffies;
 502
 503         if (ktime_compare(*timeout, now) < 0) {
 504                 remaining_jiffies = 0;
 505         } else {
 506                 ktime_t rem = ktime_sub(*timeout, now);
 507                 remaining_jiffies = ktime_divns(rem, NSEC_PER_SEC / HZ);
 508         }
 509
 510         return remaining_jiffies;
 511 }
 512
 513 #endif /* __MSM_DRV_H__ */