drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/conn.h

   1 /* SPDX-License-Identifier: MIT */
   2 #ifndef __NVBIOS_CONN_H__
   3 #define __NVBIOS_CONN_H__
   4 enum dcb_connector_type {
   5         DCB_CONNECTOR_VGA = 0x00,
   6         DCB_CONNECTOR_TV_0 = 0x10,
   7         DCB_CONNECTOR_TV_1 = 0x11,
   8         DCB_CONNECTOR_TV_3 = 0x13,
   9         DCB_CONNECTOR_DVI_I = 0x30,
  10         DCB_CONNECTOR_DVI_D = 0x31,
  11         DCB_CONNECTOR_DMS59_0 = 0x38,
  12         DCB_CONNECTOR_DMS59_1 = 0x39,
  13         DCB_CONNECTOR_LVDS = 0x40,
  14         DCB_CONNECTOR_LVDS_SPWG = 0x41,
  15         DCB_CONNECTOR_DP = 0x46,
  16         DCB_CONNECTOR_eDP = 0x47,
  17         DCB_CONNECTOR_HDMI_0 = 0x60,
  18         DCB_CONNECTOR_HDMI_1 = 0x61,
  19         DCB_CONNECTOR_HDMI_C = 0x63,
  20         DCB_CONNECTOR_DMS59_DP0 = 0x64,
  21         DCB_CONNECTOR_DMS59_DP1 = 0x65,
  22         DCB_CONNECTOR_WFD       = 0x70,
  23         DCB_CONNECTOR_USB_C = 0x71,
  24         DCB_CONNECTOR_NONE = 0xff
  25 };
  26
  27 struct nvbios_connT {
  28 };
  29
  30 u32 nvbios_connTe(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
  31 u32 nvbios_connTp(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
  32                   struct nvbios_connT *info);
  33
  34 struct nvbios_connE {
  35         u8 type;
  36         u8 location;
  37         u8 hpd;
  38         u8 dp;
  39         u8 di;
  40         u8 sr;
  41         u8 lcdid;
  42 };
  43
  44 u32 nvbios_connEe(struct nvkm_bios *bios, u8 idx, u8 *ver, u8 *hdr);
  45 u32 nvbios_connEp(struct nvkm_bios *bios, u8 idx, u8 *ver, u8 *hdr,
  46                   struct nvbios_connE *info);
  47 #endif