drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c

   1 /*
   2  * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  20  * DEALINGS IN THE SOFTWARE.
  21  */
  22 #include "ctxgf100.h"
  23
  24 static void
  25 gm20b_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
  26 {
  27         struct nvkm_device *device = gr->base.engine.subdev.device;
  28         const struct gf100_grctx_func *grctx = gr->func->grctx;
  29         u32 idle_timeout;
  30         int i, tmp;
  31
  32         gf100_gr_mmio(gr, gr->sw_ctx);
  33
  34         gf100_gr_wait_idle(gr);
  35
  36         idle_timeout = nvkm_mask(device, 0x404154, 0xffffffff, 0x00000000);
  37
  38         grctx->attrib(info);
  39
  40         grctx->unkn(gr);
  41
  42         gf100_grctx_generate_floorsweep(gr);
  43
  44         for (i = 0; i < 8; i++)
  45                 nvkm_wr32(device, 0x4064d0 + (i * 0x04), 0x00000000);
  46
  47         nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr);
  48
  49         nvkm_wr32(device, 0x408908, nvkm_rd32(device, 0x410108) | 0x80000000);
  50
  51         for (tmp = 0, i = 0; i < gr->gpc_nr; i++)
  52                 tmp |= ((1 << gr->tpc_nr[i]) - 1) << (i * 4);
  53         nvkm_wr32(device, 0x4041c4, tmp);
  54
  55         gm200_grctx_generate_smid_config(gr);
  56
  57         gf100_gr_wait_idle(gr);
  58
  59         nvkm_wr32(device, 0x404154, idle_timeout);
  60         gf100_gr_wait_idle(gr);
  61
  62         gf100_gr_mthd(gr, gr->method);
  63         gf100_gr_wait_idle(gr);
  64
  65         gf100_gr_icmd(gr, gr->bundle);
  66         grctx->pagepool(info);
  67         grctx->bundle(info);
  68 }
  69
  70 const struct gf100_grctx_func
  71 gm20b_grctx = {
  72         .main  = gm20b_grctx_generate_main,
  73         .unkn  = gk104_grctx_generate_unkn,
  74         .bundle = gm107_grctx_generate_bundle,
  75         .bundle_size = 0x1800,
  76         .bundle_min_gpm_fifo_depth = 0x182,
  77         .bundle_token_limit = 0x1c0,
  78         .pagepool = gm107_grctx_generate_pagepool,
  79         .pagepool_size = 0x8000,
  80         .attrib = gm107_grctx_generate_attrib,
  81         .attrib_nr_max = 0x600,
  82         .attrib_nr = 0x400,
  83         .alpha_nr_max = 0xc00,
  84         .alpha_nr = 0x800,
  85         .sm_id = gm107_grctx_generate_sm_id,
  86         .rop_mapping = gf117_grctx_generate_rop_mapping,
  87 };