drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.c

   1 /*
   2  * Copyright 2013 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs <bskeggs@redhat.com>
  23  */
  24 #include "gf100.h"
  25 #include "ctxgf100.h"
  26
  27 #include <nvif/class.h>
  28
  29 /*******************************************************************************
  30  * PGRAPH register lists
  31  ******************************************************************************/
  32
  33 const struct gf100_gr_init
  34 gf108_gr_init_gpc_unk_0[] = {
  35         { 0x418604,   1, 0x04, 0x00000000 },
  36         { 0x418680,   1, 0x04, 0x00000000 },
  37         { 0x418714,   1, 0x04, 0x00000000 },
  38         { 0x418384,   1, 0x04, 0x00000000 },
  39         {}
  40 };
  41
  42 const struct gf100_gr_init
  43 gf108_gr_init_setup_1[] = {
  44         { 0x4188c8,   2, 0x04, 0x00000000 },
  45         { 0x4188d0,   1, 0x04, 0x00010000 },
  46         { 0x4188d4,   1, 0x04, 0x00000001 },
  47         {}
  48 };
  49
  50 static const struct gf100_gr_init
  51 gf108_gr_init_gpc_unk_1[] = {
  52         { 0x418d00,   1, 0x04, 0x00000000 },
  53         { 0x418f08,   1, 0x04, 0x00000000 },
  54         { 0x418e00,   1, 0x04, 0x00000003 },
  55         { 0x418e08,   1, 0x04, 0x00000000 },
  56         {}
  57 };
  58
  59 static const struct gf100_gr_init
  60 gf108_gr_init_pe_0[] = {
  61         { 0x41980c,   1, 0x04, 0x00000010 },
  62         { 0x419810,   1, 0x04, 0x00000000 },
  63         { 0x419814,   1, 0x04, 0x00000004 },
  64         { 0x419844,   1, 0x04, 0x00000000 },
  65         { 0x41984c,   1, 0x04, 0x00005bc5 },
  66         { 0x419850,   4, 0x04, 0x00000000 },
  67         { 0x419880,   1, 0x04, 0x00000002 },
  68         {}
  69 };
  70
  71 static const struct gf100_gr_pack
  72 gf108_gr_pack_mmio[] = {
  73         { gf100_gr_init_main_0 },
  74         { gf100_gr_init_fe_0 },
  75         { gf100_gr_init_pri_0 },
  76         { gf100_gr_init_rstr2d_0 },
  77         { gf100_gr_init_pd_0 },
  78         { gf104_gr_init_ds_0 },
  79         { gf100_gr_init_scc_0 },
  80         { gf100_gr_init_prop_0 },
  81         { gf108_gr_init_gpc_unk_0 },
  82         { gf100_gr_init_setup_0 },
  83         { gf100_gr_init_crstr_0 },
  84         { gf108_gr_init_setup_1 },
  85         { gf100_gr_init_zcull_0 },
  86         { gf100_gr_init_gpm_0 },
  87         { gf108_gr_init_gpc_unk_1 },
  88         { gf100_gr_init_gcc_0 },
  89         { gf100_gr_init_tpccs_0 },
  90         { gf104_gr_init_tex_0 },
  91         { gf108_gr_init_pe_0 },
  92         { gf100_gr_init_l1c_0 },
  93         { gf100_gr_init_wwdx_0 },
  94         { gf100_gr_init_tpccs_1 },
  95         { gf100_gr_init_mpc_0 },
  96         { gf104_gr_init_sm_0 },
  97         { gf100_gr_init_be_0 },
  98         { gf100_gr_init_fe_1 },
  99         {}
 100 };
 101
 102 /*******************************************************************************
 103  * PGRAPH engine/subdev functions
 104  ******************************************************************************/
 105
 106 static void
 107 gf108_gr_init_r405a14(struct gf100_gr *gr)
 108 {
 109         nvkm_wr32(gr->base.engine.subdev.device, 0x405a14, 0x80000000);
 110 }
 111
 112 static const struct gf100_gr_func
 113 gf108_gr = {
 114         .oneinit_tiles = gf100_gr_oneinit_tiles,
 115         .oneinit_sm_id = gf100_gr_oneinit_sm_id,
 116         .init = gf100_gr_init,
 117         .init_gpc_mmu = gf100_gr_init_gpc_mmu,
 118         .init_r405a14 = gf108_gr_init_r405a14,
 119         .init_vsc_stream_master = gf100_gr_init_vsc_stream_master,
 120         .init_zcull = gf100_gr_init_zcull,
 121         .init_num_active_ltcs = gf100_gr_init_num_active_ltcs,
 122         .init_fecs_exceptions = gf100_gr_init_fecs_exceptions,
 123         .init_40601c = gf100_gr_init_40601c,
 124         .init_419cc0 = gf100_gr_init_419cc0,
 125         .init_419eb4 = gf100_gr_init_419eb4,
 126         .init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
 127         .init_shader_exceptions = gf100_gr_init_shader_exceptions,
 128         .init_400054 = gf100_gr_init_400054,
 129         .trap_mp = gf100_gr_trap_mp,
 130         .mmio = gf108_gr_pack_mmio,
 131         .fecs.ucode = &gf100_gr_fecs_ucode,
 132         .gpccs.ucode = &gf100_gr_gpccs_ucode,
 133         .rops = gf100_gr_rops,
 134         .grctx = &gf108_grctx,
 135         .zbc = &gf100_gr_zbc,
 136         .sclass = {
 137                 { -1, -1, FERMI_TWOD_A },
 138                 { -1, -1, FERMI_MEMORY_TO_MEMORY_FORMAT_A },
 139                 { -1, -1, FERMI_A, &gf100_fermi },
 140                 { -1, -1, FERMI_B, &gf100_fermi },
 141                 { -1, -1, FERMI_COMPUTE_A },
 142                 {}
 143         }
 144 };
 145
 146 const struct gf100_gr_fwif
 147 gf108_gr_fwif[] = {
 148         { -1, gf100_gr_load, &gf108_gr },
 149         { -1, gf100_gr_nofw, &gf108_gr },
 150         {}
 151 };
 152
 153 int
 154 gf108_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
 155 {
 156         return gf100_gr_new_(gf108_gr_fwif, device, index, pgr);
 157 }