drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c

   1 /*
   2  * Copyright 2016 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs <bskeggs@redhat.com>
  23  */
  24 #include "gf100.h"
  25 #include "ctxgf100.h"
  26
  27 #include <nvif/class.h>
  28
  29 static void
  30 gp102_gr_zbc_clear_stencil(struct gf100_gr *gr, int zbc)
  31 {
  32         struct nvkm_device *device = gr->base.engine.subdev.device;
  33         const int znum =  zbc - 1;
  34         const u32 zoff = znum * 4;
  35
  36         if (gr->zbc_stencil[zbc].format)
  37                 nvkm_wr32(device, 0x41815c + zoff, gr->zbc_stencil[zbc].ds);
  38         nvkm_mask(device, 0x418198 + ((znum / 4) * 4),
  39                           0x0000007f << ((znum % 4) * 7),
  40                           gr->zbc_stencil[zbc].format << ((znum % 4) * 7));
  41 }
  42
  43 static int
  44 gp102_gr_zbc_stencil_get(struct gf100_gr *gr, int format,
  45                          const u32 ds, const u32 l2)
  46 {
  47         struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc;
  48         int zbc = -ENOSPC, i;
  49
  50         for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) {
  51                 if (gr->zbc_stencil[i].format) {
  52                         if (gr->zbc_stencil[i].format != format)
  53                                 continue;
  54                         if (gr->zbc_stencil[i].ds != ds)
  55                                 continue;
  56                         if (gr->zbc_stencil[i].l2 != l2) {
  57                                 WARN_ON(1);
  58                                 return -EINVAL;
  59                         }
  60                         return i;
  61                 } else {
  62                         zbc = (zbc < 0) ? i : zbc;
  63                 }
  64         }
  65
  66         if (zbc < 0)
  67                 return zbc;
  68
  69         gr->zbc_stencil[zbc].format = format;
  70         gr->zbc_stencil[zbc].ds = ds;
  71         gr->zbc_stencil[zbc].l2 = l2;
  72         nvkm_ltc_zbc_stencil_get(ltc, zbc, l2);
  73         gr->func->zbc->clear_stencil(gr, zbc);
  74         return zbc;
  75 }
  76
  77 const struct gf100_gr_func_zbc
  78 gp102_gr_zbc = {
  79         .clear_color = gp100_gr_zbc_clear_color,
  80         .clear_depth = gp100_gr_zbc_clear_depth,
  81         .stencil_get = gp102_gr_zbc_stencil_get,
  82         .clear_stencil = gp102_gr_zbc_clear_stencil,
  83 };
  84
  85 void
  86 gp102_gr_init_swdx_pes_mask(struct gf100_gr *gr)
  87 {
  88         struct nvkm_device *device = gr->base.engine.subdev.device;
  89         u32 mask = 0, data, gpc;
  90
  91         for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
  92                 data = nvkm_rd32(device, GPC_UNIT(gpc, 0x0c50)) & 0x0000000f;
  93                 mask |= data << (gpc * 4);
  94         }
  95
  96         nvkm_wr32(device, 0x4181d0, mask);
  97 }
  98
  99 static const struct gf100_gr_func
 100 gp102_gr = {
 101         .oneinit_tiles = gm200_gr_oneinit_tiles,
 102         .oneinit_sm_id = gm200_gr_oneinit_sm_id,
 103         .init = gf100_gr_init,
 104         .init_gpc_mmu = gm200_gr_init_gpc_mmu,
 105         .init_vsc_stream_master = gk104_gr_init_vsc_stream_master,
 106         .init_zcull = gf117_gr_init_zcull,
 107         .init_num_active_ltcs = gm200_gr_init_num_active_ltcs,
 108         .init_rop_active_fbps = gp100_gr_init_rop_active_fbps,
 109         .init_swdx_pes_mask = gp102_gr_init_swdx_pes_mask,
 110         .init_fecs_exceptions = gp100_gr_init_fecs_exceptions,
 111         .init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2,
 112         .init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
 113         .init_419cc0 = gf100_gr_init_419cc0,
 114         .init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
 115         .init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
 116         .init_504430 = gm107_gr_init_504430,
 117         .init_shader_exceptions = gp100_gr_init_shader_exceptions,
 118         .trap_mp = gf100_gr_trap_mp,
 119         .rops = gm200_gr_rops,
 120         .gpc_nr = 6,
 121         .tpc_nr = 5,
 122         .ppc_nr = 3,
 123         .grctx = &gp102_grctx,
 124         .zbc = &gp102_gr_zbc,
 125         .sclass = {
 126                 { -1, -1, FERMI_TWOD_A },
 127                 { -1, -1, KEPLER_INLINE_TO_MEMORY_B },
 128                 { -1, -1, PASCAL_B, &gf100_fermi },
 129                 { -1, -1, PASCAL_COMPUTE_B },
 130                 {}
 131         }
 132 };
 133
 134 MODULE_FIRMWARE("nvidia/gp102/gr/fecs_bl.bin");
 135 MODULE_FIRMWARE("nvidia/gp102/gr/fecs_inst.bin");
 136 MODULE_FIRMWARE("nvidia/gp102/gr/fecs_data.bin");
 137 MODULE_FIRMWARE("nvidia/gp102/gr/fecs_sig.bin");
 138 MODULE_FIRMWARE("nvidia/gp102/gr/gpccs_bl.bin");
 139 MODULE_FIRMWARE("nvidia/gp102/gr/gpccs_inst.bin");
 140 MODULE_FIRMWARE("nvidia/gp102/gr/gpccs_data.bin");
 141 MODULE_FIRMWARE("nvidia/gp102/gr/gpccs_sig.bin");
 142 MODULE_FIRMWARE("nvidia/gp102/gr/sw_ctx.bin");
 143 MODULE_FIRMWARE("nvidia/gp102/gr/sw_nonctx.bin");
 144 MODULE_FIRMWARE("nvidia/gp102/gr/sw_bundle_init.bin");
 145 MODULE_FIRMWARE("nvidia/gp102/gr/sw_method_init.bin");
 146
 147 static const struct gf100_gr_fwif
 148 gp102_gr_fwif[] = {
 149         {  0, gm200_gr_load, &gp102_gr, &gm200_gr_fecs_acr, &gm200_gr_gpccs_acr },
 150         { -1, gm200_gr_nofw },
 151         {}
 152 };
 153
 154 int
 155 gp102_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
 156 {
 157         return gf100_gr_new_(gp102_gr_fwif, device, index, pgr);
 158 }