drivers/gpu/drm/nouveau/nvkm/engine/gr/gp108.c

   1 /*
   2  * Copyright 2019 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22 #include "gf100.h"
  23
  24 #include <subdev/acr.h>
  25
  26 #include <nvfw/flcn.h>
  27
  28 static void
  29 gp108_gr_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust)
  30 {
  31         struct flcn_bl_dmem_desc_v2 hdr;
  32         nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr));
  33         hdr.code_dma_base = hdr.code_dma_base + adjust;
  34         hdr.data_dma_base = hdr.data_dma_base + adjust;
  35         nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
  36         flcn_bl_dmem_desc_v2_dump(&acr->subdev, &hdr);
  37 }
  38
  39 static void
  40 gp108_gr_acr_bld_write(struct nvkm_acr *acr, u32 bld,
  41                        struct nvkm_acr_lsfw *lsfw)
  42 {
  43         const u64 base = lsfw->offset.img + lsfw->app_start_offset;
  44         const u64 code = base + lsfw->app_resident_code_offset;
  45         const u64 data = base + lsfw->app_resident_data_offset;
  46         const struct flcn_bl_dmem_desc_v2 hdr = {
  47                 .ctx_dma = FALCON_DMAIDX_UCODE,
  48                 .code_dma_base = code,
  49                 .non_sec_code_off = lsfw->app_resident_code_offset,
  50                 .non_sec_code_size = lsfw->app_resident_code_size,
  51                 .code_entry_point = lsfw->app_imem_entry,
  52                 .data_dma_base = data,
  53                 .data_size = lsfw->app_resident_data_size,
  54         };
  55
  56         nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
  57 }
  58
  59 const struct nvkm_acr_lsf_func
  60 gp108_gr_gpccs_acr = {
  61         .flags = NVKM_ACR_LSF_FORCE_PRIV_LOAD,
  62         .bld_size = sizeof(struct flcn_bl_dmem_desc_v2),
  63         .bld_write = gp108_gr_acr_bld_write,
  64         .bld_patch = gp108_gr_acr_bld_patch,
  65 };
  66
  67 const struct nvkm_acr_lsf_func
  68 gp108_gr_fecs_acr = {
  69         .bld_size = sizeof(struct flcn_bl_dmem_desc_v2),
  70         .bld_write = gp108_gr_acr_bld_write,
  71         .bld_patch = gp108_gr_acr_bld_patch,
  72 };
  73
  74 MODULE_FIRMWARE("nvidia/gp108/gr/fecs_bl.bin");
  75 MODULE_FIRMWARE("nvidia/gp108/gr/fecs_inst.bin");
  76 MODULE_FIRMWARE("nvidia/gp108/gr/fecs_data.bin");
  77 MODULE_FIRMWARE("nvidia/gp108/gr/fecs_sig.bin");
  78 MODULE_FIRMWARE("nvidia/gp108/gr/gpccs_bl.bin");
  79 MODULE_FIRMWARE("nvidia/gp108/gr/gpccs_inst.bin");
  80 MODULE_FIRMWARE("nvidia/gp108/gr/gpccs_data.bin");
  81 MODULE_FIRMWARE("nvidia/gp108/gr/gpccs_sig.bin");
  82 MODULE_FIRMWARE("nvidia/gp108/gr/sw_ctx.bin");
  83 MODULE_FIRMWARE("nvidia/gp108/gr/sw_nonctx.bin");
  84 MODULE_FIRMWARE("nvidia/gp108/gr/sw_bundle_init.bin");
  85 MODULE_FIRMWARE("nvidia/gp108/gr/sw_method_init.bin");
  86
  87 static const struct gf100_gr_fwif
  88 gp108_gr_fwif[] = {
  89         {  0, gm200_gr_load, &gp107_gr, &gp108_gr_fecs_acr, &gp108_gr_gpccs_acr },
  90         { -1, gm200_gr_nofw },
  91         {}
  92 };
  93
  94 int
  95 gp108_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
  96 {
  97         return gf100_gr_new_(gp108_gr_fwif, device, index, pgr);
  98 }