1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /**************************************************************************
4 * Copyright 2009-2016 VMware, Inc., Palo Alto, CA., USA
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
28 #include <linux/console.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/module.h>
31 #include <linux/pci.h>
32 #include <linux/mem_encrypt.h>
34 #include <drm/drm_drv.h>
35 #include <drm/drm_ioctl.h>
36 #include <drm/drm_sysfs.h>
37 #include <drm/ttm/ttm_bo_driver.h>
38 #include <drm/ttm/ttm_module.h>
39 #include <drm/ttm/ttm_placement.h>
41 #include "ttm_object.h"
42 #include "vmwgfx_binding.h"
43 #include "vmwgfx_drv.h"
45 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices"
46 #define VMWGFX_CHIP_SVGAII 0
47 #define VMW_FB_RESERVATION 0
49 #define VMW_MIN_INITIAL_WIDTH 800
50 #define VMW_MIN_INITIAL_HEIGHT 600
52 #ifndef VMWGFX_GIT_VERSION
53 #define VMWGFX_GIT_VERSION "Unknown"
56 #define VMWGFX_REPO "In Tree"
58 #define VMWGFX_VALIDATION_MEM_GRAN (16*PAGE_SIZE)
62 * Fully encoded drm commands. Might move to vmw_drm.h
65 #define DRM_IOCTL_VMW_GET_PARAM \
66 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \
67 struct drm_vmw_getparam_arg)
68 #define DRM_IOCTL_VMW_ALLOC_DMABUF \
69 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \
70 union drm_vmw_alloc_dmabuf_arg)
71 #define DRM_IOCTL_VMW_UNREF_DMABUF \
72 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \
73 struct drm_vmw_unref_dmabuf_arg)
74 #define DRM_IOCTL_VMW_CURSOR_BYPASS \
75 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \
76 struct drm_vmw_cursor_bypass_arg)
78 #define DRM_IOCTL_VMW_CONTROL_STREAM \
79 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \
80 struct drm_vmw_control_stream_arg)
81 #define DRM_IOCTL_VMW_CLAIM_STREAM \
82 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \
83 struct drm_vmw_stream_arg)
84 #define DRM_IOCTL_VMW_UNREF_STREAM \
85 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \
86 struct drm_vmw_stream_arg)
88 #define DRM_IOCTL_VMW_CREATE_CONTEXT \
89 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \
90 struct drm_vmw_context_arg)
91 #define DRM_IOCTL_VMW_UNREF_CONTEXT \
92 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \
93 struct drm_vmw_context_arg)
94 #define DRM_IOCTL_VMW_CREATE_SURFACE \
95 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \
96 union drm_vmw_surface_create_arg)
97 #define DRM_IOCTL_VMW_UNREF_SURFACE \
98 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \
99 struct drm_vmw_surface_arg)
100 #define DRM_IOCTL_VMW_REF_SURFACE \
101 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \
102 union drm_vmw_surface_reference_arg)
103 #define DRM_IOCTL_VMW_EXECBUF \
104 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \
105 struct drm_vmw_execbuf_arg)
106 #define DRM_IOCTL_VMW_GET_3D_CAP \
107 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \
108 struct drm_vmw_get_3d_cap_arg)
109 #define DRM_IOCTL_VMW_FENCE_WAIT \
110 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \
111 struct drm_vmw_fence_wait_arg)
112 #define DRM_IOCTL_VMW_FENCE_SIGNALED \
113 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \
114 struct drm_vmw_fence_signaled_arg)
115 #define DRM_IOCTL_VMW_FENCE_UNREF \
116 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \
117 struct drm_vmw_fence_arg)
118 #define DRM_IOCTL_VMW_FENCE_EVENT \
119 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \
120 struct drm_vmw_fence_event_arg)
121 #define DRM_IOCTL_VMW_PRESENT \
122 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \
123 struct drm_vmw_present_arg)
124 #define DRM_IOCTL_VMW_PRESENT_READBACK \
125 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \
126 struct drm_vmw_present_readback_arg)
127 #define DRM_IOCTL_VMW_UPDATE_LAYOUT \
128 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \
129 struct drm_vmw_update_layout_arg)
130 #define DRM_IOCTL_VMW_CREATE_SHADER \
131 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \
132 struct drm_vmw_shader_create_arg)
133 #define DRM_IOCTL_VMW_UNREF_SHADER \
134 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \
135 struct drm_vmw_shader_arg)
136 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE \
137 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \
138 union drm_vmw_gb_surface_create_arg)
139 #define DRM_IOCTL_VMW_GB_SURFACE_REF \
140 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \
141 union drm_vmw_gb_surface_reference_arg)
142 #define DRM_IOCTL_VMW_SYNCCPU \
143 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \
144 struct drm_vmw_synccpu_arg)
145 #define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT \
146 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT, \
147 struct drm_vmw_context_arg)
148 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE_EXT \
149 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE_EXT, \
150 union drm_vmw_gb_surface_create_ext_arg)
151 #define DRM_IOCTL_VMW_GB_SURFACE_REF_EXT \
152 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF_EXT, \
153 union drm_vmw_gb_surface_reference_ext_arg)
154 #define DRM_IOCTL_VMW_MSG \
155 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_MSG, \
156 struct drm_vmw_msg_arg)
159 * The core DRM version of this macro doesn't account for
163 #define VMW_IOCTL_DEF(ioctl, func, flags) \
164 [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_IOCTL_##ioctl, flags, func}
170 static const struct drm_ioctl_desc vmw_ioctls
[] = {
171 VMW_IOCTL_DEF(VMW_GET_PARAM
, vmw_getparam_ioctl
,
173 VMW_IOCTL_DEF(VMW_ALLOC_DMABUF
, vmw_bo_alloc_ioctl
,
175 VMW_IOCTL_DEF(VMW_UNREF_DMABUF
, vmw_bo_unref_ioctl
,
177 VMW_IOCTL_DEF(VMW_CURSOR_BYPASS
,
178 vmw_kms_cursor_bypass_ioctl
,
181 VMW_IOCTL_DEF(VMW_CONTROL_STREAM
, vmw_overlay_ioctl
,
183 VMW_IOCTL_DEF(VMW_CLAIM_STREAM
, vmw_stream_claim_ioctl
,
185 VMW_IOCTL_DEF(VMW_UNREF_STREAM
, vmw_stream_unref_ioctl
,
188 VMW_IOCTL_DEF(VMW_CREATE_CONTEXT
, vmw_context_define_ioctl
,
190 VMW_IOCTL_DEF(VMW_UNREF_CONTEXT
, vmw_context_destroy_ioctl
,
192 VMW_IOCTL_DEF(VMW_CREATE_SURFACE
, vmw_surface_define_ioctl
,
194 VMW_IOCTL_DEF(VMW_UNREF_SURFACE
, vmw_surface_destroy_ioctl
,
196 VMW_IOCTL_DEF(VMW_REF_SURFACE
, vmw_surface_reference_ioctl
,
198 VMW_IOCTL_DEF(VMW_EXECBUF
, vmw_execbuf_ioctl
,
200 VMW_IOCTL_DEF(VMW_FENCE_WAIT
, vmw_fence_obj_wait_ioctl
,
202 VMW_IOCTL_DEF(VMW_FENCE_SIGNALED
,
203 vmw_fence_obj_signaled_ioctl
,
205 VMW_IOCTL_DEF(VMW_FENCE_UNREF
, vmw_fence_obj_unref_ioctl
,
207 VMW_IOCTL_DEF(VMW_FENCE_EVENT
, vmw_fence_event_ioctl
,
209 VMW_IOCTL_DEF(VMW_GET_3D_CAP
, vmw_get_cap_3d_ioctl
,
212 /* these allow direct access to the framebuffers mark as master only */
213 VMW_IOCTL_DEF(VMW_PRESENT
, vmw_present_ioctl
,
214 DRM_MASTER
| DRM_AUTH
),
215 VMW_IOCTL_DEF(VMW_PRESENT_READBACK
,
216 vmw_present_readback_ioctl
,
217 DRM_MASTER
| DRM_AUTH
),
219 * The permissions of the below ioctl are overridden in
220 * vmw_generic_ioctl(). We require either
221 * DRM_MASTER or capable(CAP_SYS_ADMIN).
223 VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT
,
224 vmw_kms_update_layout_ioctl
,
226 VMW_IOCTL_DEF(VMW_CREATE_SHADER
,
227 vmw_shader_define_ioctl
,
229 VMW_IOCTL_DEF(VMW_UNREF_SHADER
,
230 vmw_shader_destroy_ioctl
,
232 VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE
,
233 vmw_gb_surface_define_ioctl
,
235 VMW_IOCTL_DEF(VMW_GB_SURFACE_REF
,
236 vmw_gb_surface_reference_ioctl
,
238 VMW_IOCTL_DEF(VMW_SYNCCPU
,
239 vmw_user_bo_synccpu_ioctl
,
241 VMW_IOCTL_DEF(VMW_CREATE_EXTENDED_CONTEXT
,
242 vmw_extended_context_define_ioctl
,
244 VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE_EXT
,
245 vmw_gb_surface_define_ext_ioctl
,
247 VMW_IOCTL_DEF(VMW_GB_SURFACE_REF_EXT
,
248 vmw_gb_surface_reference_ext_ioctl
,
250 VMW_IOCTL_DEF(VMW_MSG
,
255 static const struct pci_device_id vmw_pci_id_list
[] = {
256 {0x15ad, 0x0405, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, VMWGFX_CHIP_SVGAII
},
259 MODULE_DEVICE_TABLE(pci
, vmw_pci_id_list
);
261 static int enable_fbdev
= IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON
);
262 static int vmw_force_iommu
;
263 static int vmw_restrict_iommu
;
264 static int vmw_force_coherent
;
265 static int vmw_restrict_dma_mask
;
266 static int vmw_assume_16bpp
;
268 static int vmw_probe(struct pci_dev
*, const struct pci_device_id
*);
269 static int vmwgfx_pm_notifier(struct notifier_block
*nb
, unsigned long val
,
272 MODULE_PARM_DESC(enable_fbdev
, "Enable vmwgfx fbdev");
273 module_param_named(enable_fbdev
, enable_fbdev
, int, 0600);
274 MODULE_PARM_DESC(force_dma_api
, "Force using the DMA API for TTM pages");
275 module_param_named(force_dma_api
, vmw_force_iommu
, int, 0600);
276 MODULE_PARM_DESC(restrict_iommu
, "Try to limit IOMMU usage for TTM pages");
277 module_param_named(restrict_iommu
, vmw_restrict_iommu
, int, 0600);
278 MODULE_PARM_DESC(force_coherent
, "Force coherent TTM pages");
279 module_param_named(force_coherent
, vmw_force_coherent
, int, 0600);
280 MODULE_PARM_DESC(restrict_dma_mask
, "Restrict DMA mask to 44 bits with IOMMU");
281 module_param_named(restrict_dma_mask
, vmw_restrict_dma_mask
, int, 0600);
282 MODULE_PARM_DESC(assume_16bpp
, "Assume 16-bpp when filtering modes");
283 module_param_named(assume_16bpp
, vmw_assume_16bpp
, int, 0600);
286 static void vmw_print_capabilities2(uint32_t capabilities2
)
288 DRM_INFO("Capabilities2:\n");
289 if (capabilities2
& SVGA_CAP2_GROW_OTABLE
)
290 DRM_INFO(" Grow oTable.\n");
291 if (capabilities2
& SVGA_CAP2_INTRA_SURFACE_COPY
)
292 DRM_INFO(" IntraSurface copy.\n");
293 if (capabilities2
& SVGA_CAP2_DX3
)
297 static void vmw_print_capabilities(uint32_t capabilities
)
299 DRM_INFO("Capabilities:\n");
300 if (capabilities
& SVGA_CAP_RECT_COPY
)
301 DRM_INFO(" Rect copy.\n");
302 if (capabilities
& SVGA_CAP_CURSOR
)
303 DRM_INFO(" Cursor.\n");
304 if (capabilities
& SVGA_CAP_CURSOR_BYPASS
)
305 DRM_INFO(" Cursor bypass.\n");
306 if (capabilities
& SVGA_CAP_CURSOR_BYPASS_2
)
307 DRM_INFO(" Cursor bypass 2.\n");
308 if (capabilities
& SVGA_CAP_8BIT_EMULATION
)
309 DRM_INFO(" 8bit emulation.\n");
310 if (capabilities
& SVGA_CAP_ALPHA_CURSOR
)
311 DRM_INFO(" Alpha cursor.\n");
312 if (capabilities
& SVGA_CAP_3D
)
314 if (capabilities
& SVGA_CAP_EXTENDED_FIFO
)
315 DRM_INFO(" Extended Fifo.\n");
316 if (capabilities
& SVGA_CAP_MULTIMON
)
317 DRM_INFO(" Multimon.\n");
318 if (capabilities
& SVGA_CAP_PITCHLOCK
)
319 DRM_INFO(" Pitchlock.\n");
320 if (capabilities
& SVGA_CAP_IRQMASK
)
321 DRM_INFO(" Irq mask.\n");
322 if (capabilities
& SVGA_CAP_DISPLAY_TOPOLOGY
)
323 DRM_INFO(" Display Topology.\n");
324 if (capabilities
& SVGA_CAP_GMR
)
326 if (capabilities
& SVGA_CAP_TRACES
)
327 DRM_INFO(" Traces.\n");
328 if (capabilities
& SVGA_CAP_GMR2
)
329 DRM_INFO(" GMR2.\n");
330 if (capabilities
& SVGA_CAP_SCREEN_OBJECT_2
)
331 DRM_INFO(" Screen Object 2.\n");
332 if (capabilities
& SVGA_CAP_COMMAND_BUFFERS
)
333 DRM_INFO(" Command Buffers.\n");
334 if (capabilities
& SVGA_CAP_CMD_BUFFERS_2
)
335 DRM_INFO(" Command Buffers 2.\n");
336 if (capabilities
& SVGA_CAP_GBOBJECTS
)
337 DRM_INFO(" Guest Backed Resources.\n");
338 if (capabilities
& SVGA_CAP_DX
)
339 DRM_INFO(" DX Features.\n");
340 if (capabilities
& SVGA_CAP_HP_CMD_QUEUE
)
341 DRM_INFO(" HP Command Queue.\n");
345 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result
347 * @dev_priv: A device private structure.
349 * This function creates a small buffer object that holds the query
350 * result for dummy queries emitted as query barriers.
351 * The function will then map the first page and initialize a pending
352 * occlusion query result structure, Finally it will unmap the buffer.
353 * No interruptible waits are done within this function.
355 * Returns an error if bo creation or initialization fails.
357 static int vmw_dummy_query_bo_create(struct vmw_private
*dev_priv
)
360 struct vmw_buffer_object
*vbo
;
361 struct ttm_bo_kmap_obj map
;
362 volatile SVGA3dQueryResult
*result
;
366 * Create the vbo as pinned, so that a tryreserve will
367 * immediately succeed. This is because we're the only
368 * user of the bo currently.
370 vbo
= kzalloc(sizeof(*vbo
), GFP_KERNEL
);
374 ret
= vmw_bo_init(dev_priv
, vbo
, PAGE_SIZE
,
375 &vmw_sys_placement
, false, true,
377 if (unlikely(ret
!= 0))
380 ret
= ttm_bo_reserve(&vbo
->base
, false, true, NULL
);
382 vmw_bo_pin_reserved(vbo
, true);
384 ret
= ttm_bo_kmap(&vbo
->base
, 0, 1, &map
);
385 if (likely(ret
== 0)) {
386 result
= ttm_kmap_obj_virtual(&map
, &dummy
);
387 result
->totalSize
= sizeof(*result
);
388 result
->state
= SVGA3D_QUERYSTATE_PENDING
;
389 result
->result32
= 0xff;
392 vmw_bo_pin_reserved(vbo
, false);
393 ttm_bo_unreserve(&vbo
->base
);
395 if (unlikely(ret
!= 0)) {
396 DRM_ERROR("Dummy query buffer map failed.\n");
397 vmw_bo_unreference(&vbo
);
399 dev_priv
->dummy_query_bo
= vbo
;
405 * vmw_request_device_late - Perform late device setup
407 * @dev_priv: Pointer to device private.
409 * This function performs setup of otables and enables large command
410 * buffer submission. These tasks are split out to a separate function
411 * because it reverts vmw_release_device_early and is intended to be used
412 * by an error path in the hibernation code.
414 static int vmw_request_device_late(struct vmw_private
*dev_priv
)
418 if (dev_priv
->has_mob
) {
419 ret
= vmw_otables_setup(dev_priv
);
420 if (unlikely(ret
!= 0)) {
421 DRM_ERROR("Unable to initialize "
422 "guest Memory OBjects.\n");
427 if (dev_priv
->cman
) {
428 ret
= vmw_cmdbuf_set_pool_size(dev_priv
->cman
,
431 struct vmw_cmdbuf_man
*man
= dev_priv
->cman
;
433 dev_priv
->cman
= NULL
;
434 vmw_cmdbuf_man_destroy(man
);
441 static int vmw_request_device(struct vmw_private
*dev_priv
)
445 ret
= vmw_fifo_init(dev_priv
, &dev_priv
->fifo
);
446 if (unlikely(ret
!= 0)) {
447 DRM_ERROR("Unable to initialize FIFO.\n");
450 vmw_fence_fifo_up(dev_priv
->fman
);
451 dev_priv
->cman
= vmw_cmdbuf_man_create(dev_priv
);
452 if (IS_ERR(dev_priv
->cman
)) {
453 dev_priv
->cman
= NULL
;
454 dev_priv
->sm_type
= VMW_SM_LEGACY
;
457 ret
= vmw_request_device_late(dev_priv
);
461 ret
= vmw_dummy_query_bo_create(dev_priv
);
462 if (unlikely(ret
!= 0))
463 goto out_no_query_bo
;
469 vmw_cmdbuf_remove_pool(dev_priv
->cman
);
470 if (dev_priv
->has_mob
) {
471 struct ttm_resource_manager
*man
;
473 man
= ttm_manager_type(&dev_priv
->bdev
, VMW_PL_MOB
);
474 ttm_resource_manager_evict_all(&dev_priv
->bdev
, man
);
475 vmw_otables_takedown(dev_priv
);
478 vmw_cmdbuf_man_destroy(dev_priv
->cman
);
480 vmw_fence_fifo_down(dev_priv
->fman
);
481 vmw_fifo_release(dev_priv
, &dev_priv
->fifo
);
486 * vmw_release_device_early - Early part of fifo takedown.
488 * @dev_priv: Pointer to device private struct.
490 * This is the first part of command submission takedown, to be called before
491 * buffer management is taken down.
493 static void vmw_release_device_early(struct vmw_private
*dev_priv
)
496 * Previous destructions should've released
500 BUG_ON(dev_priv
->pinned_bo
!= NULL
);
502 vmw_bo_unreference(&dev_priv
->dummy_query_bo
);
504 vmw_cmdbuf_remove_pool(dev_priv
->cman
);
506 if (dev_priv
->has_mob
) {
507 struct ttm_resource_manager
*man
;
509 man
= ttm_manager_type(&dev_priv
->bdev
, VMW_PL_MOB
);
510 ttm_resource_manager_evict_all(&dev_priv
->bdev
, man
);
511 vmw_otables_takedown(dev_priv
);
516 * vmw_release_device_late - Late part of fifo takedown.
518 * @dev_priv: Pointer to device private struct.
520 * This is the last part of the command submission takedown, to be called when
521 * command submission is no longer needed. It may wait on pending fences.
523 static void vmw_release_device_late(struct vmw_private
*dev_priv
)
525 vmw_fence_fifo_down(dev_priv
->fman
);
527 vmw_cmdbuf_man_destroy(dev_priv
->cman
);
529 vmw_fifo_release(dev_priv
, &dev_priv
->fifo
);
533 * Sets the initial_[width|height] fields on the given vmw_private.
535 * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then
536 * clamping the value to fb_max_[width|height] fields and the
537 * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
538 * If the values appear to be invalid, set them to
539 * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
541 static void vmw_get_initial_size(struct vmw_private
*dev_priv
)
546 width
= vmw_read(dev_priv
, SVGA_REG_WIDTH
);
547 height
= vmw_read(dev_priv
, SVGA_REG_HEIGHT
);
549 width
= max_t(uint32_t, width
, VMW_MIN_INITIAL_WIDTH
);
550 height
= max_t(uint32_t, height
, VMW_MIN_INITIAL_HEIGHT
);
552 if (width
> dev_priv
->fb_max_width
||
553 height
> dev_priv
->fb_max_height
) {
556 * This is a host error and shouldn't occur.
559 width
= VMW_MIN_INITIAL_WIDTH
;
560 height
= VMW_MIN_INITIAL_HEIGHT
;
563 dev_priv
->initial_width
= width
;
564 dev_priv
->initial_height
= height
;
568 * vmw_dma_select_mode - Determine how DMA mappings should be set up for this
571 * @dev_priv: Pointer to a struct vmw_private
573 * This functions tries to determine what actions need to be taken by the
574 * driver to make system pages visible to the device.
575 * If this function decides that DMA is not possible, it returns -EINVAL.
576 * The driver may then try to disable features of the device that require
579 static int vmw_dma_select_mode(struct vmw_private
*dev_priv
)
581 static const char *names
[vmw_dma_map_max
] = {
582 [vmw_dma_phys
] = "Using physical TTM page addresses.",
583 [vmw_dma_alloc_coherent
] = "Using coherent TTM pages.",
584 [vmw_dma_map_populate
] = "Caching DMA mappings.",
585 [vmw_dma_map_bind
] = "Giving up DMA mappings early."};
587 /* TTM currently doesn't fully support SEV encryption. */
588 if (mem_encrypt_active())
591 if (vmw_force_coherent
)
592 dev_priv
->map_mode
= vmw_dma_alloc_coherent
;
593 else if (vmw_restrict_iommu
)
594 dev_priv
->map_mode
= vmw_dma_map_bind
;
596 dev_priv
->map_mode
= vmw_dma_map_populate
;
598 DRM_INFO("DMA map mode: %s\n", names
[dev_priv
->map_mode
]);
603 * vmw_dma_masks - set required page- and dma masks
605 * @dev: Pointer to struct drm-device
607 * With 32-bit we can only handle 32 bit PFNs. Optionally set that
608 * restriction also for 64-bit systems.
610 static int vmw_dma_masks(struct vmw_private
*dev_priv
)
612 struct drm_device
*dev
= dev_priv
->dev
;
615 ret
= dma_set_mask_and_coherent(dev
->dev
, DMA_BIT_MASK(64));
616 if (dev_priv
->map_mode
!= vmw_dma_phys
&&
617 (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask
)) {
618 DRM_INFO("Restricting DMA addresses to 44 bits.\n");
619 return dma_set_mask_and_coherent(dev
->dev
, DMA_BIT_MASK(44));
625 static int vmw_vram_manager_init(struct vmw_private
*dev_priv
)
628 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
629 ret
= vmw_thp_init(dev_priv
);
631 ret
= ttm_range_man_init(&dev_priv
->bdev
, TTM_PL_VRAM
, false,
632 dev_priv
->vram_size
>> PAGE_SHIFT
);
634 ttm_resource_manager_set_used(ttm_manager_type(&dev_priv
->bdev
, TTM_PL_VRAM
), false);
638 static void vmw_vram_manager_fini(struct vmw_private
*dev_priv
)
640 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
641 vmw_thp_fini(dev_priv
);
643 ttm_range_man_fini(&dev_priv
->bdev
, TTM_PL_VRAM
);
647 static int vmw_driver_load(struct drm_device
*dev
, unsigned long chipset
)
649 struct vmw_private
*dev_priv
;
653 bool refuse_dma
= false;
654 char host_log
[100] = {0};
656 dev_priv
= kzalloc(sizeof(*dev_priv
), GFP_KERNEL
);
657 if (unlikely(!dev_priv
)) {
658 DRM_ERROR("Failed allocating a device private struct.\n");
662 pci_set_master(dev
->pdev
);
665 dev_priv
->vmw_chipset
= chipset
;
666 dev_priv
->last_read_seqno
= (uint32_t) -100;
667 mutex_init(&dev_priv
->cmdbuf_mutex
);
668 mutex_init(&dev_priv
->release_mutex
);
669 mutex_init(&dev_priv
->binding_mutex
);
670 mutex_init(&dev_priv
->global_kms_state_mutex
);
671 ttm_lock_init(&dev_priv
->reservation_sem
);
672 spin_lock_init(&dev_priv
->resource_lock
);
673 spin_lock_init(&dev_priv
->hw_lock
);
674 spin_lock_init(&dev_priv
->waiter_lock
);
675 spin_lock_init(&dev_priv
->cap_lock
);
676 spin_lock_init(&dev_priv
->svga_lock
);
677 spin_lock_init(&dev_priv
->cursor_lock
);
679 for (i
= vmw_res_context
; i
< vmw_res_max
; ++i
) {
680 idr_init(&dev_priv
->res_idr
[i
]);
681 INIT_LIST_HEAD(&dev_priv
->res_lru
[i
]);
684 init_waitqueue_head(&dev_priv
->fence_queue
);
685 init_waitqueue_head(&dev_priv
->fifo_queue
);
686 dev_priv
->fence_queue_waiters
= 0;
687 dev_priv
->fifo_queue_waiters
= 0;
689 dev_priv
->used_memory_size
= 0;
691 dev_priv
->io_start
= pci_resource_start(dev
->pdev
, 0);
692 dev_priv
->vram_start
= pci_resource_start(dev
->pdev
, 1);
693 dev_priv
->mmio_start
= pci_resource_start(dev
->pdev
, 2);
695 dev_priv
->assume_16bpp
= !!vmw_assume_16bpp
;
697 dev_priv
->enable_fb
= enable_fbdev
;
699 vmw_write(dev_priv
, SVGA_REG_ID
, SVGA_ID_2
);
700 svga_id
= vmw_read(dev_priv
, SVGA_REG_ID
);
701 if (svga_id
!= SVGA_ID_2
) {
703 DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id
);
707 dev_priv
->capabilities
= vmw_read(dev_priv
, SVGA_REG_CAPABILITIES
);
709 if (dev_priv
->capabilities
& SVGA_CAP_CAP2_REGISTER
) {
710 dev_priv
->capabilities2
= vmw_read(dev_priv
, SVGA_REG_CAP2
);
714 ret
= vmw_dma_select_mode(dev_priv
);
715 if (unlikely(ret
!= 0)) {
716 DRM_INFO("Restricting capabilities since DMA not available.\n");
718 if (dev_priv
->capabilities
& SVGA_CAP_GBOBJECTS
)
719 DRM_INFO("Disabling 3D acceleration.\n");
722 dev_priv
->vram_size
= vmw_read(dev_priv
, SVGA_REG_VRAM_SIZE
);
723 dev_priv
->mmio_size
= vmw_read(dev_priv
, SVGA_REG_MEM_SIZE
);
724 dev_priv
->fb_max_width
= vmw_read(dev_priv
, SVGA_REG_MAX_WIDTH
);
725 dev_priv
->fb_max_height
= vmw_read(dev_priv
, SVGA_REG_MAX_HEIGHT
);
727 vmw_get_initial_size(dev_priv
);
729 if (dev_priv
->capabilities
& SVGA_CAP_GMR2
) {
730 dev_priv
->max_gmr_ids
=
731 vmw_read(dev_priv
, SVGA_REG_GMR_MAX_IDS
);
732 dev_priv
->max_gmr_pages
=
733 vmw_read(dev_priv
, SVGA_REG_GMRS_MAX_PAGES
);
734 dev_priv
->memory_size
=
735 vmw_read(dev_priv
, SVGA_REG_MEMORY_SIZE
);
736 dev_priv
->memory_size
-= dev_priv
->vram_size
;
739 * An arbitrary limit of 512MiB on surface
740 * memory. But all HWV8 hardware supports GMR2.
742 dev_priv
->memory_size
= 512*1024*1024;
744 dev_priv
->max_mob_pages
= 0;
745 dev_priv
->max_mob_size
= 0;
746 if (dev_priv
->capabilities
& SVGA_CAP_GBOBJECTS
) {
749 if (dev_priv
->capabilities2
& SVGA_CAP2_GB_MEMSIZE_2
)
750 mem_size
= vmw_read(dev_priv
,
751 SVGA_REG_GBOBJECT_MEM_SIZE_KB
);
755 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB
);
758 * Workaround for low memory 2D VMs to compensate for the
759 * allocation taken by fbdev
761 if (!(dev_priv
->capabilities
& SVGA_CAP_3D
))
764 dev_priv
->max_mob_pages
= mem_size
* 1024 / PAGE_SIZE
;
765 dev_priv
->prim_bb_mem
=
767 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM
);
768 dev_priv
->max_mob_size
=
769 vmw_read(dev_priv
, SVGA_REG_MOB_MAX_SIZE
);
770 dev_priv
->stdu_max_width
=
771 vmw_read(dev_priv
, SVGA_REG_SCREENTARGET_MAX_WIDTH
);
772 dev_priv
->stdu_max_height
=
773 vmw_read(dev_priv
, SVGA_REG_SCREENTARGET_MAX_HEIGHT
);
775 vmw_write(dev_priv
, SVGA_REG_DEV_CAP
,
776 SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH
);
777 dev_priv
->texture_max_width
= vmw_read(dev_priv
,
779 vmw_write(dev_priv
, SVGA_REG_DEV_CAP
,
780 SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT
);
781 dev_priv
->texture_max_height
= vmw_read(dev_priv
,
784 dev_priv
->texture_max_width
= 8192;
785 dev_priv
->texture_max_height
= 8192;
786 dev_priv
->prim_bb_mem
= dev_priv
->vram_size
;
789 vmw_print_capabilities(dev_priv
->capabilities
);
790 if (dev_priv
->capabilities
& SVGA_CAP_CAP2_REGISTER
)
791 vmw_print_capabilities2(dev_priv
->capabilities2
);
793 ret
= vmw_dma_masks(dev_priv
);
794 if (unlikely(ret
!= 0))
797 dma_set_max_seg_size(dev
->dev
, U32_MAX
);
799 if (dev_priv
->capabilities
& SVGA_CAP_GMR2
) {
800 DRM_INFO("Max GMR ids is %u\n",
801 (unsigned)dev_priv
->max_gmr_ids
);
802 DRM_INFO("Max number of GMR pages is %u\n",
803 (unsigned)dev_priv
->max_gmr_pages
);
804 DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n",
805 (unsigned)dev_priv
->memory_size
/ 1024);
807 DRM_INFO("Maximum display memory size is %u kiB\n",
808 dev_priv
->prim_bb_mem
/ 1024);
809 DRM_INFO("VRAM at 0x%08x size is %u kiB\n",
810 dev_priv
->vram_start
, dev_priv
->vram_size
/ 1024);
811 DRM_INFO("MMIO at 0x%08x size is %u kiB\n",
812 dev_priv
->mmio_start
, dev_priv
->mmio_size
/ 1024);
814 dev_priv
->mmio_virt
= memremap(dev_priv
->mmio_start
,
815 dev_priv
->mmio_size
, MEMREMAP_WB
);
817 if (unlikely(dev_priv
->mmio_virt
== NULL
)) {
819 DRM_ERROR("Failed mapping MMIO.\n");
823 /* Need mmio memory to check for fifo pitchlock cap. */
824 if (!(dev_priv
->capabilities
& SVGA_CAP_DISPLAY_TOPOLOGY
) &&
825 !(dev_priv
->capabilities
& SVGA_CAP_PITCHLOCK
) &&
826 !vmw_fifo_have_pitchlock(dev_priv
)) {
828 DRM_ERROR("Hardware has no pitchlock\n");
832 dev_priv
->tdev
= ttm_object_device_init(&ttm_mem_glob
, 12,
833 &vmw_prime_dmabuf_ops
);
835 if (unlikely(dev_priv
->tdev
== NULL
)) {
836 DRM_ERROR("Unable to initialize TTM object management.\n");
841 dev
->dev_private
= dev_priv
;
843 ret
= pci_request_regions(dev
->pdev
, "vmwgfx probe");
844 dev_priv
->stealth
= (ret
!= 0);
845 if (dev_priv
->stealth
) {
847 * Request at least the mmio PCI resource.
850 DRM_INFO("It appears like vesafb is loaded. "
851 "Ignore above error if any.\n");
852 ret
= pci_request_region(dev
->pdev
, 2, "vmwgfx stealth probe");
853 if (unlikely(ret
!= 0)) {
854 DRM_ERROR("Failed reserving the SVGA MMIO resource.\n");
859 if (dev_priv
->capabilities
& SVGA_CAP_IRQMASK
) {
860 ret
= vmw_irq_install(dev
, dev
->pdev
->irq
);
862 DRM_ERROR("Failed installing irq: %d\n", ret
);
867 dev_priv
->fman
= vmw_fence_manager_init(dev_priv
);
868 if (unlikely(dev_priv
->fman
== NULL
)) {
873 drm_vma_offset_manager_init(&dev_priv
->vma_manager
,
874 DRM_FILE_PAGE_OFFSET_START
,
875 DRM_FILE_PAGE_OFFSET_SIZE
);
876 ret
= ttm_bo_device_init(&dev_priv
->bdev
, &vmw_bo_driver
,
878 dev
->anon_inode
->i_mapping
,
879 &dev_priv
->vma_manager
,
880 dev_priv
->map_mode
== vmw_dma_alloc_coherent
,
882 if (unlikely(ret
!= 0)) {
883 DRM_ERROR("Failed initializing TTM buffer object driver.\n");
888 * Enable VRAM, but initially don't use it until SVGA is enabled and
892 ret
= vmw_vram_manager_init(dev_priv
);
893 if (unlikely(ret
!= 0)) {
894 DRM_ERROR("Failed initializing memory manager for VRAM.\n");
899 * "Guest Memory Regions" is an aperture like feature with
900 * one slot per bo. There is an upper limit of the number of
901 * slots as well as the bo size.
903 dev_priv
->has_gmr
= true;
904 /* TODO: This is most likely not correct */
905 if (((dev_priv
->capabilities
& (SVGA_CAP_GMR
| SVGA_CAP_GMR2
)) == 0) ||
907 vmw_gmrid_man_init(dev_priv
, VMW_PL_GMR
) != 0) {
908 DRM_INFO("No GMR memory available. "
909 "Graphics memory resources are very limited.\n");
910 dev_priv
->has_gmr
= false;
913 if (dev_priv
->capabilities
& SVGA_CAP_GBOBJECTS
&& !refuse_dma
) {
914 dev_priv
->has_mob
= true;
916 if (vmw_gmrid_man_init(dev_priv
, VMW_PL_MOB
) != 0) {
917 DRM_INFO("No MOB memory available. "
918 "3D will be disabled.\n");
919 dev_priv
->has_mob
= false;
923 if (dev_priv
->has_mob
&& (dev_priv
->capabilities
& SVGA_CAP_DX
)) {
924 spin_lock(&dev_priv
->cap_lock
);
925 vmw_write(dev_priv
, SVGA_REG_DEV_CAP
, SVGA3D_DEVCAP_DXCONTEXT
);
926 if (vmw_read(dev_priv
, SVGA_REG_DEV_CAP
))
927 dev_priv
->sm_type
= VMW_SM_4
;
928 spin_unlock(&dev_priv
->cap_lock
);
931 vmw_validation_mem_init_ttm(dev_priv
, VMWGFX_VALIDATION_MEM_GRAN
);
933 /* SVGA_CAP2_DX2 (DefineGBSurface_v3) is needed for SM4_1 support */
934 if (has_sm4_context(dev_priv
) &&
935 (dev_priv
->capabilities2
& SVGA_CAP2_DX2
)) {
936 vmw_write(dev_priv
, SVGA_REG_DEV_CAP
, SVGA3D_DEVCAP_SM41
);
938 if (vmw_read(dev_priv
, SVGA_REG_DEV_CAP
))
939 dev_priv
->sm_type
= VMW_SM_4_1
;
941 if (has_sm4_1_context(dev_priv
) &&
942 (dev_priv
->capabilities2
& SVGA_CAP2_DX3
)) {
943 vmw_write(dev_priv
, SVGA_REG_DEV_CAP
, SVGA3D_DEVCAP_SM5
);
944 if (vmw_read(dev_priv
, SVGA_REG_DEV_CAP
))
945 dev_priv
->sm_type
= VMW_SM_5
;
949 ret
= vmw_kms_init(dev_priv
);
950 if (unlikely(ret
!= 0))
952 vmw_overlay_init(dev_priv
);
954 ret
= vmw_request_device(dev_priv
);
958 DRM_INFO("Atomic: %s\n", (dev
->driver
->driver_features
& DRIVER_ATOMIC
)
960 if (dev_priv
->sm_type
== VMW_SM_5
)
961 DRM_INFO("SM5 support available.\n");
962 if (dev_priv
->sm_type
== VMW_SM_4_1
)
963 DRM_INFO("SM4_1 support available.\n");
964 if (dev_priv
->sm_type
== VMW_SM_4
)
965 DRM_INFO("SM4 support available.\n");
967 snprintf(host_log
, sizeof(host_log
), "vmwgfx: %s-%s",
968 VMWGFX_REPO
, VMWGFX_GIT_VERSION
);
969 vmw_host_log(host_log
);
971 memset(host_log
, 0, sizeof(host_log
));
972 snprintf(host_log
, sizeof(host_log
), "vmwgfx: Module Version: %d.%d.%d",
973 VMWGFX_DRIVER_MAJOR
, VMWGFX_DRIVER_MINOR
,
974 VMWGFX_DRIVER_PATCHLEVEL
);
975 vmw_host_log(host_log
);
977 if (dev_priv
->enable_fb
) {
978 vmw_fifo_resource_inc(dev_priv
);
979 vmw_svga_enable(dev_priv
);
980 vmw_fb_init(dev_priv
);
983 dev_priv
->pm_nb
.notifier_call
= vmwgfx_pm_notifier
;
984 register_pm_notifier(&dev_priv
->pm_nb
);
989 vmw_overlay_close(dev_priv
);
990 vmw_kms_close(dev_priv
);
992 if (dev_priv
->has_mob
)
993 vmw_gmrid_man_fini(dev_priv
, VMW_PL_MOB
);
994 if (dev_priv
->has_gmr
)
995 vmw_gmrid_man_fini(dev_priv
, VMW_PL_GMR
);
996 vmw_vram_manager_fini(dev_priv
);
998 (void)ttm_bo_device_release(&dev_priv
->bdev
);
1000 vmw_fence_manager_takedown(dev_priv
->fman
);
1002 if (dev_priv
->capabilities
& SVGA_CAP_IRQMASK
)
1003 vmw_irq_uninstall(dev_priv
->dev
);
1005 if (dev_priv
->stealth
)
1006 pci_release_region(dev
->pdev
, 2);
1008 pci_release_regions(dev
->pdev
);
1010 ttm_object_device_release(&dev_priv
->tdev
);
1012 memunmap(dev_priv
->mmio_virt
);
1014 for (i
= vmw_res_context
; i
< vmw_res_max
; ++i
)
1015 idr_destroy(&dev_priv
->res_idr
[i
]);
1017 if (dev_priv
->ctx
.staged_bindings
)
1018 vmw_binding_state_free(dev_priv
->ctx
.staged_bindings
);
1023 static void vmw_driver_unload(struct drm_device
*dev
)
1025 struct vmw_private
*dev_priv
= vmw_priv(dev
);
1026 enum vmw_res_type i
;
1028 unregister_pm_notifier(&dev_priv
->pm_nb
);
1030 if (dev_priv
->ctx
.res_ht_initialized
)
1031 drm_ht_remove(&dev_priv
->ctx
.res_ht
);
1032 vfree(dev_priv
->ctx
.cmd_bounce
);
1033 if (dev_priv
->enable_fb
) {
1034 vmw_fb_off(dev_priv
);
1035 vmw_fb_close(dev_priv
);
1036 vmw_fifo_resource_dec(dev_priv
);
1037 vmw_svga_disable(dev_priv
);
1040 vmw_kms_close(dev_priv
);
1041 vmw_overlay_close(dev_priv
);
1043 if (dev_priv
->has_gmr
)
1044 vmw_gmrid_man_fini(dev_priv
, VMW_PL_GMR
);
1046 vmw_release_device_early(dev_priv
);
1047 if (dev_priv
->has_mob
)
1048 vmw_gmrid_man_fini(dev_priv
, VMW_PL_MOB
);
1049 vmw_vram_manager_fini(dev_priv
);
1050 (void) ttm_bo_device_release(&dev_priv
->bdev
);
1051 drm_vma_offset_manager_destroy(&dev_priv
->vma_manager
);
1052 vmw_release_device_late(dev_priv
);
1053 vmw_fence_manager_takedown(dev_priv
->fman
);
1054 if (dev_priv
->capabilities
& SVGA_CAP_IRQMASK
)
1055 vmw_irq_uninstall(dev_priv
->dev
);
1056 if (dev_priv
->stealth
)
1057 pci_release_region(dev
->pdev
, 2);
1059 pci_release_regions(dev
->pdev
);
1061 ttm_object_device_release(&dev_priv
->tdev
);
1062 memunmap(dev_priv
->mmio_virt
);
1063 if (dev_priv
->ctx
.staged_bindings
)
1064 vmw_binding_state_free(dev_priv
->ctx
.staged_bindings
);
1066 for (i
= vmw_res_context
; i
< vmw_res_max
; ++i
)
1067 idr_destroy(&dev_priv
->res_idr
[i
]);
1072 static void vmw_postclose(struct drm_device
*dev
,
1073 struct drm_file
*file_priv
)
1075 struct vmw_fpriv
*vmw_fp
= vmw_fpriv(file_priv
);
1077 ttm_object_file_release(&vmw_fp
->tfile
);
1081 static int vmw_driver_open(struct drm_device
*dev
, struct drm_file
*file_priv
)
1083 struct vmw_private
*dev_priv
= vmw_priv(dev
);
1084 struct vmw_fpriv
*vmw_fp
;
1087 vmw_fp
= kzalloc(sizeof(*vmw_fp
), GFP_KERNEL
);
1088 if (unlikely(!vmw_fp
))
1091 vmw_fp
->tfile
= ttm_object_file_init(dev_priv
->tdev
, 10);
1092 if (unlikely(vmw_fp
->tfile
== NULL
))
1095 file_priv
->driver_priv
= vmw_fp
;
1104 static long vmw_generic_ioctl(struct file
*filp
, unsigned int cmd
,
1106 long (*ioctl_func
)(struct file
*, unsigned int,
1109 struct drm_file
*file_priv
= filp
->private_data
;
1110 struct drm_device
*dev
= file_priv
->minor
->dev
;
1111 unsigned int nr
= DRM_IOCTL_NR(cmd
);
1115 * Do extra checking on driver private ioctls.
1118 if ((nr
>= DRM_COMMAND_BASE
) && (nr
< DRM_COMMAND_END
)
1119 && (nr
< DRM_COMMAND_BASE
+ dev
->driver
->num_ioctls
)) {
1120 const struct drm_ioctl_desc
*ioctl
=
1121 &vmw_ioctls
[nr
- DRM_COMMAND_BASE
];
1123 if (nr
== DRM_COMMAND_BASE
+ DRM_VMW_EXECBUF
) {
1124 return ioctl_func(filp
, cmd
, arg
);
1125 } else if (nr
== DRM_COMMAND_BASE
+ DRM_VMW_UPDATE_LAYOUT
) {
1126 if (!drm_is_current_master(file_priv
) &&
1127 !capable(CAP_SYS_ADMIN
))
1131 if (unlikely(ioctl
->cmd
!= cmd
))
1132 goto out_io_encoding
;
1134 flags
= ioctl
->flags
;
1135 } else if (!drm_ioctl_flags(nr
, &flags
))
1138 return ioctl_func(filp
, cmd
, arg
);
1141 DRM_ERROR("Invalid command format, ioctl %d\n",
1142 nr
- DRM_COMMAND_BASE
);
1147 static long vmw_unlocked_ioctl(struct file
*filp
, unsigned int cmd
,
1150 return vmw_generic_ioctl(filp
, cmd
, arg
, &drm_ioctl
);
1153 #ifdef CONFIG_COMPAT
1154 static long vmw_compat_ioctl(struct file
*filp
, unsigned int cmd
,
1157 return vmw_generic_ioctl(filp
, cmd
, arg
, &drm_compat_ioctl
);
1161 static void vmw_master_set(struct drm_device
*dev
,
1162 struct drm_file
*file_priv
,
1166 * Inform a new master that the layout may have changed while
1170 drm_sysfs_hotplug_event(dev
);
1173 static void vmw_master_drop(struct drm_device
*dev
,
1174 struct drm_file
*file_priv
)
1176 struct vmw_private
*dev_priv
= vmw_priv(dev
);
1178 vmw_kms_legacy_hotspot_clear(dev_priv
);
1179 if (!dev_priv
->enable_fb
)
1180 vmw_svga_disable(dev_priv
);
1184 * __vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM.
1186 * @dev_priv: Pointer to device private struct.
1187 * Needs the reservation sem to be held in non-exclusive mode.
1189 static void __vmw_svga_enable(struct vmw_private
*dev_priv
)
1191 struct ttm_resource_manager
*man
= ttm_manager_type(&dev_priv
->bdev
, TTM_PL_VRAM
);
1193 spin_lock(&dev_priv
->svga_lock
);
1194 if (!ttm_resource_manager_used(man
)) {
1195 vmw_write(dev_priv
, SVGA_REG_ENABLE
, SVGA_REG_ENABLE
);
1196 ttm_resource_manager_set_used(man
, true);
1198 spin_unlock(&dev_priv
->svga_lock
);
1202 * vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM.
1204 * @dev_priv: Pointer to device private struct.
1206 void vmw_svga_enable(struct vmw_private
*dev_priv
)
1208 (void) ttm_read_lock(&dev_priv
->reservation_sem
, false);
1209 __vmw_svga_enable(dev_priv
);
1210 ttm_read_unlock(&dev_priv
->reservation_sem
);
1214 * __vmw_svga_disable - Disable SVGA mode and use of VRAM.
1216 * @dev_priv: Pointer to device private struct.
1217 * Needs the reservation sem to be held in exclusive mode.
1218 * Will not empty VRAM. VRAM must be emptied by caller.
1220 static void __vmw_svga_disable(struct vmw_private
*dev_priv
)
1222 struct ttm_resource_manager
*man
= ttm_manager_type(&dev_priv
->bdev
, TTM_PL_VRAM
);
1224 spin_lock(&dev_priv
->svga_lock
);
1225 if (ttm_resource_manager_used(man
)) {
1226 ttm_resource_manager_set_used(man
, false);
1227 vmw_write(dev_priv
, SVGA_REG_ENABLE
,
1228 SVGA_REG_ENABLE_HIDE
|
1229 SVGA_REG_ENABLE_ENABLE
);
1231 spin_unlock(&dev_priv
->svga_lock
);
1235 * vmw_svga_disable - Disable SVGA_MODE, and use of VRAM. Keep the fifo
1238 * @dev_priv: Pointer to device private struct.
1241 void vmw_svga_disable(struct vmw_private
*dev_priv
)
1243 struct ttm_resource_manager
*man
= ttm_manager_type(&dev_priv
->bdev
, TTM_PL_VRAM
);
1245 * Disabling SVGA will turn off device modesetting capabilities, so
1246 * notify KMS about that so that it doesn't cache atomic state that
1247 * isn't valid anymore, for example crtcs turned on.
1248 * Strictly we'd want to do this under the SVGA lock (or an SVGA mutex),
1249 * but vmw_kms_lost_device() takes the reservation sem and thus we'll
1250 * end up with lock order reversal. Thus, a master may actually perform
1251 * a new modeset just after we call vmw_kms_lost_device() and race with
1252 * vmw_svga_disable(), but that should at worst cause atomic KMS state
1253 * to be inconsistent with the device, causing modesetting problems.
1256 vmw_kms_lost_device(dev_priv
->dev
);
1257 ttm_write_lock(&dev_priv
->reservation_sem
, false);
1258 spin_lock(&dev_priv
->svga_lock
);
1259 if (ttm_resource_manager_used(man
)) {
1260 ttm_resource_manager_set_used(man
, false);
1261 spin_unlock(&dev_priv
->svga_lock
);
1262 if (ttm_resource_manager_evict_all(&dev_priv
->bdev
, man
))
1263 DRM_ERROR("Failed evicting VRAM buffers.\n");
1264 vmw_write(dev_priv
, SVGA_REG_ENABLE
,
1265 SVGA_REG_ENABLE_HIDE
|
1266 SVGA_REG_ENABLE_ENABLE
);
1268 spin_unlock(&dev_priv
->svga_lock
);
1269 ttm_write_unlock(&dev_priv
->reservation_sem
);
1272 static void vmw_remove(struct pci_dev
*pdev
)
1274 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1276 drm_dev_unregister(dev
);
1277 vmw_driver_unload(dev
);
1279 pci_disable_device(pdev
);
1282 static unsigned long
1283 vmw_get_unmapped_area(struct file
*file
, unsigned long uaddr
,
1284 unsigned long len
, unsigned long pgoff
,
1285 unsigned long flags
)
1287 struct drm_file
*file_priv
= file
->private_data
;
1288 struct vmw_private
*dev_priv
= vmw_priv(file_priv
->minor
->dev
);
1290 return drm_get_unmapped_area(file
, uaddr
, len
, pgoff
, flags
,
1291 &dev_priv
->vma_manager
);
1294 static int vmwgfx_pm_notifier(struct notifier_block
*nb
, unsigned long val
,
1297 struct vmw_private
*dev_priv
=
1298 container_of(nb
, struct vmw_private
, pm_nb
);
1301 case PM_HIBERNATION_PREPARE
:
1303 * Take the reservation sem in write mode, which will make sure
1304 * there are no other processes holding a buffer object
1305 * reservation, meaning we should be able to evict all buffer
1306 * objects if needed.
1307 * Once user-space processes have been frozen, we can release
1310 ttm_suspend_lock(&dev_priv
->reservation_sem
);
1311 dev_priv
->suspend_locked
= true;
1313 case PM_POST_HIBERNATION
:
1314 case PM_POST_RESTORE
:
1315 if (READ_ONCE(dev_priv
->suspend_locked
)) {
1316 dev_priv
->suspend_locked
= false;
1317 ttm_suspend_unlock(&dev_priv
->reservation_sem
);
1326 static int vmw_pci_suspend(struct pci_dev
*pdev
, pm_message_t state
)
1328 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1329 struct vmw_private
*dev_priv
= vmw_priv(dev
);
1331 if (dev_priv
->refuse_hibernation
)
1334 pci_save_state(pdev
);
1335 pci_disable_device(pdev
);
1336 pci_set_power_state(pdev
, PCI_D3hot
);
1340 static int vmw_pci_resume(struct pci_dev
*pdev
)
1342 pci_set_power_state(pdev
, PCI_D0
);
1343 pci_restore_state(pdev
);
1344 return pci_enable_device(pdev
);
1347 static int vmw_pm_suspend(struct device
*kdev
)
1349 struct pci_dev
*pdev
= to_pci_dev(kdev
);
1350 struct pm_message dummy
;
1354 return vmw_pci_suspend(pdev
, dummy
);
1357 static int vmw_pm_resume(struct device
*kdev
)
1359 struct pci_dev
*pdev
= to_pci_dev(kdev
);
1361 return vmw_pci_resume(pdev
);
1364 static int vmw_pm_freeze(struct device
*kdev
)
1366 struct pci_dev
*pdev
= to_pci_dev(kdev
);
1367 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1368 struct vmw_private
*dev_priv
= vmw_priv(dev
);
1369 struct ttm_operation_ctx ctx
= {
1370 .interruptible
= false,
1371 .no_wait_gpu
= false
1376 * Unlock for vmw_kms_suspend.
1377 * No user-space processes should be running now.
1379 ttm_suspend_unlock(&dev_priv
->reservation_sem
);
1380 ret
= vmw_kms_suspend(dev_priv
->dev
);
1382 ttm_suspend_lock(&dev_priv
->reservation_sem
);
1383 DRM_ERROR("Failed to freeze modesetting.\n");
1386 if (dev_priv
->enable_fb
)
1387 vmw_fb_off(dev_priv
);
1389 ttm_suspend_lock(&dev_priv
->reservation_sem
);
1390 vmw_execbuf_release_pinned_bo(dev_priv
);
1391 vmw_resource_evict_all(dev_priv
);
1392 vmw_release_device_early(dev_priv
);
1393 while (ttm_bo_swapout(&ctx
) == 0);
1394 if (dev_priv
->enable_fb
)
1395 vmw_fifo_resource_dec(dev_priv
);
1396 if (atomic_read(&dev_priv
->num_fifo_resources
) != 0) {
1397 DRM_ERROR("Can't hibernate while 3D resources are active.\n");
1398 if (dev_priv
->enable_fb
)
1399 vmw_fifo_resource_inc(dev_priv
);
1400 WARN_ON(vmw_request_device_late(dev_priv
));
1401 dev_priv
->suspend_locked
= false;
1402 ttm_suspend_unlock(&dev_priv
->reservation_sem
);
1403 if (dev_priv
->suspend_state
)
1404 vmw_kms_resume(dev
);
1405 if (dev_priv
->enable_fb
)
1406 vmw_fb_on(dev_priv
);
1410 vmw_fence_fifo_down(dev_priv
->fman
);
1411 __vmw_svga_disable(dev_priv
);
1413 vmw_release_device_late(dev_priv
);
1417 static int vmw_pm_restore(struct device
*kdev
)
1419 struct pci_dev
*pdev
= to_pci_dev(kdev
);
1420 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1421 struct vmw_private
*dev_priv
= vmw_priv(dev
);
1424 vmw_write(dev_priv
, SVGA_REG_ID
, SVGA_ID_2
);
1425 (void) vmw_read(dev_priv
, SVGA_REG_ID
);
1427 if (dev_priv
->enable_fb
)
1428 vmw_fifo_resource_inc(dev_priv
);
1430 ret
= vmw_request_device(dev_priv
);
1434 if (dev_priv
->enable_fb
)
1435 __vmw_svga_enable(dev_priv
);
1437 vmw_fence_fifo_up(dev_priv
->fman
);
1438 dev_priv
->suspend_locked
= false;
1439 ttm_suspend_unlock(&dev_priv
->reservation_sem
);
1440 if (dev_priv
->suspend_state
)
1441 vmw_kms_resume(dev_priv
->dev
);
1443 if (dev_priv
->enable_fb
)
1444 vmw_fb_on(dev_priv
);
1449 static const struct dev_pm_ops vmw_pm_ops
= {
1450 .freeze
= vmw_pm_freeze
,
1451 .thaw
= vmw_pm_restore
,
1452 .restore
= vmw_pm_restore
,
1453 .suspend
= vmw_pm_suspend
,
1454 .resume
= vmw_pm_resume
,
1457 static const struct file_operations vmwgfx_driver_fops
= {
1458 .owner
= THIS_MODULE
,
1460 .release
= drm_release
,
1461 .unlocked_ioctl
= vmw_unlocked_ioctl
,
1463 .poll
= vmw_fops_poll
,
1464 .read
= vmw_fops_read
,
1465 #if defined(CONFIG_COMPAT)
1466 .compat_ioctl
= vmw_compat_ioctl
,
1468 .llseek
= noop_llseek
,
1469 .get_unmapped_area
= vmw_get_unmapped_area
,
1472 static const struct drm_driver driver
= {
1474 DRIVER_MODESET
| DRIVER_RENDER
| DRIVER_ATOMIC
,
1475 .ioctls
= vmw_ioctls
,
1476 .num_ioctls
= ARRAY_SIZE(vmw_ioctls
),
1477 .master_set
= vmw_master_set
,
1478 .master_drop
= vmw_master_drop
,
1479 .open
= vmw_driver_open
,
1480 .postclose
= vmw_postclose
,
1482 .dumb_create
= vmw_dumb_create
,
1483 .dumb_map_offset
= vmw_dumb_map_offset
,
1484 .dumb_destroy
= vmw_dumb_destroy
,
1486 .prime_fd_to_handle
= vmw_prime_fd_to_handle
,
1487 .prime_handle_to_fd
= vmw_prime_handle_to_fd
,
1489 .fops
= &vmwgfx_driver_fops
,
1490 .name
= VMWGFX_DRIVER_NAME
,
1491 .desc
= VMWGFX_DRIVER_DESC
,
1492 .date
= VMWGFX_DRIVER_DATE
,
1493 .major
= VMWGFX_DRIVER_MAJOR
,
1494 .minor
= VMWGFX_DRIVER_MINOR
,
1495 .patchlevel
= VMWGFX_DRIVER_PATCHLEVEL
1498 static struct pci_driver vmw_pci_driver
= {
1499 .name
= VMWGFX_DRIVER_NAME
,
1500 .id_table
= vmw_pci_id_list
,
1502 .remove
= vmw_remove
,
1508 static int vmw_probe(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1510 struct drm_device
*dev
;
1513 ret
= pci_enable_device(pdev
);
1517 dev
= drm_dev_alloc(&driver
, &pdev
->dev
);
1520 goto err_pci_disable_device
;
1524 pci_set_drvdata(pdev
, dev
);
1526 ret
= vmw_driver_load(dev
, ent
->driver_data
);
1528 goto err_drm_dev_put
;
1530 ret
= drm_dev_register(dev
, ent
->driver_data
);
1532 goto err_vmw_driver_unload
;
1536 err_vmw_driver_unload
:
1537 vmw_driver_unload(dev
);
1540 err_pci_disable_device
:
1541 pci_disable_device(pdev
);
1545 static int __init
vmwgfx_init(void)
1549 if (vgacon_text_force())
1552 ret
= pci_register_driver(&vmw_pci_driver
);
1554 DRM_ERROR("Failed initializing DRM.\n");
1558 static void __exit
vmwgfx_exit(void)
1560 pci_unregister_driver(&vmw_pci_driver
);
1563 module_init(vmwgfx_init
);
1564 module_exit(vmwgfx_exit
);
1566 MODULE_AUTHOR("VMware Inc. and others");
1567 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device");
1568 MODULE_LICENSE("GPL and additional rights");
1569 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR
) "."
1570 __stringify(VMWGFX_DRIVER_MINOR
) "."
1571 __stringify(VMWGFX_DRIVER_PATCHLEVEL
) "."