1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2010 Google, Inc.
4 * Author: Erik Gilling <konkers@android.com>
6 * Copyright (C) 2011-2017 NVIDIA Corporation
12 #include "../channel.h"
14 static void host1x_debug_show_channel_cdma(struct host1x
*host
,
15 struct host1x_channel
*ch
,
18 struct host1x_cdma
*cdma
= &ch
->cdma
;
19 u32 dmaput
, dmaget
, dmactrl
;
23 dmaput
= host1x_ch_readl(ch
, HOST1X_CHANNEL_DMAPUT
);
24 dmaget
= host1x_ch_readl(ch
, HOST1X_CHANNEL_DMAGET
);
25 dmactrl
= host1x_ch_readl(ch
, HOST1X_CHANNEL_DMACTRL
);
26 offset
= host1x_ch_readl(ch
, HOST1X_CHANNEL_CMDP_OFFSET
);
27 class = host1x_ch_readl(ch
, HOST1X_CHANNEL_CMDP_CLASS
);
28 ch_stat
= host1x_ch_readl(ch
, HOST1X_CHANNEL_CHANNELSTAT
);
30 host1x_debug_output(o
, "%u-%s: ", ch
->id
, dev_name(ch
->dev
));
32 if (dmactrl
& HOST1X_CHANNEL_DMACTRL_DMASTOP
||
33 !ch
->cdma
.push_buffer
.mapped
) {
34 host1x_debug_output(o
, "inactive\n\n");
38 if (class == HOST1X_CLASS_HOST1X
&& offset
== HOST1X_UCLASS_WAIT_SYNCPT
)
39 host1x_debug_output(o
, "waiting on syncpt\n");
41 host1x_debug_output(o
, "active class %02x, offset %04x\n",
44 host1x_debug_output(o
, "DMAPUT %08x, DMAGET %08x, DMACTL %08x\n",
45 dmaput
, dmaget
, dmactrl
);
46 host1x_debug_output(o
, "CHANNELSTAT %02x\n", ch_stat
);
48 show_channel_gathers(o
, cdma
);
49 host1x_debug_output(o
, "\n");
52 static void host1x_debug_show_channel_fifo(struct host1x
*host
,
53 struct host1x_channel
*ch
,
57 u32 rd_ptr
, wr_ptr
, start
, end
;
58 u32 payload
= INVALID_PAYLOAD
;
59 unsigned int data_count
= 0;
63 host1x_debug_output(o
, "%u: fifo:\n", ch
->id
);
65 val
= host1x_ch_readl(ch
, HOST1X_CHANNEL_CMDFIFO_STAT
);
66 host1x_debug_output(o
, "CMDFIFO_STAT %08x\n", val
);
67 if (val
& HOST1X_CHANNEL_CMDFIFO_STAT_EMPTY
) {
68 host1x_debug_output(o
, "[empty]\n");
72 val
= host1x_ch_readl(ch
, HOST1X_CHANNEL_CMDFIFO_RDATA
);
73 host1x_debug_output(o
, "CMDFIFO_RDATA %08x\n", val
);
76 /* Peek pointer values are invalid during SLCG, so disable it */
77 host1x_hypervisor_writel(host
, 0x1, HOST1X_HV_ICG_EN_OVERRIDE
);
80 val
|= HOST1X_HV_CMDFIFO_PEEK_CTRL_ENABLE
;
81 val
|= HOST1X_HV_CMDFIFO_PEEK_CTRL_CHANNEL(ch
->id
);
82 host1x_hypervisor_writel(host
, val
, HOST1X_HV_CMDFIFO_PEEK_CTRL
);
84 val
= host1x_hypervisor_readl(host
, HOST1X_HV_CMDFIFO_PEEK_PTRS
);
85 rd_ptr
= HOST1X_HV_CMDFIFO_PEEK_PTRS_RD_PTR_V(val
);
86 wr_ptr
= HOST1X_HV_CMDFIFO_PEEK_PTRS_WR_PTR_V(val
);
88 val
= host1x_hypervisor_readl(host
, HOST1X_HV_CMDFIFO_SETUP(ch
->id
));
89 start
= HOST1X_HV_CMDFIFO_SETUP_BASE_V(val
);
90 end
= HOST1X_HV_CMDFIFO_SETUP_LIMIT_V(val
);
94 val
|= HOST1X_HV_CMDFIFO_PEEK_CTRL_ENABLE
;
95 val
|= HOST1X_HV_CMDFIFO_PEEK_CTRL_CHANNEL(ch
->id
);
96 val
|= HOST1X_HV_CMDFIFO_PEEK_CTRL_ADDR(rd_ptr
);
97 host1x_hypervisor_writel(host
, val
,
98 HOST1X_HV_CMDFIFO_PEEK_CTRL
);
100 val
= host1x_hypervisor_readl(host
,
101 HOST1X_HV_CMDFIFO_PEEK_READ
);
104 host1x_debug_output(o
, "%03x 0x%08x: ",
105 rd_ptr
- start
, val
);
106 data_count
= show_channel_command(o
, val
, &payload
);
108 host1x_debug_cont(o
, "%08x%s", val
,
109 data_count
> 1 ? ", " : "])\n");
117 } while (rd_ptr
!= wr_ptr
);
120 host1x_debug_cont(o
, ", ...])\n");
121 host1x_debug_output(o
, "\n");
123 host1x_hypervisor_writel(host
, 0x0, HOST1X_HV_CMDFIFO_PEEK_CTRL
);
124 host1x_hypervisor_writel(host
, 0x0, HOST1X_HV_ICG_EN_OVERRIDE
);
128 static void host1x_debug_show_mlocks(struct host1x
*host
, struct output
*o
)