Merge tag 'block-5.11-2021-01-10' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / gpu / host1x / hw / host1x04_hardware.h
blob4f9bcddf27e328978dbfb314c8b0164c9be6d332
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Tegra host1x Register Offsets for Tegra124
5 * Copyright (c) 2010-2013 NVIDIA Corporation.
6 */
8 #ifndef __HOST1X_HOST1X04_HARDWARE_H
9 #define __HOST1X_HOST1X04_HARDWARE_H
11 #include <linux/types.h>
12 #include <linux/bitops.h>
14 #include "hw_host1x04_channel.h"
15 #include "hw_host1x04_sync.h"
16 #include "hw_host1x04_uclass.h"
18 static inline u32 host1x_class_host_wait_syncpt(
19 unsigned indx, unsigned threshold)
21 return host1x_uclass_wait_syncpt_indx_f(indx)
22 | host1x_uclass_wait_syncpt_thresh_f(threshold);
25 static inline u32 host1x_class_host_load_syncpt_base(
26 unsigned indx, unsigned threshold)
28 return host1x_uclass_load_syncpt_base_base_indx_f(indx)
29 | host1x_uclass_load_syncpt_base_value_f(threshold);
32 static inline u32 host1x_class_host_wait_syncpt_base(
33 unsigned indx, unsigned base_indx, unsigned offset)
35 return host1x_uclass_wait_syncpt_base_indx_f(indx)
36 | host1x_uclass_wait_syncpt_base_base_indx_f(base_indx)
37 | host1x_uclass_wait_syncpt_base_offset_f(offset);
40 static inline u32 host1x_class_host_incr_syncpt_base(
41 unsigned base_indx, unsigned offset)
43 return host1x_uclass_incr_syncpt_base_base_indx_f(base_indx)
44 | host1x_uclass_incr_syncpt_base_offset_f(offset);
47 static inline u32 host1x_class_host_incr_syncpt(
48 unsigned cond, unsigned indx)
50 return host1x_uclass_incr_syncpt_cond_f(cond)
51 | host1x_uclass_incr_syncpt_indx_f(indx);
54 static inline u32 host1x_class_host_indoff_reg_write(
55 unsigned mod_id, unsigned offset, bool auto_inc)
57 u32 v = host1x_uclass_indoff_indbe_f(0xf)
58 | host1x_uclass_indoff_indmodid_f(mod_id)
59 | host1x_uclass_indoff_indroffset_f(offset);
60 if (auto_inc)
61 v |= host1x_uclass_indoff_autoinc_f(1);
62 return v;
65 static inline u32 host1x_class_host_indoff_reg_read(
66 unsigned mod_id, unsigned offset, bool auto_inc)
68 u32 v = host1x_uclass_indoff_indmodid_f(mod_id)
69 | host1x_uclass_indoff_indroffset_f(offset)
70 | host1x_uclass_indoff_rwn_read_v();
71 if (auto_inc)
72 v |= host1x_uclass_indoff_autoinc_f(1);
73 return v;
76 /* cdma opcodes */
77 static inline u32 host1x_opcode_setclass(
78 unsigned class_id, unsigned offset, unsigned mask)
80 return (0 << 28) | (offset << 16) | (class_id << 6) | mask;
83 static inline u32 host1x_opcode_incr(unsigned offset, unsigned count)
85 return (1 << 28) | (offset << 16) | count;
88 static inline u32 host1x_opcode_nonincr(unsigned offset, unsigned count)
90 return (2 << 28) | (offset << 16) | count;
93 static inline u32 host1x_opcode_mask(unsigned offset, unsigned mask)
95 return (3 << 28) | (offset << 16) | mask;
98 static inline u32 host1x_opcode_imm(unsigned offset, unsigned value)
100 return (4 << 28) | (offset << 16) | value;
103 static inline u32 host1x_opcode_imm_incr_syncpt(unsigned cond, unsigned indx)
105 return host1x_opcode_imm(host1x_uclass_incr_syncpt_r(),
106 host1x_class_host_incr_syncpt(cond, indx));
109 static inline u32 host1x_opcode_restart(unsigned address)
111 return (5 << 28) | (address >> 4);
114 static inline u32 host1x_opcode_gather(unsigned count)
116 return (6 << 28) | count;
119 static inline u32 host1x_opcode_gather_nonincr(unsigned offset, unsigned count)
121 return (6 << 28) | (offset << 16) | BIT(15) | count;
124 static inline u32 host1x_opcode_gather_incr(unsigned offset, unsigned count)
126 return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count;
129 #define HOST1X_OPCODE_NOP host1x_opcode_nonincr(0, 0)
131 #endif