Merge tag 'block-5.11-2021-01-10' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / gpu / host1x / hw / hw_host1x01_uclass.h
blob1239bfd46a5e7e8873bfa06b6dd5a11064ad4e67
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (c) 2012-2013, NVIDIA Corporation.
4 */
6 /*
7 * Function naming determines intended use:
9 * <x>_r(void) : Returns the offset for register <x>.
11 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
13 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
15 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
16 * and masked to place it at field <y> of register <x>. This value
17 * can be |'d with others to produce a full register value for
18 * register <x>.
20 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
21 * value can be ~'d and then &'d to clear the value of field <y> for
22 * register <x>.
24 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
25 * to place it at field <y> of register <x>. This value can be |'d
26 * with others to produce a full register value for <x>.
28 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
29 * <x> value 'r' after being shifted to place its LSB at bit 0.
30 * This value is suitable for direct comparison with other unshifted
31 * values appropriate for use in field <y> of register <x>.
33 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
34 * field <y> of register <x>. This value is suitable for direct
35 * comparison with unshifted values appropriate for use in field <y>
36 * of register <x>.
39 #ifndef __hw_host1x_uclass_host1x_h__
40 #define __hw_host1x_uclass_host1x_h__
42 static inline u32 host1x_uclass_incr_syncpt_r(void)
44 return 0x0;
46 #define HOST1X_UCLASS_INCR_SYNCPT \
47 host1x_uclass_incr_syncpt_r()
48 static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v)
50 return (v & 0xff) << 8;
52 #define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \
53 host1x_uclass_incr_syncpt_cond_f(v)
54 static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v)
56 return (v & 0xff) << 0;
58 #define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) \
59 host1x_uclass_incr_syncpt_indx_f(v)
60 static inline u32 host1x_uclass_wait_syncpt_r(void)
62 return 0x8;
64 #define HOST1X_UCLASS_WAIT_SYNCPT \
65 host1x_uclass_wait_syncpt_r()
66 static inline u32 host1x_uclass_wait_syncpt_indx_f(u32 v)
68 return (v & 0xff) << 24;
70 #define HOST1X_UCLASS_WAIT_SYNCPT_INDX_F(v) \
71 host1x_uclass_wait_syncpt_indx_f(v)
72 static inline u32 host1x_uclass_wait_syncpt_thresh_f(u32 v)
74 return (v & 0xffffff) << 0;
76 #define HOST1X_UCLASS_WAIT_SYNCPT_THRESH_F(v) \
77 host1x_uclass_wait_syncpt_thresh_f(v)
78 static inline u32 host1x_uclass_wait_syncpt_base_r(void)
80 return 0x9;
82 #define HOST1X_UCLASS_WAIT_SYNCPT_BASE \
83 host1x_uclass_wait_syncpt_base_r()
84 static inline u32 host1x_uclass_wait_syncpt_base_indx_f(u32 v)
86 return (v & 0xff) << 24;
88 #define HOST1X_UCLASS_WAIT_SYNCPT_BASE_INDX_F(v) \
89 host1x_uclass_wait_syncpt_base_indx_f(v)
90 static inline u32 host1x_uclass_wait_syncpt_base_base_indx_f(u32 v)
92 return (v & 0xff) << 16;
94 #define HOST1X_UCLASS_WAIT_SYNCPT_BASE_BASE_INDX_F(v) \
95 host1x_uclass_wait_syncpt_base_base_indx_f(v)
96 static inline u32 host1x_uclass_wait_syncpt_base_offset_f(u32 v)
98 return (v & 0xffff) << 0;
100 #define HOST1X_UCLASS_WAIT_SYNCPT_BASE_OFFSET_F(v) \
101 host1x_uclass_wait_syncpt_base_offset_f(v)
102 static inline u32 host1x_uclass_load_syncpt_base_r(void)
104 return 0xb;
106 #define HOST1X_UCLASS_LOAD_SYNCPT_BASE \
107 host1x_uclass_load_syncpt_base_r()
108 static inline u32 host1x_uclass_load_syncpt_base_base_indx_f(u32 v)
110 return (v & 0xff) << 24;
112 #define HOST1X_UCLASS_LOAD_SYNCPT_BASE_BASE_INDX_F(v) \
113 host1x_uclass_load_syncpt_base_base_indx_f(v)
114 static inline u32 host1x_uclass_load_syncpt_base_value_f(u32 v)
116 return (v & 0xffffff) << 0;
118 #define HOST1X_UCLASS_LOAD_SYNCPT_BASE_VALUE_F(v) \
119 host1x_uclass_load_syncpt_base_value_f(v)
120 static inline u32 host1x_uclass_incr_syncpt_base_base_indx_f(u32 v)
122 return (v & 0xff) << 24;
124 #define HOST1X_UCLASS_INCR_SYNCPT_BASE_BASE_INDX_F(v) \
125 host1x_uclass_incr_syncpt_base_base_indx_f(v)
126 static inline u32 host1x_uclass_incr_syncpt_base_offset_f(u32 v)
128 return (v & 0xffffff) << 0;
130 #define HOST1X_UCLASS_INCR_SYNCPT_BASE_OFFSET_F(v) \
131 host1x_uclass_incr_syncpt_base_offset_f(v)
132 static inline u32 host1x_uclass_indoff_r(void)
134 return 0x2d;
136 #define HOST1X_UCLASS_INDOFF \
137 host1x_uclass_indoff_r()
138 static inline u32 host1x_uclass_indoff_indbe_f(u32 v)
140 return (v & 0xf) << 28;
142 #define HOST1X_UCLASS_INDOFF_INDBE_F(v) \
143 host1x_uclass_indoff_indbe_f(v)
144 static inline u32 host1x_uclass_indoff_autoinc_f(u32 v)
146 return (v & 0x1) << 27;
148 #define HOST1X_UCLASS_INDOFF_AUTOINC_F(v) \
149 host1x_uclass_indoff_autoinc_f(v)
150 static inline u32 host1x_uclass_indoff_indmodid_f(u32 v)
152 return (v & 0xff) << 18;
154 #define HOST1X_UCLASS_INDOFF_INDMODID_F(v) \
155 host1x_uclass_indoff_indmodid_f(v)
156 static inline u32 host1x_uclass_indoff_indroffset_f(u32 v)
158 return (v & 0xffff) << 2;
160 #define HOST1X_UCLASS_INDOFF_INDROFFSET_F(v) \
161 host1x_uclass_indoff_indroffset_f(v)
162 static inline u32 host1x_uclass_indoff_rwn_read_v(void)
164 return 1;
166 #define HOST1X_UCLASS_INDOFF_INDROFFSET_F(v) \
167 host1x_uclass_indoff_indroffset_f(v)
168 #endif