Merge tag 'block-5.11-2021-01-10' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / hwtracing / coresight / coresight-etm4x.h
blob3dd3e0633328fc2434a6feb6a9de82228c7d13cc
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
4 */
6 #ifndef _CORESIGHT_CORESIGHT_ETM_H
7 #define _CORESIGHT_CORESIGHT_ETM_H
9 #include <asm/local.h>
10 #include <linux/spinlock.h>
11 #include <linux/types.h>
12 #include "coresight-priv.h"
15 * Device registers:
16 * 0x000 - 0x2FC: Trace registers
17 * 0x300 - 0x314: Management registers
18 * 0x318 - 0xEFC: Trace registers
19 * 0xF00: Management registers
20 * 0xFA0 - 0xFA4: Trace registers
21 * 0xFA8 - 0xFFC: Management registers
23 /* Trace registers (0x000-0x2FC) */
24 /* Main control and configuration registers */
25 #define TRCPRGCTLR 0x004
26 #define TRCPROCSELR 0x008
27 #define TRCSTATR 0x00C
28 #define TRCCONFIGR 0x010
29 #define TRCAUXCTLR 0x018
30 #define TRCEVENTCTL0R 0x020
31 #define TRCEVENTCTL1R 0x024
32 #define TRCSTALLCTLR 0x02C
33 #define TRCTSCTLR 0x030
34 #define TRCSYNCPR 0x034
35 #define TRCCCCTLR 0x038
36 #define TRCBBCTLR 0x03C
37 #define TRCTRACEIDR 0x040
38 #define TRCQCTLR 0x044
39 /* Filtering control registers */
40 #define TRCVICTLR 0x080
41 #define TRCVIIECTLR 0x084
42 #define TRCVISSCTLR 0x088
43 #define TRCVIPCSSCTLR 0x08C
44 #define TRCVDCTLR 0x0A0
45 #define TRCVDSACCTLR 0x0A4
46 #define TRCVDARCCTLR 0x0A8
47 /* Derived resources registers */
48 #define TRCSEQEVRn(n) (0x100 + (n * 4))
49 #define TRCSEQRSTEVR 0x118
50 #define TRCSEQSTR 0x11C
51 #define TRCEXTINSELR 0x120
52 #define TRCCNTRLDVRn(n) (0x140 + (n * 4))
53 #define TRCCNTCTLRn(n) (0x150 + (n * 4))
54 #define TRCCNTVRn(n) (0x160 + (n * 4))
55 /* ID registers */
56 #define TRCIDR8 0x180
57 #define TRCIDR9 0x184
58 #define TRCIDR10 0x188
59 #define TRCIDR11 0x18C
60 #define TRCIDR12 0x190
61 #define TRCIDR13 0x194
62 #define TRCIMSPEC0 0x1C0
63 #define TRCIMSPECn(n) (0x1C0 + (n * 4))
64 #define TRCIDR0 0x1E0
65 #define TRCIDR1 0x1E4
66 #define TRCIDR2 0x1E8
67 #define TRCIDR3 0x1EC
68 #define TRCIDR4 0x1F0
69 #define TRCIDR5 0x1F4
70 #define TRCIDR6 0x1F8
71 #define TRCIDR7 0x1FC
72 /* Resource selection registers */
73 #define TRCRSCTLRn(n) (0x200 + (n * 4))
74 /* Single-shot comparator registers */
75 #define TRCSSCCRn(n) (0x280 + (n * 4))
76 #define TRCSSCSRn(n) (0x2A0 + (n * 4))
77 #define TRCSSPCICRn(n) (0x2C0 + (n * 4))
78 /* Management registers (0x300-0x314) */
79 #define TRCOSLAR 0x300
80 #define TRCOSLSR 0x304
81 #define TRCPDCR 0x310
82 #define TRCPDSR 0x314
83 /* Trace registers (0x318-0xEFC) */
84 /* Comparator registers */
85 #define TRCACVRn(n) (0x400 + (n * 8))
86 #define TRCACATRn(n) (0x480 + (n * 8))
87 #define TRCDVCVRn(n) (0x500 + (n * 16))
88 #define TRCDVCMRn(n) (0x580 + (n * 16))
89 #define TRCCIDCVRn(n) (0x600 + (n * 8))
90 #define TRCVMIDCVRn(n) (0x640 + (n * 8))
91 #define TRCCIDCCTLR0 0x680
92 #define TRCCIDCCTLR1 0x684
93 #define TRCVMIDCCTLR0 0x688
94 #define TRCVMIDCCTLR1 0x68C
95 /* Management register (0xF00) */
96 /* Integration control registers */
97 #define TRCITCTRL 0xF00
98 /* Trace registers (0xFA0-0xFA4) */
99 /* Claim tag registers */
100 #define TRCCLAIMSET 0xFA0
101 #define TRCCLAIMCLR 0xFA4
102 /* Management registers (0xFA8-0xFFC) */
103 #define TRCDEVAFF0 0xFA8
104 #define TRCDEVAFF1 0xFAC
105 #define TRCLAR 0xFB0
106 #define TRCLSR 0xFB4
107 #define TRCAUTHSTATUS 0xFB8
108 #define TRCDEVARCH 0xFBC
109 #define TRCDEVID 0xFC8
110 #define TRCDEVTYPE 0xFCC
111 #define TRCPIDR4 0xFD0
112 #define TRCPIDR5 0xFD4
113 #define TRCPIDR6 0xFD8
114 #define TRCPIDR7 0xFDC
115 #define TRCPIDR0 0xFE0
116 #define TRCPIDR1 0xFE4
117 #define TRCPIDR2 0xFE8
118 #define TRCPIDR3 0xFEC
119 #define TRCCIDR0 0xFF0
120 #define TRCCIDR1 0xFF4
121 #define TRCCIDR2 0xFF8
122 #define TRCCIDR3 0xFFC
124 /* ETMv4 resources */
125 #define ETM_MAX_NR_PE 8
126 #define ETMv4_MAX_CNTR 4
127 #define ETM_MAX_SEQ_STATES 4
128 #define ETM_MAX_EXT_INP_SEL 4
129 #define ETM_MAX_EXT_INP 256
130 #define ETM_MAX_EXT_OUT 4
131 #define ETM_MAX_SINGLE_ADDR_CMP 16
132 #define ETM_MAX_ADDR_RANGE_CMP (ETM_MAX_SINGLE_ADDR_CMP / 2)
133 #define ETM_MAX_DATA_VAL_CMP 8
134 #define ETMv4_MAX_CTXID_CMP 8
135 #define ETM_MAX_VMID_CMP 8
136 #define ETM_MAX_PE_CMP 8
137 #define ETM_MAX_RES_SEL 32
138 #define ETM_MAX_SS_CMP 8
140 #define ETM_ARCH_V4 0x40
141 #define ETMv4_SYNC_MASK 0x1F
142 #define ETM_CYC_THRESHOLD_MASK 0xFFF
143 #define ETM_CYC_THRESHOLD_DEFAULT 0x100
144 #define ETMv4_EVENT_MASK 0xFF
145 #define ETM_CNTR_MAX_VAL 0xFFFF
146 #define ETM_TRACEID_MASK 0x3f
148 /* ETMv4 programming modes */
149 #define ETM_MODE_EXCLUDE BIT(0)
150 #define ETM_MODE_LOAD BIT(1)
151 #define ETM_MODE_STORE BIT(2)
152 #define ETM_MODE_LOAD_STORE BIT(3)
153 #define ETM_MODE_BB BIT(4)
154 #define ETMv4_MODE_CYCACC BIT(5)
155 #define ETMv4_MODE_CTXID BIT(6)
156 #define ETM_MODE_VMID BIT(7)
157 #define ETM_MODE_COND(val) BMVAL(val, 8, 10)
158 #define ETMv4_MODE_TIMESTAMP BIT(11)
159 #define ETM_MODE_RETURNSTACK BIT(12)
160 #define ETM_MODE_QELEM(val) BMVAL(val, 13, 14)
161 #define ETM_MODE_DATA_TRACE_ADDR BIT(15)
162 #define ETM_MODE_DATA_TRACE_VAL BIT(16)
163 #define ETM_MODE_ISTALL BIT(17)
164 #define ETM_MODE_DSTALL BIT(18)
165 #define ETM_MODE_ATB_TRIGGER BIT(19)
166 #define ETM_MODE_LPOVERRIDE BIT(20)
167 #define ETM_MODE_ISTALL_EN BIT(21)
168 #define ETM_MODE_DSTALL_EN BIT(22)
169 #define ETM_MODE_INSTPRIO BIT(23)
170 #define ETM_MODE_NOOVERFLOW BIT(24)
171 #define ETM_MODE_TRACE_RESET BIT(25)
172 #define ETM_MODE_TRACE_ERR BIT(26)
173 #define ETM_MODE_VIEWINST_STARTSTOP BIT(27)
174 #define ETMv4_MODE_ALL (GENMASK(27, 0) | \
175 ETM_MODE_EXCL_KERN | \
176 ETM_MODE_EXCL_USER)
178 #define TRCSTATR_IDLE_BIT 0
179 #define TRCSTATR_PMSTABLE_BIT 1
180 #define ETM_DEFAULT_ADDR_COMP 0
182 /* PowerDown Control Register bits */
183 #define TRCPDCR_PU BIT(3)
185 /* secure state access levels - TRCACATRn */
186 #define ETM_EXLEVEL_S_APP BIT(8)
187 #define ETM_EXLEVEL_S_OS BIT(9)
188 #define ETM_EXLEVEL_S_HYP BIT(10)
189 #define ETM_EXLEVEL_S_MON BIT(11)
190 /* non-secure state access levels - TRCACATRn */
191 #define ETM_EXLEVEL_NS_APP BIT(12)
192 #define ETM_EXLEVEL_NS_OS BIT(13)
193 #define ETM_EXLEVEL_NS_HYP BIT(14)
194 #define ETM_EXLEVEL_NS_NA BIT(15)
196 /* access level control in TRCVICTLR - same bits as TRCACATRn but shifted */
197 #define ETM_EXLEVEL_LSHIFT_TRCVICTLR 8
199 /* secure / non secure masks - TRCVICTLR, IDR3 */
200 #define ETM_EXLEVEL_S_VICTLR_MASK GENMASK(19, 16)
201 /* NS MON (EL3) mode never implemented */
202 #define ETM_EXLEVEL_NS_VICTLR_MASK GENMASK(22, 20)
204 /* Interpretation of resource numbers change at ETM v4.3 architecture */
205 #define ETM4X_ARCH_4V3 0x43
207 enum etm_impdef_type {
208 ETM4_IMPDEF_HISI_CORE_COMMIT,
209 ETM4_IMPDEF_FEATURE_MAX,
213 * struct etmv4_config - configuration information related to an ETMv4
214 * @mode: Controls various modes supported by this ETM.
215 * @pe_sel: Controls which PE to trace.
216 * @cfg: Controls the tracing options.
217 * @eventctrl0: Controls the tracing of arbitrary events.
218 * @eventctrl1: Controls the behavior of the events that @event_ctrl0 selects.
219 * @stallctl: If functionality that prevents trace unit buffer overflows
220 * is available.
221 * @ts_ctrl: Controls the insertion of global timestamps in the
222 * trace streams.
223 * @syncfreq: Controls how often trace synchronization requests occur.
224 * the TRCCCCTLR register.
225 * @ccctlr: Sets the threshold value for cycle counting.
226 * @vinst_ctrl: Controls instruction trace filtering.
227 * @viiectlr: Set or read, the address range comparators.
228 * @vissctlr: Set, or read, the single address comparators that control the
229 * ViewInst start-stop logic.
230 * @vipcssctlr: Set, or read, which PE comparator inputs can control the
231 * ViewInst start-stop logic.
232 * @seq_idx: Sequencor index selector.
233 * @seq_ctrl: Control for the sequencer state transition control register.
234 * @seq_rst: Moves the sequencer to state 0 when a programmed event occurs.
235 * @seq_state: Set, or read the sequencer state.
236 * @cntr_idx: Counter index seletor.
237 * @cntrldvr: Sets or returns the reload count value for a counter.
238 * @cntr_ctrl: Controls the operation of a counter.
239 * @cntr_val: Sets or returns the value for a counter.
240 * @res_idx: Resource index selector.
241 * @res_ctrl: Controls the selection of the resources in the trace unit.
242 * @ss_idx: Single-shot index selector.
243 * @ss_ctrl: Controls the corresponding single-shot comparator resource.
244 * @ss_status: The status of the corresponding single-shot comparator.
245 * @ss_pe_cmp: Selects the PE comparator inputs for Single-shot control.
246 * @addr_idx: Address comparator index selector.
247 * @addr_val: Value for address comparator.
248 * @addr_acc: Address comparator access type.
249 * @addr_type: Current status of the comparator register.
250 * @ctxid_idx: Context ID index selector.
251 * @ctxid_pid: Value of the context ID comparator.
252 * @ctxid_mask0:Context ID comparator mask for comparator 0-3.
253 * @ctxid_mask1:Context ID comparator mask for comparator 4-7.
254 * @vmid_idx: VM ID index selector.
255 * @vmid_val: Value of the VM ID comparator.
256 * @vmid_mask0: VM ID comparator mask for comparator 0-3.
257 * @vmid_mask1: VM ID comparator mask for comparator 4-7.
258 * @ext_inp: External input selection.
259 * @arch: ETM architecture version (for arch dependent config).
261 struct etmv4_config {
262 u32 mode;
263 u32 pe_sel;
264 u32 cfg;
265 u32 eventctrl0;
266 u32 eventctrl1;
267 u32 stall_ctrl;
268 u32 ts_ctrl;
269 u32 syncfreq;
270 u32 ccctlr;
271 u32 bb_ctrl;
272 u32 vinst_ctrl;
273 u32 viiectlr;
274 u32 vissctlr;
275 u32 vipcssctlr;
276 u8 seq_idx;
277 u32 seq_ctrl[ETM_MAX_SEQ_STATES];
278 u32 seq_rst;
279 u32 seq_state;
280 u8 cntr_idx;
281 u32 cntrldvr[ETMv4_MAX_CNTR];
282 u32 cntr_ctrl[ETMv4_MAX_CNTR];
283 u32 cntr_val[ETMv4_MAX_CNTR];
284 u8 res_idx;
285 u32 res_ctrl[ETM_MAX_RES_SEL];
286 u8 ss_idx;
287 u32 ss_ctrl[ETM_MAX_SS_CMP];
288 u32 ss_status[ETM_MAX_SS_CMP];
289 u32 ss_pe_cmp[ETM_MAX_SS_CMP];
290 u8 addr_idx;
291 u64 addr_val[ETM_MAX_SINGLE_ADDR_CMP];
292 u64 addr_acc[ETM_MAX_SINGLE_ADDR_CMP];
293 u8 addr_type[ETM_MAX_SINGLE_ADDR_CMP];
294 u8 ctxid_idx;
295 u64 ctxid_pid[ETMv4_MAX_CTXID_CMP];
296 u32 ctxid_mask0;
297 u32 ctxid_mask1;
298 u8 vmid_idx;
299 u64 vmid_val[ETM_MAX_VMID_CMP];
300 u32 vmid_mask0;
301 u32 vmid_mask1;
302 u32 ext_inp;
303 u8 arch;
307 * struct etm4_save_state - state to be preserved when ETM is without power
309 struct etmv4_save_state {
310 u32 trcprgctlr;
311 u32 trcprocselr;
312 u32 trcconfigr;
313 u32 trcauxctlr;
314 u32 trceventctl0r;
315 u32 trceventctl1r;
316 u32 trcstallctlr;
317 u32 trctsctlr;
318 u32 trcsyncpr;
319 u32 trcccctlr;
320 u32 trcbbctlr;
321 u32 trctraceidr;
322 u32 trcqctlr;
324 u32 trcvictlr;
325 u32 trcviiectlr;
326 u32 trcvissctlr;
327 u32 trcvipcssctlr;
328 u32 trcvdctlr;
329 u32 trcvdsacctlr;
330 u32 trcvdarcctlr;
332 u32 trcseqevr[ETM_MAX_SEQ_STATES];
333 u32 trcseqrstevr;
334 u32 trcseqstr;
335 u32 trcextinselr;
336 u32 trccntrldvr[ETMv4_MAX_CNTR];
337 u32 trccntctlr[ETMv4_MAX_CNTR];
338 u32 trccntvr[ETMv4_MAX_CNTR];
340 u32 trcrsctlr[ETM_MAX_RES_SEL];
342 u32 trcssccr[ETM_MAX_SS_CMP];
343 u32 trcsscsr[ETM_MAX_SS_CMP];
344 u32 trcsspcicr[ETM_MAX_SS_CMP];
346 u64 trcacvr[ETM_MAX_SINGLE_ADDR_CMP];
347 u64 trcacatr[ETM_MAX_SINGLE_ADDR_CMP];
348 u64 trccidcvr[ETMv4_MAX_CTXID_CMP];
349 u64 trcvmidcvr[ETM_MAX_VMID_CMP];
350 u32 trccidcctlr0;
351 u32 trccidcctlr1;
352 u32 trcvmidcctlr0;
353 u32 trcvmidcctlr1;
355 u32 trcclaimset;
357 u32 cntr_val[ETMv4_MAX_CNTR];
358 u32 seq_state;
359 u32 vinst_ctrl;
360 u32 ss_status[ETM_MAX_SS_CMP];
362 u32 trcpdcr;
366 * struct etm4_drvdata - specifics associated to an ETM component
367 * @base: Memory mapped base address for this component.
368 * @csdev: Component vitals needed by the framework.
369 * @spinlock: Only one at a time pls.
370 * @mode: This tracer's mode, i.e sysFS, Perf or disabled.
371 * @cpu: The cpu this component is affined to.
372 * @arch: ETM version number.
373 * @nr_pe: The number of processing entity available for tracing.
374 * @nr_pe_cmp: The number of processing entity comparator inputs that are
375 * available for tracing.
376 * @nr_addr_cmp:Number of pairs of address comparators available
377 * as found in ETMIDR4 0-3.
378 * @nr_cntr: Number of counters as found in ETMIDR5 bit 28-30.
379 * @nr_ext_inp: Number of external input.
380 * @numcidc: Number of contextID comparators.
381 * @numvmidc: Number of VMID comparators.
382 * @nrseqstate: The number of sequencer states that are implemented.
383 * @nr_event: Indicates how many events the trace unit support.
384 * @nr_resource:The number of resource selection pairs available for tracing.
385 * @nr_ss_cmp: Number of single-shot comparator controls that are available.
386 * @trcid: value of the current ID for this component.
387 * @trcid_size: Indicates the trace ID width.
388 * @ts_size: Global timestamp size field.
389 * @ctxid_size: Size of the context ID field to consider.
390 * @vmid_size: Size of the VM ID comparator to consider.
391 * @ccsize: Indicates the size of the cycle counter in bits.
392 * @ccitmin: minimum value that can be programmed in
393 * @s_ex_level: In secure state, indicates whether instruction tracing is
394 * supported for the corresponding Exception level.
395 * @ns_ex_level:In non-secure state, indicates whether instruction tracing is
396 * supported for the corresponding Exception level.
397 * @sticky_enable: true if ETM base configuration has been done.
398 * @boot_enable:True if we should start tracing at boot time.
399 * @os_unlock: True if access to management registers is allowed.
400 * @instrp0: Tracing of load and store instructions
401 * as P0 elements is supported.
402 * @trcbb: Indicates if the trace unit supports branch broadcast tracing.
403 * @trccond: If the trace unit supports conditional
404 * instruction tracing.
405 * @retstack: Indicates if the implementation supports a return stack.
406 * @trccci: Indicates if the trace unit supports cycle counting
407 * for instruction.
408 * @q_support: Q element support characteristics.
409 * @trc_error: Whether a trace unit can trace a system
410 * error exception.
411 * @syncpr: Indicates if an implementation has a fixed
412 * synchronization period.
413 * @stall_ctrl: Enables trace unit functionality that prevents trace
414 * unit buffer overflows.
415 * @sysstall: Does the system support stall control of the PE?
416 * @nooverflow: Indicate if overflow prevention is supported.
417 * @atbtrig: If the implementation can support ATB triggers
418 * @lpoverride: If the implementation can support low-power state over.
419 * @config: structure holding configuration parameters.
420 * @save_state: State to be preserved across power loss
421 * @state_needs_restore: True when there is context to restore after PM exit
422 * @skip_power_up: Indicates if an implementation can skip powering up
423 * the trace unit.
424 * @arch_features: Bitmap of arch features of etmv4 devices.
426 struct etmv4_drvdata {
427 void __iomem *base;
428 struct coresight_device *csdev;
429 spinlock_t spinlock;
430 local_t mode;
431 int cpu;
432 u8 arch;
433 u8 nr_pe;
434 u8 nr_pe_cmp;
435 u8 nr_addr_cmp;
436 u8 nr_cntr;
437 u8 nr_ext_inp;
438 u8 numcidc;
439 u8 numvmidc;
440 u8 nrseqstate;
441 u8 nr_event;
442 u8 nr_resource;
443 u8 nr_ss_cmp;
444 u8 trcid;
445 u8 trcid_size;
446 u8 ts_size;
447 u8 ctxid_size;
448 u8 vmid_size;
449 u8 ccsize;
450 u8 ccitmin;
451 u8 s_ex_level;
452 u8 ns_ex_level;
453 u8 q_support;
454 bool sticky_enable;
455 bool boot_enable;
456 bool os_unlock;
457 bool instrp0;
458 bool trcbb;
459 bool trccond;
460 bool retstack;
461 bool trccci;
462 bool trc_error;
463 bool syncpr;
464 bool stallctl;
465 bool sysstall;
466 bool nooverflow;
467 bool atbtrig;
468 bool lpoverride;
469 struct etmv4_config config;
470 struct etmv4_save_state *save_state;
471 bool state_needs_restore;
472 bool skip_power_up;
473 DECLARE_BITMAP(arch_features, ETM4_IMPDEF_FEATURE_MAX);
476 /* Address comparator access types */
477 enum etm_addr_acctype {
478 ETM_INSTR_ADDR,
479 ETM_DATA_LOAD_ADDR,
480 ETM_DATA_STORE_ADDR,
481 ETM_DATA_LOAD_STORE_ADDR,
484 /* Address comparator context types */
485 enum etm_addr_ctxtype {
486 ETM_CTX_NONE,
487 ETM_CTX_CTXID,
488 ETM_CTX_VMID,
489 ETM_CTX_CTXID_VMID,
492 extern const struct attribute_group *coresight_etmv4_groups[];
493 void etm4_config_trace_mode(struct etmv4_config *config);
494 #endif